A drive circuit that supports multi-host communication and multi-voltage control

Abstract

The present invention discloses a multi-host communication and multi-voltage control drive circuit, which includes an electrical interface, a main MCU unit, a secondary MCU unit, a first level conversion unit, a second level conversion unit, a TEC driver unit, a TEC unit, a DCDC boost unit, a voltage DAC unit, and an optical computing unit; the electrical interface is respectively connected to the main MCU unit and the secondary MCU unit; the first level conversion unit is connected between the electrical interface and the secondary MCU unit; the second level conversion unit is connected between the main MCU unit and the secondary MCU unit; the TEC driver unit is respectively connected to the main MCU unit and the TEC unit; the DCDC boost unit is respectively connected to the TEC driver unit, the secondary MCU unit, and the voltage DAC unit; the voltage DAC unit is respectively connected to the secondary MCU unit and the optical computing unit. The present invention can provide DAC control and temperature control for the parallel operation of an analog optical matrix, and has high market promotion value.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a drive circuit that supports multi-host communication and multi-voltage control. Background Art

[0002] Silicon photonics AI acceleration chips rely on silicon-based photon integration technology, arranging thousands of optical integration units inside the chip in a certain order to implement different types of operators. When optical signals propagate through these units inside the chip, the computing process can be completed, that is, for light, transmission is a mapping of computing. On the one hand, optical signals themselves have characteristics such as high speed, multi-dimensionality, and passivity, and are more suitable for processing high-speed data compared to electrical signals. On the other hand, the process of completing computing during the transmission of optical signals reduces the repeated transfer of data, effectively weakening the "memory wall"; in addition, as a type of wave, light inherently coincides with certain neural networks (such as RNN, etc.), which is a match between the optical physical process and the AI computing paradigm. Therefore, using optical chips can achieve certain types of operators with low power consumption, low latency, and high throughput.

[0003] At the system level, if a silicon photonics AI acceleration chip is combined with a supporting digital chip, the optical and electrical parts each play their advantages and cooperate highly to form an optoelectronic fusion AI computing architecture, and then match with a complete algorithm, the energy efficiency ratio can be improved by dozens of times compared to traditional electronic chips.

[0004] Currently, there is no relevant patent or literature on this aspect of research.

[0005] The above information is given as background information only to assist in understanding the present disclosure, and does not determine or admit whether any of the above content can be used as the prior art relative to the present disclosure. Summary of the Invention

[0006] The present invention provides a drive circuit that supports multi-host communication and multi-voltage control to solve the deficiencies of electronic operations in the prior art.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A drive circuit that supports multi-host communication and multi-voltage control includes an electrical interface, a main MCU unit, a secondary MCU unit, a first level conversion unit, a second level conversion unit, a TEC driver unit, a TEC unit, a DCDC boost unit, a voltage DAC unit, and an optical computing unit; wherein,

[0009] The electrical interface is respectively connected to the main MCU unit and the secondary MCU unit;

[0010] The first level conversion unit is connected between the electrical interface and the secondary MCU unit;

[0011] The second level conversion unit is connected between the main MCU unit and the secondary MCU unit;

[0012] The TEC driver unit is respectively connected to the main MCU unit and the TEC unit;

[0013] The DCDC boost unit is respectively connected to the TEC driver unit, the secondary MCU unit and the voltage DAC unit;

[0014] The voltage DAC unit is respectively connected to the secondary MCU unit and the optical computing unit.

[0015] Further, in the support multi-host communication and multi-voltage control drive circuit, the main MCU unit includes a main MCU chip U4;

[0016] The SCL0 pin and SDA0 pin of the main MCU chip U4 are connected to the electrical interface;

[0017] The SCL2 pin and SDA2 pin of the main MCU chip U4 are connected to the secondary MCU unit;

[0018] The DAC pin and IO pin of the main MCU chip U4 are connected to the TEC driver unit.

[0019] Further, in the support multi-host communication and multi-voltage control drive circuit, the TEC driver unit includes a TEC driver U5;

[0020] The IN2P pin of the TEC driver U5 is connected to the DAC pin of the main MCU chip U4;

[0021] The EN pin of the TEC driver U5 is connected to the IO pin of the main MCU chip U4 and grounded through the fourteenth resistor R14;

[0022] The LDR pin, SW pin and SFB pin of the TEC driver U5 are connected to the TEC unit;

[0023] The IN2N pin and OUT2 pin of the TEC driver U5 are connected.

[0024] Further, in the support multi-host communication and multi-voltage control drive circuit, the TEC driver unit further includes a temperature control sampling circuit;

[0025] The temperature control sampling circuit includes a thermistor Rt and an inverting proportional amplification sampling circuit;

[0026] The inverting proportional amplification sampling circuit is connected to the TEC driver U5;

[0027] One end of the thermistor Rt is connected to the inverting proportional amplification sampling circuit, and the other end is grounded.

[0028] Further, in the multi-host communication and multi-voltage control drive circuit, the TEC driver unit further includes a seventh resistor R7 and an eighth resistor R8;

[0029] The inverting proportional amplification sampling circuit includes a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11;

[0030] One end of the ninth resistor R9 is connected to the VREF pin of the TEC driver U5, and the other end is connected to one end of the tenth resistor R10;

[0031] The other end of the tenth resistor R10 is connected to the thermistor Rt;

[0032] The IN1N pin of the TEC driver U5 is connected between the ninth resistor R9 and the tenth resistor R10;

[0033] One end of the eleventh resistor R11 is connected to the IN1N pin of the TEC driver U5, and the other end is connected to the OUT1 pin of the TEC driver U5;

[0034] The ADC1 pin of the main MCU chip U4 is connected to the OUT1 pin of the TEC driver U5;

[0035] One end of the seventh resistor R7 is connected to the VREF pin of the TEC driver U5, and the other end is connected to one end of the eighth resistor R8;

[0036] The other end of the eighth resistor R8 is grounded.

[0037] Further, in the multi-host communication and multi-voltage control drive circuit, the TEC unit includes a TEC chip J3 and a first inductor L1;

[0038] The negative pole of the TEC chip J3 is connected to the LDR pin of the TEC driver U5;

[0039] The positive pole of the TEC chip J3 is connected to the SFB pin of the TEC driver U5;

[0040] The first inductor L1 is connected between the SW pin and the SFB pin of the TEC driver U5.

[0041] Further, in the multi-host communication and multi-voltage control drive circuit, the secondary MCU unit includes a secondary MCU chip U1;

[0042] The SCL1 pin and SDA1 pin of the secondary MCU chip U1 are connected to the electrical interface through the first level conversion unit;

[0043] The SCL2 pin and SDA2 pin of the secondary MCU chip U1 are connected to the SCL2 pin and SDA2 pin of the main MCU chip U4 through the second level conversion unit;

[0044] The SCK pin, MISO pin, MOSI pin and IO pin of the secondary MCU chip U1 are connected to the voltage DAC unit.

[0045] Further, in the multi-host communication and multi-voltage control drive circuit, the first level conversion unit includes a first MOS switch tube Q1, a second MOS switch tube Q2, a first resistor R1 and a fourth resistor R4;

[0046] The source electrode of the first MOS switch tube Q1 is connected to the electrical interface, the drain electrode of the first MOS switch tube Q1 is connected to the SDA1 pin of the secondary MCU chip U1, and the gate electrode of the first MOS switch tube Q1 is connected to the DCDC boost unit;

[0047] One end of the first resistor R1 is connected between the drain electrode of the first MOS switch tube Q1 and the SDA1 pin of the secondary MCU chip U1, and the other end is connected to the DCDC boost unit;

[0048] The source electrode of the second MOS switch tube Q2 is connected to the electrical interface, the drain electrode of the second MOS switch tube Q2 is connected to the SCL1 pin of the secondary MCU chip U1, and the gate electrode of the second MOS switch tube Q2 is connected to the DCDC boost unit;

[0049] One end of the fourth resistor R4 is connected between the drain electrode of the second MOS switch tube Q2 and the SCL1 pin of the secondary MCU chip U1, and the other end is connected to the DCDC boost unit;

[0050] The second level conversion unit includes a third MOS switch tube Q3, a fourth MOS switch tube Q4, a second resistor R2, a third resistor R3, a fifth resistor R5 and a sixth resistor R6;

[0051] The source electrode of the third MOS switch tube Q3 is connected to the electrical interface, the drain electrode of the third MOS switch tube Q3 is connected to the SCL2 pin of the secondary MCU chip U1, and the gate electrode of the third MOS switch tube Q3 is connected to the DCDC boost unit;

[0052] One end of the second resistor R2 is connected between the drain of the third MOS switch Q3 and the SCL2 pin of the secondary MCU chip U1, and the other end is connected to the DCDC boost unit;

[0053] The third resistor R3 is connected between the source and the gate of the third MOS switch Q3;

[0054] The source of the fourth MOS switch Q4 is connected to the electrical interface, the drain of the fourth MOS switch Q4 is connected to the SDA2 pin of the secondary MCU chip U1, and the gate of the fourth MOS switch Q4 is connected to the DCDC boost unit;

[0055] One end of the fifth resistor R5 is connected between the drain of the fourth MOS switch Q4 and the SDA2 pin of the secondary MCU chip U1, and the other end is connected to the DCDC boost unit;

[0056] The sixth resistor R6 is connected between the source and the gate of the fourth MOS switch Q4.

[0057] Further, in the multi-host communication and multi-voltage control drive circuit, the voltage DAC unit includes a first voltage DAC chip U2 and a second voltage DAC chip U3;

[0058] The SDI pin, SDO pin and SCLK pin of the first voltage DAC chip U2 are respectively connected to the SCK pin, MISO pin and MOSI pin of the secondary MCU chip U1, the RESET pin, SYNC pin and LDAC pin of the first voltage DAC chip U2 are respectively connected to the IO1 pin, IO2 pin and IO3 pin of the secondary MCU chip U1, and the VOUT0 pin of the first voltage DAC chip U2 is connected to the optical computing unit;

[0059] The SDI pin, SDO pin and SCLK pin of the second voltage DAC chip U3 are respectively connected to the SCK pin, MISO pin and MOSI pin of the secondary MCU chip U1, the RESET pin, SYNC pin and LDAC pin of the second voltage DAC chip U3 are respectively connected to the IO4 pin, IO5 pin and IO6 pin of the secondary MCU chip U1, and the VOUT0 pin of the second voltage DAC chip U3 is connected to the optical computing unit.

[0060] Further, in the multi-host communication and multi-voltage control drive circuit, the optical computing unit includes an optical computing chip J1;

[0061] The S1 pin of the optical computing chip J1 is connected to the VOUT0 pin of the first voltage DAC chip U2, and the S2 pin of the optical computing chip J1 is connected to the VOUT0 pin of the second voltage DAC chip U3;

[0062] The DCDC boost unit includes a DCDC boost chip U6, a twelfth resistor R12, and an RC delay circuit composed of a thirteenth resistor R13 and a first capacitor C1;

[0063] The VOUT pin of the DCDC boost chip U6 is respectively connected to the first resistor R1, the second resistor R2, the fourth resistor R4, and the fifth resistor R5;

[0064] The VIN pin of the DCDC boost chip U6 is respectively connected to the gate of the first MOS switch Q1, the gate of the second MOS switch Q2, the gate of the third MOS switch Q3, and the gate of the fourth MOS switch Q4;

[0065] The twelfth resistor R12 is connected between the VIN pin of the DCDC boost chip U6 and the VOUT0 pin of the first voltage DAC chip U2;

[0066] The first capacitor C1 is connected between the VIN pin of the DCDC boost chip U6 and the EN pin;

[0067] One end of the thirteenth resistor R13 is connected between the EN pin of the DCDC boost chip U6 and the first capacitor C1, and the other end is grounded.

[0068] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0069] A multi-host communication and multi-voltage control drive circuit provided by an embodiment of the present invention, by configuring an electrical interface, a main MCU unit, a secondary MCU unit, a first level conversion unit, a second level conversion unit, a TEC driver unit, a TEC unit, a DCDC boost unit, a voltage DAC unit, and an optical computing unit, and making them cooperate with each other, can provide DAC control and temperature control for the parallel operation of an analog optical matrix, and has high market promotion value. Description of the Drawings

[0070] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0071] Figure 1 It is a schematic diagram of a functional module that supports multi-host communication and multi-voltage control drive circuit provided by an embodiment of the present invention;

[0072] Figure 2 It is a circuit schematic diagram of the main MCU unit, TEC driver unit and TEC unit provided by an embodiment of the present invention;

[0073] Figure 3 It is a circuit schematic diagram of the secondary MCU unit, first level conversion unit, second level conversion unit, voltage DAC unit and optical computing unit provided by an embodiment of the present invention;

[0074] Figure 4 It is a circuit schematic diagram of the DCDC boost unit provided by an embodiment of the present invention. Detailed implementation manners

[0075] To make the objectives, features, and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the embodiments described below are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0076] In the description of the present invention, it should be understood that when a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be an intermediate component. When a component is considered to be "disposed on" another component, it can be directly disposed on the other component or there may be an intermediate component.

[0077] In addition, terms such as "long", "short", "inner", "outer", etc. indicating orientation or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention, rather than indicating or implying that the device or component referred to must have this specific orientation or be constructed and operated in this specific orientation, and thus should not be construed as a limitation of the present invention.

[0078] The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and through specific implementation manners.

[0079] Embodiment 1

[0080] In view of the above-mentioned deficiencies existing in the existing AI computing technologies, the applicant, based on rich practical experience and professional knowledge in the design and manufacture of such products for many years, and in cooperation with the application of academic theories, actively conducts research and innovation, hoping to create a technology that can solve the deficiencies in the existing technologies, so as to achieve a disruptive breakthrough in AI computing performance. After continuous research, design, and repeated trial production of samples and improvements, the present invention with practical value has finally been created.

[0081] Please refer to Figure 1 , an embodiment of the present invention provides a multi-host communication and multi-voltage control drive circuit, including an electrical interface 1, a main MCU unit 2, a secondary MCU unit 3, a first level conversion unit 4, a second level conversion unit 5, a TEC driver unit 6, a TEC unit 7, a DCDC boost unit 8, a voltage DAC unit 9, and an optical computing unit 10; wherein,

[0082] The electrical interface 1 is respectively connected to the main MCU unit 2 and the secondary MCU unit 3;

[0083] The first level conversion unit 4 is connected between the electrical interface 1 and the secondary MCU unit 3;

[0084] The second level conversion unit 5 is connected between the main MCU unit 2 and the secondary MCU unit 3;

[0085] The TEC driver unit 6 is respectively connected to the main MCU unit 2 and the TEC unit 7;

[0086] The DCDC boost unit 8 is respectively connected to the TEC driver unit 6, the secondary MCU unit 3, and the voltage DAC unit 9;

[0087] The voltage DAC unit 9 is respectively connected to the secondary MCU unit 3 and the optical computing unit 10.

[0088] It should be noted that this embodiment adopts an optoelectronic heterogeneous computing architecture to provide a hardware circuit design for DAC control and temperature control for the parallel operation of the analog optical matrix.

[0089] This embodiment adopts a scheme of two main and secondary MCUs, which work independently of each other and can have different operating voltages. The main MCU unit 2 is responsible for the control of the unit circuits of the entire module, such as the TEC adjustment circuit. The secondary MCU unit 3 only supports the control of the voltage DAC unit 9 to achieve the processing control of the optical computing chip by the acceleration card.

[0090] Specifically, the main MCU unit 2 is connected to the electrical interface 1 through the IIC1 interface, the secondary MCU unit 3 is connected to the electrical interface 1 through the IIC2 interface, and the main MCU unit 2 is connected to the secondary MCU unit 3 through the IIC3 interface. The IIC1 interface and the IIC2 interface of the present invention can be the gold finger definitions of two independent QSFP28 or QSFP-DD packages. The IIC1 interface meets the communication interface protocol of the corresponding package module, while the IIC2 interface only realizes the function control of the computing chip.

[0091] If the AI acceleration card requires real-time adjustment of the DAC to implement optical matrix operations, it is necessary to communicate through the external IIC2 interface; if the AI acceleration card uses a constant-value DAC to implement optical matrix operations, only the internal master-slave IIC3 interface communication method of the module needs to be selected to complete data loading.

[0092] The main MCU unit 2 is powered by 3.3V, which solves the problem of controlling and adjusting the compatibility of the 5V TEC drive level and can effectively improve the power consumption capacity of the TEC chip J3.

[0093] Please refer to Figure 2 , in this embodiment, the main MCU unit 2 includes a main MCU chip U4;

[0094] The SCL0 pin and SDA0 pin of the main MCU chip U4 are connected to the electrical interface 1;

[0095] The SCL2 pin and SDA2 pin of the main MCU chip U4 are connected to the secondary MCU unit 3;

[0096] The DAC pin and IO pin of the main MCU chip U4 are connected to the TEC driver unit 6.

[0097] In this embodiment, as Figure 2 shown, the TEC driver unit 6 includes a TEC driver U5;

[0098] The IN2P pin of the TEC driver U5 is connected to the DAC pin of the main MCU chip U4;

[0099] The EN pin of the TEC driver U5 is connected to the IO pin of the main MCU chip U4 and grounded through the fourteenth resistor R14;

[0100] The LDR pin, SW pin and SFB pin of the TEC driver U5 are connected to the TEC unit 7;

[0101] The IN2N pin and OUT2 pin of the TEC driver U5 are connected.

[0102] Preferably, the TEC driver unit 6 further includes a temperature control sampling circuit;

[0103] The temperature control sampling circuit includes a thermistor Rt and an inverting proportional amplification sampling circuit;

[0104] The inverting proportional amplification sampling circuit is connected to the TEC driver U5;

[0105] One end of the thermistor Rt is connected to the inverting proportional amplification sampling circuit, and the other end is grounded.

[0106] Preferably, the TEC driver unit 6 further includes a seventh resistor R7 and an eighth resistor R8;

[0107] The inverting proportional amplification sampling circuit includes a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11;

[0108] One end of the ninth resistor R9 is connected to the VREF pin of the TEC driver U5, and the other end is connected to one end of the tenth resistor R10;

[0109] The other end of the tenth resistor R10 is connected to the thermistor Rt;

[0110] The IN1N pin of the TEC driver U5 is connected between the ninth resistor R9 and the tenth resistor R10;

[0111] One end of the eleventh resistor R11 is connected to the IN1N pin of the TEC driver U5, and the other end is connected to the OUT1 pin of the TEC driver U5;

[0112] The ADC1 pin of the main MCU chip U4 is connected to the OUT1 pin of the TEC driver U5;

[0113] One end of the seventh resistor R7 is connected to the VREF pin of the TEC driver U5, and the other end is connected to one end of the eighth resistor R8;

[0114] The other end of the eighth resistor R8 is grounded.

[0115] In this embodiment, as Figure 2 shown, the TEC unit 7 includes a TEC chip J3 and a first inductor L1;

[0116] The negative pole of the TEC chip J3 is connected to the LDR pin of the TEC driver U5;

[0117] The positive pole of the TEC chip J3 is connected to the SFB pin of the TEC driver U5;

[0118] The first inductor L1 is connected between the SW pin and the SFB pin of the TEC driver U5.

[0119] Please refer to Figure 3 , in this embodiment, the secondary MCU unit 3 includes a secondary MCU chip U1;

[0120] The SCL1 pin and the SDA1 pin of the secondary MCU chip U1 are connected to the electrical interface through the first level conversion unit 4;

[0121] The SCL2 pin and the SDA2 pin of the secondary MCU chip U1 are connected to the SCL2 pin and the SDA2 pin of the main MCU chip U4 through the second level conversion unit 5;

[0122] The SCK pin, the MISO pin, the MOSI pin and the IO pin of the secondary MCU chip U1 are connected to the voltage DAC unit 9.

[0123] In this embodiment, as Figure 3 shown, the first level conversion unit 4 includes a first MOS switch tube Q1, a second MOS switch tube Q2, a first resistor R1 and a fourth resistor R4;

[0124] The source of the first MOS switch tube Q1 is connected to the electrical interface 1, the drain of the first MOS switch tube Q1 is connected to the SDA1 pin of the secondary MCU chip U1, and the gate of the first MOS switch tube Q1 is connected to the DCDC boost unit 8;

[0125] One end of the first resistor R1 is connected between the drain of the first MOS switch tube Q1 and the SDA1 pin of the secondary MCU chip U1, and the other end is connected to the DCDC boost unit 8;

[0126] The source of the second MOS switch tube Q2 is connected to the electrical interface 1, the drain of the second MOS switch tube Q2 is connected to the SCL1 pin of the secondary MCU chip U1, and the gate of the second MOS switch tube Q2 is connected to the DCDC boost unit 8;

[0127] One end of the fourth resistor R4 is connected between the drain of the second MOS switch tube Q2 and the SCL1 pin of the secondary MCU chip U1, and the other end is connected to the DCDC boost unit 8;

[0128] The second level conversion unit 5 includes a third MOS switch tube Q3, a fourth MOS switch tube Q4, a second resistor R2, a third resistor R3, a fifth resistor R5 and a sixth resistor R6;

[0129] The source of the third MOS switch Q3 is connected to the electrical interface 1, the drain of the third MOS switch Q3 is connected to the SCL2 pin of the secondary MCU chip U1, and the gate of the third MOS switch Q3 is connected to the DCDC boost unit 8;

[0130] One end of the second resistor R2 is connected between the drain of the third MOS switch Q3 and the SCL2 pin of the secondary MCU chip U1, and the other end is connected to the DCDC boost unit 8;

[0131] The third resistor R3 is connected between the source and the gate of the third MOS switch Q3;

[0132] The source of the fourth MOS switch Q4 is connected to the electrical interface 1, the drain of the fourth MOS switch Q4 is connected to the SDA2 pin of the secondary MCU chip U1, and the gate of the fourth MOS switch Q4 is connected to the DCDC boost unit 8;

[0133] One end of the fifth resistor R5 is connected between the drain of the fourth MOS switch Q4 and the SDA2 pin of the secondary MCU chip U1, and the other end is connected to the DCDC boost unit 8;

[0134] The sixth resistor R6 is connected between the source and the gate of the fourth MOS switch Q4.

[0135] In this embodiment, as Figure 3 shown, the voltage DAC unit 9 includes a first voltage DAC chip U2 and a second voltage DAC chip U3;

[0136] The SDI pin, SDO pin and SCLK pin of the first voltage DAC chip U2 are respectively connected to the SCK pin, MISO pin and MOSI pin of the secondary MCU chip U1, the RESET pin, SYNC pin and LDAC pin of the first voltage DAC chip U2 are respectively connected to the IO1 pin, IO2 pin and IO3 pin of the secondary MCU chip U1, and the VOUT0 pin of the first voltage DAC chip U2 is connected to the optical computing unit 10;

[0137] The SDI pin, SDO pin and SCLK pin of the second voltage DAC chip U3 are respectively connected to the SCK pin, MISO pin and MOSI pin of the secondary MCU chip U1, the RESET pin, SYNC pin and LDAC pin of the second voltage DAC chip U3 are respectively connected to the IO4 pin, IO5 pin and IO6 pin of the secondary MCU chip U1, and the VOUT0 pin of the second voltage DAC chip U3 is connected to the optical computing unit 10.

[0138] In this embodiment, as Figure 3 shown, the optical computing unit 10 includes an optical computing chip J1;

[0139] The S1 pin of the optical computing chip J1 is connected to the VOUT0 pin of the first voltage DAC chip U2, and the S2 pin of the optical computing chip J1 is connected to the VOUT0 pin of the second voltage DAC chip U3.

[0140] Please refer to Figure 4 , in this embodiment, the DCDC boost unit 8 includes a DCDC boost chip U6, a twelfth resistor R12, and an RC delay circuit composed of a thirteenth resistor R13 and a first capacitor C1;

[0141] The VOUT pin of the DCDC boost chip U6 is respectively connected to the first resistor R1, the second resistor R2, the fourth resistor R4, and the fifth resistor R5;

[0142] The VIN pin of the DCDC boost chip U6 is respectively connected to the gates of the first MOS switch Q1, the second MOS switch Q2, the third MOS switch Q3, and the fourth MOS switch Q4;

[0143] The twelfth resistor R12 is connected between the VIN pin of the DCDC boost chip U6 and the VOUT0 pin of the first voltage DAC chip U2;

[0144] The first capacitor C1 is connected between the VIN pin of the DCDC boost chip U6 and the EN pin;

[0145] One end of the thirteenth resistor R13 is connected between the EN pin of the DCDC boost chip U6 and the first capacitor C1, and the other end is grounded.

[0146] In this embodiment, the main MCU chip U4 follows the IIC standard digital diagnostic monitoring protocol and the gold finger definition requirements of traditional optical modules. The working power supply 3.3V of the main MCU chip U4 is consistent with the power supply provided by the acceleration card. The IIC1 interface (SCL0 and SDA0) is connected to the communication interface of the external acceleration card, while the IIC3 interface (SCL2 and SDA2) is connected to the slave MCU chip U1 for master-slave communication after being output by the main MCU chip U4 and passing through a first level conversion.

[0147] The control logic of the bidirectional communication switches of the third MOS switch Q3 and the fourth MOS switch Q4 is as follows:

[0148] When the main MCU chip U4 sends a high level (1) to the secondary MCU chip U1 through the IIC3 interface, the third MOS switch Q3 or the fourth MOS switch Q4 is turned off, and at this time, the secondary MCU chip U1 receives a high level (1).

[0149] When the main MCU chip U4 sends a low level (0) to the secondary MCU chip U1 through the IIC3 interface, the third MOS switch Q3 or the fourth MOS switch Q4 is turned on, and at this time, the secondary MCU chip U1 receives a low level (0).

[0150] Conversely, when the secondary MCU chip U1 responds to the main MCU chip U4 through the IIC3 interface, the logic switch control still holds because the source and drain of the MOS switch can be interchanged.

[0151] The main MCU chip U4 can control whether the TEC driver U5 outputs voltage to the TEC chip J3 through the IO. The main MCU chip U4 sets the working target temperature of the TEC and then compares it in real time with the temperature voltage signal sampled by the ADC (Tx_temp). When the target temperature of the TEC is greater than or less than the real-time sampled temperature, the voltage output by the TEC driver U5 to both ends of the TEC chip J3 is adjusted through the DAC (SET_TEMP) at this time.

[0152] Since the software PID method of the main MCU chip U4 is adopted in this embodiment, the hardware adjustment PID circuit design of the TEC driver U5 is not adopted, and the IN2N pin and the OUT2 pin are directly shorted for the design of a voltage follower.

[0153] Since the maximum sampling voltage of the ADC of the main MCU chip U4 of the present invention is 2.4V (the internal reference voltage Vref of the main MCU), the inverting proportional amplification sampling circuit composed of the ninth resistor R9, the tenth resistor R10, and the eleventh resistor R11 needs to select an appropriate amplification factor to ensure that the output voltage range of the sampling voltage OUT1 (TX_temp) is 0 to 2.4V within the maximum temperature control range of the TEC.

[0154] The positive electrode of the TEC chip J3 is connected to the output terminal of the internal Buck circuit of the TEC driver U5, and the negative electrode of the TEC chip J3 is connected to the internal high and low state control switch of the TEC driver U5. When the negative electrode of the TEC chip J3 is at a low level (0V), the higher the positive voltage of the TEC chip J3, the greater the refrigeration power consumption of the TEC chip J3. Conversely, when the negative electrode of the TEC chip J3 is at a high level (VCC), the lower the negative voltage of the TEC, the greater the heating power consumption of the TEC chip J3.

[0155] The secondary MCU chip U1 provides multi-channel parallel DAC voltage control for the optical matrix arithmetic chip, and the power supply of the secondary MCU chip U1 supports operating modes of 5V or 3.3V, and the corresponding power supply matching operation can be selected in a timely manner according to the DAC level voltage requirement. Through the hardware RC delay circuit designed by the first capacitor C1 and the thirteenth resistor R13, the DCDC boost chip U6 is powered on to support soft-start protection. In addition, according to the requirement of load power consumption, the power supply voltage can be flexibly selected through the twelfth resistor R12.

[0156] The secondary MCU chip U1 uses SPI communication and supports multi-slave design. The slave voltage DAC (the first voltage DAC chip U2 or the second voltage DAC chip U3) for communication can be selected through chip select CS1 or CS2, and the output of the Vout voltage can also be controlled through EN1 or EN2.

[0157] It should be noted that, for the purpose of achieving greater power consumption, the twelfth resistor R12 or the DCDC boost unit 8 is removed for compatibility design, and the TEC driver unit 6, the secondary MCU unit 3, and the voltage DAC unit 9 are supported to select the power supply operating mode.

[0158] In this embodiment, considering the flexibility of wiring and space, a design of multiple separate multi-channel voltage DAC circuits is adopted (the number of DAC channels supported by a single component can be 4, 8, 16, 32, 40, etc.) to achieve the purpose of expanding the DAC output port.

[0159] Although terms such as electrical interface, main MCU unit, secondary MCU unit, first level conversion unit, second level conversion unit, TEC driver unit, TEC unit, DCDC boost unit, voltage DAC unit, and optical computing unit are used more in this embodiment, the possibility of using other terms is not excluded. Using these terms is only to more conveniently describe and explain the essence of the present invention; interpreting them as any additional limitation is contrary to the spirit of the present invention.

[0160] A multi-host communication and multi-voltage control drive circuit provided by an embodiment of the present invention can provide DAC control and temperature control for the parallel operation of an analog optical matrix by configuring an electrical interface, a main MCU unit, a secondary MCU unit, a first level conversion unit, a second level conversion unit, a TEC driver unit, a TEC unit, a DCDC boost unit, a voltage DAC unit, and an optical computing unit and making them cooperate with each other, and has high market promotion value.

[0161] So far, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A drive circuit that supports multi-host communication and multi-voltage control, characterized in that, It includes an electrical interface, a main MCU unit, a secondary MCU unit, a first level conversion unit, a second level conversion unit, a TEC driver unit, a TEC unit, a DCDC boost unit, a voltage DAC unit, and an optical computing unit; among them, The electrical interface is respectively connected to the main MCU unit and the secondary MCU unit; The first level conversion unit is connected between the electrical interface and the secondary MCU unit; The second level conversion unit is connected between the main MCU unit and the secondary MCU unit; The TEC driver unit is respectively connected to the main MCU unit and the TEC unit; The DCDC boost unit is respectively connected to the TEC driver unit, the secondary MCU unit, and the voltage DAC unit; The voltage DAC unit is respectively connected to the secondary MCU unit and the optical computing unit; The main MCU unit is responsible for the unit circuit control of the entire module; The secondary MCU unit only supports controlling the voltage DAC unit to achieve the processing control of the optical computing unit by the acceleration card.

2. The drive circuit that supports multi-host communication and multi-voltage control according to claim 1, characterized in that, The main MCU unit includes a main MCU chip U4; The SCL0 pin and SDA0 pin of the main MCU chip U4 are connected to the electrical interface; The SCL2 pin and SDA2 pin of the main MCU chip U4 are connected to the secondary MCU unit; The DAC pin and IO pin of the main MCU chip U4 are connected to the TEC driver unit.

3. The drive circuit that supports multi-host communication and multi-voltage control according to claim 2, characterized in that, The TEC driver unit includes a TEC driver U5; The IN2P pin of the TEC driver U5 is connected to the DAC pin of the main MCU chip U4; The EN pin of the TEC driver U5 is connected to the IO pin of the main MCU chip U4 and grounded through the fourteenth resistor R14; The LDR pin, SW pin, and SFB pin of the TEC driver U5 are connected to the TEC unit; The IN2N pin and OUT2 pin of the TEC driver U5 are connected.

4. The drive circuit that supports multi-host communication and multi-voltage control according to claim 3, characterized in that, The TEC driver unit also includes a temperature control sampling circuit; The temperature control sampling circuit includes a thermistor Rt and an inverting proportional amplification sampling circuit; The inverting proportional amplification sampling circuit is connected to the TEC driver U5; One end of the thermistor Rt is connected to the inverting proportional amplification sampling circuit, and the other end is grounded.

5. The drive circuit that supports multi-host communication and multi-voltage control according to claim 4, characterized in that, The TEC driver unit also includes a seventh resistor R7 and an eighth resistor R8; The inverting proportional amplification sampling circuit includes a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11; One end of the ninth resistor R9 is connected to the VREF pin of the TEC driver U5, and the other end is connected to one end of the tenth resistor R10; The other end of the tenth resistor R10 is connected to the thermistor Rt; The IN1N pin of the TEC driver U5 is connected between the ninth resistor R9 and the tenth resistor R10; One end of the eleventh resistor R11 is connected to the IN1N pin of the TEC driver U5, and the other end is connected to the OUT1 pin of the TEC driver U5; The ADC1 pin of the main MCU chip U4 is connected to the OUT1 pin of the TEC driver U5; One end of the seventh resistor R7 is connected to the VREF pin of the TEC driver U5, and the other end is connected to one end of the eighth resistor R8; The other end of the eighth resistor R8 is grounded.

6. The multi-host communication and multi-voltage control drive circuit according to claim 5, wherein The TEC unit includes a TEC chip J3 and a first inductor L1; The negative pole of the TEC chip J3 is connected to the LDR pin of the TEC driver U5; The positive pole of the TEC chip J3 is connected to the SFB pin of the TEC driver U5; The first inductor L1 is connected between the SW pin and the SFB pin of the TEC driver U5.

7. The multi-host communication and multi-voltage control drive circuit according to claim 6, wherein The secondary MCU unit includes a secondary MCU chip U1; The SCL1 pin and SDA1 pin of the secondary MCU chip U1 are connected to the electrical interface through the first level conversion unit; The SCL2 pin and SDA2 pin of the secondary MCU chip U1 are connected to the SCL2 pin and SDA2 pin of the main MCU chip U4 through the second level conversion unit; The SCK pin, MISO pin, MOSI pin and IO pin of the secondary MCU chip U1 are connected to the voltage DAC unit.

8. The multi-host communication and multi-voltage control drive circuit according to claim 7, wherein The first level conversion unit includes a first MOS switch tube Q1, a second MOS switch tube Q2, a first resistor R1 and a fourth resistor R4; The source electrode of the first MOS switch tube Q1 is connected to the electrical interface, the drain electrode of the first MOS switch tube Q1 is connected to the SDA1 pin of the secondary MCU chip U1, and the gate electrode of the first MOS switch tube Q1 is connected to the DCDC boost unit; One end of the first resistor R1 is connected between the drain electrode of the first MOS switch tube Q1 and the SDA1 pin of the secondary MCU chip U1, and the other end is connected to the DCDC boost unit; The source electrode of the second MOS switch tube Q2 is connected to the electrical interface, the drain electrode of the second MOS switch tube Q2 is connected to the SCL1 pin of the secondary MCU chip U1, and the gate electrode of the second MOS switch tube Q2 is connected to the DCDC boost unit; One end of the fourth resistor R4 is connected between the drain electrode of the second MOS switch tube Q2 and the SCL1 pin of the secondary MCU chip U1, and the other end is connected to the DCDC boost unit; The second level conversion unit includes a third MOS switch tube Q3, a fourth MOS switch tube Q4, a second resistor R2, a third resistor R3, a fifth resistor R5 and a sixth resistor R6; The source electrode of the third MOS switch tube Q3 is connected to the electrical interface, the drain electrode of the third MOS switch tube Q3 is connected to the SCL2 pin of the secondary MCU chip U1, and the gate electrode of the third MOS switch tube Q3 is connected to the DCDC boost unit; One end of the second resistor R2 is connected between the drain electrode of the third MOS switch tube Q3 and the SCL2 pin of the secondary MCU chip U1, and the other end is connected to the DCDC boost unit; The third resistor R3 is connected between the source and the gate of the third MOS switch Q3; The source of the fourth MOS switch Q4 is connected to the electrical interface, the drain of the fourth MOS switch Q4 is connected to the SDA2 pin of the secondary MCU chip U1, and the gate of the fourth MOS switch Q4 is connected to the DCDC boost unit; One end of the fifth resistor R5 is connected between the drain of the fourth MOS switch Q4 and the SDA2 pin of the secondary MCU chip U1, and the other end is connected to the DCDC boost unit; The sixth resistor R6 is connected between the source and the gate of the fourth MOS switch Q4.

9. The multi-host communication and multi-voltage control drive circuit according to claim 8, wherein The voltage DAC unit includes a first voltage DAC chip U2 and a second voltage DAC chip U3; The SDI pin, SDO pin, and SCLK pin of the first voltage DAC chip U2 are respectively connected to the SCK pin, MISO pin, and MOSI pin of the secondary MCU chip U1, the RESET pin, SYNC pin, and LDAC pin of the first voltage DAC chip U2 are respectively connected to the IO1 pin, IO2 pin, and IO3 pin of the secondary MCU chip U1, and the VOUT0 pin of the first voltage DAC chip U2 is connected to the optical computing unit; The SDI pin, SDO pin, and SCLK pin of the second voltage DAC chip U3 are respectively connected to the SCK pin, MISO pin, and MOSI pin of the secondary MCU chip U1, the RESET pin, SYNC pin, and LDAC pin of the second voltage DAC chip U3 are respectively connected to the IO4 pin, IO5 pin, and IO6 pin of the secondary MCU chip U1, and the VOUT0 pin of the second voltage DAC chip U3 is connected to the optical computing unit.

10. The multi-host communication and multi-voltage control drive circuit according to claim 9, wherein The optical computing unit includes an optical computing chip J1; The S1 pin of the optical computing chip J1 is connected to the VOUT0 pin of the first voltage DAC chip U2, and the S2 pin of the optical computing chip J1 is connected to the VOUT0 pin of the second voltage DAC chip U3; The DCDC boost unit includes a DCDC boost chip U6, a twelfth resistor R12, and an RC delay circuit composed of a thirteenth resistor R13 and a first capacitor C1; The VOUT pin of the DCDC boost chip U6 is respectively connected to the first resistor R1, the second resistor R2, the fourth resistor R4, and the fifth resistor R5; The VIN pin of the DCDC boost chip U6 is respectively connected to the gate of the first MOS switch Q1, the gate of the second MOS switch Q2, the gate of the third MOS switch Q3, and the gate of the fourth MOS switch Q4; The twelfth resistor R12 is connected between the VIN pin of the DCDC boost chip U6 and the VOUT0 pin of the first voltage DAC chip U2; The first capacitor C1 is connected between the VIN pin of the DCDC boost chip U6 and the EN pin; One end of the thirteenth resistor R13 is connected between the EN pin of the DCDC boost chip U6 and the first capacitor C1, and the other end is grounded.

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