Multiple bit in-memory inner product xor unit, xor vector, and method of operation

Abstract

Multi-bit in-memory inner product and XOR unit, XOR vector and operation method, including N parallel 1FeFET1R structures, input transistor, first inverter and second inverter, N is a natural number greater than 1, the 1FeFET1R structure includes an electrically connected FeFET and a resistor, the resistor of each 1FeFET1R structure is electrically connected with the input transistor, the gate of the input transistor is electrically connected with the gate of the FeFET in one of the 1FeFET1R structures through the first inverter, and the gate of the FeFET in the 1FeFET1R structure is electrically connected with the gate of the FeFET in another 1FeFET1R structure through the second inverter. The application first proposes a unit based on a nonvolatile memory device and simultaneously supporting multi-bit in-memory inner product and XOR, and a vector thereof, which performs better in search energy consumption, search delay and area.

Description

Technical Field

[0001] This invention relates to the fields of storage, computing, and circuits, and specifically to a multi-bit memory inner product, i.e., an XOR unit, an XOR vector, and an operation method. Background Technology

[0002] In the context of massive data-intensive computation in artificial intelligence, various binary neural networks (BNNs) and high-dimensional vector computing (HDC) have been proven to be highly efficient in various practical scenarios such as object tracking, voice recognition, and image clustering. Since the separation of computing and storage units in traditional von Neumann computer architectures leads to high latency and energy consumption, replacing traditional von Neumann computer architectures with in-memory computing architectures has become a research hotspot. In-memory computing units composed of various novel non-volatile devices can perform different logical operations; for example, a single ferroelectric transistor can perform an AND operation between binary vectors.

[0003] However, in real-world applications, binary vectors cannot meet the demands of data-intensive computational scenarios; multi-bit inner product computation units can be more widely applied in artificial intelligence scenarios such as convolutional neural networks. Multi-bit in-memory inner product units based on traditional SRAM have been widely proposed in recent years, but they still have many shortcomings in terms of latency, power consumption, area, and scalability. Furthermore, a multi-bit in-memory inner product architecture based on novel non-volatile memory devices, namely XOR, has not yet been proposed. At the same time, while implementing multi-bit inner products, practical scenarios such as binary convolutional neural networks still require XOR functionality, and Hamming code distance itself is a bitwise XOR operation. Therefore, this invention proposes an in-memory computation unit that is applicable to both multi-bit vector inner products and XOR functionality. Summary of the Invention

[0004] The purpose of this invention is to propose a technical solution for a multi-bit memory inner product, namely an XOR unit and its XOR vector. It is the first to propose an implementation method based on FeFET, and the energy consumption, search delay, area and other indicators are improved compared with the existing work.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] A multi-bit memory inner product (XOR) unit includes N parallel 1FeFET1R structures, an input transistor, a first inverter, and a second inverter, where N is a natural number greater than 1. Each 1FeFET1R structure includes an electrically connected FeFET and a resistor. The resistor in each 1FeFET1R structure is electrically connected to the input transistor. The gate of the input transistor is electrically connected to the gate of the FeFET in one of the 1FeFET1R structures through the first inverter. The gate of the FeFET in the first 1FeFET1R structure is electrically connected to the gate of the FeFET in another 1FeFET1R structure through the second inverter.

[0007] Furthermore, the resistance values ​​in each 1FeFET1R structure are different, forming a series of output currents that are a series of binary 2... N-1 ,2 N-2 ,…,2 1 ,2 0 Storage unit.

[0008] Furthermore, in the 1FeFET1R structure, the resistor is electrically connected to the drain or source of the FeFET.

[0009] Furthermore, the input transistor operates in the linear region, which maps the weights of the vector elements to voltages and inputs them to the gate of the corresponding FeFET.

[0010] Furthermore, the first inverter is used to input the complementary values ​​of the vector elements.

[0011] Furthermore, the second inverter is used to store complementary values ​​in two corresponding FeFETs.

[0012] The present invention also provides a multi-bit in-memory product XOR vector, comprising M multi-bit in-memory product XOR units as described above, wherein the M multi-bit in-memory product XOR units are connected in parallel.

[0013] The present invention also provides a method for operating a multi-bit memory inner product, i.e., an XOR vector, as described above, comprising:

[0014] Each element of the S1 storage vector is first stored in a multi-bit internal product (XOR) unit. Specifically, each element is binary. Based on the binary value of the input element, if it is '1', a high voltage is applied to the corresponding FeFET gate to store '1'; if it is '0', a low voltage is applied to the corresponding FeFET gate to store '0'. Simultaneously, the value is stored in another XOR 1FeFET1R structure via an inverter.

[0015] After the vector elements of the S2-stored vector are stored in the multi-bit memory's inner product (XOR unit), when the query vector arrives, the following operations are performed simultaneously:

[0016] S2.1 The vector elements of the query vector are applied in the form of voltage to the gate of the input transistor in the multi-bit memory inner product, i.e., XOR unit; at the same time, the vector elements of the query vector correspond to the 1FeFET1R structure through the first inverter.

[0017] S2.2 To implement the multi-bit inner product function, each FeFET's gate is simultaneously input with a high voltage. Utilizing the inherent AND capability of the FeFET, when the stored value is '0', the output is '0'; when the stored value is '1', the output is '1'.

[0018] S2.3 For implementing multi-bit functionality, both inverters are in the off state; for implementing XOR functionality, both inverters are connected to the power supply and are in the working state, and the gates of the first N-1 FeFETs are simultaneously input with a low voltage, i.e., '0' is stored.

[0019] The beneficial effects of this invention are as follows:

[0020] This invention is the first to propose a cell and its vector based on non-volatile memory devices that simultaneously supports multi-bit in-memory product and XOR, which outperforms the other two major indicators: search energy consumption, search latency, and area. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of an N=4-bit multi-bit memory inner product, i.e., an XOR unit, applied to a cosine search architecture;

[0022] Figure 2 This is a circuit diagram of the invention, specifically a circuit diagram of a single N=4-bit multi-bit memory inner product, i.e., an XOR unit.

[0023] Figure 3 (a) is a schematic diagram showing the results of storing the inner product and XOR unit values ​​of a single multi-bit memory from 0000 to 1111 when N=4 bits.

[0024] Figure 3 (b) is a schematic diagram of the result of 100 Monte Carlo iterations of the inner product and XOR unit storage value of a single multi-bit memory with N=4 bits, from 0000 to 1111.

[0025] Figure 4 (a) and (b) are schematic diagrams of N=4 / N=6 expansion, respectively, which analyze the scalability of the inner product, i.e., the XOR unit, in multi-bit memory. Figure 4 (b) demonstrates that even up to N=6, in the worst case, only one bit operation will be indistinguishable.

[0026] Figure 5This is a schematic diagram showing the result of the reduction in the resistance value of the inner product (i.e., the XOR cell) of a single multi-bit memory when N=4 bits.

[0027] Figure 6 Based on Figure 1 A schematic diagram illustrating the application of the inner product and XOR unit in multi-bit memory. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0029] Please see Figure 1-6 A multi-bit in-memory product (XOR) unit includes N parallel 1FeFET1R structures 1, an input transistor 2, a first inverter 3, and a second inverter 4, where N is a natural number greater than 1. Each 1FeFET1R structure 1 includes a FeFET100 and a resistor 101. The resistor 101 is electrically connected to the drain or source of the FeFET100. The resistor 101 of each 1FeFET1R structure 1 is electrically connected to the input transistor 2. The gate of the input transistor 2 is electrically connected to the gate of the FeFET100 in one of the 1FeFET1R structures 1 through the first inverter 3. The gate of the FeFET100 in the 1FeFET1R structure 1 is electrically connected to the gate of the FeFET100 in another 1FeFET1R structure 1 through the second inverter 4.

[0030] For operation in bit-in-memory inner product mode, to form an N+1 bit inner product unit, it is only necessary to add a 1FeFET1R structure 1 to the N-bit structure. The resistor 101 of the 1FeFET1R structure 1 needs to have 2 N Double or 2 -1 The saturation drain-source current is times that of the 1FeFET1R structure 1. Therefore, the resistance value of resistor 101 in each 1FeFET1R structure 1 in this invention is different, forming a series of output currents as a series of binary 2 N-1 ,2 N-2 ,…,2 1 ,2 0 Storage unit.

[0031] The input transistor 2 operates in the linear region, which maps the weights of the vector elements to voltages and inputs them to the gate of the corresponding FeFET100.

[0032] The first inverter 3 is used to input complementary values.

[0033] The second inverter 4 is used to store complementary values ​​in two corresponding FeFET100.

[0034] Please see Figure 2The present invention also provides a multi-bit in-memory product XOR vector, comprising M multi-bit in-memory product XOR units C as described above, wherein the M multi-bit in-memory product XOR units C are connected in parallel to form a vector having M vector elements.

[0035] A method for operating a multi-bit memory inner product, i.e., an XOR vector, as described above, includes:

[0036] S1 stores each element of the vector first in a multi-bit internal product (XOR) unit. Specifically, each element is stored as binary. Taking an N=4-bit internal product unit as an example, W=w3w2w1w0, where the high-order bit is w3, representing 2. 3 The lower bit is w0, indicating 2. 0 Based on the binary value of the input vector element, if it is '1', a high voltage is applied to the corresponding FeFET gate to store '1'; if it is '0', a low voltage is applied to the corresponding FeFET gate to store '0'. Simultaneously, the value is stored in another XOR 1FeFET1R structure via an inverter.

[0037] After the vector elements of the S2-stored vector are stored in the multi-bit memory's inner product (XOR unit), when the query vector arrives, the following operations are performed simultaneously:

[0038] S2.1 The vector elements of the query vector are applied in the form of voltage to the gate of the input transistor in the multi-bit memory inner product, i.e., XOR unit; at the same time, the vector elements of the query vector correspond to the 1FeFET1R structure through the first inverter.

[0039] S2.2 To implement the multi-bit inner product function, each FeFET's gate is simultaneously input with a high voltage. Taking advantage of the FeFET's ability to perform an AND operation, when the stored value is '0', the output is '0'; when the stored value is '1', the output is '1'.

[0040] S2.3 For implementing multi-bit functionality, both inverters are in the off state; for implementing XOR functionality, both inverters are connected to power and are in the working state, and the first N-1 bits (i.e., ...) are... Figure 2 The gate of the FeFET from V[3] to V[1] is simultaneously input with a low voltage, that is, '0' is stored, so that only the rightmost two 1FeFET1R cells are working.

[0041] Unit application and architecture simulation operation process description

[0042] The input to the cosine calculation circuit is a vector composed of inner products and XOR units in multi-bit memory; for example... Figure 1As shown, taking N=4 bits as an example, the transistors of each memory cell in the memory array are connected to form a vector containing M vector elements. This inner product result is copied via a current mirror and used as the input to the cosine calculation circuit. Figure 1 The storage array on the right is used to calculate the L2 norm of each cosine value, which is the denominator of the cosine expression. The output of the cosine calculation circuit then passes through the Winner-Take-All circuit to find the storage vector with the maximum cosine distance to the query vector. The expression for the cosine calculation circuit is:

[0043] The specific operation process of the inner product and XOR unit in multi-bit memory is as follows:

[0044] 1. Before the search begins, input the storage vector to each multi-bit internal product (XOR) unit; taking N=4 bits as an example, write w3, w2, w1, and w0 respectively through V[3]~V[0] of each multi-bit internal product (XOR) unit; at the same time, another 1FeFET1R is stored through the inverter. '0' is written using a -4V voltage pulse, and '1' is written using a +4V voltage pulse. After writing the vector elements, the search process can begin.

[0045] 2.1 During the search, when the cell is working in multi-bit in-memory inner product mode, each 1FeFET1R implementing multi-bit in-memory inner product, i.e. V[3]~V[0]( Figure 2 ), written with a +4V voltage pulse, i.e., writing '1'; simultaneously, the input is input through the gate of the input transistor ( Figure 2 The voltage is selected between 0 and 1.2V based on the magnitude of the input vector element values.

[0046] 2.2 During the search, when the cell is working in XOR mode, the first N-1 1FeFET1R that implements the multi-bit in-memory inner product, i.e. V[3]~V[1]( Figure 2 Write '0' using a -4V voltage pulse.

[0047] The functions and effects of this invention are further illustrated and demonstrated through the following simulation experiments:

[0048] 1. Simulation conditions

[0049] The experiment used physical circuit-compatible SPECTRE and SPICE models to simulate a memory array consisting of 1FeFET1R memory cells, where the FeFET was based on the Preisach model. This model enables efficient design and analysis and has been widely used in FeFET circuit design. The PTM45-HP was used as the simulation model for the remaining transistors.

[0050] Simulation architecture with Figure 1 As shown. Figure 1 One application of artificial intelligence is nearest neighbor search based on cosine search. The principle is to find the storage vector that is closest to the input vector in terms of cosine distance. Figure 1 The storage unit (denoted by C) is the multi-bit memory inner product, i.e., XOR unit, proposed in this invention; wherein Figure 2 It is a multi-bit memory inner product, or XOR unit, represented by N=4 bits.

[0051] 2. Simulation Results

[0052] (1) According to Figure 2 The schematic diagram of the multi-bit memory inner product and XOR unit shows that when the current is in the nanoampere level, SPECTRE simulation shows that R0:R1:R2:R3 is 8:4:2:1.

[0053] (2) Figure 3 (a) The horizontal axis represents the voltage at the gate of the transistor in the multi-bit memory's inner product (XOR) cell, which is a continuous value. The curve from bottom to top represents the stored values ​​from 0000 to 1111; Figure 3 (b) The results obtained after considering FeFET process errors (extracted from non-patent literature 1T. Solimane et al., “Ultra-Low Power Flexible Precision FeFET Based Analog In-Memory Computing”, IEEE IEDM, 2020.), large resistance errors (extracted from non-patent literature 2D. Saito et al., “Analog In-memory Computing in FeFET-based 1T1R Array for Edge AI Applications”, IEEE Symposium on VLSI Circuits, 2021) and transistor errors, i.e., the domain default of 10% magnitude error and 10% threshold voltage error. Figure 3 (a) The horizontal axis represents the voltage at the gate of the transistor in the inner product (XOR) cell of the multi-bit memory. The curve from bottom to top represents the stored value 0001(1). (10) ), 0011(3 (10) ), 0101(5 (10) ), 0111(7 (10) ), 1001(9 (10) ),1011(11 (10) ), 1101(13 (10) ), 1111(15 (10) The results show that the inner product results of this invention are highly accurate, with a difference of more than 2 between inner product results and a sufficiently large range of inner product results (input greater than 0.101 (5)).(10) (The voltage is approximately 0.5V), and the operation does not overlap.

[0054] (3) Energy consumption and delay:

[0055] Our results are compared with those proposed in non-patent literature 3 (M. Ali et al., “IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array”, TCAS-I, 2020.) based on SRAM multi-bit in-memory inner product and XOR unit. Figure 6 By expanding the number of vectors and the vector dimension respectively, this invention obtained more than 10 4 The power consumption per multi-bit memory inner product (XOR unit) is reduced by a factor of 1, and the output latency is reduced by a factor of 4.67.

[0056] (4) Area consumed:

[0057] The area consumption of this invention is significantly reduced compared to the aforementioned non-patent document 3, mainly because it utilizes a novel non-volatile memory device, FeFET, and is simpler in design than conventional SRAM. For a single multi-bit in-memory product (XOR) cell, this invention reduces the area by 488 times compared to the aforementioned non-patent document 3 (SRAM 64.9 μm). 2 / cell, 0.133μm in this invention 2 / cell).

[0058] (5) Scalability:

[0059] Figure 4 Extending the N=4-bit multi-bit memory inner product (XOR) unit to N=6 bits demonstrates that in the worst case, only operations involving 1s are inaccurate; specifically, for N=6 units, simulation results show that 000111(7 (10) ) and 001000 (8 (10) The same current will occur.

[0060] Figure 5 The invention demonstrates that reducing the resistance of the 1FeFET1R increases the off-current, thereby increasing the current difference flowing out of each branch in the multi-bit memory inner product (XOR cell); it shows that the scalability of the invention is further enhanced in applications where current limiting is not required, such as Hamming calculations.

[0061] The above embodiments are used to explain and illustrate the present invention, but not to limit the present invention. Any modifications and changes made to the present invention within the spirit and scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A method of operating a multi-bit in-memory inner product XNOR vector unit, the method comprising: The multi-bit in-memory inner product XOR vector unit comprises M multi-bit in-memory inner product XOR units in parallel, each multi-bit in-memory inner product XOR unit comprising N 1FeFET1R structures, an input transistor, a first inverter and a second inverter in parallel, N being a natural number greater than 1, each 1FeFET1R structure comprising an FeFET and a resistor connected in series, the resistor of each 1FeFET1R structure being connected to the input transistor, the gate of the input transistor being connected to the gate of the FeFET of one of the 1FeFET1R structures through the first inverter, and the gate of the FeFET of the 1FeFET1R structure being connected to the gate of the FeFET of the other 1FeFET1R structure through the second inverter; the resistors of each 1FeFET1R structure are different, forming a series of output currents as a series of binary 2 N-1 ,2 N-2 ,...,2 1 ,2 0 memory cells; the resistor of the 1FeFET1R structure is connected to the drain or source of the FeFET; the input transistor operates in the linear region, mapping the weight of the vector element into a voltage and inputting the voltage to the gate of the corresponding FeFET; The first inverter is used for inputting complementary values of vector elements; and the second inverter is used for storing the complementary values into two corresponding FeFETs. The operation method comprises the steps of: S1 each vector element of the stored vector is first stored in the multi-bit storage on-chip inner product XOR unit, the specific storage method is: each vector element of the stored vector is binary, according to the binary value of the vector element to be input, if it is '1', a high voltage is input at the corresponding FeFET gate to make the FeFET store '1'; if it is '0', a low voltage is input at the corresponding FeFET gate to make the FeFET store '0', at the same time, the other XOR 1FeFET1R structure is stored through the second inverter , w0 is the low bit of the multi-bit storage on-chip inner product XOR unit, representing 2 0 ; S2: when a query vector arrives, the following operations are simultaneously performed after the vector elements of the query vector are stored into the multi-bit in-memory inner product XOR unit: S2.1: the vector elements of the query vector are applied to the gates of input transistors in the multi-bit in-memory inner product XOR unit in the form of voltage; meanwhile, the vector elements of the query vector pass through the first inverter corresponding to the 1FeFET1R structure; S2.2: for realizing the multi-bit inner product function, the gates of each FeFET are simultaneously inputted with high voltage, and the "AND" feature of the FeFET itself is utilized, so that when the storage value is '0', the output is '0'; and when the storage value is '1', the output is '1'; S2.3: for realizing the multi-bit function, the two inverters are in the off state; for realizing the XOR function, the two inverters are connected to the power supply and are in the working state, and the gates of the first N-1 FeFETs are simultaneously inputted with low voltage, i.e. '0' is stored.

Images