Semiconductor memory devices
By dividing the memory cell array into multiple regions and employing a specific voltage control strategy, the problem of low readout time efficiency in semiconductor memory devices is solved, resulting in faster readout time and reduced noise interference.
CN114898793BActive Publication Date: 2026-05-26KIOXIA CORP
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2017-07-27
- Publication Date
- 2026-05-26
Smart Images
Figure CN114898793B_ABST
Abstract
Embodiments of the present invention provide a semiconductor memory device intended to shorten readout time. The semiconductor memory device includes: a first memory cell (MT) electrically connected to a first bit line (BL) and a first word line (WL); a second memory cell (MT) electrically connected to a second bit line (BL) and the first word line; and a first circuit (42) applying a voltage to the first word line. During readout of the first memory cell, the first circuit supplies a first voltage (VA) to the first word line, and during readout of the second memory cell, supplies a second voltage (VK1) greater than the first voltage to the first word line.
Need to check novelty before this filing date? Find Prior Art