Z-type MEMS double-layer solenoid inductor double-layer coil and integrated preparation method

Abstract

A Z-shaped MEMS double-layer solenoid inductor double-layer coil and its integrated preparation method and inductor element, including a double-layer coil with inner and outer layers and a substrate; the double-layer coil is a MEMS double-layer solenoid inductor double-layer coil with a silicon base or a cast flexible substrate as the base substrate, which expands the existing single-layer MEMS solenoid inductor coil into a double layer, greatly expanding the dimension of the MEMS inductor coil, and making new breakthroughs in improving the inductance value and quality factor. Compared with the traditional C-shaped winding method, the capacitance effect of the Z-shaped winding at high frequency will be well suppressed, so that its resonant frequency can be further improved, so that it can be used in some RF MEMS applications. The use of a pure MEMS preparation method can improve the processing efficiency and reduce the production cost of a single-chip coil. At the same time, the use of the MEMS process method makes it compatible with IC technology, so that it has better IC compatibility in packaging applications.

Description

Technical Field

[0001] The invention discloses an inductor coil, and in particular relates to a Z-shaped MEMS double-layer solenoid inductor double-layer coil and an integrated preparation method thereof, as well as an inductor element. Background Art

[0002] Nuclear magnetic resonance (NMR) technology is a non-destructive testing technology that uses an external magnetic field to detect the difference in the nuclear signals at different positions of the sample to analyze the content and distribution of a specified substance in the sample. With the increasing requirements for sensitivity and accuracy, the use of traditional winding coils has gradually failed to meet existing requirements due to inherent defects such as winding errors and the inability to control the distance between windings. In addition, as the requirements for miniaturization and integration of electromagnetic devices with inductor windings as core components, such as fluxgate sensors, micro pumps, micro motors, micro energy harvesters, micro transformers, micro isolators, etc., are increasing, the demand for smaller inductor coils with higher quality factors and less heat generation is increasing, and the design of new MEMS coils is imminent.

[0003] MEMS coils processed using micro-electro-mechanical system (MEMS) technology, optical lithography technology, deep reactive ion etching (DRIE) technology, silicon direct bonding (SDB) technology and other MEMS technologies can overcome the inherent defects of winding errors of hand-wound coils.

[0004] Chinese patent application number CN202011454522.0 proposes a MEMS three-axis energy harvester based on the principle of electromagnetic induction and designed with a MEMS planar rectangular inductor coil. It adopts a planar folded inductor arrangement and uses it as a core device for converting vibration energy into electrical energy. It is characterized by the use of several coils that intersect and swirl vertically and horizontally. All coil windings are in the same plane, and there is a connecting wire extending from the plane into the bottom surface in the middle to connect the inner and outer circles of the coil. The use of a planar rectangular or circular MEMS inductor coil is a commonly used MEMS coil at present, with a simple process and low cost.

[0005] Chinese patent application number CN201410335299.6 proposes a probe based on the integration of gallium solenoid coil and glass microfluidic channel and its preparation method. The coil used in the invention has a glass substrate mainly composed of an upper coil slot, a number of middle through holes, and a lower coil slot. The layers of substrate are aligned and assembled by a bonding process, and the metal winding is cast from gallium with a lower melting point. This type of solenoid coil can well control the spacing between different turns of the coil, and has an improved inductance value compared to a planar coil.

[0006] However, the above prior art has the following defects:

[0007] 1) The main disadvantage of a planar rectangular or circular coil designed with a planar concept is severe magnetic leakage. It is also difficult to deploy a magnetic core to increase the magnetic flux in the coil during use. Although its manufacturing process is simple, it is difficult to achieve good results in applications such as NMR technology, micro fluxgate sensors, and micromotors that require relatively high magnetic properties.

[0008] 2) Although the three-dimensional coil with solenoid design solves part of the magnetic leakage problem, its design concept makes it difficult to make a traditional winding coil multi-layer structure, which limits the increase of its inductance value per unit volume. If you want to increase its inductance value, you must change the width and number of turns of the single-turn coil, which increases the volume of the coil and makes it impossible to achieve a higher inductance density. The development of double-layer and multi-layer coil technology is the general trend.

[0009] 3) Using low melting point metal as the body of the coil and using liquid metal casting method makes its current carrying capacity not too high. In the design of core inductance of power MEMS devices such as micro transformers, micro motors, micro isolators, etc., heat generation must be considered. The thermal effect of current will melt metals with low melting points such as gallium and aluminum, making the coil ineffective. The solution using glass substrate also further limits the temperature at which it can be cast due to the melting point of glass. If the method of electroplating metal is used, the above shortcomings can be well solved. Summary of the invention

[0010] In order to solve the deficiencies in the prior art, the present invention discloses a MEMS double-layer solenoid inductor coil and a preparation method thereof, and the technical solution thereof is as follows:

[0011] The Z-shaped MEMS double-layer solenoid inductor double-layer coil comprises an inner and outer double-layer coil and a substrate; the characteristics are as follows: a four-layer substrate is used as the double-layer coil body support; the double-layer coil is composed of an inner coil and an outer coil, the outer coil is electrically connected through an outer through hole made by a MEMS process on the four-layer substrate and a groove made by a MEMS process on the outer substrate; the inner coil is electrically connected through an inner through hole on the inner substrate and a groove made by a MEMS process; the inner and outer coils are electrically connected through a C-shaped groove on the inner substrate; the above-mentioned groove and hole are the coil body mold, and the coil entity is made by a through-hole plating (TSV) process; the double-layer solenoid coil is Z-shaped in the coil wire arrangement, with the inner coil as the wire starting point, that is, the inner layer last turn is electrically connected to the outer layer first turn; at the same time, there are double pads on the outer substrate to achieve electrical connection with the PCB circuit board; soft magnetic materials are encapsulated in batches using MEMS technology in the two inner substrates, the soft magnetic materials are located in the innermost layer of the double-layer coil, and the whole is wrapped by the double-layer coil.

[0012] The present invention also discloses a method for preparing a Z-shaped MEMS double-layer solenoid inductor double-layer coil, comprising the above-mentioned MEMS double-layer solenoid inductor double-layer coil, which is characterized by comprising the following steps:

[0013] Step 1, making the inner layer upper and lower substrates;

[0014] Step 2, making the magnetic core;

[0015] Step 3, bonding the first and second wafers;

[0016] Step 4, electroplating thinning of the inner coil;

[0017] Step 5, making the outer upper and lower substrates;

[0018] Step 6: The outer coil is thinned by electroplating to complete the preparation of the double-layer coil.

[0019] The present invention also discloses an inductor element, which is characterized by comprising an inductor coil prepared by the above-mentioned Z-type MEMS double-layer solenoid inductor double-layer coil preparation method.

[0020] Beneficial Effects

[0021] Expanding the existing single-layer MEMS solenoid inductor coil to a double-layer greatly expands the dimension of the MEMS inductor coil, further improves its space utilization, and makes new breakthroughs in improving inductance value and quality factor.

[0022] Compared with the traditional C-type winding, the Z-type winding can suppress the capacitance effect at high frequencies, so that the resonant frequency can be further increased, so that it can be used in some RF MEMS applications, such as high-frequency transformers, NFC coils, etc. Compared with the progressive winding, it can achieve more coil turns under the same volume of component winding, thereby greatly improving the inductance value at low frequencies, making it have greater potential to become a higher-performance low-frequency power device (micropump, micromotor).

[0023] The preparation method of pure Z-type MEMS can improve the processing efficiency and reduce the production cost of single-chip coils. At the same time, the MEMS process method can make it compatible with IC technology, so that it has better IC compatibility in packaging applications. Compared with glass substrates, the heat dissipation effect of using semiconductor materials as its substrate will be significantly enhanced. For MEMS power devices, the problem of heat accumulation can be well solved by integrating with micro-semiconductor heat sinks. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of a Z-shaped double-layer coil substrate of the present invention;

[0025] Figure 2 It is a schematic diagram of a Z-shaped double-layer coil of the present invention;

[0026] Figure 3 This is a schematic diagram of the substrate after step 1 and process 4) of the present invention;

[0027] Figure 4 Schematic diagram of the inner layer upper and lower substrates after step 1 process 7) of the present invention;

[0028] Figure 5 Schematic diagram of the inner layer upper and lower substrates after step 1 process 9) of the present invention;

[0029] Figure 6 This is a schematic diagram of the inner layer upper substrate after step 1 and process 12 of the present invention;

[0030] Figure 7 Schematic diagram of the inner lower substrate after step 1 and process 13) of the present invention;

[0031] Figure 8 This is a schematic diagram of the inner layer upper substrate after step 2 process 2) of the present invention;

[0032] Fig. 9 This is a schematic diagram of the inner layer upper substrate after step 2 and process 3) of the present invention;

[0033] Fig.10 Schematic diagram of the inner layer upper and lower substrates after step 2 process 6) of the present invention;

[0034] Fig.11 This is a schematic diagram of the entire inner substrate after step 3 (process 3) of the present invention;

[0035] Fig.12 This is a schematic diagram of the overall inner substrate after step 3 and process 4 of the present invention;

[0036] Fig.13 This is an overall schematic diagram of the wafer substrate after step 4 process 1) of the present invention;

[0037] Fig.14 This is an overall schematic diagram of the wafer substrate after step 4 process 2) of the present invention;

[0038] Fig.15 This is an overall schematic diagram of the wafer substrate after step 4 (process 4) of the present invention;

[0039] Fig.16 This is a schematic diagram of the whole wafer after step 4 and process 5 of the present invention;

[0040] Fig.17 This is a schematic diagram of the entire wafer after step 5 process 3) of the present invention;

[0041] Fig.18 It is a schematic diagram of the whole wafer after step 5 process 5) of the present invention;

[0042] Fig.19 It is a schematic diagram of the whole wafer after step 6 process 5) of the present invention. DETAILED DESCRIPTION

[0043] The Z-shaped MEMS double-layer solenoid inductor double-layer coil comprises an inner and outer double-layer coil and a substrate; the characteristics are as follows: a four-layer substrate is used as the double-layer coil body support; the double-layer coil is composed of an inner coil and an outer coil, the outer coil is electrically connected through an outer through hole made by a MEMS process on the four-layer substrate and a groove made by a MEMS process on the outer substrate; the inner coil is electrically connected through an inner through hole on the inner substrate and a groove made by a MEMS process; the inner and outer coils are electrically connected through a C-shaped groove on the inner substrate; the above-mentioned groove and hole are the coil body mold, and the coil entity is made by a through-hole plating (TSV) process; the double-layer solenoid coil is Z-shaped in the coil wire arrangement, with the inner coil as the wire starting point, that is, the inner layer last turn is electrically connected to the outer layer first turn; at the same time, there are double pads on the outer substrate to achieve electrical connection with the PCB circuit board; soft magnetic materials are encapsulated in batches using MEMS technology in the two inner substrates, the soft magnetic materials are located in the innermost layer of the double-layer coil, and the whole is wrapped by the double-layer coil.

[0044] The Z-shaped double-layer coil of the present invention comprises two layers of coils, inner and outer, and its substrate is as follows: Figure 1 As shown, there are four layers of substrates, which are respectively an outer layer lower substrate (10), an inner layer lower substrate (20), an inner layer upper substrate (30), and an outer layer upper substrate (40) from bottom to top. The outer layer upper coil slot (41) located on the outer layer upper substrate is connected to the outer layer lower coil slot (12) located on the outer layer lower substrate (10) through a through hole (42) located on the outer layer upper substrate (40), an outer layer through hole (32) located on the inner layer upper substrate (30), an outer layer through hole (24) located on the inner layer lower substrate (20), and a through hole (11) located on the outer layer lower substrate (10). The inner layer upper coil slot (31) located on the inner layer upper substrate (30) is connected to the inner layer lower coil slot (23) located on the inner layer lower substrate (20) through an inner layer through hole (34) located on the inner layer upper substrate (30) and an inner layer through hole (22) located on the inner layer lower substrate (20). The inner layer and the outer layer of the double-layer coil are connected through a long coil slot (35) located on the inner layer upper substrate (30) and a through hole located on the outer layer upper substrate (40). The upper magnetic core slot (33) located on the inner layer upper substrate (39) and the lower magnetic core slot (21) located on the inner layer lower substrate (20) are opposite to each other and together form the magnetic core slot of the double-layer coil. The outer layer lower substrate (10), the inner layer lower substrate (20), the inner layer upper substrate (30), and the outer layer upper substrate (40) correspond to each other in position on the through hole.

[0045] The Z-shaped double-layer coil entity of the present invention is as follows after processing is completed: Figure 2 As shown, it consists of two layers of inner and outer windings, and the starting point of the outer winding is connected to the end point of the inner winding to realize a Z-shaped winding method. This winding method has a better effect on space utilization and can arrange more turns of coils in a unit volume of the substrate, thereby improving its inductance value and quality factor.

[0046] Next, the integrated processing scheme of the Z-shaped MEMS double-layer solenoid inductor coil of the present invention will be introduced. This integrated scheme uses two wafers. The specific steps include:

[0047] Step 1, making the inner layer upper and lower substrates;

[0048] 1) using Piranha solution to clean the first and second wafers of semiconductor materials including but not limited to silicon materials;

[0049] 2) performing thermal oxidation treatment on the first and second wafers, wherein the thermal oxidation thickness is determined according to the thickness of the wafers, and forming an oxide layer of a certain thickness on the surface of the wafers;

[0050] 3) coating a layer of adhesion promoter on the surfaces of the first and second wafers;

[0051] 4) Spray or spin-coat a layer of photoresist on the upper surface of the first and second wafers, the photoresist type is a thin glue with a coating thickness of about 2 microns; place the first and second wafers in a nitrogen oven for pre-baking for a suitable time; spray or spin-coat a layer of photoresist on the lower surface of the first and second wafers, the photoresist type is the same as the upper surface; place the first and second wafers in a nitrogen oven for pre-baking for a suitable time;

[0052] 5) exposing a plurality of parallel inner upper coil groove shapes on the upper surface of the first wafer; exposing the upper magnetic core and inner and outer through-hole shapes on the lower surface of the first wafer; placing the first wafer in a developer of a corresponding photoresist type for development; placing the first wafer in a nitrogen oven for post-baking for a suitable time;

[0053] 6) exposing the lower magnetic core and the inner and outer through-hole shapes on the upper surface of the second wafer; exposing the shape of a plurality of parallel inner lower coil grooves on the lower surface of the second wafer; placing the second wafer in a developer of a corresponding photoresist type for development; placing the second wafer in a nitrogen oven for post-baking for a suitable time;

[0054] 7) placing the first and second wafers in a substrate material oxide selective etchant to etch the oxide layer exposed after development in 5) and 6) to the substrate layer;

[0055] 8) Cleaning the first and second wafers with Piranha solution; coating the surfaces of the first and second wafers with a layer of adhesion promoter;

[0056] 9) Spray or spin-coat a layer of photoresist on the upper surface of the first and second wafers, the photoresist type is a thick photoresist with a coating thickness of about 10 microns; place the first and second wafers in a nitrogen oven for pre-baking for a suitable time; spray or spin-coat a layer of photoresist on the lower surface of the first and second wafers, the photoresist type is the same as the upper surface; place the first and second wafers in a nitrogen oven for pre-baking for a suitable time;

[0057] 10) exposing the shapes of inner and outer through holes on the upper surface of the first wafer; exposing the shapes of the upper magnetic core and the inner and outer through holes on the lower surface of the first wafer; placing the first wafer in a developer of a corresponding photoresist type for development; placing the first wafer in a nitrogen oven for post-baking for a suitable time;

[0058] 11) exposing the lower magnetic core and the inner and outer through-hole shapes on the upper surface of the second wafer; exposing the inner and outer through-hole shapes on the lower surface of the second wafer; placing the second wafer in a developer of a corresponding photoresist type for development; placing the second wafer in a nitrogen oven for post-baking for a suitable time;

[0059] 12) Dry-etching the first wafer; first, etching the upper magnetic core groove and the inner and outer through-hole grooves on the back of the wafer; then etching the inner and outer through-hole grooves from the front until they are completely etched through; cleaning the first wafer with Piranha solution; finally, etching a plurality of parallel inner layer upper coil grooves on the front; completing the production of the inner layer upper substrate;

[0060] 13) Dry-etching the second wafer; first, etching the lower magnetic core groove and the inner and outer through-hole grooves on the front side of the wafer; then etching the inner and outer through-holes from the back side until they are completely etched through; cleaning the second wafer with Piranha solution; finally, etching several parallel inner lower coil grooves on the back side; completing the production of the inner substrate;

[0061] Step 2: Making the magnetic core

[0062] 1) Cleaning the first and second wafers prepared in step 1 with Piranha solution respectively;

[0063] 2) patterning a titanium or gold metal layer at the magnetic core groove on the reverse side of the first wafer; continuing to sputter or chemically plate at the patterned position to obtain a layer of iron or nickel metal layer;

[0064] 3) electroplating an iron-nickel alloy or an iron-cobalt alloy at the magnetic core groove position on the back side of the first wafer to a certain height;

[0065] 4) patterning a titanium or gold metal layer at the magnetic core groove on the front side of the second wafer; continuing to sputter or chemically plate at the patterned position to obtain a layer of iron or nickel metal layer;

[0066] 5) electroplating an iron-nickel alloy or an iron-cobalt alloy at the magnetic core groove position on the front side of the second wafer to a certain height;

[0067] 6) patterning and coating a layer of acid-resistant coating on the electroplated magnetic core grooves of the first and second wafers;

[0068] Step 3: Bonding of the first and second wafers

[0069] 1) Cleaning the first and second wafers after step 2 with Piranha solution respectively;

[0070] 2) placing the first and second wafers in a tube furnace environment exceeding the gasification temperature of the acid-resistant coating to eliminate the acid-resistant coating;

[0071] 3) placing the first and second wafers in a substrate material oxide selective etchant to etch all remaining substrate oxides;

[0072] 4) placing the lower surface of the first wafer and the upper surface of the second wafer opposite to each other, performing low-temperature silicon-silicon bonding to form a whole wafer;

[0073] 5) The entire wafer is subjected to thermal oxidation treatment.

[0074] Step 4: Electroplating thinning of the inner coil

[0075] 1) sputtering a titanium or gold metal layer on the back surface of the entire wafer obtained in step 3, and then sputtering or chemically plating a copper metal layer on the back surface of the entire wafer;

[0076] 2) Electroplating metal copper from the back of the wafer to fill the coil slot on the inner lower substrate, and electroplating the inner and outer through holes to the plane position below the coil slot on the inner upper substrate;

[0077] 3) sputtering a titanium or gold metal layer on the entire front side of the wafer that has been electroplated with copper, and then sputtering or chemically plating a copper metal layer on the entire front side of the wafer;

[0078] 4) Electroplating metal copper from the front side of the wafer to fill the inner coil slot and connect it with the coil slot on the inner lower substrate through the inner through hole.

[0079] 5) Use a chemical mechanical polisher (CMP) to thin the copper metal to the height of the substrate thermal oxide layer, and perform CMP polishing on the front and back substrate surfaces.

[0080] Step 5: Preparation of the outer upper and lower substrates

[0081] 1) coating the entire surface of the wafer polished in step 4 with a layer of adhesion promoter;

[0082] 2) Spin-coat a layer of high-thickness, high-hardness, acid-resistant photoresist on the entire front of the wafer after curing; and soft-bake at a suitable temperature;

[0083] 3) Spin-coat a layer of high-thickness, high-hardness, acid-resistant photoresist on the back side of the wafer; soft-bake at a suitable temperature;

[0084] 4) Use weak light intensity to expose the outer coil groove on the entire front of the wafer; adjust the light intensity to expose the outer through hole on the entire front of the wafer;

[0085] 5) Use weak light intensity to expose the outer lower coil groove on the back side of the entire wafer; adjust the light intensity to expose the outer through hole on the back side of the entire wafer; complete the production of the outer upper and lower substrates.

[0086] Step 6: Electroplating and thinning of the outer coil

[0087] 1) sputtering a titanium or gold metal layer on the lower surface of the outer layer lower substrate of the entire wafer obtained in step 5, and then sputtering or chemically plating a copper metal layer on the lower surface of the outer layer lower substrate;

[0088] 2) electroplating the outer layer lower coil groove from the lower surface of the inner layer lower substrate to the height of the outer layer lower substrate;

[0089] 3) sputtering a titanium or gold metal layer on the upper surface of the outer upper substrate of the entire wafer, and then sputtering or chemically plating a copper metal layer on the upper surface of the outer upper substrate;

[0090] 4) electroplating the outer layer lower coil groove from the upper surface of the outer layer upper substrate to the height of the outer layer upper substrate;

[0091] 5) Use a chemical mechanical polisher (CMP) to thin the copper metal to the substrate height, and perform CMP polishing on the upper and lower substrate surfaces.

[0092] 6) Use a dicing machine to separate the double-layer coils to complete the preparation of the double-layer coil.

[0093] Example 1: Silicon-based MEMS double-layer coil

[0094] When using silicon as the base substrate, two 4-inch 800μm thick ultra-high resistance zone melting silicon single crystal (FZ-Silicon) wafers are used, and their resistivity is greater than 1000Ω·cm. When electroplated copper is used as the winding, the inner turns of the coils are all in the silicon-based substrate. If low-resistance silicon is used, the coils between different turns will be directly connected through the silicon substrate, causing the entire inner coil to short-circuit and lose the spiral electrical connection function of the inductor itself. The use of high-resistance silicon wafers can better avoid this problem. The thermal oxidation performed after bonding the two layers of substrate in Example Step 3 also plays the same role. The high-resistance silicon surface that has been exposed by dry etching is oxidized again to produce an oxide layer to further protect the insulation of the inner turns of the coils connected through the substrate. The specific implementation steps will be introduced next. The device mainly consists of six steps.

[0095] Step 1, making the inner layer upper and lower substrates;

[0096] 1) Use Piranha solution to clean the 4-inch, 800μm thick first and second wafers made of ultra-high resistance zone melt silicon single crystal (FZ-Silicon). The specific ratio of Piranha is concentrated sulfuric acid (95%) and concentrated hydrogen peroxide solution (30%) in a volume ratio of 3:1. Remove organic and metal impurities on the surface of the silicon wafer and reduce the uneven thickness of the oxide layer of the silicon wafer in the next step of thermal oxidation.

[0097] 2) The first and second wafers are subjected to thermal oxidation treatment, and the thermal oxidation thickness is 2 μm, which ensures that a certain thickness of silicon dioxide oxide layer remains on the surface after the inner coil slot is etched in the subsequent dry process, thereby ensuring that the overall flat silicon surface can be guaranteed in the subsequent bonding process;

[0098] 3) Coating a layer of adhesion promoter composed of hexamethyldisilazane (HMDS) vapor on the surface of the first and second wafers to improve the adhesion of the photoresist in the next step of coating. The specific coating parameters are a chamber temperature of 150° C. and a chamber pressure of 20800 mTorr;

[0099] 4) Spin-coat a layer of photoresist on the upper surface of the first and second wafers, the photoresist type is Shipley1813 G2Series, the spin-coating parameters are a rotation speed of 2000rpm, a time of 30s, and a target photoresist coating thickness of 2μm; place the first and second wafers in a nitrogen oven for pre-baking, the specific parameters are an oven temperature of 115°C, a pre-baking time of 5min, so that the photoresist surface is partially solidified to ensure that the upper surface photoresist will not fall off on the vacuum chuck of the spin glue machine when the lower surface is coated with glue; spray or spin-coat a layer of photoresist on the lower surface of the first and second wafers, and the photoresist type and spin-coating parameters are the same as the upper surface; place the first and second wafers in a nitrogen oven for pre-baking, the specific parameters are an oven temperature of 115°C, and a pre-baking time of 30min, so that the photoresist is further partially solidified to ensure its stable optical performance during photolithography; the specific steps are as follows Figure 3 As shown;

[0100] 5) Photolithography is performed on the upper surface of the first wafer to form a plurality of parallel inner upper coil grooves and outer through-hole shapes; the lower surface of the first wafer is exposed to form the upper magnetic core and the inner and outer through-hole shapes; the photolithography parameters are wavelength 365nm, light intensity 10mJ / cm 2 / s, and the exposure time is 3s. The first wafer is placed in NMD-W 2.38% developer for development, and the development time is 2min; the first wafer is placed in a nitrogen oven for post-baking, and the specific parameters are oven temperature 115°C and post-baking time 15min;

[0101] 6) Photolithography the lower magnetic core and the inner and outer through-hole shapes on the upper surface of the second wafer; Photolithography the shape of a plurality of parallel inner lower coil slots on the lower surface of the second wafer; Place the second wafer in NMD-W 2.38% developer for development, and the development time is 2 minutes; Place the second wafer in a nitrogen oven for post-baking, and the specific parameters are oven temperature of 115° C. and post-baking time of 15 minutes;

[0102] 7) Place the first and second wafers in a buffered oxide etchant (BOE), specifically a mixture of 49% HF aqueous solution: 40% NH4F aqueous solution = 1:6 (volume ratio), and etch for 30 minutes. Etch the oxide layer exposed after development in 5) and 6) to the substrate layer, and use silicon dioxide as a mask when etching the coil slot in the later stage; the specific process is as follows Figure 4 As shown;

[0103] 8) Cleaning the first and second wafers with Piranha solution to remove the S1813 photoresist coated on the front and back surfaces of the wafers in the previous step; coating the first and second wafers with a layer of adhesion promoter composed of hexamethyldisilazane (HMDS) vapor, with the coating parameters being the same as those described in step 3);

[0104] 9) Spin-coat a layer of photoresist on the upper surface of the first and second wafers, the photoresist type is AZ P4620, and the spin-coating parameters are a speed of 2000 rpm and a time of 50 s; place the first and second wafers in a nitrogen oven for pre-baking, the specific parameters are an oven temperature of 95° C., and a pre-baking time of 10 min; spin-coat a layer of photoresist on the lower surface of the first and second wafers, and the photoresist type and spin-coating parameters are the same as the upper surface; place the first and second wafers in a nitrogen oven for pre-baking, the specific parameters are an oven temperature of 95° C., and a pre-baking time of 60 min; the specific steps are as follows: Figure 5 As shown;

[0105] 10) The upper surface of the first wafer is photoetched to form the inner and outer through-hole shapes; the lower surface of the first wafer is photoetched to form the upper magnetic core and the inner and outer through-hole shapes. The photolithography parameters are wavelength 365nm and light intensity 10mJ / cm 2 / s, exposure time is 9s; the first wafer is placed in a developer prepared by mixing AZ 400K and ultrapure water in a ratio of 1:3 for development, and the development time is 2min; the first wafer is placed in a nitrogen oven for post-baking, and the specific parameters are oven temperature of 95°C and post-baking time of 30min;

[0106] 11) exposing the lower magnetic core and the inner and outer through-hole shapes on the upper surface of the second wafer; exposing the inner and outer through-hole shapes on the lower surface of the second wafer, the photolithography parameters are the same as those described in 10); placing the second wafer in a developer prepared by mixing AZ 400K and ultrapure water in a ratio of 1:3 for development, the development time is 2 minutes; placing the second wafer in a nitrogen oven for post-baking, the post-baking parameters are the same as those described in 10);

[0107] 12) Dry etching the first wafer; first, dry-etch the upper magnetic core groove and the inner and outer through-hole grooves to a depth of 450 μm on the back of the wafer. The dry etching is performed using an inductively coupled plasma dry etcher (ICP). The etching parameters are that the gas excitation electric field power is 600 W. During the etching stage, sulfur hexafluoride SF6 (flow rate is 130 sccm) and oxygen O2 (flow rate is 13 sccm) are excited into plasma and then accelerated by an electric field (power is 25 W) to bombard the surface of the silicon wafer. Silicon is etched through physical and chemical reactions. This process The process lasts for 8s; in the deposition protection stage, octafluorocyclobutane C4F8 (flow rate of 85sccm) is excited into plasma and adheres to the etching sidewall by gravity to protect the silicon sidewall, thereby achieving high vertical ratio etching. This process lasts for 5s, and the etching process and the deposition process are carried out alternately; the chamber temperature is maintained at 40°C, the silicon wafer substrate stage temperature is controlled at 25°C, and helium (He) is used on the back of the silicon wafer stage for silicon wafer cooling, and its working pressure is 9800mTorr; the reaction of sulfur hexafluoride SF6 plasma during the etching process is expressed as follows

[0108] SF6+e - →S x F y + +S x F y - +F - +e - (1)

[0109] When the generated fluorine plasma bombards the silicon surface, it reacts with silicon as shown in the following formula:

[0110] Si+F - →SiF x ↑ (2)

[0111] The generated gas is pumped out of the reaction chamber by a turbomolecular pump, thereby achieving silicon etching. The plasma reaction of octafluorocyclobutane C4F8 during the deposition process is expressed as follows:

[0112] C4F8+e - →CF x + +CF x - +F - +e - (3)

[0113] The generated negative plasma is deposited on the silicon surface and sidewalls to form a polymer passivation film. The reaction process is shown in the following formula:

[0114] CF x - →nCF2 (4)

[0115] The passivation film reacts under the bombardment of fluorine plasma generated by SF6 in the next cycle to produce gas, which is then drawn out of the reaction chamber.

[0116]

[0117] During the etching process, the electric field acceleration makes it easier for the plasma to bombard the silicon bottom surface, thereby protecting the polymer passivation film deposited on the side wall and achieving graphic etching with a depth-to-width ratio greater than 10:1.

[0118] When the target depth of the core groove is 445μm, the deposition protection process is cancelled and only the process gas ratio in the etching stage (i.e., sulfur hexafluoride SF6 (flow rate of 130sccm) and oxygen O2 (flow rate of 13sccm)) is used. When the depth reaches 450μm, a bottom fillet can be generated. This improves the strength of the core groove cavity during the bonding and thinning process, and prevents cracks generated during the subsequent bonding and thinning process from extending from the bottom of the substrate to the entire device, thereby causing the device to be scrapped.

[0119] Then, the inner and outer through holes are etched from the front side until they are completely through; the first wafer is cleaned with Piranha solution to remove the residual photoresist on the surface of the wafer; finally, the oxide layer is used as a mask to etch several parallel inner layer upper coil grooves on the front side, with a specific etching depth of 200 μm; the inner layer upper substrate is completed; the specific process is as follows Figure 6 As shown;

[0120] 13) Dry-etch the second wafer; first, etch the lower magnetic core groove and the inner and outer through-hole grooves on the front side of the wafer, with the same process parameters as described in 12); then, etch the inner and outer through-holes from the back side until they are completely etched through; clean the photoresist of the second wafer with Piranha solution; finally, etch several parallel inner lower coil grooves on the back side, with a specific etching depth of 200 μm; and complete the production of the inner lower substrate; the specific process is as follows Figure 7 As shown;

[0121] Step 2: Making the magnetic core

[0122] 1) Cleaning the first and second wafers produced in step 1 with Piranha solution to remove organic and metal impurities that may be generated in the previous steps;

[0123] 2) Sputter a titanium metal layer in a patterned manner at the magnetic core groove on the reverse side of the first wafer, with a specific sputtering thickness of 100 nm; continue to sputter a nickel metal layer at the above patterned position, with a specific thickness of 100 nm; the specific process is as follows Figure 8 As shown;

[0124] 3) Electroplating iron-nickel alloy at the magnetic core groove position on the back side of the first wafer to a depth of 445 μm; the specific process is as follows: Fig. 9 As shown;

[0125] 4) patterning a titanium metal layer at the magnetic core groove on the front side of the second wafer, with a specific sputtering thickness of 100 nm; and continuing to sputter a nickel metal layer at the above patterned position, with a specific thickness of 100 nm;

[0126] 5) electroplating iron-nickel alloy at the magnetic core groove position on the front side of the second wafer to a height of 445 μm;

[0127] 6) Patterning and coating a layer of acid-resistant coating on the electroplated magnetic core grooves of the first and second wafers, wherein the coating is Teflon (polytetrafluoroethylene) coating with a coating thickness of 5 μm; Fig.10 As shown;

[0128] Step 3: Bonding of the first and second wafers

[0129] 1) Cleaning the first and second wafers after step 2 with Piranha solution respectively;

[0130] Place the first and second wafers in a tube furnace at 450°C to remove the Teflon coating;

[0131] 2) placing the first and second wafers in a silicon dioxide selective etchant, specifically using a 49% HF aqueous solution and ultrapure water in a ratio of 1:5, to etch all remaining substrate oxides and activate the wafer surfaces to make them easier to bond with each other during pre-bonding;

[0132] 3) Place the lower surface of the first wafer opposite to the upper surface of the second wafer, align them using the preset alignment marks, and then perform low-temperature silicon-silicon bonding. The specific process parameters are: first pre-bonding, pre-bonding the wafers under a force of 1500N, a temperature of 300°C, and a high vacuum environment, and then annealing them in an annealing furnace at 200 degrees Celsius for 10 hours. The wafer is formed as a whole; this process is as follows Fig.11 As shown;

[0133] 4) The entire wafer is subjected to thermal oxidation treatment with a thermal oxidation thickness of 1 μm to ensure the insulation between the turns of the coil after electroplating; the specific process is as follows Fig.12 As shown;

[0134] Step 4: Electroplating thinning of the inner coil

[0135] 1) sputtering a titanium metal layer on the back side of the whole wafer obtained in step 3, with a specific thickness of 100 nm, and then sputtering a copper metal layer on the back side of the whole wafer, with a specific thickness of 100 nm; the specific process is as follows: Fig.13 As shown;

[0136] 2) Electroplating metal copper from the back of the wafer to fill the coil groove on the inner lower substrate, and electroplating the inner and outer through holes to the plane position below the coil groove on the inner upper substrate; the specific process is as follows Fig.14 As shown;

[0137] 3) sputtering a titanium metal layer on the front surface of the wafer that has been electroplated with copper, with a specific thickness of 100 nm, and then sputtering or chemically plating a copper metal layer on the front surface of the wafer, with a specific thickness of 100 nm;

[0138] 4) Electroplating copper metal from the front of the wafer to fill the inner coil slot and connect it with the coil slot on the inner substrate through the inner through hole. Fig.15 As shown;

[0139] 5) Use a chemical mechanical polisher (CMP) to thin the copper metal to the height of the thermal oxide layer of the silicon substrate, and perform CMP polishing on the front and back substrate surfaces. Fig.16 As shown;

[0140] Step 5: Preparation of the outer upper and lower substrates

[0141] 1) coating the entire surface of the wafer polished in step 4 with a layer of adhesion promoter;

[0142] 2) Spin-coat a layer of SU-82100 photoresist on the entire front side of the wafer, with a specific thickness of 20 μm and a spinning speed of 1500 rpm; soften and bake on a hot plate at 95°C for 30 minutes;

[0143] 3) Spin-coat a layer of SU-82100 photoresist on the back side of the wafer, with a specific thickness of 20 μm and a spin speed of 1500 rpm; soften and bake on a hot plate at 95°C for 35 minutes; the specific steps are as follows: Fig.17 As shown;

[0144] 4) Use weak light intensity to expose the outer coil groove on the front of the wafer as a whole; adjust the light intensity to expose the outer through hole on the front of the wafer as a whole; the exposure parameter is light intensity 10mJ / cm 2 / s, exposure time is 28s

[0145] 5) Use weak light intensity to expose the outer layer lower coil groove on the back side of the whole wafer; adjust the light intensity to expose the outer layer through hole on the back side of the whole wafer; place the wafer on a 95°C hot plate for post-baking, and place it in SU-82000 developer for 17 minutes, and finally place the wafer on a 200°C hot plate for 20 minutes of hardening baking; obtain the outer layer substrate; the specific process is as follows Fig.18 As shown;

[0146] Step 6: Electroplating and thinning of the outer coil

[0147] 1) sputtering a titanium metal layer on the lower surface of the outer lower substrate of the entire wafer obtained in step 5, with a specific thickness of 100 nm, and then sputtering a copper metal layer on the lower surface of the outer lower substrate, with a specific thickness of 100 nm;

[0148] 2) electroplating the outer layer lower coil groove from the lower surface of the inner layer lower substrate to the height of the outer layer lower substrate;

[0149] 3) sputtering a titanium or gold metal layer on the upper surface of the outer upper substrate of the entire wafer, and then sputtering or chemically plating a copper metal layer on the upper surface of the outer upper substrate;

[0150] 4) electroplating the outer layer lower coil groove from the upper surface of the outer layer upper substrate to the height of the outer layer upper substrate;

[0151] 5) Use a chemical mechanical polisher (CMP) to thin the copper metal to the substrate height, and perform CMP polishing on the upper and lower substrate surfaces. Fig.19 As shown;

[0152] 6) Use a dicing machine to separate the double-layer coils to complete the preparation of the double-layer coil.

[0153] Example 2: PDMS flexible substrate Z-shaped double-layer coil.

[0154] When used as a flexible substrate double-layer coil, the double-layer coil processed through 6 steps mentioned in the present invention is completely digested with different substrate selection etchants according to different substrate materials to obtain the coil body and the magnetic core body. It is placed in a special mold, poured with a flexible substrate (such as PDMS), and the mold is separated from the flexible substrate to obtain a flexible substrate coil. It can be used in the core of electromagnetic devices in human implants, such as blood supply pumps, drug supply pumps and other applications.

[0155] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions only describe the principles of the present invention. The present invention may be subject to various changes and improvements without departing from the spirit and scope of the present invention. These changes and improvements fall within the scope of the present invention. The scope of protection claimed by the present invention is defined by the attached claims and their equivalents.

Claims

1. A Z-shaped MEMS double-layer solenoid inductor double-layer coil, comprising an inner and outer double-layer coil and a substrate; its characteristics are: A four-layer substrate is used as the support for the double-layer coil body, and the four layers of substrate are respectively an outer lower substrate, an inner lower substrate, an inner upper substrate, and an outer upper substrate from bottom to top; the double-layer coil is composed of an inner coil and an outer coil, and the outer coil is electrically connected through an outer through-hole made by MEMS technology on the four-layer substrate and a groove made by MEMS technology on the outer substrate; the inner coil is electrically connected through an inner through-hole on the inner substrate and a groove made by MEMS technology; the inner and outer coils are electrically connected through a C-shaped groove on the inner substrate; the above-mentioned groove and hole are the coil body mold, and the coil entity is made by through-hole electroplating TSV process; the double-layer solenoid coil is Z-shaped in the coil wire arrangement, with the inner coil as the wire starting point, that is, the last turn of the inner layer and The outer layer is initially electrically connected with a turn; at the same time, a double pad is provided on the outer substrate to realize electrical connection with the PCB circuit board; the soft magnetic material is encapsulated in batches using MEMS technology in the two inner substrates, and the soft magnetic material is located in the innermost layer of the double-layer coil and is wrapped by the double-layer coil as a whole; the MEMS double-layer solenoid inductor double-layer coil is a MEMS double-layer solenoid inductor double-layer coil with a silicon base or a cast flexible substrate as a basic substrate; the inner layer and the outer layer of the double-layer coil are connected through a long coil slot located on the inner layer upper substrate and a through hole located on the outer layer upper substrate; the capacitance effect of the Z-type winding structure at high frequencies will be suppressed, thereby increasing its resonant frequency, and it can achieve more coil turns under the same volume of component windings, thereby increasing the inductance value in the low frequency band.

2. The Z-shaped MEMS double-layer solenoid inductor double-layer coil according to claim 1 is characterized by: The outer layer upper coil slot located on the outer layer upper substrate is connected to the outer layer lower coil slot on the outer layer lower substrate through the through hole located on the outer layer upper substrate, the outer layer through hole located on the inner layer upper substrate, the outer layer through hole located on the inner layer lower substrate, and the through hole located on the outer layer lower substrate; the inner layer upper coil slot located on the inner layer upper substrate is connected to the inner layer lower coil slot on the inner layer lower substrate through the inner layer through hole located on the inner layer upper substrate and the inner layer through hole located on the inner layer lower substrate; the upper magnetic core slot located on the inner layer upper substrate is opposite to the lower magnetic core slot located on the inner layer lower substrate, and together constitutes the magnetic core slot of the double-layer coil; the above-mentioned outer layer lower substrate, inner layer lower substrate, inner layer upper substrate, and outer layer upper substrate correspond to each other in positions on the through holes.

3. A method for preparing a Z-shaped MEMS double-layer solenoid inductor double-layer coil, comprising the MEMS double-layer solenoid inductor double-layer coil according to any one of claims 1-2, characterized in that: The steps include: Step 1, making the inner layer upper and lower substrates; Step 2, making the magnetic core; Step 3, bonding the first and second wafers; Step 4, electroplating thinning of the inner coil; Step 5, making the outer upper and lower substrates; Step 6: The outer coil is thinned by electroplating to complete the preparation of the double-layer coil.

4. The method for preparing a Z-shaped MEMS double-layer solenoid inductor double-layer coil according to claim 3, wherein the step 2 further comprises the following contents: 1) Cleaning the first and second wafers prepared in step 1 with Piranha solution respectively; 2) patterning a titanium or gold metal layer at the magnetic core groove on the reverse side of the first wafer; continuing to sputter or chemically plate at the patterned position to obtain a layer of iron or nickel metal layer; 3) electroplating an iron-nickel alloy or an iron-cobalt alloy at the magnetic core groove position on the back side of the first wafer to a certain height; 4) patterning a titanium or gold metal layer at the magnetic core groove on the front side of the second wafer; continuing to sputter or chemically plate at the patterned position to obtain a layer of iron or nickel metal layer; 5) electroplating an iron-nickel alloy or an iron-cobalt alloy at the magnetic core groove position on the front side of the second wafer to a certain height; 6) Patterning and coating a layer of acid-resistant coating on the electroplated magnetic core grooves of the first and second wafers.

5. The method for preparing a Z-shaped MEMS double-layer solenoid inductor double-layer coil according to claim 4, characterized in that: The step 3 further includes the following contents: 1) Cleaning the first and second wafers after step 2 with Piranha solution respectively; 2) placing the first and second wafers in a tube furnace environment exceeding the gasification temperature of the acid-resistant coating to eliminate the acid-resistant coating; 3) placing the first and second wafers in a substrate material oxide selective etchant to etch all remaining substrate oxides; 4) placing the lower surface of the first wafer and the upper surface of the second wafer opposite to each other, performing low-temperature silicon-silicon bonding to form a whole wafer; 5) The entire wafer is subjected to thermal oxidation treatment.

6. The method for preparing a Z-shaped MEMS double-layer solenoid inductor double-layer coil according to claim 5, characterized in that: The step 5 further includes the following contents: 1) coating the entire surface of the wafer polished in step 4 with a layer of adhesion promoter; 2) Spin-coat a layer of high-thickness, high-hardness, acid-resistant photoresist on the entire front of the wafer after curing; and soft-bake at a certain temperature; 3) Spin-coat a layer of high-thickness, high-hardness, acid-resistant photoresist on the back of the wafer; soft-bake at a certain temperature; 4) Use weak light intensity to expose the outer coil groove on the entire front of the wafer; adjust the light intensity to expose the outer through hole on the entire front of the wafer; 5) Use weak light intensity to expose the outer lower coil groove on the back side of the entire wafer; adjust the light intensity to expose the outer through hole on the back side of the entire wafer; complete the production of the outer upper and lower substrates.

7. The method for preparing a Z-shaped MEMS double-layer solenoid inductor double-layer coil according to claim 6, characterized in that: The step 6 further includes the following contents: 1) sputtering a titanium or gold metal layer on the lower surface of the outer layer lower substrate of the entire wafer obtained in step 5, and then sputtering or chemically plating a copper metal layer on the lower surface of the outer layer lower substrate; 2) electroplating the outer layer lower coil groove from the lower surface of the inner layer lower substrate to the height of the outer layer lower substrate; 3) sputtering a titanium or gold metal layer on the upper surface of the outer upper substrate of the entire wafer, and then sputtering or chemically plating a copper metal layer on the upper surface of the outer upper substrate; 4) electroplating the outer layer lower coil groove from the upper surface of the outer layer upper substrate to the height of the outer layer upper substrate; 5) using a chemical mechanical polisher (CMP) to thin the copper metal to the height of the substrate, and performing CMP polishing on the upper and lower substrate surfaces; 6) Use a dicing machine to separate the double-layer coils to complete the preparation of the double-layer coil.

8. Inductive element, characterized by: A double-layer coil comprising the Z-type MEMS double-layer solenoid inductor double-layer coil preparation method described in any one of claims 2-7.

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