Three-dimensional memory, manufacturing method thereof, and storage system having the same

Abstract

The present application provides a three-dimensional memory, a manufacturing method thereof, and a storage system having the same. The manufacturing method includes the following steps: providing a first substrate having a gate stack structure on its surface, the gate stack structure having a first surface away from the first substrate, a multi-layer control gate structure including a multi-layer top selection gate close to the first surface, a top selection gate layer closest to the first substrate in the multi-layer top selection gate being a first top selection gate, and the remaining top selection gates being second top selection gates; forming a contact hole and a top selection gate opening on a side of the gate stack structure away from the first substrate, the contact hole passing through the second top selection gate to the first top selection gate, and the top selection gate opening passing through the first top selection gate; forming a top selection gate tangent in the top selection gate opening, and forming a contact portion in contact with the first top selection gate in the contact hole. The above method not only saves process time and process cost, but also saves process window, which is conducive to device miniaturization.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a three-dimensional memory, a manufacturing method thereof, and a storage system having the same. Background Art

[0002] In existing technologies, the primary function of flash memory is to retain stored information for long periods of time without power. This technology offers advantages such as high integration, fast access speeds, and ease of erasing and rewriting, making it widely used in electronic products. To further increase the bit density of flash memory while reducing bit costs, 3D NAND memory has been proposed.

[0003] In current 3D NAND memories, multiple rows of channels are typically arranged between two adjacent gate line slits (GLS). These rows of channels typically correspond to a top select gate (TSG), forming a channel array. Within the channel array, the top select gate is typically divided into multiple sections by at least one top select gate cut (TSG cut). The top select gate cut is typically formed of an insulating oxide material and serves as a blocking channel for the top select gate.

[0004] To achieve bonding between 3D NAND devices and CMOS devices, it is typically necessary to form contact holes (Stair Contacts, SCTs) connected to the control gate structures and fill the contact holes with conductive material to lead out word lines. However, due to size limitations, it is difficult to form multiple rows of SCTs connected to multiple layers of TSGs, which in turn limits further device scaling. Summary of the Invention

[0005] The main purpose of the present application is to provide a three-dimensional memory, a manufacturing method thereof, and a storage system having the same, so as to solve the problem in the prior art that memories are difficult to further miniaturize.

[0006] To achieve the above-mentioned purpose, according to one aspect of the present application, a method for manufacturing a three-dimensional memory is provided, comprising the following steps: providing a first substrate having a gate stack structure on its surface, the gate stack structure comprising a multi-layer control gate structure and a multi-layer isolation layer alternating along a direction away from the first substrate, the gate stack structure having a first surface away from the first substrate, the multi-layer control gate structure comprising a multi-layer top selection gate close to the first surface, a layer of top selection gate closest to the first substrate among the multi-layer top selection gates being a first top selection gate, and the remaining top selection gates being a second top selection gate; forming a contact hole and a top selection gate opening on a side of the gate stack structure away from the first substrate, the contact hole extending from the second top selection gate to the first top selection gate, and the top selection gate opening extending through the first top selection gate; forming a top selection gate tangent in the top selection gate opening, and forming a contact portion in the contact hole that contacts the first top selection gate.

[0007] Furthermore, the step of forming a contact hole and a top selection gate opening includes: forming an interlayer dielectric layer covering the gate stack structure on the first substrate; sequentially etching the interlayer dielectric layer and the gate stack structure to simultaneously form a contact hole and a preliminary opening extending through the first top selection gate; and etching the gate stack structure through the preliminary opening to form a top selection gate opening extending through the first top selection gate to the isolation layer.

[0008] Furthermore, the multi-layer isolation layer includes a first isolation layer adjacent to the first top selection gate, and the first isolation layer is located on the side of the first top selection gate close to the first substrate. In the step of forming the top selection gate opening, the gate stack structure is etched through the prepared opening so that the top selection gate opening passes through the first isolation layer.

[0009] Furthermore, in the step of forming contact holes and top selection gate openings, a contact hole unit is formed on the side of the gate stack structure away from the first substrate, the contact hole unit includes a plurality of contact holes distributed along a first direction, and the top selection gate opening extends along a second direction, and the second direction is perpendicular to the first direction.

[0010] Furthermore, the contact hole has a first projection surface in the first substrate, the top selection gate opening has a second projection surface in the first substrate, and a length of the first projection surface along the second direction is greater than a length of the second projection surface along the first direction.

[0011] Furthermore, the step of forming a top selection gate cut line includes: depositing a first insulating material on a side of the gate stack structure away from the first substrate so that part of the first insulating material fills the top selection gate opening; removing the first insulating material outside the top selection gate opening, and the remaining first insulating material constitutes the top selection gate cut line.

[0012] Furthermore, the step of forming a contact portion includes: filling a conductive material in the contact hole to form a conductive portion in contact with the first top selection gate; or covering the inner wall of the contact hole with a conductive material to form a conductive portion in contact with the first top selection gate, and filling the contact hole with a second insulating material so that the conductive portion wraps the second insulating material.

[0013] According to another aspect of the present application, a three-dimensional memory is provided, comprising: a first substrate having a gate stack structure on its surface, the gate stack structure comprising a multi-layer control gate structure and a multi-layer isolation layer alternating in a direction away from the first substrate, the gate stack structure having a first surface away from the first substrate, the multi-layer control gate structure comprising a multi-layer top selection gate close to the first surface, a layer of top selection gates closest to the first substrate among the multi-layer top selection gates being a first top selection gate, and the remaining top selection gates being second top selection gates; a top selection gate tangent line passing through the first top selection gate; and a contact portion passing through the second top selection gate to the first top selection gate.

[0014] Furthermore, the three-dimensional memory includes a contact unit, the contact unit includes a plurality of contacts distributed along a first direction, and the top selection gate cut line extends along a second direction, which is perpendicular to the first direction.

[0015] Furthermore, the contact portion has a first cross section in a direction parallel to the first substrate, the top selection gate cut line has a second cross section in a direction parallel to the first substrate, and a length of the first cross section along the second direction is greater than a length of the second cross section along the first direction.

[0016] Furthermore, the three-dimensional memory further includes: a second substrate having a CMOS device on its surface; and a bonding portion for connecting the CMOS device to the contact portion.

[0017] According to another aspect of the present application, a storage system is provided, including a controller and a three-dimensional memory, the three-dimensional memory being configured to store data, the controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory, the three-dimensional memory being prepared by the above-mentioned three-dimensional memory manufacturing method, or the three-dimensional memory being the above-mentioned three-dimensional memory.

[0018] By applying the technical solution of the present application, a method for manufacturing a three-dimensional memory is provided. In the manufacturing method, a first substrate having a gate stack structure on its surface is first provided, and the multi-layer control gate structure includes a multi-layer top selection gate. The top selection gate of the multi-layer top selection gate close to the first substrate is the first top selection gate. Then, a contact hole and a top selection gate opening are formed on the side of the gate stack structure away from the first substrate. The contact hole penetrates to the first top selection gate located in the non-core storage area. The top selection gate opening penetrates the multi-layer top selection gate. Then, a top selection gate cut is formed in the top selection gate opening, and a contact portion contacting the first top selection gate is formed in the contact hole. Therefore, not only is process time and process cost saved by forming the contact hole and the top selection gate opening in one step, but the formed contact portion can also be in contact with each top selection gate, thereby eliminating the need to form multiple rows of contact holes contacting each top selection gate, saving the process window and facilitating device miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0020] Figure 1 A schematic diagram showing a process of a method for manufacturing a three-dimensional memory provided in an embodiment of the present application is shown;

[0021] Figure 2 1 shows a schematic diagram of a cross-sectional structure of a substrate after providing a first substrate having a stacked body on its surface and forming a through-channel structure in a method for manufacturing a three-dimensional memory provided in an embodiment of the present application;

[0022] Figure 3 Shows the Figure 2 A schematic diagram of a cross-sectional structure of a substrate after the sacrificial layer in the stack is replaced with a control gate structure to form a gate stack structure;

[0023] Figure 4 Shown in Figure 3 The schematic diagram of the cross-sectional structure of the substrate after the gate stack structure is covered with the interlayer dielectric layer is shown;

[0024] Figure 5 shows the simultaneous formation of Figure 4 The schematic diagram of the cross-sectional structure of the contact hole of the first top selection gate and the substrate after the preliminary opening is shown;

[0025] Figure 6 Shows the formation of a through Figure 5 A schematic diagram of a cross-sectional structure of a substrate after the top selection gate opening from the first top selection gate to the isolation layer is shown;

[0026] Figure 7 Shown Figure 6 A schematic diagram of the top view of the substrate shown;

[0027] Figure 8 Shown in Figure 6 The schematic diagram of the cross-sectional structure of the gate stack structure shown is a schematic diagram of the substrate after the first insulating material is deposited on the side away from the first substrate;

[0028] Figure 9 Shows the removal of Figure 8 The schematic diagram of the cross-sectional structure of the substrate after the first insulating material outside the top selection gate opening is formed into the top selection gate cut line;

[0029] Figure 10 Shown in Figure 9 A schematic diagram of the cross-sectional structure of the substrate after the contact hole is filled with a conductive material is shown;

[0030] Figure 11 Shown in Figure 10 A schematic diagram of the cross-sectional structure of the substrate after the contact hole is filled with the second insulating material so that the conductive portion wraps the second insulating material;

[0031] Figure 12 Shown Figure 11 A schematic diagram of the top view of the substrate shown;

[0032] Figure 13 A schematic diagram showing a connection relationship of a storage system provided according to an embodiment of the present application is shown;

[0033] Figure 14 A schematic structural diagram of a mobile phone provided according to an embodiment of the present application is shown.

[0034] The above drawings include the following reference numerals:

[0035] 10. First substrate; 20. Gate stack structure; 210. Sacrificial layer; 220. Isolation layer; 230. Control gate structure; 231. Top selection gate; 2311. First top selection gate; 2312. Second top selection gate; 30. Channel structure; 40. Interlayer dielectric layer; 50. Contact portion; 501. Contact hole; 502. Conductive material; 503. Second insulating material; 510. Contact portion unit; 511. Contact hole unit; 60. Top selection gate cut line; 601. Preparatory opening; 602. Top selection gate opening; 70. First insulating material; 1000. Three-dimensional memory; 2000. Controller; 3000. Host; 4000. Chip; 10000. Mobile phone; 20000. Storage system. DETAILED DESCRIPTION

[0036] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0037] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0038] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0039] In some embodiments, due to size limitations, it is difficult to form multiple rows of SCTs connected to the multi-layer top select gate (TSG), thereby limiting further device scaling.

[0040] The inventors of this application have conducted research on the above problems and proposed a method for manufacturing a three-dimensional memory. Figure 1 As shown, the following steps are included:

[0041] Providing a first substrate having a gate stack structure on its surface, the gate stack structure including a multi-layer control gate structure and a multi-layer isolation layer alternating in a direction away from the first substrate, the gate stack structure having a first surface away from the first substrate, the multi-layer control gate structure including a multi-layer top selection gate close to the first surface, a top selection gate layer closest to the first substrate among the multi-layer top selection gates being a first top selection gate, and the remaining top selection gates being second top selection gates;

[0042] forming a contact hole and a top selection gate opening on a side of the gate stack structure away from the first substrate, wherein the contact hole passes through the second top selection gate to the first top selection gate, and the top selection gate opening passes through the first top selection gate;

[0043] A top select gate cut line is formed in the top select gate opening, and a contact portion contacting the first top select gate is formed in the contact hole.

[0044] The above-mentioned manufacturing method of the present application not only saves process time and process cost by forming the contact hole and the top selection gate opening in one step, but also enables the formed contact portion to contact each top selection gate, thereby eliminating the need to form multiple rows of contact holes in contact with each top selection gate, saving process windows and facilitating device miniaturization.

[0045] The following describes in more detail exemplary embodiments of the method for fabricating a three-dimensional memory device according to the present application. However, these exemplary embodiments can be implemented in a variety of different forms and should not be construed as being limited to the embodiments described herein. It should be understood that these exemplary embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those skilled in the art.

[0046] First, a first substrate 10 having a gate stack structure 20 on its surface is provided. Figure 2 and Figure 3 As shown, X-cut corresponds to a partial cross-section obtained by cutting the gate stack structure 20 along a first direction, and Y-cut corresponds to a partial cross-section obtained by cutting the gate stack structure 20 along a second direction. The above-mentioned second direction is perpendicular to the above-mentioned first direction. The gate stack structure 20 includes multiple layers of control gate structures 230 and isolation layers 220 alternating along a direction away from the first substrate 10. In the direction away from the first substrate 10, the multi-layer control gate structure 230 includes a multi-layer top selection gate 231 located on the outside. The top selection gate 231 of the multi-layer top selection gate 231 closest to the first substrate 10 is a first top selection gate 2311, and the remaining top selection gates are second top selection gates 2312.

[0047] It should be explained that the first direction in the present application may be the extension direction of the gate gaps, and the second direction may be the arrangement direction of the gate gaps.

[0048] In some optional embodiments, the gate stack structure 20 includes a core storage area and a non-core storage area, and a channel structure 30 penetrating to the first substrate 10 is formed in the core storage area.

[0049] In an optional embodiment, the present application further includes the step of forming the gate stack structure 20: providing a first substrate 10 having a stacked body on its surface, the stacked body including sacrificial layers 210 and isolation layers 220 alternately stacked in a direction away from the first substrate 10, such as Figure 2The sacrificial layer 210 is replaced by a control gate structure 230, and the multi-layer control gate structure 230 is stacked with a multi-layer isolation layer 220 to form a gate stack structure 20, as shown Figure 3 shown.

[0050] The sacrificial layer 210 and the isolation layer 220 can be formed using conventional deposition processes, such as chemical vapor deposition. Those skilled in the art can reasonably determine the number of layers of the sacrificial layer 210 and the isolation layer 220 based on actual needs. The isolation layer 220 can be SiO2, and the sacrificial layer 210 can be SiN, but these materials are not limited to these. Those skilled in the art can also reasonably select the types of the sacrificial layer 210 and the isolation layer 220 based on actual needs.

[0051] In an optional embodiment, the step of forming a channel structure 30 in the stack that penetrates the first substrate 10 includes: forming a channel hole in the stack that penetrates the first substrate 10; sequentially depositing a functional layer and a channel layer on the sidewalls of the channel hole, forming a dielectric filling layer in the channel hole, and the channel layer and the functional layer sequentially surround the dielectric filling layer to form the channel structure 30.

[0052] The step of forming the functional layer may include sequentially forming a stacked charge blocking layer, an electron capture layer, and a tunneling layer on the sidewalls of the channel hole.

[0053] Those skilled in the art can reasonably select materials for each functional layer and the channel layer. For example, the charge blocking layer can be made of SiO2, the charge trapping layer can be made of SiN, the tunneling layer can be made of SiO2, and the channel layer can be made of polysilicon. Furthermore, those skilled in the art can form the channel structure 30 using conventional deposition processes, which will not be further described herein.

[0054] The stack has a first region and a second region located at at least one side of the first region. In an optional embodiment, as Figure 2 and Figure 3 As shown, multiple channel structures 30 are formed in both the first and second regions of the stack, extending through the first substrate 10. The channel structures 30 in the second region constitute a dummy channel array, which is used to support the isolation layer 220 when the control gate structure 230 is replaced. The first region is used to form a core storage area in the gate stack structure through subsequent processes, and the second region is used to form a non-core storage area in the gate stack structure through subsequent processes. The above processes may include but are not limited to channel preparation processes and gate replacement processes. The channel structures 30 in the second region constitute a dummy channel array, which is used to support the isolation layer 220 when the control gate structure is subsequently replaced.

[0055] In an optional embodiment, the step of replacing the sacrificial layer 210 with the control gate structure 230 includes: forming a gate gap in the stack that penetrates the first substrate 10, so that the sacrificial layer 210 has an exposed end face located in the gate gap; starting from the above-mentioned exposed end face, the sacrificial layer 210 is wet-etched with an etching solution to remove the sacrificial layer 210; and, by removing the sacrificial layer 210, a channel extending laterally can be formed at the position where the sacrificial layer 210 is removed, and then the gate material is deposited using the above-mentioned channel as a deposition channel to obtain a gate layer. The above-mentioned deposition process can be atomic layer deposition (ALD).

[0056] The control gate structure 230 may further include a high-K dielectric layer. Prior to forming the gate layer, the channel surface may be covered with the high-K dielectric layer. The K dielectric layer and the gate layer together constitute the control gate structure 230. The high-K dielectric layer herein refers to a dielectric material having a high dielectric constant. The material forming the high-K dielectric may be selected from one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, and BaSrTiO.

[0057] In some optional embodiments, after replacing the sacrificial layer 210 with the control gate structure 230, a sidewall insulating layer may be deposited in the gate gap, and then a dielectric material may be filled in the gate gap covered with the sidewall insulating layer to form a gap segment. The gap segment may be a common source or an insulating dielectric layer to support the device.

[0058] After forming the channel structure 30 penetrating the first substrate 10 in the gate stack structure 20, as shown in FIG. Figures 4 to 7 As shown, a contact hole 501 and a top selection gate opening 602 are formed on the side of the gate stack structure 20 away from the first substrate 10 , so that the contact hole 501 passes through the second top selection gate 2312 to the first top selection gate 2311 , and the top selection gate opening 602 passes through the first top selection gate 2311 .

[0059] In an optional embodiment, the step of forming the contact hole 501 and the top selection gate opening 602 includes: forming an interlayer dielectric layer 40 covering the gate stack structure 20 on the first substrate 10, such as Figure 4 Sequentially etching the interlayer dielectric layer 40 and the gate stack structure 20 to simultaneously form a contact hole 501 and a prepared opening 601 extending through the first top select gate 2311, as shown; Figure 5 etched through the prepared opening 601 of the gate stack structure 20 to form a top selection gate opening 602 through the first top selection gate 2311 to the isolation layer 220, as shown; Figure 6As shown, by adopting the above embodiment, the contact hole 501 and the top selection gate opening 602 can be formed in the same etching process, thereby simplifying the process flow and improving the process efficiency.

[0060] In the above embodiment, the material of the interlayer dielectric layer 40 may be a conventional insulating material. For example, the interlayer dielectric layer 40 is a silicon oxide layer.

[0061] In the above embodiment, the contact hole 501 and the preliminary opening 601 penetrating the interlayer dielectric layer 40 to the first top select gate 2311 can be formed by photolithography and etching processes. Exemplarily, the surface of the interlayer dielectric layer 40 is covered with photoresist, and a photoresist plate is placed on the side of the photoresist away from the interlayer dielectric layer 40. The photoresist is a positive photoresist, and the photoresist plate has a light-transmitting area corresponding to the pre-formed contact hole 501 and the top select gate opening 602. Then, the light-transmitting area in the photoresist plate is transferred to the photoresist through an exposure and development process, so that a corresponding hollow area is formed in the photoresist. The interlayer dielectric layer 40 and the gate stack structure 20 are sequentially etched through the hollow area to form the contact hole 501 and the preliminary opening 601 corresponding to the hollow area.

[0062] In the above embodiment, the gate stack structure 20 can be further etched through the prepared opening 601 by anisotropic etching, so that the prepared opening 601 extends into the isolation layer 220. The above anisotropic etching can be a conventional dry etching process. Those skilled in the art can reasonably select the etching gas according to the specific type of dielectric material, and this application does not make any specific limitations.

[0063] For example, Figure 6 As shown, the multi-layer isolation layer 220 includes a first isolation layer adjacent to the first top selection gate 2311. The first isolation layer is located on the side of the first top selection gate 2311 close to the first substrate 10. In the step of forming the top selection gate opening 602, anisotropic etching is used to etch the gate stack structure 20 through the prepared opening 601 so that the top selection gate opening 602 penetrates the first isolation layer.

[0064] In an optional embodiment, in the step of forming the contact hole 501 and the top selection gate opening 602, as shown in FIG. Figure 7 As shown, a contact hole unit 511 is formed on a side of the gate stack structure 20 away from the first substrate 10. The contact hole unit 511 includes multiple contact holes 501 distributed along a first direction (a cross section along the X direction, X-cut). The top select gate opening 602 extends along a second direction perpendicular to the first direction (a cross section along the Y direction, Y-cut). The contact holes 501 located in the contact hole unit 511 can have the same or different shapes, which is not specifically limited in this application.

[0065] In the above embodiment, for example, adjacent contact holes 501 in the contact hole unit 511 are arranged at equal intervals, such as Figure 7 The above arrangement can facilitate the design of the photomask in the photolithography process of the contact hole 501, thereby making it possible to adjust the photolithography window of the contact hole 501 so that a larger photolithography window can be provided between adjacent contact holes 501 of the contact unit 510, thereby reducing the process difficulty of the contact hole 501.

[0066] In the above embodiments, for example, Figure 7 As shown, the projections of the contact holes 501 in the contact hole unit 511 on the first substrate 10 have the same area. By making the projections of each contact hole 501 have the same area, it is not only easier to design the photomask in the photolithography process of adjacent contact holes, but also to adjust the photolithography window of the contact holes 501 in the same contact hole unit 511.

[0067] In an optional embodiment, if Figure 7 As shown, contact hole 501 has a first projection plane in first substrate 10, and in the second direction (a cross section along the Y direction, Y-cut), the first projection plane has a length L1. Top select gate opening 602 has a second projection plane in first substrate 10, and in the first direction (a cross section along the X direction, X-cut), the second projection plane has a length L2, where L1>L2. By ensuring this dimensional relationship between contact hole 501 and top select gate opening 602, it is possible to prevent material from filling contact hole 501 and becoming difficult to remove from top select gate cut line 60 during the subsequent process of forming top select gate cut line 60.

[0068] After the steps of forming the contact hole 501 and the top selection gate opening 602, as shown in FIG. Figures 8 to 12 As shown, a top selection gate cut line 60 is formed in the top selection gate opening 602 , and a contact portion 50 contacting the first top selection gate 2311 is formed in the contact hole 501 .

[0069] In an optional embodiment, the step of forming the top selection gate cut line 60 includes: depositing a first insulating material 70 on a side of the gate stack structure 20 away from the first substrate 10, so that a portion of the first insulating material 70 fills the top selection gate opening 602, as shown in FIG. Figure 8 Remove the first insulating material 70 outside the top select gate opening 602, the remaining first insulating material 70 constitutes the top select gate cut 60, as shown Figure 9 shown.

[0070] In the above embodiment, an atomic layer deposition (ALD) process can be used to deposit a first insulating material 70 on the side of the gate stack structure 20 away from the first substrate 10. The first insulating material 70 can be a conventional insulating material used to form the top selection gate cut line 60. Exemplarily, the above first insulating material 70 is silicon oxide.

[0071] In the above embodiment, a conventional wet etching process or a dry etching process can be used to remove the first insulating material 70 located outside the top selection gate opening 602. When the width of the contact hole 501 is much larger than the width of the top selection gate opening 602, the deposited first insulating material 70 only covers the inner surface of the contact hole 501 when filling the top selection gate opening 602, and the thickness of the first insulating material 70 located on the inner surface of the contact hole 501 is close to the thickness of the upper first insulating material 70 located on the surface of the interlayer dielectric layer 40. Therefore, the first insulating material 70 located in the contact hole 501 can be removed while the first insulating material 70 on the surface of the interlayer dielectric layer 40 is removed by etching, and the first insulating material 70 located in the top selection gate opening 602 can be retained by setting a mask layer.

[0072] In an optional embodiment, the step of forming the contact portion 50 includes: filling the contact hole 501 with a conductive material 502 to form a conductive portion in contact with the first top selection gate 2311, such as Figure 10 In other optional embodiments, the inner wall of the contact hole 501 is first covered with a conductive material 502, and then filled with a second insulating material 503, so that the conductive material 502 wraps the second insulating material 503, as shown. Figure 11 shown.

[0073] In the above embodiment, the contact hole 501 may be first filled with a conductive material 502, and then the portion of the conductive material 502 not in contact with the inner wall of the contact hole 501 may be removed so that the remaining conductive material 502 covers the inner wall of the contact hole 501. The region where the conductive material 502 was removed may then be filled with a second insulating material 503. For example, the conductive material 502 may be metal tungsten, and the second insulating material 503 may be silicon oxide.

[0074] According to another embodiment of the present application, a three-dimensional memory is provided, such as Figure 11 and Figure 12As shown, it includes: a first substrate 10 with a gate stack structure 20 on its surface, the gate stack structure 20 includes a multi-layer control gate structure 230 and a multi-layer isolation layer 220 alternating in a direction away from the first substrate 10, the gate stack structure 20 has a first surface away from the first substrate 10, the multi-layer control gate structure 230 includes a multi-layer top selection gate 231 close to the first surface, a layer of the top selection gate 231 closest to the first substrate 10 in the multi-layer top selection gate 231 is a first top selection gate 2311, and the remaining top selection gates are second top selection gates 2312; a channel structure 30, which runs through the core storage area to the first substrate 10; a top selection gate cut line 60, which runs through the first top selection gate 2311; and a contact portion 50, which runs through the second top selection gate 2312 to the first top selection gate 2311.

[0075] In the three-dimensional memory of the present application, since the contact portion 50 can contact each top selection gate 231 , there is no need to form multiple rows of contact holes 501 contacting each top selection gate 231 , which saves the process window and is conducive to device miniaturization.

[0076] The gate stack structure 20 includes a control gate structure 230 and an isolation layer 220 alternately stacked in a direction away from the first substrate 10. Figure 11 As shown, those skilled in the art can reasonably set the number of layers of the control gate structure 230 and the isolation layer 220 according to actual needs. The isolation layer 220 can be SiO2, but is not limited to the above types. Those skilled in the art can also reasonably select the type of the isolation layer 220.

[0077] The control gate structure 230 includes a gate layer, which is located between adjacent isolation layers 220. The control gate structure 230 may also include a high-k dielectric layer, at least a portion of which is disposed between the gate layer and the channel structure 30 to form a gate dielectric layer. The contact portion 50 is disposed through the high-k dielectric layer and in contact with the gate layer. The high-k dielectric layer and the gate layer together constitute the control gate structure 230.

[0078] In the above-mentioned three-dimensional memory of the present application, the gate stack structure 20 may include a core storage area and a non-core storage area. The above-mentioned core storage area is used to form a channel array, and the channel array includes a channel structure 30 that penetrates the first substrate 10 and corresponds one-to-one to the channel hole. Multiple channel structures 30 may also be distributed in the above-mentioned non-core storage area to form a pseudo-channel array, which is used to support the isolation layer 220 when the control gate structure 230 is replaced.

[0079] In an optional embodiment, as Figure 12As shown, the three-dimensional memory includes a contact unit 510, which includes multiple contacts 50 distributed along a first direction (a cross section along the X direction, X-cut). The top select gate cut line 60 extends along a second direction (a cross section along the Y direction, Y-cut) perpendicular to the first direction. The contacts 50 in the contact unit 510 can have the same or different shapes, which is not specifically limited in this application.

[0080] In an optional embodiment, if Figure 12 As shown, the contact portion 50 has a first cross-section in a direction parallel to the first substrate 10, and in the second direction (a section along the Y direction, Y-cut), the length of the first cross-section is L3. The top selection gate cut line 60 has a second cross-section in a direction parallel to the first substrate 10, and in the first direction (a section along the X direction, X-cut), the length of the second cross-section is L4, and L3>L4.

[0081] In one embodiment of the present application, adjacent contact portions 50 in the contact portion unit 510 are arranged at equal intervals, such as Figure 12 The above arrangement not only facilitates the design of the photoresist plate in the photolithography process of the contact holes, but also enables the photolithography windows of adjacent contact holes to be evenly expanded, thereby reducing the difficulty of the photolithography process.

[0082] In one embodiment of the present application, the projections of the contact portions 50 in the contact portion unit 510 on the first substrate 10 have the same area, such as Figure 12 By making the projections of each contact portion 50 have the same area, not only can the design of the photomask in the photolithography process of adjacent contact holes be facilitated, but also the spacing between adjacent contact holes can be adjusted so that the contact holes have photolithography windows of approximately the same size, thereby reducing the difficulty of the photolithography process.

[0083] The three-dimensional memory of the present application may further include a CMOS device disposed on the second substrate, and the CMOS device is electrically connected to the contact portion 50 via a bonding portion.

[0084] According to an embodiment of the present application, a storage system 20000 is further provided. Figure 13 2 is an internal block diagram of a storage system 20000 according to an embodiment of the present application. Figure 13 As shown, the memory system 20000 may include a three-dimensional memory 1000 and a controller 2000 .

[0085] The three-dimensional memory 1000 may be the same as the three-dimensional memory described in any of the above embodiments, and will not be described in detail in this application.

[0086] The controller 2000 can control the three-dimensional memory 1000 via a channel CH, and the three-dimensional memory 1000 can perform operations based on the control of the controller 2000 in response to a request from the host 3000. The three-dimensional memory 1000 can receive a command CMD and an address ADDR from the controller 2000 via the channel CH and access a region selected from the memory cell array in response to the address. In other words, the three-dimensional memory 1000 can perform internal operations corresponding to the command on the region selected by the address.

[0087] In some embodiments, the above-mentioned storage system can be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0088] An embodiment of the present application further provides an electronic device, including: the above-mentioned memory structure.

[0089] In the above-mentioned embodiments of the present application, the electronic device includes at least one of the following: a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a wearable device, and a mobile power bank. In this embodiment, the memory structure of the present application can be applied to any electronic device. Because the memory structure of the present application reduces leakage problems caused by defects and improves product reliability, the performance of electronic devices using this memory structure is further improved. Figure 14 A schematic diagram of the structure of a mobile phone according to an embodiment of the present application is shown. Figure 14 As shown, the mobile phone 10000 includes a chip 4000 adopting the memory structure of the present application.

[0090] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0091] 1. The formed contact portion can contact each top select gate, eliminating the need to form multiple rows of contact holes for contacting each top select gate, thus saving process windows and facilitating device miniaturization.

[0092] 2. The contact hole and the top selection gate opening can be formed in the same etching process, thereby simplifying the process flow and improving process efficiency.

[0093] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that: The following steps are involved: Providing a first substrate having a gate stack structure on its surface, the gate stack structure comprising a multi-layer control gate structure and a multi-layer isolation layer alternating in a direction away from the first substrate, the gate stack structure having a first surface away from the first substrate, the multi-layer control gate structure comprising a multi-layer top select gate close to the first surface, a top select gate layer closest to the first substrate among the multi-layer top select gates being a first top select gate, and the remaining top select gates being second top select gates; forming a contact hole and a top select gate opening on a side of the gate stack structure away from the first substrate, wherein the contact hole passes through the second top select gate to the first top select gate, and the top select gate opening passes through the first top select gate; A top selection gate cut line is formed in the top selection gate opening, and a contact portion contacting the first top selection gate is formed in the contact hole.

2. The production method according to claim 1, characterized in that The step of forming the contact hole and the top select gate opening comprises: forming an interlayer dielectric layer covering the gate stack structure on the first substrate; Sequentially etching the interlayer dielectric layer and the gate stack structure to simultaneously form the contact hole and the preliminary opening penetrating to the first top select gate; The gate stack structure is etched through the prepared opening to form the top select gate opening penetrating the first top select gate to the isolation layer.

3. The production method according to claim 2, characterized in that: The multi-layer isolation layer includes a first isolation layer adjacent to the first top selection gate, and the first isolation layer is located on a side of the first top selection gate close to the first substrate. In the step of forming the top selection gate opening, the gate stack structure is etched through the prepared opening so that the top selection gate opening passes through the first isolation layer.

4. The production method according to any one of claims 1 to 3, characterized in that In the step of forming the contact hole and the top selection gate opening, a contact hole unit is formed on the side of the gate stack structure away from the first substrate, and the contact hole unit includes a plurality of contact holes distributed along a first direction, and the top selection gate opening extends along a second direction, and the second direction is perpendicular to the first direction.

5. The production method according to claim 4, characterized in that: The contact hole has a first projection surface in the first substrate, the top selection gate opening has a second projection surface in the first substrate, and a length of the first projection surface along the second direction is greater than a length of the second projection surface along the first direction.

6. The manufacturing method according to claim 5, characterized in that: The step of forming the top selection gate cut line includes: Depositing a first insulating material on a side of the gate stack structure away from the first substrate, so that a portion of the first insulating material fills the top select gate opening; The first insulating material outside the top selection gate opening is removed, and the remaining first insulating material constitutes the top selection gate cut line.

7. The production method according to claim 6, characterized in that: The step of forming the contact portion includes: filling the contact hole with a conductive material to form a conductive portion contacting the first top selection gate; or The inner wall of the contact hole is covered with a conductive material to form a conductive portion contacting the first top selection gate, and the contact hole is filled with a second insulating material so that the conductive portion wraps the second insulating material.

8. A three-dimensional memory, characterized in that: include: a first substrate having a gate stack structure on its surface, the gate stack structure comprising a multi-layer control gate structure and a multi-layer isolation layer alternating in a direction away from the first substrate, the gate stack structure having a first surface away from the first substrate, the multi-layer control gate structure comprising a multi-layer top select gate close to the first surface, a top select gate layer closest to the first substrate among the multi-layer top select gates being a first top select gate, and the remaining top select gates being second top select gates; a top selection gate cut line, passing through the first top selection gate; A contact portion passes through the second top selection gate to the first top selection gate.

9. The three-dimensional memory according to claim 8, characterized in that The three-dimensional memory includes a contact unit, wherein the contact unit includes a plurality of contacts distributed along a first direction, and the top selection gate cut line extends along a second direction, which is perpendicular to the first direction.

10. The three-dimensional memory according to claim 9, wherein: The contact portion has a first cross section in a direction parallel to the first substrate, the top selection gate cut line has a second cross section in a direction parallel to the first substrate, and a length of the first cross section along the second direction is greater than a length of the second cross section along the first direction.

11. The three-dimensional memory according to claim 9, wherein: The three-dimensional memory further includes: a second substrate having a CMOS device on its surface; The bonding portion is used to connect the CMOS device to the contact portion.

12. A storage system comprising a controller and a three-dimensional memory, wherein the three-dimensional memory is configured to store data, the controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory, wherein: The three-dimensional memory is manufactured by the method for manufacturing a three-dimensional memory according to any one of claims 1 to 7, or the three-dimensional memory is the three-dimensional memory according to any one of claims 8 to 11.

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