Multi-level buck converter and its control circuit

Abstract

The present invention discloses a multi-level buck converter and a control circuit thereof. The multi-level buck converter converts an input voltage signal into an output voltage signal. The multi-level buck converter has N pairs of switches, where N is an integer greater than or equal to 2. The control circuit includes a comparison circuit, a selection circuit, and N COT controllers. The comparison circuit compares a voltage feedback signal representing the output voltage signal with a reference signal to generate a comparison signal. The selection circuit receives the comparison signal and generates N set signals based on the comparison signal. Each COT controller receives an output voltage signal, an input voltage signal, and a corresponding set signal, and generates a control signal based on the output voltage signal, the input voltage signal, and the set signal to control the corresponding pair of switches to complementarily turn on and off.

Description

Technical Field

[0001] The present invention relates to an electronic circuit, in particular to a multi-level buck converter and a control circuit thereof. Background Art

[0002] Multilevel buck converters offer many advantages over traditional (single-phase) buck converters. For example, the voltage stress on the switches of a multilevel buck converter is lower than that of a traditional buck converter. Furthermore, at the same switching frequency, the ripple of a multilevel buck converter is significantly lower than that of a traditional buck converter.

[0003] Figure 1 is a three-level buck converter. Figure 1 As shown in FIG, a three-level buck converter includes a first flying capacitor C1, an inductor LOUT, a capacitor COUT, and switches M1a, M1b, M2a, and M2b. Therefore, the three-level buck converter has four switching states: 00, 01, 10, and 11. "1" indicates that the high-side switch (e.g., M1a or M2a) is on and the corresponding low-side switch (e.g., M1b or M2b) is off, while "0" indicates that the high-side switch is off and the corresponding low-side switch is on. In each switching state, only two of the four switches are on.

[0004] In switching state 00, switches M1a and M2a are off, while switches M1b and M2b are on. The current flowing through inductor LOUT flows sequentially through switches M1b and M2b. In switching state 01, switches M1a and M2b are off, while switches M1b and M2a are on. The first flying capacitor C1 is discharged, and the switch node voltage VSW is 1 / 2 of the input voltage VIN of the three-level buck converter. In switching state 10, switches M1a and M2b are on, while switches M1b and M2a are off. The input voltage VIN charges the first flying capacitor C1, and the switch node voltage VSW is 1 / 2VIN. In switching state 11, switches M1a and M2a are on, while switches M1b and M2b are off. The switch node voltage VSW is equal to the input voltage VIN. Table 1 summarizes the four switching states of the three-level buck converter.

[0005] Table 1 Switching states of three-level buck converter

[0006] state 00 01 10 11 M1a Shutdown Shutdown conduction conduction M2a Shutdown conduction Shutdown conduction M1b conduction conduction Shutdown Shutdown M2b conduction conduction Shutdown Shutdown

[0007] Table 2 shows the switch node voltage VSW and the potentials of the first terminal C1+ and the second terminal C1- of the first flying capacitor C1 in different switching states.

[0008] Table 2 Potentials under different switching states

[0009] state VSW C1+ C1- 00 0V 1 / 2VIN 0V 01 1 / 2VIN 1 / 2VIN 0V 10 1 / 2VIN VIN 1 / 2VIN 11 VIN VIN 1 / 2VIN

[0010] As can be seen in Table 2, the potential of the switch node voltage VSW switches between logic ground (0V), half the input voltage vIN (1 / 2VIN), and the input voltage VIN. Compared to a conventional buck converter, the root-mean-square (RMS) value of the switch node voltage VSW in a three-level buck converter is reduced by 50%, which reduces the voltage stress on the switches and the breakdown voltage rating of the switches. Therefore, a multi-level buck converter can reduce switching losses.

[0011] Multilevel buck converters offer superior performance compared to traditional buck converters, but their regulation complexity increases. Furthermore, multilevel buck converters face control stability issues not encountered in traditional buck converters, particularly when switching from one operating state to another. A common solution is to restrict the multilevel buck converter to operating in only one of these operating states, but this can limit the duty cycle range. Therefore, this application proposes a control scheme for a multilevel buck converter with a wide duty cycle range and good stability. Summary of the Invention

[0012] In view of the problems existing in the prior art, an object of the present invention is to provide a multi-level buck converter and a control circuit having a wide duty cycle range and good stability.

[0013] According to one embodiment of the present invention, a control circuit for a multi-level buck converter is provided. The multi-level buck converter includes N pairs of switches coupled in series between an input terminal and a logic ground. The multi-level buck converter converts an input voltage signal at the input terminal into an output voltage signal at the output terminal, where N is an integer greater than or equal to 2. The control circuit includes a comparison circuit, a selection circuit, and N COT controllers. The comparison circuit receives a reference signal and a voltage feedback signal representing an output voltage signal, and compares the reference signal and the voltage feedback signal to generate a comparison signal. The selection circuit receives the comparison signal and generates N set signals based on the comparison signal. For each i=1, 2, ..., N, the i-th COT controller receives the output voltage signal, the input voltage signal, and the i-th set signal, and generates an i-th control signal based on the output voltage signal, the input voltage signal, and the i-th set signal to control the corresponding i-th pair of switches to complementarily turn on and off.

[0014] According to another embodiment of the present invention, a multi-level buck converter is provided for converting an input voltage signal at an input terminal into an output voltage signal at an output terminal. The multi-level buck converter includes N pairs of switches coupled in series between an input terminal and a logic ground, where N is an integer greater than or equal to 2. The converter also includes a comparison circuit, a selection circuit, and N COT controllers. The comparison circuit receives a reference signal and a voltage feedback signal representing an output voltage, and compares the reference signal with the voltage feedback signal to generate a comparison signal. The selection circuit receives the comparison signal and generates N set signals based on the comparison signal. For each i=1, 2, ..., N, the i-th COT controller receives the i-th set signal, the output voltage signal, and the input voltage signal, and generates the i-th control signal based on the i-th set signal, the output voltage signal, and the input voltage signal to control the i-th pair of switches to complementarily turn on and off.

[0015] According to another embodiment of the present invention, a multi-level buck converter is provided for converting an input voltage signal at an input terminal into an output voltage signal at an output terminal. The multi-level buck converter includes two pairs of switches coupled in series between an input terminal and a logic ground, a comparison circuit, a selection circuit, a first COT controller, and a second COT controller. The comparison circuit receives a reference signal and a voltage feedback signal representing an output voltage, and compares the reference signal with the voltage feedback signal to generate a comparison signal. The selection circuit receives the comparison signal and generates a first set signal and a second set signal based on the comparison signal. The first COT controller receives the first set signal, an output voltage signal, and an input voltage signal, and generates a first control signal based on the first set signal, the output voltage signal, and the input voltage signal to control the first pair of switches to be complementary turned on and off. The second COT controller receives the second set signal, the output voltage signal, and the input voltage signal, and generates a second control signal based on the second set signal, the output voltage signal, and the input voltage signal to control the second pair of switches to be complementary turned on and off.

[0016] According to the embodiment of the present invention, the multi-level buck converter can switch between multiple working states, has a wide duty cycle range, and has good stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a three-level buck converter;

[0018] Figure 2 A four-level buck converter 100 according to an embodiment of the present invention;

[0019] Figure 3 is a switching state of a four-level buck converter 100 according to an embodiment of the present invention;

[0020] Figure 4200 is a working waveform diagram of a four-level buck converter with a duty cycle of 0 to 1 / 3 according to an embodiment of the present invention;

[0021] Figure 5 300 is an operating waveform diagram of a four-level buck converter with a duty cycle of 1 / 3 to 2 / 3 according to yet another embodiment of the present invention;

[0022] Figure 6 400 is an operating waveform diagram of a four-level buck converter with a duty cycle of 2 / 3 to 1 according to yet another embodiment of the present invention;

[0023] Figure 7 According to one embodiment of the present invention Figure 2 The selection circuit 20 shown;

[0024] Figure 8 According to one embodiment of the present invention Figure 2 The first COT controller 301 is shown;

[0025] Figure 9 According to one embodiment of the present invention Figure 8 The on-time generating circuit 3011 is shown;

[0026] Figure 10 According to one embodiment of the present invention Figure 2 The comparison circuit 10 shown;

[0027] Figure 11 A four-level buck converter 500 according to yet another embodiment of the present invention;

[0028] Figure 12 A four-level buck converter 600 according to yet another embodiment of the present invention;

[0029] Figure 13 A multi-level buck converter 700 according to an embodiment of the present invention;

[0030] Figure 14 According to one embodiment of the present invention Figure 13 The delay circuit 50 is shown. DETAILED DESCRIPTION

[0031] Specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the present invention. In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that these specific details are not necessarily required to practice the present invention. In other instances, well-known circuits, materials, or methods are not specifically described to avoid obscuring the present invention.

[0032] Throughout this specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout this specification do not necessarily all refer to the same embodiment or example. Furthermore, particular features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples. Furthermore, those skilled in the art will appreciate that the figures provided herein are for illustrative purposes only and are not necessarily drawn to scale. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements. Identical reference numerals indicate identical elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] Figure 2 1 is a four-level buck converter 100 according to an embodiment of the present invention. Figure 2 In the illustrated embodiment, a four-level buck converter 100 has an input terminal and an output terminal, wherein the input terminal receives an input voltage signal VIN and the output terminal provides an output voltage signal VOUT. The four-level buck converter 100 includes three pairs of switches (M1a, M1b, M2a, M2b, M3a, and M3b), a first flying capacitor C1, a second flying capacitor C2, an output capacitor COUT, and an inductor LOUT. Specifically, the first high-side switch M1a, the second high-side switch M2a, and the third high-side switch M3a are sequentially coupled in series between the input terminal of the four-level buck converter 100 and a switch node SW, and the first low-side switch M1b, the second low-side switch M2b, and the third low-side switch M3b are sequentially coupled in series between a logic ground and the switch node SW. The first flying capacitor C1 is coupled between a common connection point between the first high-side switch M1a and the second high-side switch M2a and a common connection point between the first low-side switch M1b and the second low-side switch M2b. The second flying capacitor C2 is coupled between a common connection point between the second high-side switch M2a and the third high-side switch M3a and a common connection point between the second low-side switch M2b and the third low-side switch M3b. The inductor LOUT is coupled between the switch node SW and the output terminal of the four-level buck converter 100. The output capacitor COUT is coupled between the output terminal of the four-level buck converter 100 and logic ground.

[0034] The switch node voltage VSW includes four potentials: 1 / 3 of the input voltage signal VIN (1 / 3VIN), 2 / 3 of the input voltage signal VIN (2 / 3VIN), the input voltage signal VIN, and logic ground (0V).

[0035] exist Figure 2 In the illustrated embodiment, the four-level buck converter 100 includes a control circuit comprising a comparison circuit 10 , a selection circuit 20 , and first, second, and third constant on time (COT) controllers 301 , 302 , and 303 .

[0036] The comparison circuit 10 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives a voltage feedback signal VFB representing the output voltage signal VOUT, and the second input terminal receives a reference signal VREF. The comparison circuit 10 compares the voltage feedback signal VFB with the reference signal VREF and generates a comparison signal CA at its output terminal. The comparison signal CA can be a logic signal having an active state (e.g., a logic high state) and an inactive state (e.g., a logic low state). In one embodiment, when the voltage feedback signal VFB is less than the reference signal VREF, the comparison signal CA is active; when the voltage feedback signal VFB is greater than the reference signal VREF, the comparison signal CA is inactive. In one embodiment, the comparison circuit 10 includes a voltage comparator 101 having a non-inverting input terminal, an inverting input terminal, and an output terminal. In one embodiment, the inverting input terminal of the voltage comparator 101 serves as the first input terminal of the comparison circuit 10, and the non-inverting input terminal serves as the second input terminal of the comparison circuit 10.

[0037] The selection circuit 20 receives a comparison signal CA and generates first, second, and third set signals (CA1, CA2, and CA3) based on the comparison signal CA. The first, second, and third set signals (CA1, CA2, and CA3) can be logic signals having an active state (e.g., a logic high state) and an inactive state (e.g., a logic low state). Each of the three set signals (CA1, CA2, and CA3) triggers a corresponding COT controller when it switches from an inactive state to an active state. In one embodiment, upon the arrival of a rising edge of the comparison signal CA, the three set signals (CA1, CA2, and CA3) switch from an inactive state to an active state in turn. For example, when the rising edge of the comparison signal CA arrives for the first time, only the first set signal CA1 switches to an active state; when the rising edge of the comparison signal CA arrives for the second time, only the second set signal CA2 switches to an active state; when the rising edge of the comparison signal CA arrives for the third time, only the third set signal CA3 switches to an active state; when the rising edge of the comparison signal CA arrives for the fourth time, the first set signal CA1 switches to an active state again, and so on.

[0038] The first COT controller 301 receives the output voltage signal VOUT, the input voltage signal VIN, and a first set signal CA1. When the first set signal CA1 is active, the first COT controller 301 generates a first control signal PWM1 based on the output voltage signal VOUT, the input voltage signal VIN, and the first set signal CA1 to control the first pair of switches M1a and M1b. In one embodiment, when the first set signal CA1 is active, the first control signal PWM1 turns on the first high-side switch M1a and turns off the first low-side switch M1b.

[0039] The second COT controller 302 receives the output voltage signal VOUT, the input voltage signal VIN, and the second set signal CA2. When the second set signal CA2 is active, the second COT controller 302 generates a second control signal PWM2 based on the output voltage signal VOUT, the input voltage signal VIN, and the second set signal CA2 to control the second pair of switches M2a and M2b. In one embodiment, when the second set signal CA2 is active, the second control signal PWM2 turns on the second high-side switch M2a and turns off the second low-side switch M2b.

[0040] The third COT controller 303 receives the output voltage signal VOUT, the input voltage signal VIN, and a third set signal CA3. When the third set signal CA3 is active, the third COT controller 303 generates a third control signal PWM3 based on the output voltage signal VOUT, the input voltage signal VIN, and the third set signal CA3 to control the third pair of switches M3a and M3b. In one embodiment, when the third set signal CA3 is active, the third control signal PWM3 turns on the third high-side switch M3a and turns off the third low-side switch M3b.

[0041] In one embodiment, each of the first to third control signals PWM1-PWM3 includes a high-side control signal and a low-side control signal to control a corresponding pair of switches. For example, the first control signal PWM1 includes a first high-side control signal PWM1a and a first low-side control signal PWM1b (e.g., Figure 8 ), to control the first high-side switch M1a and the first low-side switch M1b to alternately and complementary turn on and off, respectively. That is, when the first high-side switch M1a is on, the first low-side switch M1b is off, and vice versa. Similarly, the second control signal PWM2 controls the second high-side switch M2a and the second low-side switch M2b to alternately and complementary turn on and off, and the third control signal PWM3 controls the third high-side switch M3a and the third low-side switch M3b to alternately and complementary turn on and off.

[0042] Figure 3represents the switching states of a four-level buck converter 100 according to one embodiment of the present invention. Four-level buck converter 100 has eight switching states: 000, 100, 010, 001, 110, 011, 101, and 111, where "1" indicates that the high-side switch (e.g., M1a, M2a, or M3a) is on and the corresponding low-side switch (e.g., M1b, M2b, or M3b) is off, while "0" indicates that the high-side switch is off and the corresponding low-side switch is on. In each switching state, only three of the six switches are on.

[0043] In the switching state 000 , the switches M1 a , M2 a , and M3 a are turned off, the switches M1 b , M2 b , and M3 b are turned on, and the current IL flowing through the inductor LOUT flows through the switches M1 b , M2 b , and M3 b in sequence.

[0044] In switching state 100 , switches M1a, M2b, and M3b are turned on, while switches M1b, M2a, and M3a are turned off. The input voltage signal VIN charges the first flying capacitor voltage C1, and the switch node voltage VSW is 1 / 3 VIN. Meanwhile, the second flying capacitor C2 is left floating during switching state 100 .

[0045] In the switching state 010 , the switches M1 a , M2 b , and M3 a are turned off, the switches M1 b , M2 a , and M3 b are turned on, the first flying capacitor C1 is discharged, the second flying capacitor C2 is charged, and the switch node voltage VSW is 1 / 3 VIN.

[0046] In switch state 001, switches M1a, M2a, and M3b are turned off, switches M1b, M2b, and M3a are turned on, the second flying capacitor C2 is discharged, and the switch node voltage VSW is 1 / 3 VIN. Meanwhile, the first flying capacitor C1 is suspended during switch state 001.

[0047] In the switching state 110 , switches M1a, M2a, and M3b are turned on, switches M1b, M2b, and M3a are turned off, the input voltage signal VIN charges the second flying capacitor C2, and the switch node voltage VSW is 2 / 3 VIN. Meanwhile, the first flying capacitor C1 is suspended during the switching state 110 .

[0048] In switch state 011, switches M1a, M2b, and M3b are turned off, switches M1b, M2a, and M3a are turned on, the first flying capacitor C1 is discharged, and the switch node voltage VSW is 2 / 3 VIN. Meanwhile, the second flying capacitor C2 is suspended during switch state 011.

[0049] In the switching state 101 , the switches M1 a , M2 b , and M3 a are turned on, the switches M1 b , M2 a , and M3 b are turned off, the first flying capacitor C1 is charged, the second flying capacitor C2 is discharged, and the switch node voltage VSW is 2 / 3 VIN.

[0050] In the switching state 111 , the switches M1 a , M2 a , and M3 a are turned on, the switches M1 b , M2 b , and M3 b are turned off, and the switch node voltage VSW is equal to the input voltage signal VIN.

[0051] Table 3 summarizes the eight switching states of the four-level buck converter 100 .

[0052] Table 3 Switching states of four-level buck converter

[0053] state 000 001 010 011 100 101 110 111 M1a Shutdown Shutdown Shutdown Shutdown conduction conduction conduction conduction M2a Shutdown Shutdown conduction conduction Shutdown Shutdown conduction conduction M3a Shutdown conduction Shutdown conduction Shutdown conduction Shutdown conduction M1b conduction conduction conduction conduction Shutdown Shutdown Shutdown Shutdown M2b conduction conduction Shutdown Shutdown conduction conduction Shutdown Shutdown M3b conduction Shutdown conduction Shutdown conduction Shutdown conduction Shutdown

[0054] In addition, Table 4 shows the switch node voltage VSW, the potentials of the first terminal C1+ and the second terminal C1 − of the first flying capacitor C1 , and the first terminal C2+ and the second terminal C2 − of the second flying capacitor C2 in different switching states.

[0055] Table 4 Potentials under different switching states

[0056] state VSW C1+ C2+ C1- C2- 000 0V 2 / 3VIN 1 / 3 VIN 0V 0V 001 1 / 3 VIN VIN 2 / 3VIN 1 / 3 VIN 1 / 3 VIN 010 1 / 3 VIN 2 / 3VIN 2 / 3VIN 0V 1 / 3 VIN 011 1 / 3 VIN 2 / 3VIN 1 / 3 VIN 0V 0V 100 2 / 3VIN VIN VIN 1 / 3 VIN 2 / 3VIN 101 2 / 3VIN 2 / 3VIN 2 / 3VIN 0V 1 / 3 VIN 110 2 / 3VIN VIN 2 / 3VIN 1 / 3 VIN 1 / 3 VIN 111 VIN VIN VIN 1 / 3 VIN 2 / 3VIN

[0057] Compared to conventional buck converters, the RMS value of the switch node voltage VSW of the four-level buck converter 100 is reduced by 2 / 3. As can be seen from Table 4, the potential of the switch node voltage VSW switches between logic ground (0V), 1 / 3 of the input voltage VIN (1 / 3VIN), 2 / 3 of the input voltage VIN (2 / 3VIN), and the input voltage VIN. Simultaneously, by controlling the six switches to switch between eight switching states, the four-level buck converter 100 has first, second, and third operating states. Specifically, in the first operating state, the output voltage signal VOUT is less than 1 / 3 of the input voltage signal VIN, and the switch node voltage VSW switches between 0V and 1 / 3 VIN. In the second operating state, the output voltage signal VOUT is between 1 / 3 and 2 / 3 of the input voltage signal VIN, and the switch node voltage VSW switches between 1 / 3 VIN and 2 / 3 VIN. In the third working state, the output voltage signal VOUT is between 2 / 3 of the input voltage signal VIN and the input voltage signal VIN, and the switch node voltage VSW switches between 2 / 3 VIN and VIN.

[0058] Figure 4 FIG2 is an operating waveform diagram 200 of a four-level buck converter with a duty cycle of 0 to 1 / 3 according to an embodiment of the present invention. In one embodiment, the duty cycle of the four-level buck converter is defined as the ratio of the output voltage signal VOUT to the input voltage signal VIN. A duty cycle of 0 to 1 / 3 indicates that the output voltage signal VOUT ranges from 0 to 1 / 3 VIN. Figure 4As shown, Figure 200 shows, from top to bottom, the waveforms of the feedback signal VFB, the reference signal VREF, the first to third control signals PWM1-PWM3, and the switch node voltage VSW. During a switching cycle T, the corresponding state switching sequence is as follows: 100, 000, 010, 000, 001, and 000. The first to third control signals PWM1-PWM3 have a phase shift of 120° within a switching cycle T. That is, the first high-side switch M1a, the second high-side switch M2a, and the third high-side switch M3a are turned on sequentially within a switching cycle T. The duty cycle range of the four-level buck converter 100 is 0 to 1 / 3. Therefore, the on-time D1 of each switch (M1a, M2a, and M3a) is between 0 and 1 / 3T depending on the change in the output voltage signal VOUT.

[0059] Figure 5 FIG3 is an operating waveform diagram 300 of a four-level buck converter with a duty cycle of 1 / 3 to 2 / 3 according to another embodiment of the present invention. The duty cycle of 1 / 3 to 2 / 3 indicates that the range of the output voltage signal VOUT is 1 / 3VIN to 2 / 3VIN. Figure 5 As shown, Figure 300 shows, from top to bottom, the waveforms of the feedback signal VFB, the reference signal VREF, the first to third control signals PWM1-PWM3, and the switch node voltage VSW. During a switching cycle T, the corresponding state switching sequence is as follows: 101, 100, 110, 010, 011, and 001. The first to third control signals PWM1-PWM3 have a phase shift of 120° within a switching cycle T. That is, the first high-side switch M1a, the second high-side switch M2a, and the third high-side switch M3a are turned on sequentially within a switching cycle T. The duty cycle range of the four-level buck converter 100 is 1 / 3 to 2 / 3. Therefore, depending on the change in the output voltage signal VOUT, the on-time D2 of each switch (M1a, M2a, and M3a) is between 1 / 3T and 2 / 3T.

[0060] Figure 6 FIG4 is an operating waveform diagram 400 of a four-level buck converter with a duty cycle of 2 / 3 to 1 according to another embodiment of the present invention. The duty cycle of 2 / 3 to 1 indicates that the range of the output voltage signal VOUT is 2 / 3VIN to VIN. Figure 6As shown, Figure 400 shows, from top to bottom, the waveforms of the feedback signal VFB, the reference signal VREF, the first to third control signals PWM1-PWM3, and the switch node voltage VSW. During a switching cycle T, the corresponding state switching sequence is as follows: 101, 100, 110, 010, 011, and 001. The first to third control signals PWM1-PWM3 have a phase shift of 120° within a switching cycle T. That is, the first high-side switch M1a, the second high-side switch M2a, and the third high-side switch M3a are turned on sequentially within a switching cycle T. The duty cycle range of the four-level buck converter 100 is 2 / 3 to 1. Therefore, the on-time D3 of each switch (M1a, M2a, and M3a) is between 2 / 3T and T according to the change in the output voltage signal VOUT.

[0061] Figure 7 According to one embodiment of the present invention Figure 2 The selection circuit 20 shown. Figure 7 As shown, the selection circuit 20 includes a first AND gate circuit 201, a second AND gate circuit 202, a third AND gate circuit 203, and an enable circuit 204. The enable circuit 204 receives a comparison signal CA and generates first, second, and third enable signals EN1, EN2, and EN3 based on the comparison signal CA. In one embodiment, the first enable signals EN1-EN3 can be logic signals having an active state (e.g., a logic high state) and an inactive state (e.g., a logic low state). In one embodiment, the first enable signals EN1-EN3 alternately transition from an inactive state to an active state. For example, one of the enable signals (e.g., the first enable signal EN1) is initially active. After the rising edge of the comparison signal CA reaches a specific time for the first time, the first enable signal EN1 switches to an inactive state, and the second enable signal EN2 switches from an inactive state to an active state. Similarly, after the rising edge of the comparison signal CA reaches a specific time for the second time, the second enable signal EN2 switches to an inactive state, and the third enable signal EN3 switches from an inactive state to an active state. In the next switching cycle, after the rising edge of the comparison signal CA reaches the specified time for the third time, the first enable signal EN1 is switched to the active state again, and the third enable signal EN3 is switched to the inactive state, and so on. In one embodiment, the specified time is less than 1 / 3T and can be set according to the specific application.

[0062] The first AND gate circuit 201 receives the comparison signal CA and the first enable signal EN1 , and performs a logic AND operation on the comparison signal CA and the first enable signal EN1 to generate a first set signal CA1 .

[0063] The second AND gate circuit 202 receives the comparison signal CA and the second enable signal EN2 , and performs a logic AND operation on the comparison signal CA and the second enable signal EN2 to generate a second set signal CA2 .

[0064] The third AND gate circuit 203 receives the comparison signal CA and the third enable signal EN3 , and performs a logic AND operation on the comparison signal CA and the third enable signal EN3 to generate a third set signal CA3 .

[0065] Figure 8 According to one embodiment of the present invention Figure 2 The first COT controller 301 is shown. Figure 8 As shown, the first COT controller 301 includes an on-time generation circuit 3011 and a logic circuit 3012. The on-time generation circuit 3011 receives a first set signal CA1, an input voltage signal VIN, and an output voltage signal VOUT to generate an on-time signal TON. The on-time signal TON can be a logic signal with an active state and an inactive state. The logic circuit 3012 receives the first set signal CA1 and the on-time signal TON and performs a logic operation on the first set signal CA1 and the on-time signal TON to generate a first control signal PWM1. In one embodiment, the logic circuit 3012 includes a RS flip-flop FFL. The RS flip-flop FFL has a set terminal S, a reset terminal R, a first output terminal Q1, and a second output terminal Q2. The set terminal S receives the first set signal CA1, and the reset terminal R receives the on-time signal TON. The RS flip-flop FFL generates a first high-side control signal PWM1a and a first low-side control signal PWM1b at the first output terminal Q1 and the second output terminal Q2, respectively.

[0066] Those skilled in the art will understand that Figure 8 Only schematically shown Figure 2 The implementation of the first COT controller 301, the second and third COT controllers 302 and 303 are similar to the first COT controller 301, and are not described again here.

[0067] Figure 9 According to one embodiment of the present invention Figure 8 The conduction time generating circuit 3011 is shown. Figure 9As shown, the on-time generation circuit 3011 includes a controlled current generation circuit 911, a controlled voltage generation circuit 912, a capacitor 913, a comparator 914, and a reset switch 915. The controlled current generation circuit 911 has a first terminal and a second terminal, wherein the first terminal receives an input voltage signal VIN. The controlled current generation circuit 911 generates a controlled current signal ICH based on the input voltage signal VIN. In one embodiment, the controlled current signal ICH is proportional to the input voltage signal VIN. The capacitor 913 is coupled between the second terminal of the controlled current generation circuit 911 and a logic ground. The controlled current signal ICH charges the capacitor 913 to generate a capacitor voltage signal VC across the capacitor 913. The controlled voltage generation circuit 912 receives the output voltage signal VOUT to generate a controlled voltage signal VD. In one embodiment, the controlled voltage signal VD is proportional to the output voltage signal VOUT. The comparator 914 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the controlled voltage signal VD, and the second input terminal receives the capacitor voltage signal VC. Comparator 914 compares the controlled voltage signal VD with the capacitor voltage signal VC and generates an on-time signal TON at its output terminal. Reset switch 915 has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the second terminal of controlled current generating circuit 911, the second terminal is coupled to logic ground, and the control terminal receives a first set signal CA1. When the first set signal CA1 controls reset switch 915 to turn on, capacitor 913 discharges through reset switch 915. When the first set signal CA1 controls reset switch 915 to turn off, controlled current signal ICH charges capacitor 913.

[0068] Figure 10 According to one embodiment of the present invention Figure 2 The comparison circuit 10 shown in FIG. Figure 10 As shown, the comparison circuit 10 includes an error amplifier 102 , first, second and third ramp signal generating circuits 103 , 104 and 105 , an adder 106 and a voltage comparator 107 .

[0069] The error amplifier 102 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the voltage feedback signal VFB, and the second input terminal receives the reference signal VREF. The error amplifier 102 generates an error signal EA at the output terminal based on the error between the voltage feedback signal VFB and the reference signal VREF. The error signal EA represents the difference between the voltage feedback signal VFB and the reference signal VREF.

[0070] The first ramp signal generating circuit 103 receives the first control signal PWM1. In each switching cycle T, when the first high-side switch M1a is turned on, ie, when the first control signal PWM1 switches from an inactive state to an active state, the first ramp signal generating circuit 103 starts generating the first ramp signal Ramp1.

[0071] The second ramp signal generating circuit 104 receives the second control signal PWM2. In each switching period T, when the second high-side switch M2a is turned on, that is, when the second control signal PWM2 switches from an inactive state to an active state, the second ramp signal generating circuit 104 starts generating the second ramp signal Ramp2.

[0072] The third ramp signal generating circuit 105 receives the third control signal PWM3. In each switching period T, when the third high-side switch M3a is turned on, that is, when the third control signal PWM3 switches from an inactive state to an active state, the third ramp signal generating circuit 105 starts generating the third ramp signal Ramp3.

[0073] The adder 106 receives the voltage feedback signal VFB and the first to third ramp signals Ramp1 ˜ Ramp3 , and performs a sum operation on the voltage feedback signal VFB and the first to third ramp signals Ramp1 ˜ Ramp3 to generate a sum signal Ramp_sum.

[0074] The voltage comparator 107 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the error signal EA and the second input terminal receives the sum signal Ramp_sum. The voltage comparator 107 compares the sum signal Ramp_sum with the error signal EA and generates a comparison signal CA at its output terminal. In one embodiment, Figure 10 The comparison circuit 10 shown can improve the stability of the four-level buck converter 100 .

[0075] Figure 11 FIG. 5 is a four-level buck converter 500 according to another embodiment of the present invention. Figure 2 Compared to the four-level buck converter 100 shown, the four-level buck converter 500 further includes a current limiting circuit 40. The current limiting circuit 40 includes a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal is coupled to a common connection point between the first low-side switch M1b and a logic ground to receive a first current detection signal CS1, wherein the first current detection signal CS1 represents the current flowing through the first low-side switch M1b; the second input terminal is coupled to a common connection point between the second low-side switch M2b and the second terminal of the first flying capacitor C1 to receive a second current detection signal CS2, wherein the second current detection signal CS2 represents the current flowing through the second low-side switch M2b; and the third input terminal is coupled to a common connection point between the third low-side switch M3b and the second terminal of the second flying capacitor C2 to receive a third current detection signal CS3, wherein the third current detection signal CS3 represents the current flowing through the third low-side switch M3b.

[0076] The current limiting circuit 40 is configured to determine whether any of the first to third current detection signals CS1-CS3 is greater than a current limit threshold ILIM. The current limiting circuit 40 compares the first to third current detection signals CS1-CS3 with the current limit threshold ILIM and generates an overcurrent indication signal OC at its output terminal based on the comparison result. The overcurrent indication signal OC is a logic signal having an active state and an inactive state. In one embodiment, when any of the first to third current detection signals CS1-CS3 is greater than the current limit threshold ILIM, the overcurrent indication signal OC is in an active state (e.g., a logic low state); otherwise, the overcurrent indication signal OC is in an inactive state (e.g., a logic high state).

[0077] exist Figure 11 In the illustrated embodiment, the current limiting circuit 40 includes first, second, and third comparators 401, 402, and 403, and an AND gate circuit 404. The first comparator 401 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the current limit threshold ILIM, and the second input terminal receives the first current detection signal CS1. The first comparator 401 compares the current limit threshold ILIM with the first current detection signal CS1 and generates a first indication signal OC1 at the output terminal based on the comparison result. The second comparator 402 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the current limit threshold ILIM, and the second input terminal receives the second current detection signal CS2. The second comparator 402 compares the current limit threshold ILIM with the second current detection signal CS2 and generates a second indication signal OC2 at the output terminal based on the comparison result. The third comparator 402 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the current limit threshold ILIM, and the second input terminal receives the third current detection signal CS3. The third comparator 403 compares the current limit threshold ILIM with the third current detection signal CS3 and generates a third indication signal OC3 at the output terminal based on the comparison result. The AND gate circuit 404 receives the first, second, and third indication signals OC1, OC2, and OC3 and generates an overcurrent indication signal OC based on the first, second, and third indication signals OC1, OC2, and OC3.

[0078] exist Figure 11In the illustrated embodiment, the overcurrent indication signal OC is input to the selection circuit 20. Specifically, the overcurrent indication signal OC is input to the first AND gate circuit 201, the second AND gate circuit 202, and the third AND gate circuit 203, respectively. The first AND gate circuit 201 generates a first set signal CA1 based on the comparison signal CA, the first enable signal EN1, and the overcurrent indication signal OC. Similarly, the second AND gate circuit 202 generates a second set signal CA2 based on the comparison signal CA, the second enable signal EN2, and the overcurrent indication signal OC. The third AND gate circuit 203 generates a third set signal CA3 based on the comparison signal CA, the third enable signal EN3, and the overcurrent indication signal OC. When any of the first to third current detection signals CS1-CS3 is greater than the current limit threshold ILIM, the first to third set signals CA1-CA3 are all in an inactive state. The first to third control signals PWM1-PWM3 respectively control the high-side switches M1a, M2a and M3a to turn off and the low-side switches M1b, M2b and M3b to turn on until the corresponding current detection signal decreases to less than the current limit threshold ILIM.

[0079] Figure 12 4-level buck converter 600 according to another embodiment of the present invention. In one embodiment, when the output voltage signal VOUT is close to or That is, the output voltage signal VOUT falls into or When the output voltage signal VOUT is within the range, there is no ripple to be detected, and the four-level buck converter 500 is unstable. Where k is a proportional coefficient, and its value depends on the specific application. In one embodiment, the proportional coefficient k is less than 10, for example, 5. Figure 11 Compared to the four-level buck converter 500 shown, the four-level buck converter 600 further includes a delay circuit 50 to improve stability.

[0080] The delay circuit 50 receives the input voltage signal VIN, the output voltage signal VOUT, and the first to third set signals CA1 to CA3, and generates the first, second, and third delayed set signals CA1-dly, CA2-dly, and CA3-dly based on the input voltage signal VIN, the output voltage signal VOUT, and the first to third set signals CA1 to CA3. In the four-level buck converter 600, when the output voltage signal VOUT is close to or When , only one of the first to third setting signals CA1-CA3 is delayed to generate a corresponding delayed setting signal, and the other two setting signals remain unchanged. Figure 12 As shown, when the output voltage signal VOUT is close to or When , the delay circuit 50 receives the input voltage signal VIN, the output voltage signal VOUT and the first set signal CA1, and delays the first set signal CA1 to generate a first delayed set signal CA1-dly. The second set signal CA2 and the third set signal CA3 remain unchanged, that is, the second delayed set signal CA2-dly is equal to the second set signal CA2, and the third delayed set signal CA3-dly is equal to the third set signal CA3. It will be understood by those skilled in the art that when the output voltage signal VOUT is close to or When the delay circuit 50 can also delay the second set signal CA2, generating

[0081] The second delayed set signal CA2-dly or the third set signal CA3 is delayed to generate a third delayed set signal CA3-dly.

[0082] exist Figure 12 In the illustrated embodiment, the delay circuit 50 includes a voltage divider circuit 501 , a first hysteresis comparator 5021 , a second hysteresis comparator 5022 , an OR gate circuit 503 , and a delay module 504 .

[0083] The voltage divider circuit 501 receives the input voltage signal VIN and generates a first voltage divider signal and the second voltage divider signal

[0084] The first hysteresis comparator 5021 receives the output voltage signal VOUT and the first voltage-divided signal The output voltage signal VOUT and the first voltage division signal In one embodiment, the first hysteresis comparator 5021 presets a proportional coefficient k. When the output voltage signal is and During this time, the first confirmation signal DET1 is in a valid state (eg, a logic high state).

[0085] The second hysteresis comparator 5022 receives the output voltage signal VOUT and the second voltage-divided signal And the output voltage signal VOUT and the second voltage division signal In one embodiment, the second hysteresis comparator 5022 presets the proportional coefficient k. When the output voltage signal is and During this time, the second confirmation signal DET2 is in a valid state (such as a logic high state).

[0086] OR gate circuit 503 receives first confirmation signal DET1 and second confirmation signal DET2 and performs a logical OR operation on the first confirmation signal DET1 and the second confirmation signal DET2 to generate a delay enable signal EN-dly. Delay enable signal EN-dly is a logic signal having an active state (e.g., a logic high state) and an inactive state (e.g., a logic low state). In one embodiment, if either first confirmation signal DET1 or second confirmation signal DET2 is active, delay enable signal EN-dly is active; otherwise, delay enable signal EN-dly is inactive.

[0087] When the delay enable signal EN-dly is in an active state, the delay module 504 delays the first set signal CA1 to generate a first delayed set signal CA1 -dly.

[0088] Figure 13 A multi-level buck converter 700 according to one embodiment of the present invention is shown. The multi-level buck converter 700 includes N pairs of switches M1a-MNa and M1b-MNb, N-1 flying capacitors C1-C(N-1), an output capacitor COUT, and an inductor LOUT, where N is an integer greater than 2. Specifically, the high-side switches M1a-MNa are sequentially coupled in series between the input terminal and the switch node SW, and the low-side switches M1b-MNb are sequentially coupled in series between the logic ground and the switch node SW. Each flying capacitor Ci (i=1, 2, ..., N-1) is coupled between the common connection point of the high-side switch Mia and M(i+1)a and the common connection point of the low-side switch Mib and M(i+1)b.

[0089] Similar to the four-level buck converter 600 , the multi-level buck converter 700 further includes a control circuit, which includes a comparison circuit 10 , a selection circuit 20 , a current limiting circuit 40 , a delay circuit 50 , and N COT controllers 301 ˜ 30N.

[0090] exist Figure 13 In the illustrated embodiment, the selection circuit 20 receives a comparison signal CA and generates set signals CA1-CAN based on the comparison signal CA. When any of the set signals CA1-CAN switches from an inactive state (e.g., a logic low state) to an active state (e.g., a logic high state), the i-th COT controller 30i corresponding to the active set signal CAi is triggered. In one embodiment, the N set signals CA1-CAN switch from an inactive state to an active state in turn on the rising edge of the comparison signal CA.

[0091] The current limiting circuit 40 is used to determine whether any of the N current detection signals CS1-CSN is greater than the current limit threshold ILM. The current limiting circuit 40 compares the N current detection signals CS1-CSN with the current limit threshold ILIM and generates an overcurrent indication signal OC based on the comparison result. When any of the current detection signals CS1-CSN is greater than the current limit threshold ILIM, the overcurrent indication signal OC is asserted.

[0092] The delay circuit 50 receives the input voltage signal VIN, the output voltage signal VOUT and N set signals CA1-CAN, and when the output voltage signal VOUT is close to ……,or That is, the output voltage signal VOUT falls into ……,or When the delay setting signals CA1-dly to CAN-dly are within the range, N delay setting signals CA1-dly to CAN-dly are generated.

[0093] In one embodiment, when N is an odd number, a total of (N-1) / 2 set signals are delayed. ……,or When the delay circuit 50 delays the set signal CA(2i-1) for each i=1, ..., (N-1) / 2, to generate a corresponding delayed set signal CA(2i-1)-dly. Meanwhile, the remaining (N+1) / 2 set signals remain unchanged.

[0094] In one embodiment, when N is an odd number, a total of (N-1) / 2 set signals are delayed. ……,or When the delay circuit 50 delays the set signal CA(2i+1) for each i=1, ..., (N-1) / 2, to generate a corresponding delayed set signal CA(2i+1)-dly. Meanwhile, the remaining (N+1) / 2 set signals remain unchanged.

[0095] In one embodiment, when N is an odd number, a total of (N-1) / 2 set signals are delayed. ……,or When the delay circuit 50 delays the set signal CA(2i) for each i=1, ..., (N-1) / 2, to generate a corresponding delayed set signal CA(2i)-dly. Meanwhile, the remaining (N+1) / 2 set signals remain unchanged.

[0096] In one embodiment, when N is an even number, a total of N / 2 set signals are delayed. ……,or When the delay circuit 50 delays the set signal CA(2i-1) for each i=1, ..., N / 2 to generate a corresponding delayed set signal CA(2i-1)-dly. Meanwhile, the remaining N / 2 set signals remain unchanged.

[0097] In one embodiment, when N is an even number, a total of N / 2 set signals are delayed. ……,or When the delay circuit 50 sets the set signal CA(2i) for each i=1, ..., (N-1) / 2, it generates the corresponding delayed set signal CA(2i)-dly. Meanwhile, the remaining N / 2 set signals remain unchanged.

[0098] exist Figure 13 In the illustrated embodiment, each COT controller 30i (i=1, 2, ..., N) receives an output voltage signal VOUT, an input voltage signal VIN, and a corresponding delayed set signal CAi-dly. When the delayed set signal CAi-dly is active, the COT controller 30i generates a corresponding control signal PWMi based on the output voltage signal VOUT, the input voltage signal VIN, and the delayed set signal CAi-dly to control a corresponding pair of switches Mia and Mib.

[0099] Figure 14 According to one embodiment of the present invention Figure 13 The delay circuit 50 is shown. Figure 14 In the illustrated embodiment, the delay circuit 50 includes a voltage divider circuit 501, N-1 hysteresis comparators 5021-502(N-1), an OR gate circuit 503, and a plurality of delay modules, where the number of delay modules is determined by the value of N. In one embodiment, when N is an even number, the number of delay modules is N / 2, and when N is an odd number, the number of delay modules is (N-1) / 2.

[0100] The voltage dividing circuit 501 receives an input voltage signal VIN to generate N−1 voltage dividing signals.

[0101] Each hysteresis comparator 502i (i=1, 2, ..., N-1) receives the output voltage signal VOUT and the i-th voltage division signal And the output voltage signal VOUT and the i-th voltage division signal In one embodiment, the hysteresis comparator 502i is pre-set with a proportional coefficient k. When the output voltage signal VOUT is at and During the period between , the i-th confirmation signal DETi is in a valid state (eg, a logic high state).

[0102] OR gate circuit 503 receives N-1 confirmation signals DET1-DET(N-1) and performs a logical operation on these signals to generate a delay enable signal EN-dly. In one embodiment, if any one of the N-1 confirmation signals DET1-DET(N-1) is in an active state, the delay enable signal EN-dly is in an active state (e.g., a logic high state). Otherwise, the delay enable signal EN-dly is in an inactive state (e.g., a logic low state).

[0103] When the delay enable signal EN-dly is in an active state, each of the plurality of delay modules delays a corresponding set signal to generate a delayed set signal.

[0104] In one embodiment, when N is an odd number, there are a total of (N-1) / 2 delay modules. When the delay enable signal EN-dly is in an active state, for each i=1, ..., (N-1) / 2, the delay module 504-i delays the set signal CA(2i-1) to generate a delayed set signal CA(2i-1)-dly.

[0105] In one embodiment, when N is an odd number, there are a total of (N-1) / 2 delay modules. When the delay enable signal EN-dly is in an active state, for each i=1, ..., (N-1) / 2, the delay module 504-i delays the set signal CA(2i+1) to generate a delayed set signal CA(2i+1)-dly.

[0106] In one embodiment, when N is an odd number, there are (N-1) / 2 delay modules. When the delay enable signal EN-dly is in an active state, for each i=1, ..., (N-1) / 2, the delay module 504-i delays the set signal CA(2i) to generate a delayed set signal CA(2i)-dly.

[0107] In one embodiment, when N is an even number, there are N / 2 delay modules. When the delay enable signal EN-dly is in an active state, for each i=1, ..., N / 2, the delay module 504-i delays the set signal CA(2i-1) to generate a delayed set signal CA(2i-1)-dly.

[0108] In one embodiment, when N is an even number, there are N / 2 delay modules. When the delay enable signal EN-dly is in an active state, for each i=1, ..., N / 2, the delay module 504-i delays the set signal CA(2i) to generate a delayed set signal CA(2i)-dly.

[0109] While the present invention has been described with reference to several exemplary embodiments, it should be understood that the terms used are descriptive and illustrative, rather than restrictive. Since the present invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above-described embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope of the appended claims. All changes and modifications that fall within the scope of the claims or their equivalents are intended to be covered by the appended claims.

Claims

1. A control circuit for a multi-level buck converter, wherein the multi-level buck converter converts an input voltage signal at an input terminal into an output voltage signal at an output terminal, the multi-level buck converter having N pairs of switches coupled in series between the input terminal and a logic ground, where N is an integer greater than or equal to 2, the control circuit comprising: a comparison circuit configured to receive a reference signal and a voltage feedback signal representing the output voltage signal, and compare the reference signal with the voltage feedback signal to generate a comparison signal; a selection circuit configured to receive the comparison signal and generate N set signals based on the comparison signal; a delay circuit configured to receive an input voltage signal, an output voltage signal, and N set signals, and generate N delayed set signals based on the input voltage signal, the output voltage signal, and the N set signals; and N COT controllers, wherein for each i=1, 2, ..., N, the i-th COT controller is configured to receive an output voltage signal, an input voltage signal, and an i-th delayed set signal, and generate an i-th control signal based on the output voltage signal, the input voltage signal, and the i-th delayed set signal to control the corresponding i-th pair of switches to be complementary turned on and off.

2. The control circuit according to claim 1 , wherein the comparison circuit comprises: an error amplifier configured to receive the reference signal and the voltage feedback signal and generate an error signal based on the reference signal and the voltage feedback signal; N ramp signal generating circuits are configured to generate N ramp signals, wherein for each i=1, 2, ..., N, the i-th ramp signal generating circuit is configured to receive the i-th control signal and generate the i-th ramp signal based on the i-th control signal; an adder configured to receive the voltage feedback signal and N ramp signals, and perform a sum operation on the voltage feedback signal and the N ramp signals to generate a sum signal; as well as The voltage comparator is configured to receive the sum signal and the error signal and compare the sum signal and the error signal to generate the comparison signal.

3. The control circuit according to claim 1, wherein When N is an odd number, a total of (N-1) / 2 set signals are delayed, wherein when the output voltage signal falls within the range of the input voltage signal or When within the range, for each i=1,...,(N-1) / 2, the delay circuit is configured to delay the 2i-1th set signal to generate a corresponding 2i-1th delayed set signal, where k is a proportional coefficient.

4. The control circuit according to claim 1, wherein When N is an odd number, a total of (N-1) / 2 set signals are delayed, wherein when the output voltage signal falls within the range of the input voltage signal or When within the range, for each i=1,...,(N-1) / 2, the delay circuit is configured to delay the 2i+1th set signal to generate a corresponding 2i+1th delayed set signal, where k is a proportional coefficient.

5. The control circuit according to claim 1, wherein When N is an odd number, a total of (N-1) / 2 set signals are delayed, wherein when the output voltage signal falls within the range of the input voltage signal or When within the range, for each i=1,...,(N-1) / 2, the delay circuit is configured to delay the 2i th set signal to generate a corresponding 2i th delayed set signal, where k is a proportional coefficient.

6. The control circuit according to claim 1, wherein When N is an even number, a total of N / 2 set signals are delayed, wherein when the output voltage signal falls within the range of the input voltage signal or When within the range, for each i=1, ..., N / 2, the delay circuit is configured to delay the 2i-1th set signal to generate a corresponding 2i-1th delayed set signal, where k is a proportional coefficient.

7. The control circuit according to claim 1, wherein When N is an even number, a total of N / 2 set signals are delayed, wherein when the output voltage signal falls within the range of the input voltage signal or When within the range, for each i=1, ..., N / 2, the delay circuit is configured to delay the 2i th set signal to generate a corresponding 2i th delayed set signal, where k is a proportional coefficient.

8. The control circuit of claim 1 , wherein the delay circuit comprises: The voltage divider circuit is configured to receive an input voltage signal to generate N-1 divided voltage signals, and for each i=1, 2, ..., N-1, the i-th divided voltage signal is equal to the input voltage signal. N-1 hysteresis comparators are configured to generate N-1 confirmation signals, where for each i=1, 2, ..., N-1, the i-th hysteresis comparator is configured to receive the output voltage signal and the i-th voltage divided signal, and compare the output voltage signal with the i-th voltage divided signal to generate the i-th confirmation signal; an OR gate circuit configured to receive N-1 confirmation signals and perform a logic operation on the N-1 confirmation signals to generate a delay enable signal; as well as A plurality of delay modules are provided, each delay module being configured to receive a delay enable signal and a corresponding set signal, and to generate a corresponding delayed set signal based on the delay enable signal and the corresponding set signal.

9. The control circuit of claim 8, wherein when N is an odd number, the number of delay modules is (N-1) / 2, and when N is an even number, the number of delay modules is N / 2.

10. The control circuit according to claim 1, wherein for each i=1, 2, ..., N, the i-th COT controller comprises: a conduction time generating circuit configured to receive the ith delayed setting signal, the input voltage signal, and the output voltage signal, and generate a conduction time signal based on the ith delayed setting signal, the input voltage signal, and the output voltage signal; as well as The logic circuit is configured to receive the i-th delayed setting signal and the on-time signal, and perform a logic operation on the i-th delayed setting signal and the on-time signal to generate an i-th control signal.

11. The control circuit according to claim 10, wherein the on-time generating circuit comprises: a controlled current generating circuit having a first terminal and a second terminal, wherein the first terminal is configured to receive an input voltage signal, and the controlled current generating circuit is configured to generate a controlled current signal at the second terminal based on the input voltage signal; a capacitor coupled between the second terminal of the controlled current generating circuit and a logic ground; a controlled voltage generating circuit having a first terminal and a second terminal, wherein the first terminal is configured to receive the output voltage signal, and the controlled voltage generating circuit is configured to generate a controlled voltage signal at the second terminal based on the output voltage signal; a comparator having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is configured to receive a controlled voltage signal, the second input terminal is configured to receive a voltage signal across the capacitor, the comparator is configured to compare the controlled voltage signal with the voltage signal across the capacitor, and generate the on-time signal at its output terminal; as well as The reset switch has a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the controlled current generating circuit, the second terminal is coupled to the logic ground, and the control terminal is configured to receive the i-th delayed setting signal.

12. The control circuit of claim 1 , wherein the selection circuit comprises: an enable circuit configured to receive a comparison signal and generate N enable signals based on the comparison signal, wherein the N enable signals are switched from an invalid state to a valid state in sequence; and N AND gate circuits, for each i=1, 2, ..., N, the i-th AND gate circuit is configured to receive the i-th enable signal and the comparison signal, and perform a logic operation on the i-th enable signal and the comparison signal to generate the i-th set signal.

13. A control circuit for a multi-level buck converter, the multi-level buck converter converting an input voltage signal at an input terminal into an output voltage signal at an output terminal, the multi-level buck converter having N pairs of switches coupled in series between the input terminal and a logic ground, each pair of the N pairs of switches including a high-side switch and a low-side switch, wherein N is an integer greater than or equal to 2, the control circuit comprising: a comparison circuit configured to receive a reference signal and a voltage feedback signal representing the output voltage signal, and compare the reference signal with the voltage feedback signal to generate a comparison signal; a selection circuit configured to receive the comparison signal and generate N set signals based on the comparison signal; N COT controllers, wherein for each i=1, 2, ..., N, the i-th COT controller is configured to receive an output voltage signal, an input voltage signal, and an i-th set signal, and generate an i-th control signal based on the output voltage signal, the input voltage signal, and the i-th set signal to control the corresponding i-th pair of switches to be complementary turned on and off; as well as A current limiting circuit is configured to receive N current detection signals, compare the N current detection signals with current limiting thresholds respectively, and generate an overcurrent indication signal based on the comparison results, wherein when any one of the N current detection signals is greater than the current limiting threshold, the overcurrent indication signal is configured to turn off all high-side switches in the N pairs of switches, wherein for each i=1, 2, ..., N, the i-th current detection signal represents the current flowing through the low-side switch in the i-th pair of switches.

14. The control circuit of claim 13 , wherein the current limiting circuit comprises: N comparators, for each i=1, 2, ..., N, the i-th comparator has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is configured to receive the current limit threshold, the second input terminal is configured to receive the i-th current detection signal, the i-th comparator is configured to compare the current limit threshold with the i-th current detection signal, and generate an i-th indication signal at the output terminal; as well as The AND gate circuit is configured to receive N indication signals and perform a logic operation on the N indication signals to generate the overcurrent indication signal. 15 . The control circuit according to claim 13 , wherein the N set signals are configured to switch from an inactive state to an active state in turn at a rising edge of the comparison signal.

16. A multi-level buck converter, configured to convert an input voltage signal at an input end into an output voltage signal at an output end, the multi-level buck converter comprising: N pairs of switches coupled in series between the input terminal and a logic ground, where N is an integer greater than or equal to 2; a comparison circuit configured to receive a reference signal and a voltage feedback signal representing an output voltage, and compare the reference signal with the voltage feedback signal to generate a comparison signal; a selection circuit configured to receive the comparison signal and generate N set signals based on the comparison signal; N COT controllers, for each i=1, 2, ..., N, the i-th COT controller is configured to receive an i-th set signal, an output voltage signal, and an input voltage signal, and generate an i-th control signal based on the i-th set signal, the output voltage signal, and the input voltage signal to control the i-th pair of switches to be complementary turned on and off; as well as A current limiting circuit is configured to receive N current detection signals, compare the N current detection signals with current limiting thresholds respectively, and generate an overcurrent indication signal based on the comparison results, wherein when any one of the N current detection signals is greater than the current limiting threshold, the overcurrent indication signal is configured to turn off all high-side switches in the N pairs of switches, wherein for each i=1, 2, ..., N, the i-th current detection signal represents the current flowing through the low-side switch in the i-th pair of switches.

17. A multi-level buck converter, configured to convert an input voltage signal at an input end into an output voltage signal at an output end, the multi-level buck converter comprising: two pairs of switches coupled in series between the input terminal and a logic ground; a comparison circuit configured to receive a reference signal and a voltage feedback signal representing an output voltage, and compare the reference signal with the voltage feedback signal to generate a comparison signal; a selection circuit configured to receive the comparison signal and generate a first set signal and a second set signal based on the comparison signal; a first COT controller configured to receive a first set signal, an output voltage signal, and an input voltage signal, and generate a first control signal based on the first set signal, the output voltage signal, and the input voltage signal to control the first pair of switches to be complementary turned on and off; as well as a second COT controller configured to receive a second set signal, an output voltage signal, and an input voltage signal, and generate a second control signal based on the second set signal, the output voltage signal, and the input voltage signal to control the second pair of switches to be complementary turned on and off; The comparison circuit includes: an error amplifier configured to receive the reference signal and the voltage feedback signal and generate an error signal based on the reference signal and the voltage feedback signal; a first ramp signal generating circuit configured to receive a first control signal and generate a first ramp signal based on the first control signal; a second ramp signal generating circuit configured to receive a second control signal and generate a second ramp signal based on the second control signal; an adder configured to receive the voltage feedback signal, the first ramp signal, and the second ramp signal, and perform a sum operation on the voltage feedback signal, the first ramp signal, and the second ramp signal to generate a sum signal; and The voltage comparator is configured to receive the sum signal and the error signal and compare the sum signal and the error signal to generate the comparison signal.

18. The multi-level buck converter according to claim 17, further comprising: The delay circuit is configured to receive an input voltage signal, an output voltage signal, a first set signal and a second set signal, and when the output voltage signal falls within the range of the input voltage signal When the delay circuit is within the range of , the delay circuit is configured to delay one of the first setting signal and the second setting signal to generate a corresponding delayed setting signal, where k is a proportional coefficient.

Images