A charge pump mismatch calibration circuit, phase-locked loop and calibration method

Abstract

This invention discloses a charge pump mismatch calibration circuit, a phase-locked loop (PLL), and a calibration method, including a frequency and phase detector, a charge pump, and a mismatch monitoring and adjustment unit. The mismatch monitoring and adjustment unit includes a mismatch detection circuit, an AND gate, and two delay chains. The input of the mismatch detection circuit is connected to the VO output of the charge pump, and the output of the mismatch detection circuit is connected to the delay control terminals of the two delay chains. The input of the AND gate is connected to the UP and DN outputs of the frequency and phase detector, respectively, and the output of the AND gate is connected to the inputs of the two delay chains. The outputs of the two delay chains are connected to the two REST signal terminals of the frequency and phase detector, respectively. This invention is based on the current integration principle and compensates for mismatch through delay chains. Therefore, it can achieve charge pump current mismatch calibration with very little cost, which helps to reduce PLL output spurious signals and improve the PLL output clock quality.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, and in particular to a charge pump mismatch calibration circuit, phase-locked loop and calibration method, which is mainly applicable to the fields of clock generation and frequency synthesizers. Background Technology

[0002] Phase-locked loop (PLL) circuits are widely used in various fields, including digital baseband, microwave RF wireless communication, and digital-to-analog converters, all requiring a high-quality and stable clock. With the continuous development of information technology and the increasing bandwidth of wireless communication, higher demands are placed on wireless transceiver systems, which in turn places more stringent requirements on PLL circuits that perform spectrum shifting. One of the core modules of a PLL, the charge pump circuit, suffers from clock spurious signals due to current mismatch, which degrades the system's signal-to-noise ratio. The charge pump circuit consists of a P-type current mirror and an N-type current mirror; due to current limitations, current mismatch is unavoidable. For example... Figure 1 The conventional charge pump circuit shown includes a frequency and phase detector and a charge pump, in which the mismatch between current source I1 and current source I2 is unavoidable.

[0003] Existing methods for charge pump mismatch calibration, such as using programmable current arrays to compensate for charge pump current, include... Figure 2 As shown, this is a charge pump mismatch calibration circuit from an existing patent (application number: 201910955515.X). The main drawback of this method is that it is difficult to simultaneously meet the requirements of high charge pump current and high calibration accuracy. The calibration accuracy is limited by the accuracy of the smallest current mirror unit in the programmable current mirror array. Firstly, implementing a current mirror unit with extremely small current is very difficult; secondly, increasing the number of programmable current mirror arrays makes the leakage problem more complex. For example... Figure 3 The calibration accuracy of a charge pump mismatch calibration circuit shown in the existing patent (application number: 201911167004.8) is still limited by the programmable current source array.

[0004] It is evident that the inherent structure of charge pump circuits cannot prevent mismatches, and existing mismatch calibration schemes not only have limited accuracy but also require complex programmable current mirror arrays. Achieving high-precision mismatch detection and calibration of charge pumps is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The technical problem this invention aims to solve is to address the shortcomings of the existing technology by providing a charge pump mismatch calibration circuit, phase-locked loop, and calibration method. This circuit, loop, and method are based on the principle of current integration, theoretically achieving infinite detection accuracy. Mismatch adjustment is achieved by controlling the conduction time of the charge pump current source using a variable delay chain. Improving the accuracy of a variable delay chain is far less difficult than improving the accuracy of a programmable current array. By compensating for mismatch through a delay chain, the charge pump current and the compensation current array can be decoupled, allowing for separate calibration of the charge pump current and the compensation circuit. Therefore, the charge pump mismatch calibration circuit proposed in this invention is easy to implement for high-precision calibration. The method is intuitive, the circuit is simple, and it is easy to implement.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A charge pump mismatch calibration circuit includes a frequency and phase detector, a charge pump, and a mismatch monitoring and adjustment unit.

[0008] The frequency and phase detector has two REST signal terminals, a UP output terminal, and a DN output terminal.

[0009] The charge pump includes a first current source I1, a second current source I2, a switch S1, and a switch S2.

[0010] One end of the first current source I1 is connected to the power supply, and the other end is connected to the switch S1. The on / off control input of the switch S1 is connected to the UP output.

[0011] One end of the second current source I2 is connected to the power supply or ground, and the other end is connected to switch S2. The on / off control input of switch S2 is connected to the output of DN.

[0012] When switches S1 and S2 are connected, they form the VO output terminal.

[0013] The mismatch monitoring and adjustment unit includes a mismatch detection circuit MIS_DET, an AND gate, a first delay chain Delay Line 1, and a second delay chain Delay Line 2.

[0014] The input terminal of the mismatch detection circuit MIS_DET is connected to the output terminal of VO. The output terminals of the mismatch detection circuit MIS_DET are UP_TUNE and DN_TUNE, which are respectively connected to the delay control terminal of the first delay chain Delay Line 1 and the delay control terminal of the second delay chain Delay Line 2.

[0015] The inputs of the AND gate are connected to the outputs of UP and DN, respectively; the outputs of the AND gate are connected to the inputs of the first delay chain Delay Line 1 and the second delay chain Delay Line 2, respectively.

[0016] The output of the first delay line (Delay Line 1) and the output of the second delay line (Delay Line 2) are respectively connected to two REST signal terminals.

[0017] The frequency and phase detector module includes two D flip-flops and two MUXs.

[0018] The two D flip-flops are designated as DFF1 and DFF2. The output of DFF1 is the UP output, and the output of DFF2 is the DN output. Each D flip-flop has a REST signal terminal and a clock input terminal.

[0019] The two MUXs are MUX1 and MUX2; the inputs of each MUX are connected to the reference clock REFCLK and the feedback clock FBCLK, respectively; the output of MUX1 is connected to the clock input of the first D flip-flop DFF1; the output of MUX2 is connected to the clock input of the second D flip-flop DFF2.

[0020] The mismatch detection circuit MIS_DET includes a comparator CMP and a digital logic unit (Digital). The positive terminal of the comparator CMP is connected to the reference voltage VREF, and the negative terminal of the comparator CMP is connected to the VO output terminal. The output terminal of the comparator CMP is connected to the input terminal of the digital logic unit (Digital). The digital logic unit (Digital) has two output terminals, namely UP_TUNE and DN_TUNE.

[0021] A grounding capacitor is also connected in parallel to the VO output terminal of the frequency and phase detector.

[0022] Both the first delay chain (Delay Line 1) and the second delay chain (Delay Line 2) are variable delay chains, capable of achieving capacitance values ​​in the 1e-15 range.

[0023] The first delay line (Delay Line 1) and the second delay line (Delay Line 2) each include several capacitor arrays connected in series, with adjacent capacitor arrays connected by inverters; each capacitor array includes n capacitors in parallel, and each capacitor is controlled by a switch; where n≥2.

[0024] A phase-locked loop comprising the charge pump mismatch calibration circuit described in any of the preceding claims.

[0025] A charge pump mismatch calibration method includes the following steps.

[0026] Step 1, Equal Width Pulse Control: When the charge pump mismatch requires calibration, the inputs of the two MUXs in the frequency and phase detector are both connected to the reference clock REFCLK. The UP and DN outputs of the frequency and phase detector output equal width pulse signals to control the charge switch S1 and charge switch S2 respectively.

[0027] Step 2, VO output voltage comparison: The mismatch detection circuit MIS_DET includes a comparator CMP and digital logic; the comparator CMP acquires the VO output voltage and compares the acquired VO output voltage with the built-in reference voltage VREF.

[0028] Step 3: CMP output value control: When the voltage at the VO output terminal is greater than the reference voltage VREF, the current of the first current source I1 is greater than the current of the second current source I2, and the comparator CMP outputs the digital value "0"; otherwise, it outputs the digital value "1".

[0029] Step 4, Delay Control: The digital logic unit (Digital) acquires the output of the comparator (CMP) in real time and performs the following delay control:

[0030] A. When the comparator CMP outputs two or more consecutive digits "0", the digital logic increases the delay of the second delay chain Delay Line 2 or decreases the delay of the first delay chain Delay Line 1.

[0031] B. When the comparator CMP outputs two or more consecutive "1" numbers, the digital logic will either decrease the delay of the second delay chain Delay Line 2 or increase the delay of the first delay chain Delay Line 1.

[0032] Step 5, Variable Width Pulse Control: The first D flip-flop DFF1 in the frequency and phase detector generates a pulse signal with a width of T1 based on the output of the first delay line 1 in step 4, which is used to control the charge switch S1; the second D flip-flop DFF2 in the frequency and phase detector generates a pulse signal with a width of T2 based on the output of the second delay line 2 in step 4, which is used to control the charge switch S2; the control method for T1 and T2 is as follows:

[0033] A. When the comparator CMP outputs two or more consecutive digits "0", T1 < T2.

[0034] B. When the comparator CMP outputs two or more consecutive numbers "1", T1 > T2.

[0035] Step 6: Repeat steps 2 to 5 until the comparator CMP output alternates between the digital "0" and "1" and the switching frequency is equal to the frequency of the reference clock REFCLK. At this point, the mismatch calibration is complete. The input signals of the first delay chain DelayLine1 and the second delay chain DelayLine2 are latched. MUX1 in the frequency and phase detector is connected to the reference clock REFCLK, and MUX2 in the frequency and phase detector is connected to the feedback clock FBCLK.

[0036] In step 1, the charge pump mismatch calibration occurs when the comparator CMP outputs two or more consecutive digits "0" or "1".

[0037] The present invention has the following beneficial effects:

[0038] 1. This invention uses a variable delay connection to perform charge pump mismatch calibration, making it easier to achieve high-precision calibration.

[0039] 2. The charge pump mismatch calibration circuit of the present invention helps to improve the output clock quality of the phase-locked loop circuit. Attached Figure Description

[0040] Figure 1 A schematic diagram of a conventional frequency and phase detector and a charge pump is shown.

[0041] Figure 2 A schematic diagram of a charge pump mismatch calibration circuit in the prior art is shown.

[0042] Figure 3 A schematic diagram of a charge pump mismatch calibration circuit in the prior art is shown.

[0043] Figure 4 A schematic diagram of a charge pump mismatch calibration circuit according to the present invention is shown.

[0044] Figure 5 A schematic diagram of the mismatch detection circuit MIS_DET in this invention is shown.

[0045] Figure 6 A schematic diagram of the variable delay chain in this invention is shown.

[0046] Figure 7 The output of the UP and DN signals is shown during mismatch calibration when both MUXs are connected to the reference clock REFCLK.

[0047] Figure 8 The output UP and DN signals are shown when the second current source I2 is greater than the first current source I1. Detailed Implementation

[0048] The present invention will now be described in further detail with reference to the accompanying drawings and specific preferred embodiments.

[0049] In the description of this invention, it should be understood that the terms "left side," "right side," "upper part," "lower part," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. "First," "second," etc., do not indicate the importance of the components, and therefore should not be construed as a limitation of this invention. The specific dimensions used in this embodiment are only for illustrating the technical solution and do not limit the scope of protection of this invention.

[0050] like Figure 4 As shown, a charge pump mismatch calibration circuit includes a frequency and phase detector, a charge pump, and a mismatch monitoring and adjustment unit.

[0051] The frequency and phase detector module includes two D flip-flops and two MUXs.

[0052] The two D flip-flops are designated as DFF1 and DFF2. The output of DFF1 is the UP output, and the output of DFF2 is the DN output. Each D flip-flop has a REST signal terminal and a clock input terminal.

[0053] The two MUXs are MUX1 and MUX2; the inputs of each MUX are connected to the reference clock REFCLK and the feedback clock FBCLK, respectively; the output of MUX1 is connected to the clock input of the first D flip-flop DFF1; the output of MUX2 is connected to the clock input of the second D flip-flop DFF2.

[0054] The charge pump includes a first current source I1, a second current source I2, a switch S1, and a switch S2.

[0055] One end of the first current source I1 is connected to the power supply, and the other end is connected to the switch S1. The on / off control input of the switch S1 is connected to the UP output.

[0056] One end of the second current source I2 is connected to the power supply or ground, and the other end is connected to switch S2. The on / off control input of switch S2 is connected to the output of DN.

[0057] When switches S1 and S2 are connected, they form the VO output terminal.

[0058] The mismatch monitoring and adjustment unit includes a mismatch detection circuit MIS_DET, an AND gate, a first delay chain Delay Line 1, and a second delay chain Delay Line 2.

[0059] like Figure 5As shown, the mismatch detection circuit MIS_DET preferably includes a comparator CMP and a digital logic unit (Digital). The positive terminal of the comparator CMP is connected to the reference voltage VREF, and the negative terminal of the comparator CMP (i.e., the input terminal of MIS_DET) is connected to the output terminal VO. The output terminal of the comparator CMP is connected to the input terminal of the digital logic unit (Digital). The digital logic unit (Digital) has two output terminals, namely UP_TUNE and DN_TUNE. UP_TUNE and DN_TUNE are respectively connected to the delay control terminals of the first delay chain Delay Line 1 and the second delay chain Delay Line 2.

[0060] Furthermore, a grounding capacitor is connected in parallel to the VO output of the frequency and phase detector for filtering and integration.

[0061] Alternatively, the mismatch detection circuit MIS_DET can also employ other structures found in the prior art.

[0062] The input terminals of the AND gate are connected to the UP output terminal and the DN output terminal, respectively; the output terminals of the AND gate are connected to the input terminals of the first delay chain Delay Line 1 and the second delay chain Delay Line 2, respectively.

[0063] The output of the first delay line (Delay Line 1) and the output of the second delay line (Delay Line 2) are respectively connected to two REST signal terminals.

[0064] Both the first delay chain (Delay Line 1) and the second delay chain (Delay Line 2) are variable delay chains, capable of achieving capacitance values ​​in the 1e-15 range. Since the delay of a variable delay chain is continuously adjustable, using an analog delay chain allows for higher precision calibration.

[0065] like Figure 6 As shown, both the first delay chain Delay Line 1 and the second delay chain Delay Line 2 include several capacitor arrays connected in series, and adjacent capacitor arrays are connected by inverters; each capacitor array includes n capacitors in parallel, and each capacitor is controlled by a switch; where n≥2.

[0066] Alternatively, the first delay chain Delay Line 1 and the second delay chain Delay Line 2 can also adopt other structures in the prior art, such as analog delay chains or digital delay chains.

[0067] Modern CMOS processes easily achieve capacitance values ​​in the 1e-15 range, enabling precise femtosecond-level delay control through small capacitance values. This invention achieves current mismatch calibration by controlling the conduction time of current mirrors I1 and I2 through Delay Line 1 and Delay Line 2. Since the delay lines are easily controlled at the femtosecond level, this scheme facilitates high-precision charge pump mismatch calibration. Currently, existing calibration schemes all use current mirror arrays for calibration (e.g., Figure 2 and Figure 3 The cost of implementing a high-precision current mirror array using modern CMOS technology is far greater than the cost of implementing a high-precision delay connection. Therefore, the mismatch calibration circuit method proposed in this invention has higher accuracy than existing solutions.

[0068] A phase-locked loop comprising the charge pump mismatch calibration circuit described in any of the preceding claims.

[0069] A charge pump mismatch calibration method includes the following steps.

[0070] Step 1, Equal Width Pulse Control: When the charge pump mismatch requires calibration (i.e., the comparator CMP continuously outputs two or more digital "0"s or "1"), the inputs of both MUXs in the frequency and phase detector are connected to the reference clock REFCLK. The UP and DN outputs of the frequency and phase detector are as follows: Figure 7 The equal-width pulse signals shown control charge switch S1 and charge switch S2 respectively.

[0071] Step 2, VO output voltage comparison: The mismatch detection circuit MIS_DET includes a comparator CMP and digital logic; the comparator CMP acquires the VO output voltage and compares the acquired VO output voltage with the built-in reference voltage VREF.

[0072] Step 3: CMP output value control: When the voltage at the VO output terminal is greater than the reference voltage VREF, the current of the first current source I1 is greater than the current of the second current source I2, and the comparator CMP outputs the digital value "0"; otherwise, it outputs the digital value "1".

[0073] Step 4, Delay Control: The digital logic unit (Digital) acquires the output of the comparator (CMP) in real time and performs the following delay control:

[0074] A. When the comparator CMP outputs two or more consecutive "0"s (also known as a long "0"), the digital logic increases the delay of the second delay chain Delay Line 2 or decreases the delay of the first delay chain Delay Line 1.

[0075] B. When the comparator CMP outputs two or more consecutive digital "1"s (also known as a long "1"), the digital logic will either decrease the delay of the second delay chain Delay Line 2 or increase the delay of the first delay chain Delay Line 1.

[0076] Step 5, Variable Width Pulse Control: The first D flip-flop DFF1 in the frequency and phase detector generates a pulse signal with a width of T1 based on the output of the first delay line 1 in step 4, which is used to control the charge switch S1; the second D flip-flop DFF2 in the frequency and phase detector generates a pulse signal with a width of T2 based on the output of the second delay line 2 in step 4, which is used to control the charge switch S2; the control method for T1 and T2 is as follows:

[0077] A. When the comparator CMP outputs two or more consecutive digits "0", T1 < T2.

[0078] B. When the comparator CMP outputs two or more consecutive "1"s, T1 > T2. At this time, the waveforms output by the UP and DN terminals of the frequency and phase detector are as follows: Figure 8 As shown.

[0079] Step 6: Repeat steps 2 to 5 until the comparator CMP output alternates between the digital "0" and "1" and the switching frequency is equal to the frequency of the reference clock REFCLK. At this point, the mismatch calibration is complete. The input signals of the first delay chain DelayLine1 and the second delay chain DelayLine2 are latched. MUX1 in the frequency and phase detector is connected to the reference clock REFCLK, and MUX2 in the frequency and phase detector is connected to the feedback clock FBCLK.

[0080] This invention achieves charge pump current mismatch calibration at minimal cost, helping to reduce PLL output spurious signals and improve PLL output clock quality. The beneficial effects are: First, this circuit reduces charge pump current mismatch, thereby improving PLL output clock quality; second, this circuit is easier to calibrate with high precision compared to traditional numerically controlled current array structures; third, this circuit can be applied to systems such as charge pump PLLs and delay PLLs, and is easy to integrate directly.

[0081] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A charge pump mismatch calibration circuit, characterized in that: Includes a frequency and phase detector, a charge pump, and a mismatch monitoring and adjustment unit; The frequency and phase detector has two REST signal terminals, a UP output terminal, and a DN output terminal; The charge pump includes a first current source I1, a second current source I2, a charge switch S1, and a charge switch S2; One end of the first current source I1 is connected to the power supply, and the other end is connected to the charge switch S1. The on / off control input of the charge switch S1 is connected to the UP output. One end of the second current source I2 is connected to the power supply or ground, and the other end is connected to the charge switch S2. The on / off control input terminal of the charge switch S2 is connected to the output terminal of DN. Charge switch S1 and charge switch S2 are connected to form the VO output terminal; The mismatch monitoring and adjustment unit includes a mismatch detection circuit MIS_DET, an AND gate, a first delay chain Delay Line 1, and a second delay chain Delay Line 2; The input terminal of the mismatch detection circuit MIS_DET is connected to the output terminal of VO. The output terminals of the mismatch detection circuit MIS_DET are UP_TUNE and DN_TUNE, which are connected to the delay control terminal of the first delay chain Delay Line 1 and the delay control terminal of the second delay chain Delay Line 2, respectively. The mismatch detection circuit MIS_DET includes a comparator CMP and a digital logic unit (Digital). The positive terminal of the comparator CMP is connected to the reference voltage VREF, and the negative terminal of the comparator CMP is connected to the VO output terminal. The output terminal of the comparator CMP is connected to the input terminal of the digital logic unit (Digital). The digital logic unit (Digital) has two output terminals, namely UP_TUNE and DN_TUNE. The inputs of the AND gate are connected to the outputs of UP and DN, respectively; the outputs of the AND gate are connected to the inputs of the first delay chain Delay Line 1 and the second delay chain Delay Line 2, respectively. The output of the first delay line (Delay Line 1) and the output of the second delay line (Delay Line 2) are respectively connected to two REST signal terminals.

2. The charge pump mismatch calibration circuit according to claim 1, characterized in that: The frequency and phase detector module includes two D flip-flops and two MUXs; The two D flip-flops are designated as DFF1 (first D flip-flop) and DFF2 (second D flip-flop). The output of the first D flip-flop DFF1 is the UP output, and the output of the second D flip-flop DFF2 is the DN output; each D flip-flop has a REST signal terminal and a clock input terminal. The two MUXs are MUX1 and MUX2; the inputs of each MUX are connected to the reference clock REFCLK and the feedback clock FBCLK, respectively; the output of MUX1 is connected to the clock input of the first D flip-flop DFF1; the output of MUX2 is connected to the clock input of the second D flip-flop DFF2.

3. The charge pump mismatch calibration circuit according to claim 1, characterized in that: A grounding capacitor is also connected in parallel to the VO output terminal of the frequency and phase detector.

4. The charge pump mismatch calibration circuit according to claim 1, characterized in that: Both the first delay chain (Delay Line 1) and the second delay chain (Delay Line 2) are variable delay chains, capable of achieving 1e. -15 Level of capacitance value.

5. The charge pump mismatch calibration circuit according to claim 4, characterized in that: The first delay line (Delay Line 1) and the second delay line (Delay Line 2) each include several capacitor arrays connected in series, with adjacent capacitor arrays connected by inverters; each capacitor array includes n capacitors in parallel, and each capacitor is controlled by a switch; where n≥2.

6. A phase-locked loop, characterized in that: Includes the charge pump mismatch calibration circuit as described in any one of claims 1 to 5.

7. A charge pump mismatch calibration method, characterized in that: Includes the following steps: Step 1, Equal Width Pulse Control: When the charge pump mismatch requires calibration, the inputs of the two MUXs in the frequency and phase detector are both connected to the reference clock REFCLK. The UP and DN outputs of the frequency and phase detector output equal width pulse signals to control the charge switch S1 and charge switch S2 respectively. Step 2, VO output voltage comparison: The mismatch detection circuit MIS_DET includes a comparator CMP and digital logic; the comparator CMP acquires the VO output voltage and compares the acquired VO output voltage with the built-in reference voltage VREF; Step 3, CMP output value control: When the voltage at the VO output terminal is greater than the reference voltage VREF, the current of the first current source I1 is greater than the current of the second current source I2, and the comparator CMP outputs the digital value "0"; otherwise, it outputs the digital value "1". Step 4, Delay Control: The digital logic unit (Digital) acquires the output of the comparator (CMP) in real time and performs the following delay control: A. When the comparator CMP outputs two or more consecutive "0" numbers, the digital logic increases the delay of the second delay chain Delay Line 2 or decreases the delay of the first delay chain Delay Line 1. B. When the comparator CMP outputs two or more consecutive "1" numbers, the digital logic will either decrease the delay of the second delay chain Delay Line 2 or increase the delay of the first delay chain Delay Line 1. Step 5, Variable Width Pulse Control: The first D flip-flop DFF1 in the frequency and phase detector generates a pulse signal with a width of T1 based on the output of the first delay line 1 in step 4, which is used to control the charge switch S1; the second D flip-flop DFF2 in the frequency and phase detector generates a pulse signal with a width of T2 based on the output of the second delay line 2 in step 4, which is used to control the charge switch S2; the control method for T1 and T2 is as follows: A. When the comparator CMP outputs two or more consecutive digits "0", T1 < T2; B. When the comparator CMP outputs two or more consecutive "1" numbers, T1 > T2; Step 6: Repeat steps 2 to 5 until the comparator CMP output alternates between the digital "0" and "1" and the switching frequency is equal to the frequency of the reference clock REFCLK. At this point, the mismatch calibration is complete. The input signals of the first delay chain Delay Line 1 and the second delay chain Delay Line 2 are latched. MUX1 in the frequency and phase detector is connected to the reference clock REFCLK, and MUX2 in the frequency and phase detector is connected to the feedback clock FBCLK.

8. The charge pump mismatch calibration method according to claim 7, characterized in that: In step 1, the charge pump mismatch calibration timing is when the comparator CMP outputs two or more consecutive digits "0" or "1".

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