Methods and systems for forming stable tetragonal barium titanate

Abstract

An electro-optical device includes a substrate and a waveguide on the substrate. The waveguide includes a layer stack including a plurality of electro-optical material layers interleaved with a plurality of intermediate layers, a waveguide core adjacent to the layer stack, a waveguide cladding, and a pair of electrodes in electrical contact with the plurality of electro-optical material layers. The plurality of intermediate layers maintain a first crystal lattice structure at room temperature and at a cryogenic temperature. The plurality of electro-optical material layers maintain a second crystal lattice structure and a crystalline phase at room temperature and at the cryogenic temperature.

Description

[0001] Cross-references to other applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 927,373, filed October 29, 2019, entitled “Method and System for Forming Stable Tetragonal Barium Titanate,” the entire contents of which are incorporated herein by reference. Background Technology

[0003] Electro-optic (EO) devices, such as EO modulators and EO switches, have been used in various optical systems, including optical communication and optical computing systems. For example, optical phase modulators can be used in integrated optical systems, optical communication transmitters, or transceivers. EO modulators or EO switches can utilize various EO effects (such as free-carrier electrorefraction, free-carrier electroabsorption, Pockels effect, Kerr effect, etc.) to alter optical properties during operation, such as changing the phase or amplitude of light propagating through certain paths in the EO modulator or EO switch. EO devices using materials with high EO effects can operate at lower control voltages, lower power consumption, and often at higher speeds. Summary of the Invention

[0004] The techniques disclosed herein generally relate to electro-optic (EO) devices. More specifically, the embodiments disclosed herein relate to techniques for achieving high EO effects in EO devices (e.g., optical switches or optical modulators) at low temperatures (e.g., cooling temperatures). In one specific embodiment, an EO device comprising a stack of EO materials is used to improve the modulation and / or switching performance of the EO device at low temperatures, the EO material stack being characterized by a high electro-optic coefficient at low temperatures (e.g., cooling temperatures). The EO material stack may include interleaved and interlocked thin EO material layers and intermediate layers. The EO materials in the EO material layers, when used in bulk, can change their crystal structure at different operating temperatures, while the intermediate layers may have a lattice structure that does not change at the operating temperature. Therefore, when the operating temperature changes, the thin EO material layers interlocked to the intermediate layers can maintain their lattice structure and thus maintain the EO coefficient. The techniques disclosed herein can be used in a variety of photonic and optoelectronic devices operating at low temperatures.

[0005] According to some embodiments, the electro-optic device may include a substrate and a waveguide on the substrate. The waveguide may include a layer stack comprising a plurality of electro-optic material layers interleaved with a plurality of intermediate layers. The waveguide may also include a waveguide core, a waveguide cladding, and a pair of electrodes electrically contacting the plurality of electro-optic material layers adjacent to the layer stack. The plurality of intermediate layers may be configured to maintain a first lattice structure at room temperature and at a cooling temperature. The plurality of electro-optic material layers may maintain a second lattice structure and crystalline phase at room temperature and at a cooling temperature. In some embodiments, the plurality of intermediate layers and the plurality of electro-optic material layers may be characterized by a tetragonal lattice structure at a cooling temperature. In some embodiments, the plurality of electro-optic material layers may be characterized by in-plane polarization at a cooling temperature.

[0006] In some embodiments of the electro-optic device, the plurality of electro-optic material layers may include ferroelectric crystals or ferroelectric thin films. Ferroelectric crystals may include at least one of BaTiO3, (Ba,Sr)TiO3, Pb(Zr,Ti)O3, or (Pb,La)(Zr,Ti)O3. In some embodiments, the plurality of electro-optic material layers may be characterized by a Pockels coefficient greater than 300 pm / V at a cooling temperature. The plurality of intermediate layers may include at least one of MgO, LaAlO3, (Ba,Sr)TiO3, BaHfO3, BaMoO3, BaNbO3, BaZrO3, SrHfO3, SrTiO3, SrMoO3, SrNbO3, or SrZrO3. In some embodiments, the ratio between the thickness of each of the plurality of electro-optic material layers and the thickness of each of the plurality of intermediate layers may be equal to or less than 20:1.

[0007] In some embodiments of electro-optic devices, the waveguide core may include one or more of the plurality of electro-optic material layers. The waveguide cladding may be in physical contact with one of the plurality of electro-optic material layers, and its characteristic may be that its coefficient of thermal expansion and optical refractive index differ from those of the electro-optic material layers. The waveguide cladding may include at least one of, for example, Si3N4, SiO2, Al2O3, MgO, SiCN, SiON, SiCO, SiOCN, or HfO2.

[0008] In some embodiments, the EO device may further include an epitaxial seed layer between the substrate and the waveguide. The epitaxial seed layer may include at least one of, for example, MgO, LaAlO3, BaHfO3, BaZrO3, SrHfO3, SrTiO3, SrMoO3, or SrZrO3. In some embodiments, the EO device may further include a buffer layer between the epitaxial seed layer and the substrate. Each of the electrode pairs may be in physical contact with each of the plurality of electro-optic material layers. In some embodiments, a waveguide cladding may be located between the substrate and the layer stack. The waveguide may be part of a Mach-Zehnder interferometer, a resonator, an optical switch, an electro-optic modulator, etc.

[0009] According to some embodiments, the wafer may include a substrate and a stack of layers on the substrate. The stack of layers may include a plurality of electro-optic material layers and a plurality of intermediate layers interleaved with the plurality of electro-optic material layers. The plurality of intermediate layers may maintain a first lattice structure at room temperature and a cooling temperature, and the plurality of electro-optic material layers may maintain a second lattice structure and a crystalline phase at room temperature and a cooling temperature. In some embodiments, the first lattice structure and the second lattice structure may be the same lattice structure, such as a tetragonal lattice structure. In some embodiments, the wafer may further include an epitaxial seed layer between the substrate and the stack of layers, wherein the epitaxial seed layer may include at least one of, for example, MgO, LaAlO3, BaHfO3, BaZrO3, SrHfO3, SrTiO3, or SrZrO3. In some embodiments, the wafer may further include an oxide layer of the substrate between the epitaxial seed layer and the substrate.

[0010] In some embodiments of the wafer, the plurality of electro-optic material layers may include at least one of BaTiO3, (Ba,Sr)TiO3, Pb(Zr,Ti)O3, or (Pb,La)(Zr,Ti)O3. The plurality of intermediate layers may include at least one of MgO, LaAlO3, (Ba,Sr)TiO3, BaHfO3, BaZrO3, SrHfO3, SrZrO3, or SrNbO3. In some embodiments, the ratio between the thickness of each of the plurality of electro-optic material layers and the thickness of each of the plurality of intermediate layers may be equal to or less than 20:1.

[0011] According to some embodiments, a method may include: depositing a seed layer on a substrate; epitaxially depositing a first electro-optic material layer on the seed layer; annealing the substrate, seed layer, and first electro-optic material layer in an oxygen environment to form an oxide buffer layer between the substrate and the seed layer; depositing a first intermediate layer on the first electro-optic material layer, the first intermediate layer comprising a material capable of maintaining a first lattice structure at room temperature and a cooling temperature; depositing a second electro-optic material layer on the first intermediate layer; and annealing the second electro-optic material layer and the first intermediate layer. The first and second electro-optic material layers may comprise an electro-optic material characterized in that the second lattice structure at a cooling temperature differs from the third lattice structure at room temperature. In some embodiments, the third lattice structure and the first lattice structure may be the same lattice structure, such as a tetragonal lattice structure. In some embodiments, the ratio between the thickness of the first electro-optic material layer and the thickness of the first intermediate layer may be equal to or less than 20:1.

[0012] In some embodiments, annealing the substrate, seed layer, and first electro-optic material layer may include annealing at a temperature higher than the softening temperature of the oxide buffer layer. The method may also include depositing a second intermediate layer (comprising a material that maintains the first lattice structure at room temperature and cooling temperatures) on the second electro-optic material layer, depositing a third electro-optic material layer on the second intermediate layer, and annealing the third electro-optic material layer and the second intermediate layer.

[0013] In some embodiments, the method may further include patterning a third electro-optic material layer to form a waveguide core, and depositing a dielectric coating on the waveguide core. Patterning the third electro-optic material layer may include using a second intermediate layer as an etch barrier to etch the third electro-optic material layer. In some embodiments, the method may further include etching trenches in the first, second, and third electro-optic material layers, as well as the first and second intermediate layers, and filling the trenches with a conductive material. Etching the trenches may include using an oxide buffer layer as an etch barrier to etch the first, second, and third electro-optic material layers.

[0014] In some embodiments, the method may include forming a waveguide on a third electro-optic material layer. In some embodiments, forming a waveguide on the third electro-optic material layer may include forming a waveguide core on the third electro-optic material layer and depositing a dielectric cladding layer on the waveguide core. In some embodiments, forming a waveguide core on the third electro-optic material layer may include depositing a high-refractive-index material layer on the third electro-optic material layer and patterning the high-refractive-index material layer. In some embodiments, forming a waveguide core on the third electro-optic material layer may include depositing a dielectric layer on the third electro-optic material layer, depositing a high-refractive-index material layer on the dielectric layer, and patterning the high-refractive-index material layer. In some embodiments, forming a waveguide on the third electro-optic material layer may include bonding a wafer including the waveguide to the third electro-optic material layer.

[0015] Many benefits are achieved through this disclosure compared to conventional techniques. For example, examples of methods, devices, and systems disclosed herein can maintain the lattice structure at low temperatures (e.g., cooling temperatures), thereby preserving the EO coefficients of ferroelectric materials (e.g., the tetragonal phase and Pockels coefficients of BaTiO3), thus improving the performance of EO devices (e.g., EO switches or EO modulators) at cooling temperatures. This allows for the use of reduced electric fields or bias signals to achieve desired refractive index modulation and / or phase modulation for optical modulation or switching, thereby reducing power consumption and improving device efficiency and / or speed. Furthermore, the embodiments disclosed herein enable a larger effective refractive index change at low temperatures compared to conventional techniques. As a result, device length can be reduced, which in turn reduces the optical loss and physical size of the EO device. These and other embodiments, along with their many advantages and features, will be described in more detail below in conjunction with the accompanying text and figures. Attached Figure Description

[0016] Figure 1A This is a simplified diagram illustrating an example of an optical switch including a Mach-Zehnder interferometer according to certain embodiments; Figure 1B According to certain embodiments Figure 1A A cross-sectional view of an example of the phase adjustment portion in an embodiment of the optical switch shown;

[0017] Figure 2 The effective Pockels coefficients of ABO3 perovskite crystals (e.g., BaTiO3 crystals) with different lattice orientations at temperatures of about 4K to about 340K are shown according to certain embodiments.

[0018] Figures 3A to 3D The phase transitions of BaTiO3 at different temperatures according to certain embodiments are shown;

[0019] Figure 4This is a simplified flowchart illustrating an example of a method for manufacturing an EO device comprising an EO material layer according to certain embodiments, wherein the EO material layer is characterized by a substantially constant EO coefficient from room temperature to a cooling temperature.

[0020] Figure 5A An example of a substrate on which a seed layer is grown, according to certain embodiments, is shown;

[0021] Figure 5B The internal stress and lattice orientation of the ferroelectric material layer epitaxially deposited on the seed layer according to certain embodiments are shown;

[0022] Figure 5C The internal stress and lattice orientation of a ferroelectric material layer epitaxially deposited on a seed layer after high-temperature oxidation annealing, according to certain embodiments, are shown.

[0023] Figure 5D The internal stress and lattice orientation of a ferroelectric material layer interleaved with an intermediate layer in a engineered wafer, according to certain embodiments, are shown.

[0024] Figure 5E The internal stress and lattice orientation of a ferroelectric material layer interleaved with an intermediate layer in a waveguide structure according to certain embodiments are shown.

[0025] Figure 6 The improvement in crystal quality after annealing is shown by an example of an ion channel for an epitaxial layer before and after annealing, according to certain embodiments;

[0026] Figure 7 An example of X-ray diffraction data according to certain embodiments is shown, which illustrates the heterogeneous lattice constant relaxation in an example of an epitaxial layer at high temperature;

[0027] Figure 8 This is a simplified cross-sectional view of an example of a waveguide structure including an EO material layer that maintains a tetragonal phase at a cooling temperature, according to certain embodiments;

[0028] Figure 9 This is a simplified cross-sectional view of another example of a waveguide structure including an EO material layer that maintains a tetragonal phase at a cooling temperature, according to certain embodiments;

[0029] Figure 10 This is a simplified cross-sectional view of yet another example of a waveguide structure comprising an EO material layer that maintains a tetragonal phase at a cooling temperature, according to certain embodiments.

[0030] Figure 11This is a simplified flowchart illustrating an example of a method for manufacturing engineered wafers and / or EO devices according to certain embodiments, the EO devices comprising an EO material layer characterized by a substantially constant EO coefficient from room temperature to low temperature; and

[0031] Figure 12 This is a simplified system block diagram of an example of a hybrid quantum computing system including electro-optic devices according to certain embodiments. Detailed Implementation

[0032] The techniques disclosed herein generally relate to electro-optic (EO) devices. More specifically, the embodiments disclosed herein relate to techniques for achieving high EO effects in EO materials (e.g., ferroelectric materials) at low temperatures such as cooling temperatures, and for utilizing the high EO effects of EO materials in EO devices such as optical modulators and optical switches to reduce power consumption and improve efficiency and speed during cryogenic operation of the EO devices. Embodiments are provided only as examples within the context of integrated optical systems including active optics; however, the techniques disclosed herein are not limited to this example and have broad applicability to a wide range of optical and optoelectronic systems. Various embodiments of the invention are described herein, including methods, processes, materials, wafers, systems, devices, etc.

[0033] EO devices using materials with higher EO effects can operate at lower control voltages, lower power consumption, and higher speeds compared to devices using materials with relatively low EO coefficients. In some applications (e.g., linear optical quantum computing), EO devices can operate at very low temperatures, such as cooling temperatures (e.g., around 4K). The EO effects (e.g., Pockels coefficient) of some EO materials can degrade significantly at low temperatures. For example, BaTiO3 (BTO) can be used for EO switches due to its high Pockels coefficient (e.g., greater than about 900 picometers / V at room temperature) and compatibility with silicon CMOS processes. However, the Pockels coefficient of BTO at about 4K can degrade to less than one-third of the Pockels coefficient at room temperature. Therefore, the efficiency of EO switches can decrease significantly at low temperatures. Room temperature, as defined herein, is a temperature of about 20°C, and more specifically, a temperature between 18°C ​​and 22°C. Cooling temperature, as defined herein, is a temperature below -150°C, and more specifically, a temperature between -150°C and -273°C.

[0034] According to certain embodiments, it has been determined that the degradation of the EO effect (e.g., Pockels coefficient) of some EO materials at low temperatures can be caused by crystalline phase transitions of the EO material lattice at different temperatures. For example, BTO can undergo a crystalline phase transition from a tetragonal phase at room temperature to an orthorhombic phase below room temperature, and then to a rhombohedral phase tending towards the cooling temperature. The crystalline phase transition from the tetragonal to the rhombohedral phase may contribute to the degradation of the Pockels effect from room temperature to the cooling temperature. Therefore, according to certain embodiments, by maintaining the tetragonal lattice structure of the EO material at low temperatures, the EO effect of the EO material can be maintained at a high level (e.g., close to room temperature) at low temperatures. In some embodiments, this can be achieved, for example, by interlocking a thin layer of EO material with an intermediate layer that does not undergo lattice structure (or crystalline phase) and polarization changes when the operating temperature drops from room temperature to the cooling temperature, or by subjecting the EO material to a crystalline phase transition at a temperature different from the crystalline phase transition temperature of the EO material, thereby hindering the crystalline phase transition of the EO material. As the operating temperature decreases, the intermediate layer can help maintain stress in the EO material and prevent the EO material layer from changing its lattice structure and polarization. As a result, the EO coefficient of the EO material can be maintained at a level close to that at room temperature. Therefore, EO devices, including those with interleaved structures, can maintain high efficiency and speed at cooling temperatures.

[0035] According to certain embodiments, the active photonic devices described herein can utilize high electro-optic effects, such as the Pockels effect, to efficiently modulate and / or switch optical signals at low temperatures. For example, the techniques disclosed herein can be applied to optical modulators and optical switches, in which the intensity of transmitted light can be modulated according to, for example, a sine or square function, and in which light can be selected from one or more input ports (e.g., waveguides) and output to one or more output ports (e.g., waveguides).

[0036] According to certain embodiments, EO materials can be used in devices with different waveguide structures and / or waveguide structures manufactured using different processes. For example, EO materials can be used as waveguide cores, lower cladding layers, and / or upper cladding layers in waveguide structures. In various embodiments, the waveguide core can be deposited on or etched in the EO material layer, or it can be formed on a semiconductor substrate and then bonded to a wafer or device containing the EO material layer.

[0037] Several illustrative embodiments will now be described with reference to the accompanying drawings, which form part of this disclosure. The following description provides only one or more embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of the embodiments will provide those skilled in the art with a feasible description for implementing one or more embodiments. It should be understood that various changes can be made to the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for purposes of explanation to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that various embodiments can be practiced without these specific details. The drawings and description are not intended to be limiting. The words “example” or “exemplary” are used herein to mean “serves as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0038] Silicon photonic integrated circuits (PICs) can offer superior performance compared to electrical integrated circuits (EICs) (e.g., lower losses, higher speeds, higher bandwidths, and thermal insulation) and can be used for quantum communication or quantum computing, where photons, due to their quantum properties, can be used as qubits, and optical interconnects can provide higher bandwidth for digital data transmission between cryogenic processors and room-temperature environments. However, due to the lack of effective EO modulation for optical switching and / or optical modulation at cryogenic temperatures, there is a need to partially improve the performance of PICs at cooled temperatures. For example, some integrated circuits operating at cooled temperatures can use thermo-optical phase shifters or plasmonic dispersive switches, which are subject to some inherent limitations. Thermo-optical switches, which use heat to change the refractive index of materials, require significant cooling power and can have low bandwidth and low switching speeds. Plasmonic dispersive switches can use high doping levels to compensate for charge carrier freezing at cryogenic temperatures, thus allowing the use of small resonators with high resistance, high insertion loss, and low bandwidth.

[0039] Some EO materials can exhibit a linear electro-optic effect, where the refractive index of the material can vary proportionally to the strength of the electric field applied to it. This linear electro-optic effect is called the Pockels effect and can occur in non-centrosymmetric materials such as crystalline materials like lithium niobate (LiNbO3), lithium tantalate (LiTaO3), potassium dideuterium phosphate (KDP), barium β-borate (BBO), and potassium titanium phosphate (KTP), as well as some compound semiconductors such as gallium arsenide (GaAs) and indium phosphide (InP). EO switches based on the Pockels effect can exhibit low propagation loss, high bandwidth, and low quiescent power consumption at room temperature. Furthermore, EO switches based on the EO Pockels effect may not be inherently limited by thermo-optic effects and plasmonic dispersion effects at cooled temperatures.

[0040] Figure 1A This is a simplified diagram illustrating an example of an optical switch 100 including a Mach-Zehnder interferometer 120 according to certain embodiments. In the example shown in FIG1, the optical switch 100 includes two input ports (input port 1 and input port 2) and two output ports (output port 1 and output port 2). The input and output ports of the optical switch 100 can be implemented, for example, using optical waveguides operable to support single-mode or multimode beams. The optical switch 100 can be implemented using a Mach-Zehnder interferometer 120 integrated with a set of 50 / 50 beamsplitters (or directional couplers) (such as a first 50 / 50 beamsplitter 105 and a second 50 / 50 beamsplitter 107). As shown in FIG1, input ports 1 and 2 can be optically coupled to the first 50 / 50 beamsplitter 105, which can receive light from either input port 1 or input port 2. The first 50 / 50 beam splitter 105 can guide approximately 50% of the input light from input port 1 into the first waveguide 110 and approximately 50% of the input light from input port 1 into the second waveguide 112 via evanescent coupling. Similarly, the first 50 / 50 beam splitter 105 can guide approximately 50% of the input light from input port 2 into the first waveguide 110 and approximately 50% of the input light from input port 2 into the second waveguide 112. Therefore, the input light from the input ports can be split approximately uniformly and guided into the first waveguide 110 and the second waveguide 112.

[0041] The Mach-Zehnder interferometer 120 may include a phase adjustment section 122, which includes a waveguide 124 and electrodes 126. A voltage signal V0 can be applied across the waveguide 124 via the electrodes 126 in the phase adjustment section 122 to adjust the refractive index of the waveguide 124, thereby adjusting the phase delay of the light after passing through the phase adjustment section 122. Because the light in the first waveguide 110 and the second waveguide 112 is in phase after propagating through the first 50 / 50 beam splitter 105, the phase adjustment in the phase adjustment section 122 can introduce a predetermined phase difference between the light propagating in waveguides 130 and 132. As will be apparent to those skilled in the art, the phase relationship between the light propagating in waveguides 130 and 132 can cause the output light to appear at output port 1 (e.g., when the beams are in phase) or output port 2 (e.g., when the beams are out of phase), thus providing a switching function when guiding light to output port 1 or output port 2 based on the voltage signal V0 applied to the phase adjustment section 122. Although a single active arm is shown in Figure 1, in some other embodiments, both arms of the Mach-Zehnder interferometer 120 may include phase adjustment sections.

[0042] As shown in Figure 1, compared to all optical switching technologies, electro-optical switching technology applies an electrical bias voltage (e.g., a voltage signal V0 in Figure 1) across the active region of the switch to produce optical changes. The electric field or current generated by the applied bias voltage can cause changes in one or more optical properties (e.g., refractive index or light absorption) of the active region. In addition to the power consumed by the current (in the case where the current is generated by the applied bias voltage), energy can also be consumed by generating an electric field, which can have an E0 2 The energy density is κ / 8π (cgs units), where E is the electric field and κ is the dielectric constant.

[0043] Although Figure 1 shows an example of a Mach-Zehnder interferometer implementation, other switching architectures and / or other phase adjustment devices can be used in various embodiments, including ring resonator designs, disk resonator designs, Mach-Zehnder modulators, universal Mach-Zehnder modulators, etc. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0044] The aforementioned phase adjustment can be achieved using EO effects, such as the Pockels effect and / or the Kerr effect. The Pockels effect alters or produces birefringence in an optical medium subjected to an electric field, where birefringence is proportional to the applied electric field. The Pockels effect can occur in crystals lacking inversion symmetry, such as perovskite crystals, ferroelectric crystals, or other non-centrosymmetric media (such as electrically polarized polymers or glass). In the Kerr effect, the change in refractive index (or birefringence) is proportional to the power (e.g., squared) of the applied electric field. All materials can exhibit the Kerr effect, but some materials can exhibit a higher Kerr effect than others. Typically, the Pockels effect can be a much higher EO effect than the Kerr effect.

[0045] Ferroelectric crystals typically exhibit spontaneous polarization that can be reoriented by an electric field or stress. Spontaneous polarization can be induced by non-centrosymmetric crystal structures that are stable over certain temperature ranges. Some examples of ferroelectric crystals exhibiting the Pockels effect include BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), (Pb(Zr,Ti)O3 (PZT), (Pb,La)(Zr,Ti)O3 (PLZT), and (Sr,Ba)Nb2O6 (SBN). For example, barium titanate (BTO) has a relatively large Pockels coefficient at room temperature. Furthermore, BTO can be grown on large Si substrates and integrated into Si photonic platforms using silicon CMOS processes. Therefore, BTO is suitable for a wide range of electronic applications due to its excellent ferroelectric properties, high dielectric constant, low dielectric loss, chemical and mechanical stability, and CMOS process compatibility.

[0046] Figure 1B According to certain embodiments Figure 1A A cross-sectional view of an example of a phase adjustment portion 150 (e.g., phase adjustment portion 122) in an embodiment of the optical switch 100 shown. The phase adjustment portion 150 may utilize the EO effect, such as the Pockels effect described above. The phase adjustment portion 150 may include a substrate 152, optionally a buffer layer 154, a seed layer 156, an EO material layer 158, a waveguide core 162, a waveguide cladding 160, and an electrode 164. The EO material layer 158 may have a high Pockels coefficient and may include, for example, a perovskite ferroelectric or other ferroelectric crystal, such as barium titanate (BaTiO3 or BTO) as described herein.

[0047] Substrate 152 may include a semiconductor substrate, such as a silicon wafer, germanium wafer, germanium-on-silicon wafer, silicon-on-insulator (SOI) wafer, etc. Seed layer 156 may have a lattice structure similar to that of EO material layer 158, and may include, for example, MgO, BaHfO3, BaZrO3, LaAlO3, SrHfO3, SrTiO3, SrMoO3, or SrZrO3. Seed layer 156 may be deposited (e.g., epitaxially grown) on substrate 152. In some embodiments, buffer layer 154 may be located between seed layer 156 and substrate 152. Buffer layer 154 may include, for example, an oxide layer of the substrate (e.g., a SiO2 layer). In one example, buffer layer 154 (e.g., SiO2) may be formed by high-temperature oxidative annealing of seed layer 156 (e.g., SrTiO3) and substrate 152 (e.g., Si) in an oxygen environment.

[0048] An EO material layer 158 may be epitaxially deposited on a seed layer 156. A waveguide core 162 may be formed directly on top of the EO material layer 158, or indirectly on the EO material layer 158, for example, by deposition and photolithography, wherein a buffer layer is located between the EO material layer 158 and the waveguide core 162. This buffer layer may be used to prevent interaction between the EO material layer 158 and the waveguide core 162, and / or as an etching barrier layer for forming the waveguide core 162. The waveguide core 162 may include, for example, Si, SiN, SiGe, EO materials (e.g., BTO), etc. The waveguide cladding 160 may include a dielectric material with a refractive index lower than that of the waveguide core 162, such as oxides, nitrides or oxynitrides, carbon oxides, etc. (e.g., SiO2, Si3N4, SiON, SiCO, etc.), and may be deposited on the waveguide core 162. Trenches may be etched in the waveguide cladding 160 and filled with a conductive material (e.g., metal) to form electrodes 164. Electrode 164 can be used to apply a bias voltage and thus an electric field across the EO material layer 158 to modulate its refractive index for phase adjustment.

[0049] As mentioned above, some perovskite ferroelectrics (e.g., barium titanate) can possess large Pockels coefficients at room temperature. The Pockels coefficient of perovskite ferroelectric materials can vary with different lattice orientations. Furthermore, the Pockels coefficient of perovskite ferroelectric materials can differ at different operating temperatures. For example, at low temperatures, the Pockels coefficient of ferroelectric materials can decrease significantly.

[0050] Figure 2 The effective Pockels coefficients of BaTiO3 with different lattice orientations at temperatures ranging from about 4 K to about 340 K are shown, as reported, for example, in "An integrated Cryogenic Optical Modulator" published in the 2019 issue of the Journal of Applied Physics by Felix Eltes et al. In Figure 2 In the diagram, the x-axis corresponds to the operating temperature between 4K and 340K, and the y-axis corresponds to the Pockels coefficient (in pm / V). Curve 210 shows the corresponding Pockels coefficient for a BTO layer with a 45° lattice orientation at different temperatures. Curve 220 shows the corresponding Pockels coefficient for a BTO layer with a 22.5° lattice orientation at different temperatures. Curve 230 shows the corresponding Pockels coefficient for a BTO layer with a 67.5° lattice orientation at different temperatures. Curve 240 shows the corresponding Pockels coefficient for a BTO layer with a 90° lattice orientation at different temperatures. Curves 210-240 show that the Pockels effect of BTO is anisotropic; therefore, the EO effect can be a function of the lattice orientation in the BTO layer of an EO device.

[0051] Curves 210-240 also show the temperature dependence of the Pockels coefficient. For example, Figure 2 The results show that when the lattice orientation in the BTO layer is approximately 45°, the Pockels coefficient can be highest between approximately 200 K and approximately 260 K, for example, at approximately 240 K, where the Pockels coefficient can be greater than 700 pm / V. Below approximately 240 K, the Pockels coefficient gradually decreases to approximately 200 pm / V at 4 K, which is less than one-third of the Pockels coefficient at room temperature. Furthermore, the Pockels coefficient decreases rapidly from approximately 140 K to approximately 100 K.

[0052] Although the Pockels coefficient of BaTiO3 decreases significantly at 4 K compared to its room-temperature Pockels coefficient, this value (e.g., approximately 200 pm / V) is still greater than that of some other materials at room temperature. The impact of the reduced Pockels coefficient on the energy efficiency of EO switches can be partially compensated for by lowering the dielectric constant of BaTiO3 at low temperatures. Furthermore, the conductivity of BaTiO3 decreases at low temperatures, which helps to reduce the quiescent power consumption of BaTiO3 devices in cooled environments.

[0053] To improve the performance of Pockels-based EO devices at cooling temperatures, it is desirable to maintain a high room-temperature Pockels coefficient for the EO material at these temperatures. According to some embodiments, it has been determined that a reduction in the Pockels effect can be at least partially caused by changes in the strain and polarization of the crystal with temperature, as well as transitions in the crystallographic phase and polarization at certain temperatures, because, as mentioned above, the Pockels effect can occur in crystals lacking inversion symmetry (e.g., non-centrosymmetric), and the non-zero elements of the Pockels tensor can depend on crystal symmetry. Therefore, if the EO material can maintain its room-temperature crystal structure at cooling temperatures, the Pockels coefficient of the EO material at low temperatures can be improved.

[0054] Figures 3A to 3D The crystallization phase transitions of ABO3 perovskite crystals (e.g., BaTiO3) at different temperatures are shown. Barium titanate (BaTiO3) can typically be in a paraelectric phase without net polarization above the Curie temperature (e.g., at about 120 °C). Figure 3A The cubic crystal structure 310 of BaTiO3 above the Curie temperature is shown. Large barium ions (A ions) typically occupy corner positions. Small titanate ions (B ions) are typically located at the center of the cube. Oxygen anions are typically located at the surface center. Unlike many other oxide crystals, oxygen anions in perovskite crystals may not form a close-packed structure. Therefore, the crystal structure of perovskite crystals (e.g., BaTiO3) can be altered by temperature variations and stress within the perovskite crystal. At approximately the Curie temperature, the crystal can undergo a phase transition (also known as a displacement phase transition) and can adopt a polar tetragonal phase in the temperature range of approximately 5 °C to approximately 120 °C.

[0055] Figure 3BA polar tetragonal crystal structure 320 in BaTiO3 is shown in the temperature range of approximately 5 °C to approximately 120 °C. The polar tetragonal crystal structure 320 can be formed when cooled from the Curie temperature. The formation of the tetragonal structure can permanently polarize the unit cell, which can lead to spontaneous polarization along the c-axis, which can be parallel to the six equivalent polarization axes in the cubic crystal structure 310. <100> Any one of the axes. Therefore, a polar tetragonal phase can have 6 stable polarization directions parallel to the cell edge, resulting in 6 different crystal variants.

[0056] Figure 3C The orthorhombic crystal structure 330 in BaTiO3 is shown in the temperature range from about -90°C to about 5°C. (Example) Figure 3C As shown, upon further cooling to below approximately 5°C, the unit cell of BaTiO3 can be expanded along its face diagonal ( <110> The crystal structure 332 elongates and deforms further, and the tetragonal crystal structure 320 can be transformed into an orthorhombic crystal structure 330. There can be 12 identical crystal structures in the cubic crystal structure 310. <110> The direction of polarity can result in 12 possible polarity directions in the orthorhombic phase. The orthorhombic phase is stable from about 5°C to about -90°C.

[0057] Figure 3D The rhombohedral crystal structure 340 in BaTiO3 is shown at temperatures below approximately -90°C. Figure 3D As shown, upon further cooling to below approximately -90°C, the unit cell of BaTiO3 can be oriented along the main diagonal ( <111> Direction 342 undergoes another deformation, resulting in a rhombohedral symmetric structure. In the cubic crystal structure 310, along... <111> A rhombohedral phase can have 8 equivalent polar directions.

[0058] Therefore, bulk BaTiO3 crystals can transform from a tetragonal phase at room temperature to a tetragonal phase at or below 270 K, and then to a rhombohedral phase at or below 180 K. This crystal structure and phase transition can be found in many perovskite ferroelectrics. The phase transition can change the elements of the Pockels tensor and modify the magnitude of the effective Pockels coefficient.

[0059] As mentioned above, crystal structure and phase transitions can also influence the available polarization orientation. At the microstructural level, regions with uniform polarization can form domains, where each domain is a region comprising a single-crystal variant. The interface between domains can be called a domain wall. Ferroelectric crystals can employ domains and domain walls arranged in a stable minimum energy order. In many cases, a global minimum may not be achievable, and the steady state may be a local energy minimum. Energy minimization may result in crystals with multiple domains separated by domain walls, which are oriented to minimize energy by maintaining compatibility between strain and polarization across the walls.

[0060] Therefore, by maintaining the room-temperature crystal structure and polarization orientation at cooling temperatures, the Pockels coefficient of the EO material at low temperatures can be improved. For example, according to some embodiments, the EO material layer may comprise interleaved and interlocked thin EO material layers and an intermediate layer. The intermediate layer may have a lattice structure that does not change at the operating temperature. Thus, the thin EO material layers interlocked to the intermediate layer can maintain their lattice structure and polarization orientation, and thus maintain the EO coefficient without undergoing a phase transition when the operating temperature changes (as mentioned above). Figures 3A-3D The above).

[0061] Figure 4 This is a simplified flowchart 400 illustrating an example of a method for manufacturing an EO device comprising an EO material layer according to certain embodiments, the EO material layer being characterized by a substantially constant EO coefficient from room temperature to cooling temperature. Even Figure 4 The operations are described in a sequential flow, but some operations may also be performed in parallel or simultaneously. Some operations may be performed in a different order. Operations may have additional steps not included in the figures. Some operations may be optional and therefore may be omitted in various embodiments. Some operations may be performed together with another operation.

[0062] At frame 410, a seed layer (e.g., seed layer 156) may be deposited on a substrate (e.g., substrate 152). As described above, the substrate may be a semiconductor wafer, such as a single-crystal silicon wafer, a germanium wafer, a germanium-on-silicon wafer, a silicon-on-insulator (SOI) wafer, etc. The substrate may include semiconductor wafers of various sizes, such as 4 inches, 6 inches, 8 inches, 10 inches, 12 inches, or larger. Typically, it is desirable to use larger wafers to improve productivity. For example, a 12-inch silicon wafer may be used as the substrate.

[0063] The seed layer can have a lattice structure similar to that of the EO material used in EO devices, and can include, for example, SrTiO3 (STO), MgO, or LaAlO3. The seed layer can be epitaxially deposited or grown on the substrate using, for example, molecular beam epitaxy (MBE). In one embodiment, Sr and Ti can be deposited on the surface of a silicon wafer in an oxygen environment to form an amorphous SrTiO3 layer, and the amorphous SrTiO3 layer can be crystallized at a higher temperature to form an epitaxially crystalline SrTiO3 layer. The lattice mismatch between Si and STO can be approximately 2%, and when the thickness of the STO layer is less than, for example, approximately 5 nm, high-quality STO can be primarily coherent with silicon.

[0064] Figure 5AExamples of substrates 510 (e.g., semiconductor wafers) having an epitaxial seed layer 520 according to certain embodiments are described. In the example shown in FIG. 5, substrate 510 may include a silicon or SOI wafer. Epitaxial seed layer 520 may include a coherent epitaxial STO layer, which may have a thickness of, for example, a few nanometers or tens of nanometers, such as less than about 8 nm or less than about 5 nm.

[0065] See again Figure 4 At frame 420, a thin first EO material layer can be deposited on the seed layer, for example, by epitaxial deposition. The thin first EO material layer can include, for example, ferroelectric or perovskite ferroelectric materials, such as BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), (Pb(Zr,Ti)O3 (PZT), (Pb,La)(Zr,Ti)O3 (PLZT), etc. The thin first EO material layer can have a thickness of less than, for example, 100 nm. The lattice mismatch between BTO and silicon can be approximately 4%, and when the thickness of the BTO layer is less than approximately 100 nm, the BTO layer can be partially coherent with Si / STO, which may lead to compressive stress in the BTO layer. Therefore, the thin first EO material layer (e.g., BTO) deposited on the seed layer may exhibit out-of-plane polarization due to compressive stress.

[0066] Figure 5B The internal stress and lattice orientation of an EO material layer 530 epitaxially deposited on a seed layer 520 according to certain embodiments are shown. As described above, the EO material may include, for example, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), (Pb(Zr,Ti)O3 (PZT), (Pb,La)(Zr,Ti)O3 (PLZT), etc. When deposited, the EO material layer 530 (e.g., BTO on STO / Si) may primarily comprise domains having a tetragonal structure 525, wherein the c-direction of the tetragonal structure 525 is perpendicular to the layer 530 (i.e., out-of-plane polarization), due to... Figure 5B The compressive stress is shown. Layer 530 can be a thin layer, for example, less than 100 nm or thinner, so that the ferroelectric material in layer 530 is locked to the intermediate layer with a tetragonal structure at low temperature.

[0067] exist Figure 4At frame 430, the substrate, seed layer, and thin first EO material layer can be annealed in an oxygen environment at a relatively high temperature (e.g., above the melting point of SiO2). For example, the annealing temperature can be above 600°C, such as 750°C or higher. High-temperature annealing can help release stress and form a buffer layer at the interface between the substrate (e.g., Si) and the seed layer (e.g., STO). The buffer layer can include an oxide layer, such as a SiO2 layer. For example, silicon at the interface between the substrate and the seed (e.g., STO) layer can be oxidized in a high annealing temperature and an oxygen environment to form a SiO2 layer. When the annealing temperature is above the melting point of the buffer layer (e.g., about 600°C), the buffer layer (e.g., SiO2) can soften, and therefore the seed layer and thin first EO material layer can separate from the substrate and allow stress release in the seed layer and thin first EO material layer. Therefore, due to the softening of SiO2 during high-temperature annealing, the stress in the EO material (e.g., BTO) can change from compressive stress to natural stress, and the quality of the seed layer and thin first EO material layer can be improved.

[0068] At high temperatures, the coefficients of thermal expansion (CTE) between BTO (e.g., approximately 3.5E-6 / ℃) and silicon (e.g., approximately 2.6E-6 / ℃) can differ significantly. Therefore, when the buffer layer (e.g., SiO2) hardens below 550℃ during cooling, the large CTE difference between silicon and BTO can cause the stress in BTO to undergo a transition from natural stress to tensile stress. Thus, at room temperature, the net stress, or principal stress, in BTO may have changed from compressive stress to tensile stress, potentially leading to a change in polarization from out-of-plane polarization to in-plane orientation. Therefore, an annealing temperature can be selected such that BTO is under tensile stress and, upon cooling, exhibits in-plane polarization due to the stress caused by the large CTE difference between BTO and silicon.

[0069] Figure 5C The internal stress and lattice orientation of an EO material layer 530 epitaxially deposited on a seed layer 520 after high-temperature oxidation annealing, according to certain embodiments, are shown. As shown, due to the tensile stress in the layer 530 after annealing as described above, the ferroelectric material layer 530 (e.g., BTO on STO / Si) can primarily comprise domains having a tetragonal structure 535, wherein the c-direction of the tetragonal structure 535 is parallel to the layer 530 (i.e., in-plane polarization). Figure 5C Also shown is a buffer layer 540, such as an oxide layer (e.g., SiO2), formed by oxidation of the substrate during high-temperature oxidation annealing.

[0070] Figure 6An improvement in crystal quality after annealing according to certain embodiments is illustrated by using Rutherford backscattering spectroscopy (RBS) / channel measurements of ion channels for epitaxial layers (e.g., SrTiO3 epitaxial layers) before and after annealing. In the RBS / channel, atoms displaced from their lattice sites can interact with the guided light beam, resulting in an increase in scattering yield. Figure 6 Curve 610 in the figure shows the total number (energy of backscattered particles) detected in different channels of the SrTiO3 epitaxial layer before annealing. As shown, before annealing, the SrTiO3 epitaxial layer comprises many displaced Sr and Ti atoms. Figure 6 Curve 620 in the figure shows the total number of backscattered particles detected in different channels by backscattering from the SrTiO3 epitaxial layer after annealing. Curve 620 shows that the number or percentage of displaced Sr and Ti atoms is significantly reduced, and therefore the quality of the crystalline SrTiO3 epitaxial layer is significantly improved. Even in Figure 6 As not shown in the figure, the quality of the BTO epitaxial layer can also be similarly improved through the annealing process.

[0071] Figure 7 An example of X-ray diffraction data is shown, demonstrating the heterogeneous lattice constant relaxation of an epitaxial layer (e.g., a SrTiO3 epitaxial layer) at high temperatures. SrTiO3 epitaxial layers can be deposited on silicon wafers using, for example, MBE. Figure 7 The results show that, at temperatures below approximately 600°C, heterogeneous thermal lattice expansion can be a linear function of temperature. The heterogeneous lattice constant can begin to relax at approximately 600°C, indicating that STO is under compressive stress below approximately 600°C, and that this compressive stress can be released at temperatures above 600°C.

[0072] Return to reference Figure 4 At frame 440, a thin intermediate layer can be deposited on the first EO material layer (e.g., a BTO layer), and a thin EO material layer (e.g., another BTO layer) can be deposited on the intermediate layer. The intermediate layer and the EO material layer can also be annealed using the high-temperature oxidation annealing described above to relax the BTO, improve crystal quality, and ensure in-plane polarization in the thin BTO layer. The thin intermediate layer and the thin EO material layer can be alternately deposited and annealed in each of multiple process cycles to form a staggered and interlocked stack of intermediate and EO material layers until the total thickness of the EO material layers reaches the target thickness.

[0073] In various embodiments, the intermediate layer may include a crystal structure similar to that of the EO material and may not undergo a phase transition at low temperatures. Therefore, at low temperatures, the intermediate layer may have a crystal structure similar to the room-temperature crystal structure of the EO material. The intermediate layer may include certain oxides, such as MgO, BST, BaHfO3, BaZrO3, SrHfO3, SrNbO3, SrZrO3, or other oxides having a lattice constant close to that of the tetragonal crystal structure of BTO. The intermediate layer may restrict the transformation of BTO from its tetragonal phase at room temperature to other phases at lower temperatures.

[0074] Figure 5D The internal stress and lattice orientation of an EO material layer interleaved with an intermediate layer are shown in an example of an engineered wafer 500 according to certain embodiments. Figure 5D In the example shown, the engineered wafer 500 may include a substrate 510 (e.g., a silicon wafer), a buffer layer 540 (e.g., a SiO2 buffer layer), a seed layer 520 (e.g., an STO layer with a thickness of less than about 8 nm), and a plurality of thin EO material layers 530, 532, 534, etc. (e.g., thin BTO layers, each with a thickness of less than about 100 nm). Between the plurality of thin EO material layers 530, 532, and 534 are a plurality of intermediate layers 550, 552, etc., such as MgO, BST, BaHfO3, BaZrO3, SrHfO3, SrZrO3, SrNbO3, or other oxide layers. Each intermediate layer 550 or 552 may have a thickness of less than, for example, about 10 nm, and may be used to separate the thin BTO layers from each other and to apply tensile stress to the thin BTO layers. In some embodiments, the ratio between the thickness of each EO material layer and the thickness of each intermediate layer may be less than about 20:1, 10:1, 8:1, 5:1, or lower. The net stress or principal stress in the EO material layer can be tensile stress. As described above, the stack of layers including staggered intermediate layers and thin EO material layers can be annealed in a high-temperature annealing process to relax the EO material, improve material quality, and ensure in-plane polarization in the EO material layer (e.g., the c-axis of the crystal structure is parallel to the EO material layer), as shown by the tetragonal structure 535.

[0075] As also described above, the stacking of interlaced and interlocked thin EO material layers and intermediate layers (e.g., BTO / MgO stacks) can maintain tensile stress in the EO material at low temperatures, thereby maintaining the tetragonal structure of the EO material at low temperatures (e.g., cooling temperatures) due to tensile stress. Therefore, the EO effect (e.g., Pockels effect) of the EO material at cooling temperatures can be close to the Pockels effect of the EO material at room temperature.

[0076] At frame 450, the waveguide can be formed on or bonded to a stack of staggered thin EO material layers and intermediate layers. For example, in some embodiments, the waveguide layer (e.g., silicon, SiGe, or Si3N4 layers) can be deposited directly on the stack. The silicon, SiGe, or Si3N4 layers can be patterned using photolithography to form the waveguide core, and a cladding layer (also called a capping layer) can subsequently be deposited on the waveguide core to form the waveguide. The silicon, SiGe, or Si3N4 layers can also be deposited indirectly on the stack, with buffer layers in between. The buffer layers can prevent interaction between the waveguide core and the EO material, and / or serve as an etch barrier layer for patterning the waveguide layers. In some embodiments, a waveguide core and an upper and / or lower cladding layer may be formed on a second substrate and then bonded to a stack of staggered thin EO material layers and intermediate layers (e.g., engineered wafer 500), wherein the substrate of the engineered wafer 500 may later be removed by, for example, horizontal wet etching (e.g., using a sacrificial layer) or other lift-off techniques (e.g., laser lift-off). In some embodiments, some of these thin EO material layers may be used to form the waveguide core.

[0077] The waveguide cladding may include a dielectric material or an EO material having a refractive index lower than that of the waveguide core. The cladding may include, for example, Si3N4, oxides (e.g., SiO2, Al2O3, and MgO), high-κ materials (e.g., hafnium oxide (HfO2), etc.). In some embodiments, an amorphous dielectric cladding with compressive stress (e.g., Si3N4, SiO2, Al2O3, etc.) may be deposited on a stack of staggered thin EO material layers and intermediate layers at a temperature below about 550°C. The cladding may apply tensile stress to the stack of staggered thin EO material layers and intermediate layers to further maintain the tetragonal phase of the EO material. The cladding may also serve as a dielectric layer for wafer-to-wafer or die-to-wafer bonding. In some embodiments, the cladding may serve as an etch barrier layer for certain etching processes. Examples of waveguide structures and EO device configurations using stacks of staggered thin EO material layers and intermediate layers are described in detail below.

[0078] Figure 5EThe internal stress and lattice orientation of EO material layers interleaved with intermediate layers in waveguide structure 505 according to certain embodiments are illustrated. As shown, waveguide core 560 may be adjacent to engineered wafer 500 and may be covered by waveguide cladding 570. Waveguide cladding 570 may include amorphous dielectric cladding (e.g., Si3N4, SiO2, Al2O3, etc.) and may apply tensile stress on the stack of thin EO material layers to maintain the tetragonal phase of the EO material at low temperatures. For example, SiO2 and BTO may have very different CTE characteristics at low temperatures (e.g., cryogenic temperatures), where the CTE of SiO2 may become negative at low temperatures (i.e., expand as the temperature decreases). Therefore, when cooled to cryogenic temperatures, the SiO2 cladding may apply tensile stress on the BTO layer due to the large difference in CTE between the BTO layer and the SiO2 cladding. Thus, the dominant stress in the EO material layer may be tensile stress at temperatures ranging from room temperature to cooling temperature. In this way, the EO material layer can maintain a tetragonal crystal structure and in-plane polarization, wherein the c-axis of the crystal structure can be parallel to the EO material layer.

[0079] At frame 460, the stacked EO material layers can be electrically connected to apply a voltage signal to the EO material layers. For example, trenches can be etched in the overlay and through the stacked EO material layers. A thin conductive liner material layer, such as TiN or Ti and TiN, can first be coated on the trench sidewalls to promote adhesion and prevent diffusion. Then, a conductive electrode material (e.g., W or Co) can fill the trench to form an electrode for the EO device. Alternatively, a conductive barrier material (e.g., TaN) and a liner (e.g., Ta, Co, or Ru) can be first coated on the trench sidewalls to deposit a Cu conductive electrode. In this way, each of the EO material layers can contact the electrode and can receive a voltage signal to change its refractive index due to the electric field generated by the voltage signal.

[0080] Figure 8 This is a simplified cross-sectional view of an example waveguide structure 800 including EO material layers according to certain embodiments, which can maintain a tetragonal phase under cooling. The waveguide structure 800 may include a first portion 802 and a second portion 804, which are bonded together, for example, by wafer-to-wafer fusion bonding. The first portion 802 may include a stack of thin EO material layers 830, 832, 834, and 836 interleaved with thin intermediate layers 840, 842, and 844. (As stated above regarding...) Figure 4 and Figures 5B to 5DThe EO material layers 830, 832, 834, and 836 may include ferroelectric crystals, such as BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), (Pb(Zr,Ti)O3 (PZT), (Pb,La)(Zr,Ti)O3 (PLZT), etc. The intermediate layers 840, 842, and 844 may include, for example, MgO, BST, BaHfO3, BaZrO3, SrHfO3, SrNbO3, SrTiO3, SrZrO3, or other oxides.

[0081] EO material layers and intermediate layers can be formed alternately, allowing them to be interleaved and interlocked to form a staggered stack of layers. The EO material layers and intermediate layers can be thin layers, where the ratio between the thickness of each EO material layer and the thickness of each intermediate layer can be less than about 20:1, 10:1, 8:1, 5:1, or lower. In one example, the thickness of each EO material layer can be about 100 nm or less, and the thickness of each intermediate layer can be about 10 nm or less. The total thickness of the multiple EO material layers in the stack can be greater than a certain value, for example, greater than about 300 nm. The staggered stack of layers can be formed on a seed layer 820, which in turn can be deposited on a semiconductor substrate (e.g., a silicon substrate) as described above. Figure 8 (Not shown in the image). A buffer layer 810 can be formed between the seed layer 820 and the semiconductor substrate using, for example, the high-temperature oxidation annealing process described above.

[0082] The second portion 804 may include a waveguide formed on a substrate 860, which may be a semiconductor substrate (e.g., a silicon-supported wafer) or a glass, quartz, ceramic, or metal substrate. The waveguide may include a waveguide core 870 and a waveguide cladding 880. The waveguide core 870 may include a material with a high refractive index, such as silicon, SiN, SiGe, etc. The waveguide cladding 880 may include a dielectric material with a lower refractive index than the waveguide core 870. The waveguide cladding 880 may include an amorphous dielectric cladding such as Si3N4, SiO2, Al2O3, MgO, SiON, SiCN, SiCON, SiCO, etc. The waveguide cladding 880 can be used as a dielectric layer for wafer-to-wafer bonding and die transfer. When bonded to the first portion 802, the waveguide cladding 880 may apply tensile stress to the staggered stack of thin EO material layers and intermediate layers to maintain the tetragonal phase of the EO material at low temperatures as described above. The second part 804 of the waveguide structure 800 may also include other passive or active devices formed on top of the substrate 860.

[0083] After the first portion 802 and the second portion 804 are bonded together, the stacked semiconductor substrate on which thin EO material layers 830, 832, 834, and 836 and thin intermediate layers 840, 842, and 844 are formed can be thinned or removed, for example, by back grinding, back polishing, horizontal wet etching, lift-off techniques (e.g., laser lift-off), etc. A trench can then be etched down in the first portion 802 from the buffer layer 810 side to the interface between the first portion 802 and the second portion 804, wherein the waveguide cladding 880 can be used as an etch barrier layer for the etching process. Conductive materials such as Ti, TiN, and TaN can be deposited together with electrode metals (e.g., Cu, W, Co, etc.) or otherwise filled into the trench to form electrodes 850.

[0084] Electrode 850 can be used to apply voltage signals to thin EO material layers 830, 832, 834, and 836 via edge contacts rather than surface contacts. Edge contacts can apply voltage signals directly to the EO material layers without passing through an intermediate layer, which may have a different dielectric constant than the EO material. For example, MgO may have a lower dielectric constant than BTO. Therefore, edge contacts can help eliminate field interference caused by the intermediate layer due to the difference in dielectric constant. In some embodiments, the intermediate layer (e.g., a BST layer) may have a dielectric constant similar to that of the EO material (e.g., BTO), and surface contacts can be used to apply voltage signals to the EO material layers.

[0085] Figure 9 This is a simplified cross-sectional view of another example of a waveguide structure 900 including an EO material layer according to certain embodiments, the EO material layer being able to maintain a tetragonal phase under cooling. The waveguide structure 900 may include a substrate 910, which may be similar to substrate 152 or 510 described above. In one example, substrate 910 includes a large (e.g., 12-inch) silicon wafer. The waveguide structure 900 may also include a buffer layer 922 and a seed layer 920 on substrate 910. Buffer layer 922 may be similar to buffer layers 154, 540, or 810 described above. An example of buffer layer 922 is a SiO2 layer. Seed layer 920 may be similar to seed layers 156, 520, or 820 described above. An example of seed layer 920 is an STO layer. As described above, a buffer layer 922 can be formed by high-temperature oxidation annealing of a seed layer 920 deposited on a substrate 910 (e.g., a silicon wafer), wherein the substrate 910 can be oxidized at the interface between the seed layer 920 and the substrate 910 to form the buffer layer 922 between the seed layer 920 and the substrate 910.

[0086] The waveguide structure 900 may include multiple EO material layers 930, 932, 934, etc., and multiple intermediate layers 940, 942, etc. As described above, the EO material layers 930, 932, and 934 may include ferroelectric crystals, such as BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), (Pb(Zr,Ti)O3 (PZT), (Pb,La)(Zr,Ti)O3 (PLZT), etc. The intermediate layers 940 and 942 may include, for example, MgO, BST, BaHfO3, BaZrO3, SrHfO3, SrNbO3, SrTiO3, SrZrO3, or other oxides. The EO material layers and intermediate layers may be deposited alternately on the seed layer. At the top of layer 920, the EO material layers and intermediate layers can be staggered and interlocked to form a stack of staggered layers. The EO material layers and intermediate layers can be thin layers, where the ratio between the thickness of each EO material layer and the thickness of each intermediate layer can be less than approximately 20:1, 10:1, 8:1, 5:1, or lower. In one example, the thickness of each EO material layer can be approximately 100 nm or less, and the thickness of each intermediate layer can be approximately 10 nm or less. The total thickness of the multiple EO material layers in the stack can be greater than a certain value, such as greater than approximately 300 nm.

[0087] A waveguide, including a waveguide core 950 and a cladding layer 960, can be formed on a stack of interleaved layers, as described above for example. Figure 4 The frame 450 and Figure 5E As described. The waveguide core 950 may include, for example, Si, SiGe or SiN, and the cladding 960 may include, for example, Si3N4, SiO2, Al2O3, MgO, SiCN, SiON, SiCO, HfO2, etc.

[0088] Trenches can then be etched in a stack of alternating layers, including the cladding layer 960 and the seed layer 920 or buffer layer 922, which can serve as an etching barrier layer in the etching process. Conductive materials such as metals (e.g., Cu, W, Co, etc.) can be deposited or otherwise filled into the trenches to form the electrode 970. (See above regarding...) Figure 8 The electrode 970 can be used to apply voltage signals to the EO material layers 930, 932 and 934 through edge contact rather than surface contact, in order to avoid field interference caused by intermediate layers 940 and 942, which may have dielectric constants different from those of the EO material layers 930, 932 and 934.

[0089] Figure 10This is a simplified cross-sectional view of yet another example of a waveguide structure 1000 including an EO material layer according to certain embodiments, the EO material layer being able to maintain a tetragonal phase at cooling temperatures. The waveguide structure 1000 may include a substrate 1010, which may be similar to substrates 152, 510, or 910 described above. The waveguide structure 1000 may also include a buffer layer 1022 and a seed layer 1020 on the substrate 1010. The buffer layer 1022 may be similar to buffer layers 154, 540, 810, or 922 described above. An example of the buffer layer 1022 is a SiO2 layer. The seed layer 1020 may be similar to seed layers 156, 520, 820, or 920 described above. An example of the seed layer 1020 is an STO layer. As described above, the buffer layer 1022 can be formed by high-temperature oxidation annealing of the seed layer 1020 deposited on the substrate 1010 (e.g., a silicon wafer), wherein the substrate 1010 can be oxidized at the interface between the seed layer 1020 and the substrate 1010 to form the buffer layer 1022 between the seed layer 1020 and the substrate 1010.

[0090] The waveguide structure 1000 may include multiple EO material layers 1030, 1032, 1034, 1036, etc., and multiple intermediate layers 1040, 1042, 1044, etc. As described above, the EO material layers 1030, 1032, 1034, and 1036 may include ferroelectric crystals, such as BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), (Pb(Zr,Ti)O3 (PZT), (Pb,La)(Zr,Ti)O3 (PLZT), etc. The intermediate layers 1040, 1042, and 1044 may include, for example, MgO, BST, BaHfO3, BaZrO3, SrHfO3, SrNbO3, SrTiO3, SrZrO3, or other oxides. The EO material layers and intermediate layers may... Alternating deposition on top of the seed layer 1020 allows the EO material layers and intermediate layers to be staggered and interlocked to form an interleaved stack of layers. The EO material layers and intermediate layers can be thin layers, where the ratio between the thickness of each EO material layer and the thickness of each intermediate layer can be less than about 20:1, 10:1, 8:1, 5:1, or lower. In one example, the thickness of each EO material layer can be about 100 nm or less, and the thickness of each intermediate layer can be about 10 nm or less. The total thickness of the multiple EO material layers in the stack can be greater than a certain value, such as greater than about 300 nm.

[0091] The waveguide structure 1000 may further include a waveguide comprising a cladding 1050 and a waveguide core, the waveguide core comprising a series of interlaced layers. Figure 10In the example shown, the waveguide core may include EO material layers 1034 and 1036 and intermediate layers 1042 and 1044, which can be patterned, for example, by photolithography. In some embodiments, intermediate layers 1044 and 1042 may serve as etch stop layers for etching EO 1034 and 1036. For example, intermediate layer 1044 may serve as an etch stop layer for etching EO material layer 1036 using a first process, and then intermediate layer 1044 may be etched using a second process, and intermediate layer 1042 may serve as an etch stop layer for etching EO material layer 1034 using the first process. In this way, the waveguide core can be formed as a mesa structure including several EO material layers and intermediate layers.

[0092] As mentioned above, for example Figure 4 The frame 450 and Figure 5E As described, a cladding layer 1050 can be formed on the waveguide core. The cladding layer 1050 may include, for example, Si3N4, SiO2, Al2O3, MgO, SiCN, SiON, SiCO, SiOCN, HfO2, etc. Trenches can be etched in the cladding layer 1050 and in some layers of an interleaved stack of layers extending down from the cladding layer 1050 to the seed layer 1020 or buffer layer 1022, the buffer layer 1022 serving as an etch barrier layer for etching the trenches. A conductive material such as a metal (e.g., Cu, W, Co, etc.) can be deposited or otherwise filled into the trenches to form electrodes 1060. As described above, electrodes 1060 can be used to apply voltage signals to EO material layers 1030 and 1032 via edge contacts, and / or to EO material layers 1034 and 1036.

[0093] The waveguide structures 800, 900, and 1000 described above may each comprise a stack of staggered layers, including alternating EO material layers and intermediate layers. The EO material layers and intermediate layers may be thin and have similar lattice structures at room temperature, and thus can be interlocked after the manufacturing process. The intermediate layers may comprise materials that do not undergo phase transitions when the operating temperature changes. Therefore, the interlocking between the thin EO material layers and the intermediate layers prevents phase transitions in the EO material layers when the operating temperature changes, for example, to a cooling temperature. Thus, the EO material layers can substantially maintain their room-temperature lattice structure (e.g., tetragonal phase) and polarization (e.g., in-phase polarization) at cooling temperatures, thereby preserving the EO effect (e.g., Pockels coefficient). Waveguide structures 800, 900, and 1000 can be used for optical switches, EO modulators, or other active photonic devices operating at low temperatures using phase modulation or refractive index modulation, such as the aforementioned Mach-Zehnder interferometer 120 or optical switch 100.

[0094] In the various embodiments of the waveguide structures and EO devices disclosed herein, single-mode waveguides (e.g., waveguide cores with widths in the submicron to micron range) or multimode waveguides (having wider waveguide cores supporting two or more transverse modes) can be used. Various materials, layers, and structures can be formed to fabricate EO devices using, for example, epitaxial growth, deposition, layer transfer, etc. Even though techniques for improving the Pockels effect at cooling temperatures are described in some embodiments, the techniques disclosed herein can also be used to improve other EO effects at different temperatures. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0095] Figure 11 This is a simplified flowchart 1100 illustrating an example of a method for manufacturing engineered wafers and / or EO devices including an EO material layer according to certain embodiments, the EO material layer being characterized by a substantially constant EO coefficient from room temperature to cooling temperature. Even Figure 11 The operations are described in a sequential sequence, but some operations may also be performed in parallel or simultaneously. Some operations may be performed in a different order. Operations may have additional steps not included in the figures. Some operations may be optional and therefore may be omitted in various embodiments. Some operations may be performed together with another operation.

[0096] In block 1110, the operation may include depositing a seed layer on a substrate. The substrate may include, for example, a semiconductor substrate (e.g., a silicon wafer), a glass substrate, a quartz substrate, a ceramic substrate, etc., as described above. The seed layer may be epitaxially grown on the substrate using, for example, MBE technology, and may include, for example, SrTiO3 (STO), MgO, or LaAlO3.

[0097] In box 1120, the operation may include epitaxially depositing a first electro-optic material layer on a seed layer using, for example, an MBE technique. The seed layer may have a lattice structure similar to that of the first EO material layer and / or the substrate, and may include, for example, a ferroelectric material or a perovskite ferroelectric material (e.g., BTO, BST, PZT, PLZT, etc.). The material in the first EO material layer may have a tetragonal lattice structure at room temperature, and its lattice structure and crystalline phase may be altered at lower temperatures when used in bulk. The first EO material layer may have a thickness of less than, for example, 100 nm.

[0098] In block 1130, the operation may include annealing the substrate, seed layer, and first electro-optic material layer in an oxygen environment to form an oxide buffer layer between the substrate and the seed layer. Annealing may be performed at a temperature, for example, above the softening temperature of the oxide buffer layer, such as above 600°C (e.g., 750°C or higher). High-temperature annealing may facilitate the formation of an oxide buffer layer (e.g., SiO2) at the interface between the substrate (e.g., Si) and the seed layer (e.g., STO). When the annealing temperature is above the softening temperature of the oxide buffer layer, the oxide buffer layer can soften, thus allowing the seed layer and the first EO material layer to separate from the substrate and allowing stress release in the seed layer and the first EO material layer.

[0099] At frame 1140, the operation may include depositing a first intermediate layer on the first electro-optic material layer. The first intermediate layer may include a crystal structure similar to that of the first EO material layer and may not undergo a phase transition at low temperatures. Therefore, the first intermediate layer may include a material capable of maintaining a first lattice structure at room temperature and a cooling temperature (e.g., about 4 K). The first intermediate layer may include at least one of, for example, MgO, (Ba,Sr)TiO3, BaHfO3, BaZrO3, SrHfO3, SrNbO3, SrTiO3, SrZrO3, etc.

[0100] At block 1150, the operation may include depositing a second electro-optic material layer on the first intermediate layer. The second electro-optic material layer may be similar to the first electro-optic material layer. At block 1160, the operation may include annealing the second electro-optic material layer and the first intermediate layer in a high-temperature annealing process to relax the second EO material layer, improve material quality, and ensure in-plane polarization in the second EO material layer.

[0101] In some embodiments, additional intermediate layers and EO material layers may be deposited alternately until the total thickness of the EO material layers is greater than a desired value. In some embodiments, the additional layers comprising staggered intermediate layers and EO material layers may be annealed in a high-temperature annealing process. The first intermediate layer, the second intermediate layer, and the additional intermediate layers may have a thickness of less than, for example, about 10 nm, and may be used to separate the EO material layers from each other and to apply tensile stress to the EO material layers to confine the phase transition of the EO material layers. In some embodiments, the ratio between the thickness of each EO material layer and the thickness of each intermediate layer may be less than about 20:1, 10:1, 8:1, 5:1, or lower. Because the intermediate layers do not change their lattice structure and crystalline phase at lower temperatures (e.g., cooling temperatures), the intermediate layers can confine the EO material layers from changing their room-temperature lattice structure and crystalline phase at lower temperatures. Therefore, the EO material layers may have a high EO effect (e.g., Pockels effect) at lower temperatures. For example, the EO material layers may include BTO and may have a Pockels coefficient greater than 300 pm / V at cooling temperatures.

[0102] Optionally, at block 1170, a waveguide may be formed on the stack of staggered intermediate layers and EO material layers. The waveguide may be part of a Mach-Zehnder interferometer, resonator, optical switch, electro-optic modulator, etc. In some embodiments, the waveguide may include a waveguide core comprising a dielectric or semiconductor material, or comprising one or more electro-optic material layers. In some embodiments, the waveguide may include a waveguide cladding that is in physical contact with one of the plurality of electro-optic material layers, and the waveguide cladding may be characterized by having a different coefficient of thermal expansion than the electro-optic material layers. The waveguide cladding may include at least one of, for example, Si3N4, SiO2, Al2O3, MgO, SiCN, SiON, SiCO, SiOCN, or HfO2.

[0103] In some embodiments, forming a waveguide may include patterning one or more electro-optic material layers to form a waveguide core, and depositing a dielectric overlay on the waveguide core. Patterning one or more electro-optic material layers may include etching one or more electro-optic material layers using an intermediate layer as an etch stop layer. In some embodiments, forming a waveguide may include depositing a high-refractive-index material layer on a layer stack including an intermediate layer and an EO material layer, patterning the high-refractive-index material layer to form a waveguide core, and depositing a dielectric overlay on the waveguide core. In some embodiments, forming a waveguide may include bonding a wafer including a waveguide to a layer stack including an intermediate layer and an EO material layer. In some embodiments, the method may further include etching trenches in the layer stack including the intermediate layer and the EO material layer, and filling the trenches with a conductive material. In some embodiments, etching trenches in the layer stack may include using an oxide buffer layer as an etch stop layer.

[0104] Figure 12 This is a simplified system block diagram of an example of a hybrid quantum computing system 1200 including electro-optic devices (e.g., switches) according to certain embodiments. For operation at cryogenic temperatures (e.g., liquid helium temperatures), embodiments of the invention integrate the electro-optic switches discussed herein into a system including a cooling system. Therefore, embodiments of the invention provide a hybrid computing system, such as... Figure 12 As shown, the hybrid quantum computing (QC) system 1200 includes a user interface device 1204 communicatively coupled to the hybrid quantum computing subsystem 1206. The user interface device 1204 can be any type of user interface device, such as a terminal including a monitor, keyboard, mouse, touchscreen, etc. Furthermore, the user interface device itself can be a computer, such as a personal computer (PC), laptop computer, tablet computer, etc.

[0105] In some embodiments, the user interface device 1204 provides an interface for a user to interact with the hybrid QC subsystem 1206. For example, the user interface device 1204 may run software such as a text editor, an interactive development environment (IDE), command prompt, a graphical user interface, etc., allowing the user to program or otherwise interact with the QC subsystem to run one or more quantum algorithms. In other embodiments, the hybrid QC subsystem 1206 may be pre-programmed, and the user interface device 1204 may simply be an interface for a user to initiate quantum computing, monitor the process, and receive results from the hybrid QC subsystem 1206. The hybrid QC subsystem 1206 also includes a classical computing system 1208 coupled to one or more quantum computing chips 1210. In some examples, the classical computing system 1208 and the quantum computing chips 1210 may be coupled to other electronic components 1212, such as pulsed pump lasers, microwave oscillators, power supplies, networking hardware, etc.

[0106] In some embodiments utilizing refrigerated temperature operation, the quantum computing system 1209 may be housed within a cryostat (e.g., cryostat 1214). In some embodiments, the quantum computing chip 1210 may include one or more constituent chips, such as a hybrid electronics chip 1216 and an integrated photonics chip 1218, which may include various waveguide structures and / or EO devices disclosed herein. Signals may be routed on and off the chip in any manner, for example, via optical interconnects 1220 and other electronic interconnects 1222. Furthermore, the hybrid quantum computing system 1200 may employ quantum computing processes, such as measurement-based quantum computing (MBQC), which employs a cluster state of one or more qubits.

[0107] It will be apparent to those skilled in the art that substantial variations can be made to specific implementations. For example, custom hardware may be used, and / or specific elements may be implemented in hardware, software (including portable software such as applets), or both. Furthermore, connections to other computing devices (such as network input / output devices) may be employed.

[0108] Referring to the accompanying drawings, components that may include memory may include non-transitory machine-readable media. As used herein, the terms "machine-readable media" and "computer-readable media" refer to any storage medium that participates in providing data that enables a machine to operate in a particular manner. In the embodiments provided above, providing instructions / code to a processor and / or one or more other devices for execution may involve a variety of machine-readable media. Additionally or alternatively, machine-readable media may be used to store and / or carry such instructions / code. In many embodiments, computer-readable media are physical and / or tangible storage media. Such media can take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic and / or optical media, punched cards, paper tape, any other physical media with a perforated pattern, RAM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), flash EPROM (FLASH-EPROM), any other memory chip or magnetic tape, a carrier wave as described below, or any other medium from which a computer can read instructions and / or code.

[0109] The methods, systems, and devices discussed herein are examples. Various procedures or components may be appropriately omitted, substituted, or added in various embodiments. For example, features described with respect to certain embodiments may be combined in various other embodiments. Different aspects and elements of embodiments may be combined in a similar manner. Various components of the accompanying drawings provided herein may be implemented in hardware and / or software. Furthermore, technology evolves, and therefore many elements are examples, which do not limit the scope of this disclosure to those specific examples.

[0110] Sometimes, primarily for reasons of general use, referring to signals as bits, information, values, elements, symbols, characters, variables, terms, numbers, etc., has proven convenient. However, it should be understood that all these or similar terms are associated with appropriate physical quantities and are merely convenient notations. Unless otherwise specifically stated, as is clear from the above discussion, it should be understood that the use of terms such as “processing,” “calculating,” “accounting,” “determining,” “determining,” “identifying,” “associating,” “measuring,” “executing,” etc., throughout this specification refers to the actions or processes of a specific device such as a dedicated computer or similar dedicated electronic computing device. Therefore, in the context of this specification, a dedicated computer or similar dedicated electronic computing device is capable of manipulating or transforming signals (generally referred to as physical electronic, electrical, or magnetic quantities within the memory, registers, or other information storage devices, transmission devices, or display devices of the dedicated computer or similar dedicated electronic computing device).

[0111] Those skilled in the art will understand that information and signals used to transmit the messages described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0112] As used herein, the terms “and,” “or,” and “one / or” can include and are contemplated to have various meanings, at least in part, depending on the context in which these terms are used. Generally, “or,” when used in an associated list, such as A, B, or C, means A, B, and C, used herein in an inclusive sense, and A, B, or C, used herein in an exclusive sense. Furthermore, the term “one or more,” as used herein, can be used to describe any feature, structure, or characteristic in the singular, or to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. Additionally, the term “at least one,” when used in an associated list, such as A, B, or C, can be interpreted as meaning any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0113] Throughout this specification, references to "an example," "example," "some examples," or "exemplary implementation" refer to a particular feature, structure, or characteristic described in connection with that feature and / or example that may be included in at least one feature and / or example of the claimed subject matter. Therefore, the appearance of the phrases "in one example," "example," "some examples," "some implementations," or other similar phrases throughout this specification does not necessarily refer to the same feature, example, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined in one or more examples and / or features.

[0114] In some implementations, the operation or processing may involve the physical manipulation of physical quantities. Typically, although not essential, such quantities may take the form of electrical or magnetic signals capable of being stored, transmitted, combined, compared, or otherwise manipulated. Sometimes, primarily for common reasons, it has proven convenient to refer to signals as bits, data, values, elements, symbols, characters, terms, numbers, digits, etc. However, it should be understood that all these or similar terms are associated with appropriate physical quantities and are merely convenient notations. Unless otherwise specifically stated, as is apparent from the discussion herein, it should be understood that throughout this specification, discussions using terms such as “processing,” “calculating,” “accounting,” “determining,” etc., refer to the actions or processes of a specific device such as a dedicated computer, dedicated computing device, or similar dedicated electronic computing device. Therefore, in the context of this specification, a dedicated computer or similar dedicated electronic computing device capable of manipulating or transforming signals generally refers to physical electronic or magnetic quantities within the memory, registers, or other information storage devices, transmission devices, or display devices of the dedicated computer or similar dedicated electronic computing device.

[0115] In the foregoing detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those skilled in the art have not been described in detail to avoid obscuring the claimed subject matter. Therefore, the claimed subject matter is not limited to the specific examples disclosed, but may also include all aspects falling within the scope of the appended claims and their equivalents.

Claims

1. A method for manufacturing an electro-optical device, comprising: Deposit a seed layer on the substrate; A first electro-optic material layer is epitaxially deposited on the seed crystal layer; The substrate, the seed layer, and the first electro-optic material layer are annealed in an oxygen environment at an annealing temperature to form an oxide buffer layer between the substrate and the seed layer, wherein the annealing temperature is higher than the softening temperature of the oxide buffer layer. The substrate is cooled after annealing, thereby subjecting the first electro-optic material layer to tensile stress. A first intermediate layer is deposited on the first electro-optic material layer, wherein the first intermediate layer comprises a material that maintains a first lattice structure at room temperature and cooling temperature; Deposit a second electro-optic material layer on the first intermediate layer; and Annealing the second electro-optic material layer and the first intermediate layer; and The oxide buffer layer is configured to release stress in the seed layer and the first electro-optic material layer of the wafer. Through the above structure, the first electro-optic material layer and the second electro-optic material layer maintain a second lattice structure and crystalline phase at the room temperature and the cooling temperature.

2. The method according to claim 1, wherein, The first electro-optic material layer and the second electro-optic material layer comprise electro-optic materials, wherein the electro-optic materials are characterized in that the second lattice structure at the cooling temperature is different from the third lattice structure at the room temperature.

3. The method according to claim 2, wherein, The third lattice structure has the same crystal structure as the first lattice structure.

4. The method according to claim 1, further comprising: A second intermediate layer is deposited on the second electro-optic material layer, wherein the second intermediate layer comprises a material that maintains the first lattice structure at the room temperature and the cooling temperature; A third electro-optic material layer is deposited on the second intermediate layer; and The third electro-optic material layer and the second intermediate layer are annealed.

5. The method according to claim 4, further comprising: The third electro-optic material layer is patterned to form a waveguide core; and A dielectric coating is deposited on the waveguide core.

6. The method according to claim 5, wherein, Patterning the third electro-optic material layer includes using the second intermediate layer as an etch barrier layer to etch the third electro-optic material layer.

7. The method according to claim 4, further comprising forming a waveguide on the third electro-optic material layer.

8. The method according to claim 7, wherein, Forming the waveguide on the third electro-optic material layer includes: A waveguide core is formed on the third electro-optic material layer; and A dielectric coating is deposited on the waveguide core.

9. The method according to claim 7, wherein, Forming the waveguide on the third electro-optic material layer includes bonding a wafer including the waveguide to the third electro-optic material layer.

10. The method of claim 7, further comprising: Trenches are etched in the first electro-optic material layer, the second electro-optic material layer, the third electro-optic material layer, the first intermediate layer, and the second intermediate layer. and The trench is filled with a conductive material.

11. The method according to claim 1, wherein, The ratio between the thickness of the first electro-optic material layer and the thickness of the first intermediate layer is equal to or less than 20:

1.

12. A method for manufacturing an electro-optical device, comprising: Provide substrate; A seed layer is formed on the substrate; A first electro-optic material layer is formed on the seed crystal layer; A buffer layer is formed between the substrate and the seed layer by annealing at an annealing temperature in an oxygen environment, wherein the annealing temperature is higher than the softening temperature of the oxide buffer layer. The substrate is cooled after the buffer layer is formed; A first intermediate layer is formed on the first electro-optic material layer, wherein the first intermediate layer includes a material that maintains a first lattice structure at room temperature and cooling temperature; A second electro-optic material layer is formed on the first intermediate layer; and Annealing is performed on the second electro-optic material layer and the first intermediate layer; Wherein, cooling the substrate after annealing subjects the first electro-optic material layer to tensile stress; and The buffer layer is configured to release stress in the seed layer and the first electro-optic material layer of the wafer. Through the above structure, the first electro-optic material layer and the second electro-optic material layer maintain a second lattice structure and crystalline phase at the room temperature and the cooling temperature.

13. The method according to claim 12, wherein, The first electro-optic material layer is epitaxially deposited on the seed crystal layer.

14. The method according to claim 12, wherein, The first electro-optic material layer, the first intermediate layer, and the second electro-optic material layer are formed using a deposition process.

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