Mobile storage random read performance estimation enhancement

Abstract

A computing system (100) having a storage system including a storage device (130) and a host device (105), where the host device (105) is configured to issue memory access commands to the storage device (130). The computing system (100) further includes a prediction system (190) comprising processing circuitry configured to perform operations that cause the prediction system (190) to identify one or more components of the storage system (918) that limit random read performance of the storage system (918). The operations further cause the prediction system (190) to obtain characterization data indicative of an impact of the one or more components on random read performance, and generate a model based on the characterization data to predict random read performance of the storage system (918). The operations additionally cause the prediction system (190) to execute the model when simulating the storage system (918) to generate random read performance parameters of the storage system (918).

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to computer storage systems, and more specifically, but not in a limiting way, to random read performance estimation in systems comprising array-based storage devices. Background Technology

[0002] A computer data storage system (hereinafter referred to as a "storage system") may use one or more data storage devices to store or retrieve data generated or manipulated by a host computing system. Such storage devices may include one or more storage controllers that use a combination of firmware and hardware components to facilitate the movement of data between the host computing system and the storage medium associated with the storage device. The storage controller may serve as an interface between the host computing system and the storage medium. In an example, the storage medium includes one or more arrays of semiconductor memories. The memory arrays may include volatile or non-volatile memories. Volatile memories may include one or more semiconductor circuits that require power to maintain the stored data. In an example, volatile memories include circuitry or devices such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), etc. Non-volatile memories may include one or more semiconductor circuits configured to maintain the stored data when no power is supplied. In examples, non-volatile memory includes circuitry or devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistive variable memory such as phase-change random access memory (PCRAM), resistive random access memory (RRAM) or magnetoresistive random access memory (MRAM), and 3D-Xpoint memory, etc.

[0003] During operation, the storage system may receive memory access commands from the host computing system. These commands may be issued by an operating system or software application executing on the host computing system. A memory access command may contain instructions to read data from or write data to one or more logical addresses of the storage device. The storage device can process these instructions by translating logical addresses to physical addresses and using the translated address access memory at a specific physical location in the memory array.

[0004] Random read input operations per second (IOPs) is a useful metric for measuring the performance of a storage device or a system incorporating storage devices. Random read operations issued to an array-based storage device involve reading data from any location within the memory array. Predicting in-situ random read IOPs for array-based storage devices through modeling or simulation can be challenging. Attached Figure Description

[0005] In accompanying drawings that are not necessarily drawn to scale, similar reference numerals can describe similar components in different views. Similar reference numerals with different letter suffixes can represent different instances of similar components. The accompanying drawings are provided by way of example and are not restrictive in their generalization of the various instances discussed in this document.

[0006] Figure 1 A computing system according to an example of this disclosure is shown.

[0007] Figure 2A This disclosure describes the intended use of bare dies for configuring computing systems for different host queue depths, based on examples of this disclosure.

[0008] Figure 2B Curves depicting predicted random read performance of systems that can be compared based on simulations ignoring interface bus contention and simulations considering interface bus contention, according to examples of this disclosure.

[0009] Figure 2C The random read performance improvements caused by MPR under different queue depths and topologies are described in the examples of this disclosure.

[0010] Figure 3A The impact of logical address to physical address cache hit rate on examples according to this disclosure is described.

[0011] Figure 3B The random read single command execution is described in a computing system according to an example of this disclosure.

[0012] Figure 4A Results of system overhead benchmarks for random read performance and effective queue depth based on examples of this disclosure are presented.

[0013] Figure 4B The effective queue depth statistics are depicted based on benchmarks of random read performance and effective queue depth according to examples of this disclosure.

[0014] Figure 5 A block diagram of a prediction system according to an example of this disclosure is shown.

[0015] Figure 6 A block diagram of a prediction system according to an example of this disclosure is shown.

[0016] Figure 7 This describes a process for determining parameters or characteristics of components in a system comprising an array-based storage device, according to an example of this disclosure.

[0017] Figure 8 The present disclosure describes a process for predicting system performance based on the capabilities of an array storage device, according to examples of this disclosure.

[0018] Figure 9 Examples of computer systems having a data host system and storage devices to perform any one or more processes or techniques discussed herein are shown according to the present disclosure. Detailed Implementation

[0019] Various aspects of this disclosure relate to random read prediction or estimation in computing systems comprising array-based storage devices. Such predictions can be used to determine the performance of a computing system based on the capabilities of its array-based storage devices and one or more components. Such predictions can also be used to evaluate the impact of one or more components of the computing system on the system's random read performance.

[0020] As used herein, an array-based storage device comprises a storage device in which the storage medium includes one or more dies having an array of semiconductor memory cells (hereinafter referred to as a “storage array”). In an example, the storage array may include NAND storage medium (hereinafter referred to as a “NAND device”), such as a NAND die or an array of NAND memory cells. The number of random read operations per second (IOPs) served by a computing system configured with a particular array-based storage device is a useful metric or performance measure for characterizing the data read performance of the computing system. This metric essentially depends on the time taken to read random blocks or strings of data from the storage array. This array read time, or indirectly device-level IOPs, can be obtained through the manufacture of the storage device or storage array, for example, by examining the technical specifications associated with the storage device or storage array. Converting array read time into IOPs from the perspective of the host system (hereinafter referred to as “host IOPs”) is complex because of the fact that array-based storage devices are often used in resource-constrained environments, such as systems where multiple relevant factors (e.g., resource limitations) interact with device IOPs to determine the actual random read performance obtained at the host device.

[0021] In this example, the storage device can receive random read commands from the host computing system via a front-side communication bus, such as commands to read or retrieve a target memory block (hereinafter referred to as a "data block") from a storage array (e.g., a NAND die). The target data block is typically specified based on a host logical block address (LBA), determined, for example, by an operating system running on the host device. The storage device can translate the LBA into a physical address (PA) and use the physical address to locate the target data block within the storage array. The storage device can retrieve the target data block by actuating the storage array using the physical address (e.g., sensing) and transfer the data block to the storage device using a back-side communication bus (e.g., an open NAND flash interface communication channel).

[0022] Techniques used to estimate or predict the random read performance (RR) of array-based computing systems assume that the largest component of random read latency is the array read time and the time taken to transfer a data block from the storage device to the storage device (e.g., a buffer in the storage device controller). Random read latency includes the time difference between when the host device issues a random read command and when the host device receives the requested data block. According to these techniques, random read performance is estimated as the product of the number of storage arrays that the storage device can access simultaneously (e.g., die count) and the reciprocal of the sum of the array read time and the time taken to transfer the data block to the storage device. However, these techniques fail to account for the impact of host system and storage device resource constraints on RR performance.

[0023] Examples of this disclosure are based on the understanding that the accuracy of predicting the random read performance of a computing system can be improved by incorporating the capabilities of the storage media (e.g., the capabilities of the storage array) and elements or aspects of the computing system used to improve or limit the use of the storage media into the prediction method. Therefore, examples of this disclosure include techniques for predicting the random read performance of computing systems using array-based storage devices. Such techniques include existing prediction techniques improved by incorporating the capabilities or architecture of the storage media used by the storage device and one or more system elements used to limit or improve random read performance into the prediction. Such system elements may include characterizing data such as storage array utilization, front-end or back-end communication channel contention, parallelism characteristics of the storage array, storage device logic-to-physical address translation cache, storage device firmware overhead, and host system overhead. The impact of each of these elements on the system's random read performance can be characterized by modeling or experimentation. Data indicating such impact or effect of each of these elements can then be combined in a model, such as a linear model, to predict or determine the system's random read performance (e.g., the random read performance observed by the host device). In some aspects of this disclosure, the model can be used to predict or determine the system random read performance of a computing system based on the capabilities of adjustable component system components (e.g., NAND dies or NAND architecture).

[0024] Now turn to the diagram. Figure 1A system 100 according to an example of this disclosure is illustrated. The computing system 100 may include any computing resource configured with one or more hardware or software components to implement the techniques described herein. In the example, the computing system 100 is an endpoint device (e.g., a mobile computing device), a computing server, a storage system, or a network-based or hosted computing environment (e.g., a virtual machine, cloud storage system, cloud messaging platform, cloud-based email system, or other cloud-based computing environment). The computing system 100 may also include any computing system configured with means for generating, storing, accessing, or otherwise operating or transmitting digital data. The computing system 100 may be a standalone computing system, such as a server, or a distributed computing system. In the example, the computing system 100 includes a host device 105, a storage device 130, and a prediction system 190. In the example, one or more components of the computing system 100 are configured to model the operation of the physical components of the system or to simulate the operation of said operation.

[0025] Host device 105 may include any computing resources associated with computing system 100 and configured to interface with storage device 130 to handle data access operations (e.g., random read operations). Host device 105 may include a host processor, central processing unit, or one or more other computing devices, processors, controllers, or control circuitry systems. Host device 105 may also include a host interface (I / F) 120, such as a bidirectional parallel or serial communication interface, for communicating with storage device 130. Examples of device interface 120 may include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), eMMC™ interfaces, etc. In this example, host device 105 includes application program 110, operating system 115, and front-end interface 120. Application program 110 includes any software application configured with instructions that can be executed by host device 105 to issue data access requests to operating system 115 to write data to or retrieve data from storage device 130. Data access requests can be transmitted through one or more layers or abstractions, such as software drivers, software packages, or applications, and then received at operating system 115. Operating system 115 is configured to transmit data access requests to storage device 130 using device interface 120. In some instances, operating system 115 may delay the transmission of one or more data access requests due to front-side bus contention or communication latency associated with device interface 120 or storage device 130. In some instances, operating system 115 stores the delayed data access requests in one or more host queues and dispatches the requests from such queues to storage device 130 when access to the storage device becomes available.

[0026] In this example, host device 105 is configured to use logical block addressing technology to access data blocks stored by storage device 130. Therefore, data access requests transmitted by operating system 115 from host device 105 via device interface 120 may include the logical addresses of data blocks to be written to or read from storage device 130.

[0027] Storage device 130 may include any array-based storage device configured with one or more circuits or software applications to process data access requests received from host device 105. Storage device 130 may be configured as or may include a general-purpose flash memory (UFS) device, embedded MMC (eMMC) device, etc. TM The storage device 130 may be a UFS device or one or more other memory devices. For example, if storage device 130 includes a UFS device, the communication interface for coupling host device 105 to the storage device may include a serial bidirectional interface, as defined in one or more Joint Electron Device Engineering Council (JEDEC) standards (e.g., JEDEC Standard D223D (JESD223D), commonly referred to as JEDEC UFS Host Controller Interface (UFSHCI) 3.0, etc.). In another instance, if storage device 130 includes an eMMC device, the communication interface for coupling host device 105 to the storage device (e.g., device interface 120 or front-side communication bus) may include multiple parallel bidirectional data lines (e.g., DAT[7:0]) and one or more command lines, as defined in one or more JEDEC standards (e.g., JEDEC Standard D84-B51 (JESD84-A51), commonly referred to as JEDEC eMMC Standard 5.1, etc.). In other instances, storage device 130 may include one or more other memory devices, or a communication interface for coupling host device 105 to storage device.

[0028] In this example, storage device 130 includes a storage controller 135 and one or more data storage arrays 180 and 185. Storage controller 135 may include a processor 140 or other control circuitry (which may be software or hardware; in this example, it is described as firmware 145) configured to execute instructions to process data access requests received from host device 105. In this example, storage controller 135 is a microcontroller, a special-purpose logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor. Storage controller 135 may also include firmware 145, device interface 150, device queue 155, memory 160, array interface 175, and other hardware circuitry, such as one or more integrated circuits and / or discrete components. Firmware 145 may contain computer code or instructions executable by storage controller 135 or processor 140 to perform operations of passing data to or receiving data from storage arrays 180 or 185. In this example, firmware 145 is encoded in one or more hardware circuitry associated with storage controller 135. Firmware 145 may include firmware routines for translating logical block addresses to physical block addresses, and other things. Host interface 150 includes any data communication interface configured to interface with host device 105 via storage interface 120. Device queue 155 includes one or more hardware or software queues configured to temporarily store translated storage array commands (e.g., commands to read data from or write data to physical addresses in storage arrays 180 or 185) to be dispatched to storage arrays 180 or 185 via array interface 175. In this example, device queue 155 includes a portion of memory 160.

[0029] Memory 160 may contain an array of memory cells whose data write cost is lower than that of writing data to memory arrays 180 or 185. In one example, memory 160 contains an array of static memory, such as an array of static random access memory 165 (SRAM). At least a portion of the SRAM may be used as a cache for storing logical address to physical address (L2P) translations. In another example, memory 160 contains an array of dynamic random access memory 165 (DRAM) or persistent memory, such as randomly addressable memory that is retained through power cycling. Memory 160 typically contains volatile memory, but some non-volatile memory technologies may be used for write caching, provided that such technologies make the data write cost lower than that of writing data to memory arrays 180 or 185 (e.g., faster write speeds).

[0030] Storage arrays 180 or 185 can be configured to provide non-volatile storage for data received from host device 105. Such non-volatile storage can be provided by one or more types of non-volatile memory devices, such as NAND flash memory devices or NOR flash memory devices. Such non-volatile memory devices can comprise one or more arrays of memory cells, such as single-level cell (SLC) or multi-level cell (MLC) (e.g., three-level cell (TLC) or four-level cell (QLC)). In some traditional industry uses, the term MLC has been used to identify a memory cell that can store two data bits per cell (e.g., one of four programming states); however, it is also widely used to refer to a memory cell that can store more than one data bit per cell (i.e., can represent more than two programming states). Unless otherwise clearly indicated by explicit language or context, MLC is used herein in a broad sense and includes, for example, TLC and QLC memory cells. Each memory cell can be configured to store data bits (e.g., data blocks) received from host device 105. In one example, storage array 180 or 185 may include random access memory (RAM), such as RAM with a backup battery. In other examples, storage array 180 or 185 may include read-only memory (ROM), phase-change memory (PCM), magnetic random access memory (MRAM), and electrically erasable programmable read-only memory (EEPROM).

[0031] In an example, memory arrays 180 or 185 may include one or more non-volatile memory devices (e.g., one or more NAND dies) configured with one or more parallelism features, such as support for multi-plane read (MPR) or independent word line read (iWL). A non-volatile memory device configured to support MPR can simultaneously process two or more independent commands to read two or more different planes of the MLC memory array in parallel, provided that the commands are issued simultaneously, completed simultaneously, and are of the same type (e.g., each command is a command to read SLC or MLC memory). A non-volatile memory device configured to support iWL can simultaneously process two or more independent commands to read two or more planes of the MLC array in parallel without MPR limitations.

[0032] Prediction system 190 includes one or more hardware circuits or software applications configured to provide performance prediction capabilities (e.g., for predicting the random read performance of computing system 100). In one instance, predicting the random read performance of computing system 100 includes predicting or determining the rate at which random reads can be issued by host device 105 and served by storage device 130. In other words, determining the random read performance of computing system 100 includes predicting or determining the random read IOPS seen by host device 105. In one instance, prediction system 190 is part of computing system 100. In another instance, prediction system 190 is a standalone component or system. Prediction system 190 may be coupled to, or may have, components that interface with host device 105, storage device 140, or one or more of their sub-components to monitor and capture performance data. Prediction system 190 may include one or more logical or analytical models of one or more components of computing system 100 and may interface these models with hardware, software, or simulation components of computing system 100 to obtain simulated performance data. In this example, the performance data includes data indicating the impact of the components of computing system 100 on the system's random read performance. In this example, the performance data includes data indicating the configuration of the components of the computing system or one or more data processing characteristics. In this example, prediction system 190 uses the performance data to generate and manipulate a random read performance model for determining the random read performance of computing system 100.

[0033] In this example, prediction system 190 predicts the random read performance of computing system 100 based on performance data obtained from one or more components of computing system 100 and the predicted, modeled, or simulated performance of non-volatile storage devices (e.g., storage arrays 180 or 185). Prediction system 190 may predict the random read performance of computing system 100 based on any metric or performance measurement of the components of computing system 100 that can be used to identify factors affecting or altering the random read performance at host device 105. Prediction system 190 may also predict the random read performance of computing system 100 based on any metric or performance measurement that can be used to characterize the impact of these components on the random read performance observed at host device 105. In this example, prediction system 190 predicts the random read performance of computing system 100 based on read queue depth of host device 105, front-end or back-end communication bus contention and latency, parallelism characteristics of storage arrays 180 or 185, storage device L2P translation cache hit rate, storage device firmware overhead, and / or host overhead.

[0034] An overly optimistic estimate or prediction of the random read performance of computing system 100 can be obtained from equation (1), where the random read performance RR performance Based on the number of parallel-accessible memory arrays 180 or 185 (D count), the time taken to read a data block from a storage array (t) R_snap ) and the time (t) taken to transfer the data block to host 105 Xfer Equation (1) assumes that each storage array has 100% utilization, for example by ensuring that random read commands can always be issued to each storage array. Because such conditions do not always exist, real-world performance may not typically achieve such a deterministic random read performance.

[0035]

[0036] I. Host queue depth

[0037] The host queue depth (QD) corresponds to the number of unprocessed commands maintained by the host device 105 during the operation of computing system 100 (e.g., while executing application 110 or a task associated with operating system 115). In an example, host queue depth 8 (QD8) indicates that host device 105 initially issues 8 read commands, and when the first command completes, it is replaced by another command to ensure that the host queue remains carrying 8 unprocessed commands. The host queue depth can be obtained from the hardware or software specifications of host device 105 or from other documentation associated with system 100. Based on the architecture of storage device 130, or based on the communication or interfacing protocol used to interface host device 105 with storage device 130, the host queue depth may be limited to a specified maximum queue depth. In an example, systems implementing UFS and eMMC interfaces are limited to a maximum QD32 (e.g., QD32). Limitations on the host queue depth restrict the number of commands that can be issued to the storage die, thereby constraining storage array utilization (e.g., die utilization). The prediction system 190 can determine the expected storage array utilization of the computing system 100 by simulating for a given host queue depth, and can incorporate such utilization into a prediction model used to predict the random read performance of the computing system 100.

[0038] Figure 2A The diagram illustrates the expected die utilization for a computing system 100 in which the host device 105 is configured with QD1-QD32 and the storage device 130 is configured with 2, 4, or 8 memory arrays. For example... Figure 2A As shown, storage array utilization can vary with storage array count and host queue depth. The lowest utilization was observed at a high storage array count and low host queue depth angle, while the highest utilization was observed at a low storage array count and high queue depth angle.

[0039] Host queue depth is a resource constraint that can limit the random read performance of computing system 100, for example, by limiting storage array utilization. Prediction system 190 can use host queue depth or simulated storage array utilization to improve the prediction of the random read performance of computing system 100 by incorporating these parameters into the prediction model. In this example, the prediction model is a linear model, and prediction system 190 simulates data based on host queue depth and the corresponding storage array utilization (e.g., in...). Figure 2A The model uses simulation data provided in the database to derive the coefficients of one or more terms of a linear model. In another instance, the predictive model includes simulation components configured to simulate the impact of host queue depth on storage array utilization, random read performance, or the performance of one or more components of computing system 100.

[0040] II. Bus contention and latency

[0041] The computing system 100 includes a front-end communication bus that couples the device interface 120 to the host interface 150. The computing system 100 further includes a memory array interface bus (e.g., a back-end communication bus) that couples the memory controller 130 to the memory array 180 or 185. Each communication bus has an associated data rate that determines its communication latency, such as the time required to serially transmit or receive commands and associated data through the communication channel formed by the bus. Communication latency can lead to bus contention, for example, when two or more components of the computing system 100 compete for access to the communication bus. Bus contention can limit the random read performance of the computing system 100. Figure 2B Curves are plotted to compare the predicted random read performance of systems based on simulations that ignore bus contention and those that take bus contention into account. In a representative example, the simulation uses a channel with 800 Mbps transfers and a UFS G3x2L host interface. For each pair of lines, the upper line ignores bus contention, while the lower line considers contention. Figure 2B As shown, simulations that ignore bus contention tend to overestimate random read performance, and the overestimation increases with the random read performance of the computing system.

[0042] Interface bus contention is a limiting characteristic of computing system 100 that can limit or reduce the system's random access performance. In one instance, prediction system 190 incorporates bus contention, derived through simulation, modeling, or experimentation, into a prediction model to improve the prediction of the random access performance of computing system 100. In another instance, the prediction model is a linear model, and prediction system 190 derives the coefficients of one or more terms of the linear model based on interface bus contention, communication latency, or other associated parameters of the front-end or back-end communication bus (e.g., communication bus bandwidth). In yet another instance, prediction system 190 or the prediction model includes simulation components configured to simulate the impact of bus contention on random access performance or one or more other characteristics or components of computing system 100.

[0043] III. Parallelism Characteristics of Memory Arrays

[0044] Storage arrays 180 or 185 can be configured with parallelism features, such as MPR and iWL, to increase the number of concurrent read commands in the storage array to more than one. In the case of MPR, the impact of three characteristics of this parallelism feature on random read performance can be considered.

[0045] Depending on the target storage array plane from which data will be read, the hardware or firmware satisfies the requirement of issuing commands simultaneously by using a back-end queue (e.g., device queue 155) of storage read commands via L2P conversion. Commands targeting different planes of the same storage array can be combined into a single MPR command and issued to the storage array. The probability of finding a pair of matching commands (e.g., commands not targeting the same plane) depends on the number of storage arrays in a given storage device and the number of commands in the back-end queue. The number of commands in the back-end queue depends on the host queue depth. Figure 2C The diagram illustrates simulated data indicating that the MPR provides an improvement in random read performance. Given the requirement for simultaneous command issuance, this improvement is maximized when the per-memory array command ratio is at its maximum (e.g., when computed with a low memory array count and a large host queue depth). In this example, prediction system 190 uses any suitable technique and incorporates the impact of commands per die with an increasing number of actions into the prediction model using one or more model terms or parameters derived through simulation, modeling, or experimentation.

[0046] The requirement for simultaneous command completion introduces a read penalty, which is the time (t) required to read a data block from the storage array. R_snap The increased latency is in the form of [the increased latency]. This increased latency can be determined through simulation, for example, by simulating the operation of storage devices implementing MPR and those not implementing MPR and determining the time interval between these simulations. R_snap The difference is used to determine this. In the example, Figure 2C The data depicted can be used to determine the average impact of this loss for each MPR command by dividing the simulated, experimentally derived delay loss by the number of MPR operations.

[0047] The requirement that commands must be of the same type (e.g., SLC / MLC) improves the random read performance of MPR-enabled storage devices. This performance improvement is achieved, at least in part, by reducing the number of L2P translations that need to be cached by the storage controller 135, thereby increasing the L2P cache hit rate for random reads. In this example, the prediction system 190 incorporates the impact of this requirement on the L2P cache hit rate into the prediction model using one or more simulation, model, or experimentally derived model terms or parameters, as described herein.

[0048] Prediction 190 can be achieved by incorporating iWL parallelism features associated with benefits or penalties into the predictive model used to predict random read performance using one or more of the techniques discussed previously.

[0049] IV. Storage device L2P cache hit rate

[0050] L2P translations are typically stored in an L2P translation table. The size of the L2P translation table depends on the range of addresses accessible by the host device 105 or the storage device 130, or their address space. This, in turn, depends on the size and topology of the storage arrays 180 or 185. In an ideal configuration, the entire L2P translation table is stored in the internal SRAM of the storage controller, such as storage controller 135. This reduces latency by ensuring that address translations are available quickly without having to access secondary memory. However, real storage devices, such as storage device 130, are configured with storage controllers that have limited resources and therefore generally do not have enough SRAM to store the entire L2P translation table. In such devices, a portion of the L2P translation table is stored in the SRAML2P cache within the storage controller, while other portions of the translation table are stored in slower secondary memory, such as DRAM or reserved portions of the storage array (e.g., on a NAND die). The L2P cache hit rate corresponds to the rate at which logical-to-physical address translations are found in the storage controller's L2P cache for translating logical addresses in random read requests. Random read requests in the L2P cache that contain logical addresses without translation incur latency penalties, corresponding to the time required to retrieve the address translation from secondary storage. In this example, the latency penalty is the time required to read data blocks from storage arrays 180 or 185.

[0051] Traditional techniques for estimating random read performance, such as those using equation (1), do not adequately account for the impact of L2P cache hit rates. The latency loss caused by L2P cache misses can significantly reduce random read performance. Figure 3A This illustrates the impact of L2P cache hit rate, or latency loss due to L2P cache misses, on the random read performance of various storage device architectures in simulated systems. In one example, prediction system 190 incorporates the impact of L2P cache hit rate, derived through simulation, modeling, or experimentation, into its prediction model to improve the prediction of random read performance of computing system 100. In another example, prediction system 190 derives the coefficients of one or more terms of a linear prediction model based on simulated or experimentally derived L2P cache hit rate data, for example… Figure 3AAs shown in the diagram. In another instance, the prediction system 190 includes a simulation component configured to simulate the impact of L2P cache hit rate on the random read performance or one or more characteristics or components of the computing system 100. For example, the simulation component can be incorporated into the logical prediction model using any suitable model construction technique.

[0052] V. Storage device firmware overhead

[0053] Random read commands received by storage device 130 are processed by firmware 145. Figure 3B The flowchart illustrates the random read execution process. For example... Figure 3B As shown, executing a random read command includes allocating memory for temporary storage of the requested data, performing address translation, issuing the read request to the memory array die, retrieving the requested data from the memory array die, and delivering the retrieved data to the host device. Storage device firmware overhead (hereinafter referred to as "firmware overhead") can reduce or limit random read performance, for example, by increasing the latency associated with the execution of random read commands. However, such firmware overhead can vary based on the storage device architecture. In this example, firmware overhead is affected by the size of the storage controller's L2P cache or the L2P cache hit rate. In this example, during address translation, the measured or simulated firmware overhead for each random read command of the computing system is 13.2 seconds with an L2P cache hit and 20.4 seconds with a cache miss. In this example, firmware overhead determines the upper limit of the computing system's random read performance. Continuing with the previous example, this performance cap includes (1 / 13.2us) = 75.7K IOPs for cache hit performance limits or (1 / 20.4us) = 49.0K IOPs for cache miss performance limits. Firmware overhead is also affected by the use of hardware acceleration in the storage controller. This hardware acceleration can be achieved by... Figure 3B The execution of one or more operations shown is parallelized to reduce latency.

[0054] In one instance, prediction system 190 incorporates the impact of firmware overhead, derived through simulation, modeling, or experimentation, into a prediction model to improve the prediction of random read performance of computing system 100. In another instance, prediction system 190 derives the coefficients of one or more terms of a linear performance model or limits their values ​​based on a performance cap or latency penalty specified by the firmware overhead. In yet another instance, prediction system 190 includes a simulation component configured to simulate the impact of firmware overhead (e.g., a performance cap specified by the firmware overhead) on random read performance or one or more other characteristics or components of computing system 100. For example, the simulation component can be incorporated into a logical prediction model using any suitable modeling technique.

[0055] VI. Hosting overhead

[0056] Host overhead includes overhead attributable to one or more host components of system 100, such as the operating system and associated inefficiencies, the number of threads that can be executed concurrently by processes, storage block size, and other installation options. Host overhead is system-dependent and can affect random read performance by its impact on the performance or utilization of one or more systems of the storage device components described herein. In an example, host overhead can reduce a specified host queue depth to a smaller effective or implemented queue depth, for example, due to inefficiencies in the host device limiting the full utilization of the host queue. Figure 4A The results show benchmarks of random read performance and system overhead for effective queue depth for a simulated system with QD8, 4KB block size, and 8 threads running simultaneously. Figure 4B Describe the effective queue depth statistics obtained from the baseline. For example... Figure 4B As shown, a host queue depth of 8 can result in an average device-level queue depth (e.g., effective queue depth) as low as 5, which significantly reduces performance below the capacity of the storage device.

[0057] In one example, prediction system 190 incorporates the impact of host overhead, derived through simulation, modeling, or experimentation, into a prediction model to improve the prediction of random read performance of computing system 100. In another example, prediction system 190 derives coefficients for one or more terms of a linear performance model based on the difference between the host queue depth and the effective queue depth specified by the host overhead. In yet another example, prediction system 190 includes a simulation component configured to determine the impact of host overhead (e.g., the difference between the host queue depth and the effective queue depth) on random read performance or one or more other characteristics or components of computing system 100. For example, the simulation component can be incorporated into a logical prediction model using any suitable modeling technique.

[0058] Figure 5 A block diagram of a prediction system 500 according to an example of this disclosure is shown. The prediction system 500 may be... Figure 1 An example of a prediction system 190 is shown. In this example, prediction system 500 can be used to determine the values ​​of one or more adjustable parameters or adjustable capabilities of components of computing system 100 so that the system achieves a target random read performance 535. In this example, prediction system 500 includes system component 505, prediction model 530, evaluation component 540, feedback component 545, and selection component 550.

[0059] In one instance, system component 505 includes system components representing, as models, simulations, experimental data, or any other information suitable for characterizing the performance of one or more components of computing system 100 or their impact on random access performance. In another instance, system component 505 includes an analytical or simulation model configured to receive parameters indicative of the configuration of components of computing system 100 and to provide output data indicative of the impact of components on random access performance. In yet another instance, system component 505 includes a database of simulated or experimentally obtained data indicative of the impact of components on random access performance. Such a database can be queried or indexed using parameters or variable parameters indicative of component configuration. In another instance, parameters may be provided by prediction system 500, user or feedback component 545, or computing system 100.

[0060] In this example, system component 505 includes storage array component 510, channel component 515, controller component 520, and host component 525. Storage array component 510 is configured to model, simulate, or characterize storage array characteristics that affect random read performance. Such storage array characteristics may include storage array read time (e.g., t0). R_snap ), data transfer rate (e.g., t) Xfer The controller component 520 is configured to model, simulate, or characterize the impact of the front-end or back-end communication bus on random read performance. In this example, the channel component 515 considers parameters such as the communication bus data transfer rate, the number of communication channels, and latency (e.g., latency caused by bus contention). The controller component 520 is configured to model, simulate, or characterize controller characteristics that affect random read performance. Such controller characteristics may include the size of the L2P cache, L2P cache hit rate, or firmware overhead, as described herein. The host component 525 is configured to model, simulate, or characterize host capabilities or characteristics that affect random read performance. Such host capabilities or characteristics may include the host operating system and associated inefficiencies, the number of threads that a process can execute concurrently, block size, and other installation options, as described herein.

[0061] In this example, prediction model 530 includes a model that can be used to predict the random read performance of computing system 100. In this example, prediction model 530 is an analytical model composed of outputs received from system component 505. In this example, the analytical model is a linear model that combines one or more outputs of system component 505 using regression techniques. In this example, prediction model 530 is a logical model incorporating one or more constraints or relationships derived from the outputs of system component 505. In this example, prediction model 530 includes equation (1) or a mathematical or logical variation of equation (1). Prediction model 530 can be executed or simulated to predict the random read performance of computing system 100.

[0062] Evaluation component 540 may include one or more circuits of a software application configured to compare random read predictions provided by prediction model 530 with random read performance target 535. The error or difference between the random read predictions provided by prediction model 530 and random read performance target 535 may be provided to feedback component 550 so that the feedback component adjusts system component 505 or the prediction model to reduce the error. In an example, adjusting system component 505 includes adjusting or changing one or more parameters used to determine the configuration of the components of system component 505. In an example, the storage array size or parallelism characteristics may be adjusted, for example, by selecting from one or more available characteristics, to change prediction model 530 or provide data characterizing the operation of the storage array. In an example, adjusting prediction model 530 includes adjusting one or more terms, weights, or coefficients of the model to enhance, reduce, eliminate, or include the impact of one or more components of system component 505 on random read performance. In an example, one or more parameters that can be adjusted may be provided to system component 505, prediction model 530, or feedback component 545.

[0063] If the random read prediction provided by prediction model 530 is consistent with random read performance target 535 within a specified threshold, then the output of evaluation component 540 is provided to selection component 550 to provide the parameters of the currently selected system component 505 as selection parameter 555. In this example, selection parameter 555 is used to identify the system's configuration or characteristics, or one or more components, for achieving the random read performance target.

[0064] The selected parameter 555 can be analyzed to determine improvements to system 100 to achieve random read performance target 535. In an example, the selected parameter 555 indicates that random read performance target 535 can be achieved by improving the initial configuration (e.g., basic or default configuration) of system 100 by implementing the storage array assembly 510 with a NAND device that includes one or more parallelism features, such as MPR or iWL. Further analysis of the selected parameter 555 may indicate that the random read performance of system 100 is particularly sensitive to, or related to, random read latency, such as latency induced by the dispatch of delayed read instructions to storage array assembly 510 (e.g., delayed read instructions to satisfy MPR requirements). In view of this additional understanding, system 100 is improved to achieve the random read performance target by implementing storage array assembly 510 with a NAND device that supports iWL instead of MPR.

[0065] The selected parameter 555 can be analyzed to determine which specific component of system component 505 is a performance bottleneck, and improvements to this component should be included in any improvements to computing system 100 to achieve the random read performance target improvement. In an example, the planned improvement to computing system 100 includes an upgrade implementation of storage array component 510 to a NAND device with one or more parallelism features. However, the selected performance parameter 555, derived from a simulated configuration of a system including the upgraded storage array component 510, indicates that the latency attributable to the L2P paging operation of controller component 520 is a random read performance bottleneck limiting the achievable performance of the improved computing system 100. For example, the selected performance parameter 555 indicates that the random read performance target can only be achieved by improving computing system 100 by increasing the L2P cache size of storage controller component 510 to the indicated cache size. Based on this understanding, computing system 100 is implemented as an upgrade implementation including storage array component 510 and an upgraded storage controller including an L2P cache at least as large as the indicated cache size.

[0066] Figure 6 A block diagram of a prediction system 600 according to an example of this disclosure is shown. The prediction system 600 may be... Figure 1The example shown is of prediction system 190. Prediction system 600 is also an example of prediction system 500, but modified as described herein. In this example, prediction system 600 is used to determine or characterize the random read performance of computing system 100. In another example, prediction system 600 determines the configuration of one or more components of computing system 100 configured with specified storage array components to achieve the indicated random read performance. Prediction system 600 includes system component 605, storage array 610, prediction model 630, and feedback component 635. System component 605 is an example of system component 505. In this example, system component 605 includes channel component 615, controller component 620, and host component 625, all of which are similar to the corresponding components of system component 500. In this example, storage array 610 is a model of the storage array whose performance will be evaluated using prediction system 600.

[0067] Predictive model 630 contains a model that can be used to predict the random read performance of computing system 100. In one instance, predictive model 630 is an analytical model consisting of storage array 610 and outputs received from system component 605. In another instance, the analytical model is a linear model that combines the model of storage array 610 with one or more outputs of system component 605 using regression techniques. In yet another instance, predictive model 630 is a logical model incorporating one or more constraints or relationships derived from the model of storage array and the outputs of system component 605.

[0068] In operation, prediction model 630 predicts the random read performance 640 of computing system 100 based on system component 605 and storage array 610. In one example, feedback component 635 is configured to adjust system component 605 or the prediction model to iteratively generate a series of possible random read performances indicative of a range of random read performances achievable by computing system 100 based on specified storage array capabilities and one or more adjustable system components. In another example, feedback component 635 iteratively adjusts parameters of one or more component parts of system component 605 to determine, based on the predicted random read performance, components that have a threshold-limiting impact (e.g., limiting the maximum impact or a specified degree of impact) on the random read performance of computing system 100. In one example, the selected parameters of system component 645 may be provided after each iteration of the random read prediction.

[0069] Analysis using predicted random read performance 640 and selected parameters 645 determines the configuration of components in system component 605 that have a threshold-limiting impact (e.g., limiting the maximum impact or a specified degree of impact) on the random read performance of computing system 100. This understanding can be used to determine or select configurations of one or more of system components 605 to construct an implementation of system 100 that optimizes the random read performance of the indicated configuration of storage array component 610. In an example, for the indicated configuration of storage array 610, predicted random read performance 640 and selected parameters 645 indicate that the indicated predicted random read performance (e.g., a significant improvement in random read performance) can be achieved by increasing storage array utilization, for example, by increasing the host queue depth of host 625 to, for example, the indicated host queue depth indicated by selected parameter 645. Based on this understanding, system 100 is implemented to include the indicated storage array 610, and host component 625 is configured with a host queue that is at least as deep or as large as the indicated host queue depth. In one example, this includes configuring host component 625 with a storage array driver or a storage interface component, such as storage interface 120, that implements or supports the indicated host queue depth. In another example, this includes configuring system 100 with a front-side communication bus (including storage interface 120 and device interface 150 and associated communication protocols) that implements or supports the indicated host queue depth.

[0070] Figure 7This disclosure describes a process 700 for determining parameters or characteristics of components in a computing system (e.g., computing system 100) comprising an array-based storage device, according to an example of this disclosure. In this example, process 700 includes steps for implementing techniques for a prediction system 500. At 705, characterization data for one or more components of the computing system 100 is obtained. Such characterization data includes any data suitable for characterizing the effect of the components of the computing system on random read performance or limiting said effect, as described herein. In this example, the characterization data includes models of system components or simulated or experimentally derived data indicating the effect or change of the components of the computing system on random read performance, as described herein. The characterization data can be obtained experimentally (e.g., by instrumentation and operation of software applications and hardware circuitry) or by simulating the operation of the computing system based on the indicated configuration of the one or more system components. The configuration of the one or more system components can be determined or selected using system parameters obtained from the prediction system, an operator, or one or more other sources. In this example, such parameters are used to determine or select the configuration of components of computing system 100, such as the configuration of storage array component 510, channel component 515, controller component 520, or host component 525. At 710, a predictive model, such as predictive model 530, is generated based on the configuration and characterization data of the one or more system components, as described herein. At 715, the predictive model is evaluated (e.g., simulated or executed) to predict the random read performance of computing system 100 (e.g., generating random read performance figures). At 720, the predicted random read performance is compared with a target random read performance. At 725, when the predicted random read performance matches the target random read performance within a specified threshold, the current configuration of the one or more system components is provided. At 730, when the predicted random read performance does not match the target random read performance within a specified threshold, the configuration of at least one of the one or more system components is adjusted.

[0071] Process 700 may include any other steps or operations for implementing the techniques described herein. In an example, the system component configuration provided at 725 is analyzed to identify the configuration of one or more components of computing system 100 used to implement the computing system to achieve random read performance target 535. In an example, the system component configuration includes information indicating host queue depth, front-end or back-end communication bus latency, storage controller cache size, storage array read time, or storage array parallelism characteristics that can be used to implement system 100 to achieve the target random read performance. Understanding derived from this information selects at least one of the following for the implementation of system 100: host queue depth, front-end or back-end communication bus configuration (e.g., bus data width or data rate), storage controller cache size, or storage array configuration (e.g., size, read time, parallelism characteristics, or another characteristic of the NAND device). Understanding derived from this information selects the configuration of any other components of system 100 to achieve the target random read performance.

[0072] Although the operations of process 700 are shown to occur in a specific order, in other instances, one or more of the operations may be performed in parallel or in a different order. Furthermore, one or more operations may be repeated two or more times.

[0073] Figure 8 A process 800 for predicting the performance of a system (e.g., computing system 100) based on the capabilities of an array of storage devices, according to an example of this disclosure, is illustrated. In one example, process 800 includes operations for implementing techniques for the prediction system 600. In another example, process 800 is used to identify one or more components of computing system 100 that limit the random read performance of computing system 100 for a specified storage array configuration or architecture. In yet another example, process 800 is used to determine the random read performance of computing system 100 given a specified storage array configuration or architecture. At 805, characterization data of one or more components of computing system 100 is obtained, as described herein. At 810, a storage array or a model of the storage array is obtained. At 815, a prediction model, such as prediction model 630, is generated by the prediction system based on the storage array and the characterization data, as described herein. At 820, the prediction model is evaluated (e.g., simulated or executed) to predict the random read performance of the system. At 830, the predicted random read performance of the system is provided to an operator or another computing system for evaluation or other purposes.

[0074] In this example, process 800 includes steps 825 and 835. In this example, steps 815, 820, 825, and 830 are repeatedly performed to adjust the configuration or characteristics of one or more system components, for example, as shown at step 835, to generate a set of one or more random read performance predictions, and to analyze said set of predictions, for example, as shown at 825, to identify components of the computing system that have a threshold impact on the predicted random read performance. The identified components or the configuration of the identified components can be used to improve the random read performance of the computing system 100, for example, by replacing the identified components with another component that has more capabilities.

[0075] Process 800 may include any other steps or operations for implementing the techniques described herein. In an example, at 830, a set of selected component parameters, such as selected parameter 645, and a random read performance prediction are provided. The set of selected component parameters and the random read performance prediction are analyzed to identify or determine the configuration of components in system 100 that have a threshold-limiting effect (e.g., limiting the maximum effect or a specified degree of effect) on the random read performance of computing system 100. An embodiment of system 100 can then be constructed using the identified components, as described herein.

[0076] Although the operations of process 800 are shown to occur in a specific order, in other instances, one or more of the operations may be performed in parallel or in a different order. Furthermore, one or more operations may be repeated two or more times.

[0077] Figure 9 This illustration shows an example of a computer system 900 having a data host system and storage devices to perform any one or more processes or techniques discussed herein, according to an example of this disclosure. The computer system 900 may be a computing system 100 (… Figure 1 ) or an instance of host device 105, while storage device 918 may be storage device 130 ( Figure 1 Examples of ).

[0078] In alternative embodiments, machine 900 may be used as a standalone device or may be connected (e.g., via a network) to other machines. In a network-connected deployment, machine 900 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, machine 900 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 900 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network device, IoT device, automotive system, or any machine capable of executing instructions (sequentially or otherwise) specifying the actions to be taken by the machine. Furthermore, although only a single machine is shown, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any of the methods discussed herein, such as cloud computing, Software as a Service (SaaS), or other computer cluster configurations.

[0079] The examples described herein may include logic, components, devices, packages, or mechanisms, or may be operable through logic, components, devices, packages, or mechanisms. A circuit system is a collection (e.g., set) of circuits implemented in a tangible entity containing hardware (e.g., simple circuits, gates, logic, etc.). Circuit system members can be flexible over time and as the underlying hardware changes. A circuit system contains components that, when operated, can perform specific tasks individually or in combination. In some examples, the hardware of a circuit system can be designed immutably to perform specific operations (e.g., hardwired). In some examples, the hardware of a circuit system may contain physically connected components (e.g., execution units, transistors, simple circuits, etc.) and computer-readable media that are physically modified (e.g., magnetically, electrically, with movable placement of constantly aggregated particles, etc.) to encode instructions for specific operations. When connecting physical components, the underlying electrical characteristics of the hardware may be changed, for example, from an insulator to a conductor, or vice versa. Instructions enable participating hardware (e.g., execution units or loading mechanisms) to create portions of the circuit system components in the hardware via variable connections to perform specific tasks when in operation. Therefore, when the device is operational, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any one of the physical components can be used in more than one part of more than one circuit system. For instance, in operation, an execution unit can be used at one point in time in a first circuit of a first circuit system and reused by a second circuit of the first circuit system, or reused at different times by a third circuit of the second circuit system.

[0080] The machine (e.g., computer system, host system, etc.) 900 may include processing device 902 (e.g., hardware processor, central processing unit (CPU), graphics processing unit (GPU), hardware processor core or any combination thereof, etc.), main memory 904 (e.g., read-only memory (ROM), dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 906 (e.g., static random access memory (SRAM), etc.) and storage system 918, some or all of which may communicate with each other via a communication interface (e.g., bus) 930.

[0081] Processing device 902 may represent one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing combinations of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 902 may be configured to execute instructions 926 to perform the operations and steps discussed herein. Computer system 900 may further include a network interface device 908 for communication via network 920.

[0082] Storage system 918 may include machine-readable storage media (also referred to as computer-readable media) on which one or more sets of instructions 926 or software embodying any one or more of the methods or functions described herein are stored. Storage system 918 may also include prediction system 928, which may be configured according to the techniques and methods of this disclosure, for example, to perform operations of prediction systems 190, 500, or 600. Instructions 926 may also reside wholly or at least partially in main memory 904 or processing device 902, which also constitute machine-readable storage media during execution of the instructions by computer system 900.

[0083] The term "machine-readable storage medium" should be understood to include a single or multiple media storing one or more sets of instructions, or any media capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more methods of this disclosure. The term "machine-readable storage medium" should accordingly be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media. In examples, aggregated machine-readable media includes machine-readable media in which multiple particles have constant (e.g., rest) mass. Thus, aggregated machine-readable media is a non-transitory propagating signal. Specific examples of aggregated machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0084] Machine 900 may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, one or more of the display unit, input device, or UI navigation device may be a touchscreen display. The machine may include a signal generating device (e.g., a speaker) or one or more sensors, such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or one or more other sensors. Machine 900 may include an output controller, such as serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.)) connection, to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0085] Instructions 926 (e.g., software, programs, operating systems (OS), etc.) or other data stored on storage system 918 can be accessed by main memory 904 for use by processing device 902. Main memory 904 (e.g., DRAM) is typically faster but volatile, and therefore its storage type differs from storage system 918 (e.g., SSD), which is designed for long-term storage, including under "disconnect" conditions. Instructions 926 or data are typically loaded into main memory 904 for use by processing device 902 when used by user or machine 900. When main memory 904 is full, virtual space from storage system 918 can be allocated to supplement main memory 904; however, because storage system 918 devices are typically slower than main memory 904, and write speeds are typically at least twice as slow as read speeds, using virtual memory can significantly degrade the user experience (compared to main memory 904, such as DRAM) due to storage system latency. Furthermore, using storage system 918 for virtual memory can significantly shorten the lifespan of storage system 918.

[0086] Instruction 924 may further transmit or receive data via network interface device 908 and using a transmission medium through network 920 using any of a plurality of transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., those referred to as…). The Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, known as The IEEE 802.16 series of standards, the IEEE 802.15.4 series of standards, peer-to-peer (P2P) networks, etc. In an example, network interface device 908 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to network 920. In an example, network interface device 908 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 900, and includes digital or analog communication signals or other intangible media facilitating communication of such software.

[0087] The above detailed description includes reference to the accompanying drawings, which form part of the detailed description. The drawings illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate that only examples of those elements shown or described are provided herein. Furthermore, the inventors also contemplate examples (or aspects thereof) of any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0088] All publications, patents, and patent documents mentioned in this document are incorporated herein by reference in their entirety, as if they were individually incorporated by reference. In the event of any inconsistency between this document and those incorporated by reference, the usage in the incorporated reference shall be considered supplementary to the usage in this document; in the case of irreconcilable inconsistencies, the usage in this document shall prevail.

[0089] In this document, the term "a" is used as is common in patent documents to include one or more, independent of any other examples or uses of "at least one" or "one or more". In this document, the term "or" is used to refer to a non-exclusive "or", such that unless otherwise indicated, "A or B" includes "A but not B", "B but not A", and "A and B". In the appended claims, the terms "comprising" and "in which" are used as concise equivalents to the corresponding terms "including" and "wherein". Furthermore, in the appended claims, the terms "comprising" and "including" are open-ended, meaning that a system, apparatus, article, or process that includes elements other than those listed after such terms is still considered to be within the scope of the claims. Additionally, in the appended claims, the terms "first", "second", and "third", etc., are used only as designations and are not intended to impose numerical requirements on their objects.

[0090] In various instances, the components, controllers, processors, units, engines, or tables described herein may include physical circuitry systems or firmware stored on a physical device. As used herein, "processor" means any type of computing circuitry, such as (but not limited to) a microprocessor, microcontroller, graphics processor, digital signal processor (DSP), or any other type of processor or processing circuitry, including groups of processors or multi-core devices.

[0091] The various embodiments described herein include memories that utilize vertical structures of memory cells (e.g., NAND memory cell strings). As used herein, directional adjectives will be understood relative to the substrate surface forming the memory cells (i.e., a vertical structure will be understood as extending away from the substrate surface, the bottom end of a vertical structure will be understood as the end closest to the substrate surface, and the top end of a vertical structure will be understood as the end farthest from the substrate surface).

[0092] According to one or more embodiments of this disclosure, a memory controller (e.g., processor, controller, firmware, etc.) located inside or outside the memory device can determine (e.g., select, set, adjust, calculate, change, clear, transfer, adapt, derive, limit, utilize, modify, apply, etc.) a certain number of wear cycles or wear states (e.g., record wear cycles, count the operations of the memory device when the operation of the memory device occurs, track the memory device operation that started it, evaluate the memory device characteristics corresponding to the wear state, etc.).

[0093] It should be understood that when a component is referred to as "on another component," "connected to another component," or "coupled to another component," it can be directly on, connected to, or coupled to another component, or there may be intermediate components. Conversely, when a component is referred to as "directly on another component," "directly connected to another component," or "directly coupled to another component," there are no intermediate components or layers. If two components are shown in a diagram and a line connects them, then unless otherwise indicated, the two components can be coupled or directly coupled.

[0094] The methods described herein can be implemented, at least in part, by a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions that can be used to configure an electronic device to perform the methods described in the examples above. Implementations of such methods may include code, such as microcode, assembly language code, higher-level language code, etc. Such code may contain computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, the code may be tangibly stored, for example, during execution or at other times, on one or more volatile or non-volatile tangible computer-readable media. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical discs (e.g., compressed optical discs and digital video optical discs), magnetic tapes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), etc.

[0095] Example 1 is a computing system comprising: a storage system including: a storage device including non-volatile memory; and a host device configured to issue memory access commands to the storage device; and a prediction system including a processing circuitry system comprising one or more processors configured to perform operations that cause the prediction system to: identify one or more components of the storage system that limit the random read performance of the storage system; obtain characterization data indicating the impact of the one or more components on the random read performance; generate a model based on the characterization data to predict the random read performance of the storage system; execute the model while simulating the storage system to generate random read performance parameters of the storage system; and adjust the configuration of the components of the computing system based on the random read performance parameters to achieve a target random read performance.

[0096] In Example 2, the subject of Example 1 includes the processing circuitry system further configured to perform the following operations to cause the prediction system to: determine whether the random read performance parameters have reached a performance threshold; adjust the configuration of a first component among the one or more components based on the determination; obtain second characterization data indicating the impact of the first component on the random read performance; update the model based on the second characterization data; and execute the updated model while simulating the storage system to generate updated random read performance parameters for the storage system.

[0097] In Example 3, the subject matter of Examples 1-2 includes the processing circuitry system being further configured to perform the following operations that cause the prediction system to: adjust the configuration of a first component among the one or more components based on the determination; obtain second characterization data indicating the impact of the first component on the random read performance; update the model based on the second characterization data; execute the updated model while simulating the storage system to generate updated random read performance parameters of the storage system; and determine, based on the random read performance parameters and the updated random read performance parameters, whether the first component has at least a threshold impact on the predicted random read performance.

[0098] In Example 4, the subject matter of Examples 1-3 includes the following: wherein the characterization data indicates the configuration of the one or more components, and the processing circuitry is further configured to perform the following operations: determine whether the random read performance parameter has reached a performance threshold; and based on the determination, present the configuration of the one or more components.

[0099] In Example 5, the subject matter of Examples 1-4 includes, wherein one or more components include the non-volatile memory, and characterization data indicates at least one of the effects of the device-level parallelism characteristics of the non-volatile memory on random read performance.

[0100] In Example 6, the subject matter of Examples 1-5 includes, wherein one or more components include a data communication bus that couples the storage device to the host device, and the characterization data indicates the impact of access contention of the data communication bus on the random read performance.

[0101] In Example 7, the subject matter of Examples 1-6 includes one or more components comprising the command queue depth of the host device, and the characterization data indicating the impact of non-volatile memory die utilization resulting from the command queue depth on the random read performance.

[0102] In Example 8, the subject of Examples 1-7 includes the storage device comprising a storage controller, one or more components comprising an address translation cache of the storage controller, and the characterization data indicating the impact of the size of the address translation cache on the random read performance.

[0103] In Example 9, the subject of Examples 1-8 includes the storage device comprising a storage controller, the one or more components comprising storage controller firmware overhead, and the characterization data indicating the impact of random read latency caused by the storage controller firmware overhead on the random read performance.

[0104] Example 10 is a method for operating a computing system to predict the random read performance of a storage system, the method comprising: identifying one or more components of the storage system that limit the random read performance of the storage system; obtaining characterization data indicating the impact of the one or more components on the random read performance; generating a model based on the characterization data to predict the random read performance of the storage system; and executing the model while simulating the storage system to generate random read performance parameters of the storage system.

[0105] In Example 11, the subject of Example 10 includes: determining whether the random read performance parameters have reached a performance threshold; adjusting the configuration of a first component among the one or more components based on the determination; obtaining second characterization data indicating the impact of the first component on the random read performance; updating the model based on the second characterization data; and executing the updated model while simulating the storage system to generate updated random read performance parameters for the storage system.

[0106] In Example 12, the subject of Examples 10-11 includes: adjusting the configuration of a first component among the one or more components based on the determination; obtaining second characterization data indicating the impact of the first component on the random read performance; updating the model based on the second characterization data; executing the updated model while simulating the storage system to generate updated random read performance parameters of the storage system; and determining, based on the random read performance parameters and the updated random read performance parameters, whether the first component has at least a threshold impact on the predicted random read performance.

[0107] In Example 13, the subject of Examples 10-12 includes the method comprising: determining whether the random read performance parameter has reached a performance threshold; and presenting the configuration of the one or more components based on the determination.

[0108] In Example 14, the subject of Examples 10-13 includes, wherein one or more components include the non-volatile memory, and characterization data indicates at least one of the effects of the device-level parallelism characteristics of the non-volatile memory on random read performance.

[0109] In Example 15, the subject matter of Examples 10-14 includes, wherein one or more components include a data communication bus that couples the storage device to the host device, and the characterization data indicates the impact of access contention on the data communication bus on the random read performance.

[0110] In Example 16, the subject of Examples 10-15 includes one or more components comprising the command queue depth of the host device, and the characterization data indicating the impact of non-volatile memory die utilization resulting from the command queue depth on the random read performance.

[0111] In Example 17, the subject of Examples 10-16 includes the storage device comprising a storage controller, one or more components comprising an address translation cache of the storage controller, and the characterization data indicating the impact of the size of the address translation cache on the random read performance.

[0112] Example 18 is a device-readable storage medium that provides instructions, when executed by a processor of a host device, to cause the processor to perform operations including: identifying one or more components of a storage system that limit the random read performance of the storage system; obtaining characterization data indicating the impact of the one or more components on the random read performance; generating a model based on the characterization data to predict the random read performance of the storage system; and executing the model when simulating the storage system to generate random read performance parameters of the storage system.

[0113] In Example 19, the subject of Example 18 includes the operation further comprising: determining whether the random read performance parameters have reached a performance threshold; adjusting the configuration of a first component among the one or more components based on the determination; obtaining second characterization data indicating the impact of the first component on the random read performance; updating the model based on the second characterization data; and executing the updated model while simulating the storage system to generate updated random read performance parameters for the storage system.

[0114] In Example 20, the subject of Examples 18-19 includes the operation further comprising: adjusting the configuration of a first component among the one or more components based on the determination; obtaining second characterization data indicating the impact of the first component on the random read performance; updating the model based on the second characterization data; and executing the updated model while simulating the storage system to generate updated random read performance parameters of the storage system; and determining, based on the random read performance parameters and the updated random read performance parameters, whether the first component has at least a threshold impact on the predicted random read performance.

[0115] Example 21 is at least one machine-readable medium containing instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform operations to implement any one of Examples 1-20.

[0116] Example 22 is a device that includes components for implementing any one of Examples 1-20.

[0117] Example 23 is a system for implementing any one of Examples 1-20.

[0118] Example 24 is a method for implementing any of Examples 1-20.

[0119] In Example 25, any of the computing systems in Examples 1 through 9 can be adapted and operated to perform any of the operations according to the methods in Examples 10-17.

[0120] In Example 26, any of the methods of Examples 10 to 17 may be incorporated into an electronic system, which further includes a host processor and a communication bus extending between the host processor and the memory device.

[0121] In Example 27, any of the storage media in Examples 18-20 can be modified to any structure presented in another of Examples 1-9.

[0122] In Example 28, any of the methods in Examples 10-17 can be executed by an electronic system that includes a host processor and a communication bus extending between the host processor and a memory device.

[0123] In Example 29, any of the methods in Examples 10-17 can be modified to include the operations described in any other examples in Examples 18-20.

[0124] In Example 30, any of the methods in Examples 10-17, 28, or 29 may be implemented at least in part by using instructions stored as physical state in one or more machine-readable storage devices.

Claims

1. A computing system comprising: a storage system comprising: a storage device comprising a non-volatile memory, and a host device configured to issue memory access commands to the storage device; and a prediction system comprising processing circuitry including one or more processors, the processing circuitry configured to perform operations to cause the prediction system to: identify one or more components of the storage system that limit random read performance of the storage system, obtain characterization data indicative of an impact of the one or more components on random read performance, generate a model based on the characterization data to predict random read performance of the storage system, execute the model when simulating the storage system to generate a random read performance parameter of the storage system, and based on the random read performance parameter, adjust a configuration of a component of the computing system to achieve a target random read performance.

2. The computing system of claim 1, the processing circuitry further configured to perform operations to cause the prediction system to: determine whether the random read performance parameter meets a performance threshold; based on the determination, adjust a configuration of a first component of the one or more components; obtain second characterization data indicative of an impact of the first component on the random read performance; based on the second characterization data, update the model; and execute the updated model when simulating the storage system to generate an updated random read performance parameter of the storage system.

3. The computing system of claim 2, the processing circuitry further configured to perform operations to cause the prediction system to: based on the determination, adjust a configuration of a first component of the one or more components; obtain second characterization data indicative of an impact of the first component on the random read performance; based on the second characterization data, update the model; and execute the updated model when simulating the storage system to generate an updated random read performance parameter of the storage system; and based on the random read performance parameter and the updated random read performance parameter, determine whether the first component has at least a threshold impact on predicted random read performance.

4. The computing system of claim 1, wherein the characterization data is indicative of a configuration of the one or more components, and the processing circuitry is further configured to perform operations to cause the system to: determine whether the random read performance parameter meets a performance threshold; and based on the determination, present the configuration of the one or more components.

5. The computing system of claim 1, wherein the one or more components comprise the non-volatile memory, and the characterization data is indicative of at least one of a device-level parallelism feature of the non-volatile memory impact on random read performance.

6. The computing system of claim 1, wherein the one or more components comprise a data communication bus coupling a storage device to the host device, and the characterization data is indicative of an impact of access contention of the data communication bus on the random read performance.

7. The computing system of claim 1, wherein the one or more components comprise a command queue depth of the host device, and the characterization data indicates an effect of non-volatile memory die utilization resulting from the command queue depth on the random read performance.

8. The computing system of claim 1, wherein the storage device comprises a storage controller, the one or more components comprise an address translation cache of the storage controller, and the characterization data indicates an effect of a size of the address translation cache on the random read performance.

9. The computing system of claim 1, wherein the storage device comprises a storage controller, the one or more components comprise a storage controller firmware overhead, and the characterization data indicates an effect of a random read latency resulting from the storage controller firmware overhead on the random read performance.

10. A method for operating a computing system to predict random read performance of a storage system, the method comprising: identifying one or more components of the storage system that limit random read performance of the storage system; obtaining characterization data indicating an effect of the one or more components on random read performance; generating a model based on the characterization data to predict random read performance of the storage system; executing the model when simulating the storage system to generate random read performance parameters of the storage system; and based on the random read performance parameters, adjusting a configuration of a component of the computing system to achieve a target random read performance.

11. The method of claim 10, further comprising: determining whether the random read performance parameters meet a performance threshold; based on the determination, adjusting a configuration of a first component of the one or more components; obtaining second characterization data indicating an effect of the first component on the random read performance; based on the second characterization data, updating the model; and executing the updated model when simulating the storage system to generate updated random read performance parameters of the storage system.

12. The method of claim 11, further comprising: based on the determination, adjusting a configuration of a first component of the one or more components; obtaining second characterization data indicating an effect of the first component on the random read performance; based on the second characterization data, updating the model; and executing the updated model when simulating the storage system to generate updated random read performance parameters of the storage system; and based on the random read performance parameters and the updated random read performance parameters, determining whether the first component has at least a threshold effect on predicted random read performance.

13. The method of claim 10, wherein the characterization data indicates a configuration of the one or more components, and the method further comprises: determining whether the random read performance parameters meet a performance threshold; and based on the determination, presenting the configuration of the one or more components. ​ ​ ​ ​ 14. The method of claim 10, wherein the one or more components comprise a non-volatile memory, and the characterization data indicates at least one of an effect of a device-level parallelism feature of the non-volatile memory on random read performance.

15. The method of claim 10, wherein the one or more components comprise a data communication bus coupling a storage device to a host device, and the characterization data indicates an effect of access contention of the data communication bus on the random read performance.

16. The method of claim 10, wherein one or more components comprise a command queue depth of a host device, and the characterization data indicates an effect of non-volatile memory die utilization resulting from the command queue depth on the random read performance.

17. The method of claim 10, wherein a storage device comprises a storage controller, and the one or more components comprise an address translation cache of the storage controller, and the characterization data indicates an effect of a size of the address translation cache on the random read performance.

18. A device-readable storage medium providing instructions that, when executed by a processor of a host device, cause the processor to perform operations comprising: identifying one or more components of a storage system that limit random read performance of the storage system; obtaining characterization data indicating an effect of the one or more components on random read performance; generating a model based on the characterization data to predict random read performance of the storage system; executing the model when simulating the storage system to generate a random read performance parameter of the storage system; and based on the random read performance parameter, adjusting a configuration of a component of a computing system to achieve a target random read performance.

19. The device-readable storage medium of claim 18, the operations further comprising: determining whether the random read performance parameter meets a performance threshold; based on the determination, adjusting a configuration of a first component of the one or more components; obtaining second characterization data indicating an effect of the first component on the random read performance; based on the second characterization data, updating the model; and executing the updated model when simulating the storage system to generate an updated random read performance parameter of the storage system.

20. The device-readable storage medium of claim 19, the operations further comprising: based on the determination, adjusting a configuration of a first component of the one or more components; obtaining second characterization data indicating an effect of the first component on the random read performance; based on the second characterization data, updating the model; executing the updated model when simulating the storage system to generate an updated random read performance parameter of the storage system; and based on the random read performance parameter and the updated random read performance parameter, determining whether the first component has at least a threshold effect on predicted random read performance. ​ ​ ​

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