High frequency amplifier

Abstract

A high-frequency amplifier includes: an asymmetric Doherty amplifier that amplifies an input high-frequency signal of a wavelength λ, and includes a carrier amplifier and a peaking amplifier that starts an amplification operation when an output of the carrier amplifier reaches a saturation region and has a saturation output different from that of the carrier amplifier; a driver amplifier that drives the asymmetric Doherty amplifier; a branching circuit that branches the high-frequency signal amplified by the driver amplifier into an input path to the peaking amplifier side and an input path to the carrier amplifier side; a phase adjustment circuit that is provided on either of the path to the peaking amplifier side and the path to the carrier amplifier side and delays either of a phase of an input signal of the peaking amplifier and a phase of an input signal of the carrier amplifier; a first substrate on which the carrier amplifier and the peaking amplifier are mounted; and a second substrate on which the driver amplifier, the branching circuit, and the phase adjustment circuit are mounted, wherein, when the second substrate is stacked on the first substrate in an overlapping manner, an input terminal of the driver amplifier and an input terminal of the carrier amplifier are located at positions that project onto each other, and, when n is set to an integer of 0 or more, an electrical length from the input terminal of the driver amplifier to an output terminal of the carrier amplifier is set in such a manner that a phase becomes (2n+1)π.

Description

Technical Field

[0001] This disclosure relates to high-frequency amplifiers.

[0002] This application claims priority based on Japanese Application No. 2020-002882, filed on January 10, 2020, and invokes all the contents of that Japanese application. Background Technology

[0003] In recent years, broadband technology has been advancing in mobile communication systems such as mobile phones. Therefore, high power efficiency over a wide bandwidth is desired for power amplifiers used in base station devices and the like in these systems. As a power amplifier used to achieve this high power efficiency, a Dougherty amplifier, which includes a carrier amplifier (also called a main amplifier) ​​and a peak amplifier, is known. For example, the structure of a Dougherty amplifier (Dougherty-type amplifier) ​​is disclosed in Patent Document 1. It should be noted that the Dougherty amplifier is typically used after a driver amplifier.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: International Publication No. 2005 / 093948 Summary of the Invention

[0007] One aspect of this disclosure provides a high-frequency amplifier comprising: an asymmetric Dougherty amplifier, including a carrier amplifier and a peak amplifier that amplifies an input high-frequency signal of wavelength λ, having a different saturation output than the carrier amplifier and starting amplification when the output of the carrier amplifier reaches a saturation region; a driver amplifier that drives the asymmetric Dougherty amplifier; a branching circuit that branches the high-frequency signal amplified by the driver amplifier to an input path on the peak amplifier side and an input path on the carrier amplifier side; and a phase adjustment circuit disposed on either the path on the peak amplifier side or the path on the carrier amplifier side, such that the peak amplifier... The phase of the input signal of the device and the phase of the input signal of the carrier amplifier are delayed; a first substrate is equipped with the carrier amplifier and the peak amplifier; and a second substrate is equipped with the drive amplifier, the branch circuit and the phase adjustment circuit. When the second substrate is stacked on the first substrate in an overlapping manner, the input terminal of the drive amplifier and the input terminal of the carrier amplifier are in a mutually projected position. When n is set to an integer greater than or equal to 0, the electrical length from the input terminal of the drive amplifier to the output terminal of the carrier amplifier is set in a phase of (2n+1)×π. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view schematically illustrating a high-frequency amplifier according to one embodiment of the present disclosure.

[0009] Figure 2 This is an explanation Figure 1 Block diagram of a high-frequency amplifier.

[0010] Figure 3 yes Figure 1 A top-down view of the upper level.

[0011] Figure 4 yes Figure 1 The top view of the lower level.

[0012] Figure 5 yes Figure 1 The circuit diagram of the driver amplifier.

[0013] Figure 6 It is an explanation and Figure 5 The circuit diagram corresponds to the upper-level diagram.

[0014] Figure 7 yes Figure 1 The circuit diagram of the Doherty amplifier.

[0015] Figure 8 It is an explanation and Figure 7 The lower layer corresponding to the circuit diagram. Detailed Implementation

[0016] The problem this disclosure aims to solve

[0017] When a driver amplifier and a Dougherty amplifier are mounted on a printed circuit board (PCB), mounting the driver amplifier, carrier amplifier, and peak amplifier on the same plane requires a large PCB, making amplifier miniaturization difficult. In this case, a three-dimensional mounting of the driver amplifier and Dougherty amplifier can be considered. However, if the amplifier is configured as, for example, a two-layer structure with the driver amplifier on the upper layer and the carrier amplifier and peak amplifier on the lower layer, the driver amplifier and carrier amplifier may be close together in the vertical direction. This can lead to instability in the driver amplifier at times.

[0018] This disclosure is made in view of the facts as described above, and its purpose is to provide a stable high-frequency amplifier.

[0019] The effect of this disclosure

[0020] According to this disclosure, a stable high-frequency amplifier can be provided.

[0021] [Description of embodiments of this disclosure]

[0022] First, the contents of the embodiments of this disclosure will be listed for explanation.

[0023] For the high-frequency amplifier of this disclosure, (1) it comprises: an asymmetric Dougherty amplifier having a carrier amplifier and a peak amplifier having a different saturation output than the carrier amplifier when the output of the carrier amplifier reaches the saturation region, for amplifying a high-frequency signal of input wavelength λ; a drive amplifier for driving the asymmetric Dougherty amplifier; a branching circuit for branching the high-frequency signal amplified by the drive amplifier to the input path on the peak amplifier side and the input path on the carrier amplifier side; and a phase adjustment circuit disposed on either the path on the peak amplifier side or the path on the carrier amplifier side, such that the peak amplifier... The phase of the input signal of the amplifier and the phase of the input signal of the carrier amplifier are delayed; a first substrate is equipped with the carrier amplifier and the peak amplifier; and a second substrate is equipped with the drive amplifier, the branch circuit and the phase adjustment circuit. When the second substrate is stacked on the first substrate in an overlapping manner, the input terminals of the drive amplifier and the input terminals of the carrier amplifier are in mutually projected positions. When n is set to an integer greater than or equal to 0, the electrical length from the input terminal of the drive amplifier to the output terminal of the carrier amplifier is set in a phase of (2n+1)×π.

[0024] Therefore, even when signal feedback occurs (causing a portion of the output signal to return from the output of the carrier amplifier to the input of the driver amplifier), the driver amplifier remains in the instability-free region (negative feedback region), rather than the positive feedback region. Thus, even with a two-layer structure, the amplifier can be stabilized.

[0025] (2) In one embodiment of the high-frequency amplifier disclosed herein, the phase difference between the high-frequency signal at the output terminal of the carrier amplifier and the high-frequency signal at the output terminal of the peak amplifier is in the range of π / 2 to 3π / 2.

[0026] Since the phase difference between the output signals of the carrier amplifier and the peak amplifier is in the range of π / 2 to 3π / 2, the electromagnetic waves emitted from the carrier amplifier and the peak amplifier can be minimized.

[0027] (3) In one embodiment of the high-frequency amplifier disclosed herein, a grounded metal layer is disposed between the first substrate and the second substrate.

[0028] The grounded metal layer can block electromagnetic waves. As a result, the first substrate is less affected by electromagnetic waves generated on the second substrate side, and the second substrate is less affected by electromagnetic waves generated on the first substrate side.

[0029] (4) In one embodiment of the high-frequency amplifier disclosed herein, the first substrate has a planar shape that projects onto the second substrate.

[0030] It enables the miniaturization of high-frequency amplifiers.

[0031] (5) In one embodiment of the high-frequency amplifier disclosed herein, the peak amplifier is configured to have a larger saturation output than the carrier amplifier.

[0032] In a peak amplifier, the phase shift required to achieve optimal matching is larger than that in a carrier amplifier.

[0033] [Details of the embodiments of this disclosure]

[0034] Hereinafter, specific examples of the high-frequency amplifier of this disclosure will be described with reference to the accompanying drawings. Figure 1 This is a cross-sectional view schematically illustrating a high-frequency amplifier according to one embodiment of the present disclosure.

[0035] The high-frequency amplifier 1 is mounted on a communication device such as a base station device in a mobile communication system, for example, to amplify transmitted signals. The high-frequency amplifier 1 has a base member La4.

[0036] The base component La4 is a metal (e.g., copper) plate that serves as both a heat sink and an external terminal, and is disposed on the printed circuit board 100 of the communication device.

[0037] A lower layer 10, an upper layer 20, and a cover material 25 are mounted on a base component La4. The lower layer 10 corresponds to the first substrate of this disclosure, and the upper layer 20 corresponds to the second substrate of this disclosure.

[0038] The lower layer 10 is sandwiched between the base member La4 and the upper layer 20. The lower layer 10 is composed of a first dielectric layer 11 (e.g., with a thickness of 0.25 mm or more and 0.35 mm or less), a third wiring layer La3 (e.g., with a thickness of 18 μm or more and 35 μm or less), and a second dielectric layer 12 (e.g., with a thickness of 0.8 mm or more and 1.0 mm or less). The first dielectric layer 11 is disposed on the base member La4 (e.g., with a thickness of 0.25 mm). A high-frequency circuit pattern is formed on the third wiring layer La3, with the base member La4 forming the GND surface as a reference voltage. Active components such as the carrier amplifier 54 and the peak amplifier 64, as well as the inductor L and the capacitor C are mounted thereon.

[0039] The carrier amplifier 54 and the peak amplifier 64 each have surfaces 54a and 64a on which a defined circuit is formed, and back surfaces 54b and 64b on the opposite side of the surfaces 54a and 64a, which, for example, do not form a circuit. The carrier amplifier 54 and the peak amplifier 64 are embedded in the first dielectric layer 11, with surfaces 54a and 64a facing upwards and mounted on the third wiring layer La3. The back surfaces 54b and 64b are both arranged downwards in connection with the base member La4, and are adhered to the base member La4, which is coated with sintered silver paste or sintered copper paste.

[0040] The upper layer 20 is stacked on top of the lower layer 10. The upper layer 20 is composed of a third dielectric layer 23 (e.g., with a thickness of 0.25 mm or more and 0.35 mm or less), a first wiring layer La1 (e.g., with a thickness of 18 μm or more and 35 μm or less), and a fourth dielectric layer 24 (e.g., with a thickness of 0.25 mm or more and 0.35 mm or less). A second wiring layer La2 is disposed between the third dielectric layer 23 and the lower layer 10 (the second dielectric layer 12). The second wiring layer La2 (e.g., with a thickness of 35 μm) is, for example, a solid surface made of copper, and serves as a GND surface relative to the first wiring layer La1 and shields electromagnetic waves generated between the upper layer 20 and the lower layer 10. The second wiring layer La2 is equivalent to the grounded metal layer of this disclosure.

[0041] A high-frequency circuit pattern is formed on the first wiring layer La1, and active components such as the driver amplifier 40, as well as inductors L and capacitors C are installed.

[0042] The driver amplifier 40 has a surface 40a on which a defined circuit is formed and a back surface 40b located opposite the surface 40a and, for example, not on which a circuit is formed. The driver amplifier 40 is embedded in a fourth dielectric layer 24, with the surface 40a facing the lower layer 10 and mounted on a first wiring layer La1. The back surface 40b is configured to face upwards in a manner that separates it from the lower layer 10.

[0043] The upper layer 20 is covered by a metal cover 25. The driver amplifier 40 is mounted face-down; therefore, from a thermal management point of view, the back surface 40b of the driver amplifier 40 is positioned upwards in contact with the heat sink (zeroth wiring layer La0) of the cover 25. The heat sink (zeroth wiring layer La0), like the other wiring layers, is formed of a thin metal film layer for signal wiring. Furthermore, the heat sink (zeroth wiring layer La0) is adjacent to a nearby GND via (e.g., (The heat dissipation through holes 15d, 15c, 15b, and 15a) are in contact. Thus, a heat dissipation path (hereinafter referred to as the first heat dissipation path) is formed from the driver amplifier 40 to the base member La4.

[0044] It should be noted that the electrical path between the first wiring layer La1 of the upper layer 20 and the third wiring layer La3 of the lower layer 10 is ensured using signal vias 14b and 14a. Additionally, the electrical path between the first wiring layer La1 and the second wiring layer La2 is ensured using a signal via 17a. Furthermore, the electrical path between the first wiring layer La1 and the base member La4 is ensured using signal vias 13c, 13b, and 13a. The electrical path between the third wiring layer La3 and the base member La4 is ensured using a signal via 16a.

[0045] In this way, by stacking the upper layer 20 on the lower layer 10 in an overlapping manner, and mounting the drive amplifier 40, carrier amplifier 54 and peak amplifier 64 in three dimensions, it is possible to achieve miniaturization of the high-frequency amplifier 1, with the outermost shape being 6mm×6mm and the thickness being 2.2mm.

[0046] Furthermore, no lead bonding connection is required in this high-frequency amplifier 1. As a result, for example, a large panel of about 500mm × 500mm can be sent to the manufacturing process, from which, for example, 6,000 6mm × 6mm panels can be obtained, thus achieving a significant cost reduction through reduced processing and material costs.

[0047] Here, in the future Figure 3 The upper layer 20, as described in the text, overlaps with... Figure 4 In the case of the lower layer 10 described above, the input terminals of the drive amplifier 40 and the carrier amplifier 54 are vertically aligned, and the distance between them in the vertical direction is, for example, less than 1 mm, which is significantly narrower than when the drive amplifier 40 and the carrier amplifier 54 are arranged on the same plane. In this physical configuration, if the phase difference between the two input signals is within ±π / 2, interference occurs between the two input signals, thus making the operation of the drive amplifier 40 unstable. Specifically, the output signal of the drive amplifier 40 feeds back to the input, and the drive amplifier 40 may oscillate.

[0048] Therefore, in the high-frequency amplifier 1, the electrical length (that is, the electrical length taking into account the amount of chip components in the wiring length) from the input terminal of the driver amplifier 40 to the output terminal of the carrier amplifier 54, or the delay time of the input signal with wavelength λ propagating from the input terminal of the driver amplifier 40, including the intermediate chip components, to the output terminal of the carrier amplifier 54, is converted into the phase of the input signal with wavelength λ, and set in such a way that the phase between the terminals is (2n+1)×π. n is an integer greater than or equal to 0.

[0049] To achieve this, in the path from the drain output of the driver amplifier 40 to the branch circuit 51, for example, as... Figure 3 As shown in the curved pattern 49, it extends significantly from the center of the upper layer 20 to the right half, as... Figure 3 The path from the output of branch circuit 51 to via 52a, as shown in the curved pattern 52, is not a straight line, but is intentionally formed as a curve.

[0050] Thus, the electrical length from the input terminal of the drive amplifier 40 to the output terminal of the carrier amplifier 54 is set in a phase of (2n+1)×π. Therefore, even in the event of signal feedback (i.e., feedback that causes a portion of the output signal to return from the output of the carrier amplifier 54 towards the input of the drive amplifier 40), the drive amplifier 40 remains in a region free from instability (generally, the negative feedback region), rather than in the 2nπ region (i.e., the positive feedback region that generates instability). Thus, even with a two-layer structure, amplifier 1 can be stabilized.

[0051] Furthermore, in a typical Dougherty amplifier, the phase difference between the carrier amplifier and the peak amplifier is set to π / 2, but in the high-frequency amplifier 1, this phase difference is specifically set to π. That is, the phase difference between the RF signal at the output terminal of the carrier amplifier 54 and the RF signal at the output terminal of the peak amplifier 64 is set to a range of π / 2 to 3π / 2.

[0052] As a result, the electromagnetic waves emitted from the carrier amplifier 54 and the electromagnetic waves emitted from the peak amplifier 64 cancel each other out in the vicinity, thus suppressing the electromagnetic waves emitted to the outside of the high-frequency amplifier 1 to a small extent.

[0053] It should be noted that the phase of the carrier amplifier 54 and the phase of the peak amplifier 64 are connected through... Figure 3 The phase adjustment circuit 61 described in the text is in... Figure 7 , 8 The input matching circuits 53 and 63, the output matching circuits 55 and 65, and the transmission line TRL1 described herein (in) Figure 4 The 90° transmission line 56a) described in the text is synchronized at the output terminal RFout.

[0054] Figure 2 This is an explanation Figure 1 A block diagram of a high-frequency amplifier. Additionally, Figure 3 yes Figure 1 Top view of the upper level Figure 4 yes Figure 1 The top view of the lower level.

[0055] The high-frequency amplifier 1 has a driver amplifier 40 and a Dougherty amplifier 50 disposed at the rear end of the driver amplifier 40, and is configured to amplify signals in a frequency band, for example, above 5 GHz and below 6 GHz.

[0056] The driver amplifier 40 amplifies the RF (Radio Frequency) signal input to the input terminal RFin, which is defined by wavelength λ, to a level that the Dougherty amplifier 50 can amplify to a specified transmission power.

[0057] The Dougherty amplifier 50 includes a branch circuit 51, a phase adjustment circuit 61, a carrier amplifier 54, a peak amplifier 64, and Dougherty networks 56 and 66, which further amplify the RF signal amplified by the driver amplifier 40 and output it from the output terminal RFout.

[0058] The driver amplifier 40, carrier amplifier 54, and peak amplifier 64 are amplifiers that, for example, use GaN-HEMT (High Electron Mobility Transistor) as amplifying elements. The driver amplifier 40, carrier amplifier 54, and peak amplifier 64 all have their gate pads located on one side of a rectangular shape, while their drain pads are located on the side opposite the gate pad.

[0059] It should be noted that the drive amplifier 40, carrier amplifier 54, and peak amplifier 64 have source pads on both sides of the gate pad. However, regarding the drive amplifier 40, the two source pads are connected to GND formed on the upper layer 20. On the other hand, regarding the carrier amplifier 54 and peak amplifier 64, the source pads are connected via... Figure 1 The back faces 54b and 64b are connected to the base member La4 as described in the diagram. This ensures GND and forms a heat dissipation path (hereinafter referred to as the second heat dissipation path) from the carrier amplifier 54, the peak amplifier 64 to the base member La4.

[0060] The second heat dissipation path is considered to have superior heat dissipation compared to the first heat dissipation path. In the second heat dissipation path, the source pads of the carrier amplifier 54 and the peak amplifier 64 are connected to the base member La4 via the back surfaces 54b and 64b. The base member La4 is a metal (e.g., copper) plate, which has excellent heat dissipation. On the other hand, in the first heat dissipation path, the source pad of the driver amplifier 40 is connected to the heat sink (zero wiring layer La0) via the back surface 40b and to the base member La4 via a nearby GND via. The zero wiring layer La0 is a thin metal film for signal wiring, and therefore, from the point of view, it is less efficient than the base member La4, which is a metal (e.g., copper) plate. As a result, the heat sink (zero wiring layer La0) limits the rate of heat conduction, so the second heat dissipation path is considered to have superior heat dissipation compared to the first heat dissipation path.

[0061] Regarding the first heat dissipation path, it can be considered that by further expanding the diameter of the heat dissipation through holes 15a, 15b, 15c, and 15d, and by further providing heat dissipation through holes in parallel with the existing heat dissipation path (first heat dissipation path) in the heat dissipation path connecting the heat dissipation part (zero wiring layer La0) and the base member La4, the heat dissipation efficiency of the first heat dissipation path can be improved.

[0062] Figure 3 The upper layer 20 and shown Figure 4 The lower layer 10 shown has planes with roughly similar shapes, all formed, for example, 6mm × 6mm.

[0063] like Figure 1 As shown, the RF signal input to the input terminal RFin (signal via 13a) via the signal wiring 101a provided on the printed circuit board 100 of the communication device originates from... Figure 1 The base component La4 described in the text penetrates the lower layer 10, through... Figure 1 The signal vias 13a, 13b, and 13c shown are not connected to any part of the lower layer 10. Figure 3 Let's look at the input at the lower left corner of the upper layer 20. The driver amplifier 40 is installed near the lower left corner of the upper layer 20. The RF signal amplified by the driver amplifier 40 is as follows: Figure 3 The curve pattern 49 shows a large rotation. Specifically, with this... Figure 3 After going to the top of the upper layer 20, turn right and proceed along that top edge to the right, then turn right again to go to the bottom of the upper layer 20, reaching the branch circuit 51 that is also located on the upper layer 20, just like the drive amplifier 40.

[0064] Branch circuit 51, for example, is a Wilkinson type distributor that equally divides the RF signal amplified by drive amplifier 40 into the input path on the peak amplifier side and the input path on the carrier amplifier side.

[0065] One side of the RF signal distributed by branch circuit 51 (the input path on the carrier amplifier side) passes through the prescribed curve pattern 52, from which... Figure 3 Let's look at the via 52a formed near the lower edge of the upper layer 20, which leads to the lower layer 10. This is, for example, through... Figure 1 The signal paths of the signal vias 14a and 14b shown are the same. In contrast, the other side of the RF signal distributed by the branch circuit 51 (the input path on the peak amplifier side) reaches the phase adjustment circuit 61, which is also located on the upper layer 20, just like the driver amplifier 40.

[0066] Phase adjustment circuit 61 delays the phase of the input signal to peak amplifier 64 by a predetermined constant amount. For example, it delays it by 90°. The RF signal after passing through phase adjustment circuit 61 from... Figure 3 Let's look at the via 61a formed near the lower edge of the upper layer 20, which leads to the lower layer 10. This is also achieved through... Figure 1 The signal paths of the signal vias 14a and 14b shown are the same.

[0067] It should be noted that, in this embodiment, an example is given where the phase adjustment circuit 61 is positioned between the branch circuit 51 and the peak amplifier 64, rather than between the branch circuit 51 and the carrier amplifier 54. However, this disclosure is not limited to this example. For instance, it is also possible to position the phase adjustment circuit between the branch circuit 51 and the carrier amplifier 54, rather than between the branch circuit 51 and the peak amplifier 64, thereby delaying the phase of the input signal to the carrier amplifier 54.

[0068] The Dougherty amplifier 50 in this embodiment is an asymmetric Dougherty amplifier, where the peak amplifier 64 and the carrier amplifier 54 exhibit different maximum output strengths for the input RF signal. For example, the peak amplifier 64 has a saturation output (size) approximately twice that of the carrier amplifier 54, and the peak amplifier 64 begins amplification operation when the output of the carrier amplifier 54 reaches the saturation region. Specifically, the carrier amplifier 54 operates in class AB or class B, while the peak amplifier 64 operates in class C. When the instantaneous power is low, the carrier amplifier 54 operates, preventing the peak amplifier 64 from operating, thus increasing power efficiency. When the instantaneous power is high, both the carrier amplifier 54 and the peak amplifier 64 operate, thereby maintaining high power efficiency and increasing saturation power.

[0069] As an example, the outputs of the driver amplifier 40, carrier amplifier 54, and peak amplifier 64 are described. The driver amplifier 40 uses an amplifier with an output of 10W, the carrier amplifier 54 uses an amplifier with an output of 15W, and the peak amplifier 64 uses an amplifier with an output of 30W. Here, 10W output specifically refers to the size of the FET, and is used to mean that it has a size sufficient for 10W output, rather than always outputting 10W.

[0070] The RF signal amplified by carrier amplifier 54 reaches the Dougherty network 56 located on the carrier amplifier side of the lower layer 10. A 90° transmission line (also called a λ / 4 line) 56a is provided in this Dougherty network 56. Therefore, the RF signal amplified by carrier amplifier 54 travels from the lower layer 10 to the lower layer 10 via the 90° transmission line 56a. Figure 4 The output terminal RFout, located in the upper right corner of the lower layer 10, is combined with the output signal of the peak amplifier 64 (described later) and output.

[0071] On the other hand, the RF signal amplified by peak amplifier 64 reaches the Dougherty network 66 located on the peak amplifier side of the lower layer 10, and is combined with the output signal of carrier amplifier 54, and then... Figure 1 The signal path of the signal via 16a shown is output from the output terminal RFout. The signal output from the output terminal RFout is via, as shown... Figure 1 The signal wiring 101b, arranged on the printed circuit board 100 of the communication device as shown, propagates from the high-frequency amplifier 1 to the outside. It should be noted that the Dougherty network 56 on the carrier amplifier side and the Dougherty network 66 on the peak amplifier side are equivalent to the Dougherty networks of this disclosure.

[0072] Figure 5 yes Figure 1 The driver amplifier circuit diagram, Figure 6 It is an explanation and Figure 5 The circuit diagram corresponds to the upper-level diagram. Additionally, Figure 7 yes Figure 1 The circuit diagram of the Dougherty amplifier. Figure 8 Explanation and Figure 7 The lower layer corresponding to the circuit diagram.

[0073] from Figure 5 The RF signal input at the shown input terminal RFin is fed to the gate of the driver amplifier 40 via the input matching circuit 30 (inductor L1, capacitors C1 to C4, a total of 5). The gate bias voltage is supplied from the power supply Vg through inductor L2. Capacitor C5 is the bypass capacitor for the power supply Vg, and resistor R1 is the adjustment resistor.

[0074] The drain output of the driver amplifier 40 is supplied to the branch circuit 51 via the output matching circuit 41 (inductors L4 and L5, capacitors C7 to C9). The drain bias is supplied from the power supply Vd via inductor L3. Capacitor C6 is a bypass capacitor for the power supply Vd.

[0075] Next, as Figure 7 As shown, in branch circuit 51, the RF signal from the driver amplifier 40 is equally distributed to the matching circuit based on L11 and C24 and the matching circuit based on C23, L12 and C29.

[0076] The RF signal, whose phase was adjusted by the matching circuit based on L11 and C24, passes through... Figure 3 The curved pattern 52 and the via 52a described in the text reach the lower layer 10 and go to the carrier amplifier 54.

[0077] The RF signal that has reached the lower layer 10 is input to the gate of the carrier amplifier 54 via the input matching circuit 53 (capacitors C31, C11-14). The gate bias voltage is supplied from the power supply Vg through the inductor L6. Capacitor C15 is the bypass capacitor of the power supply Vg, and resistor R4 is the adjustment resistor.

[0078] The drain output of carrier amplifier 54 is supplied to the Dougherty network 56 on the carrier amplifier side via capacitor C26 for DC cutoff. The drain bias is supplied from power supply Vd via inductor L9. Capacitor C21 is a bypass capacitor for power supply Vd.

[0079] The Dougherty network 56 on the carrier amplifier side consists of an output matching circuit 55 and a transmission line TRL1 for combining the output of the carrier amplifier 54 and the output of the peak amplifier 64 (included in...). Figure 4 The 90° transmission line 56a) described herein is configured, and the output matching circuit 55 is configured by the transmission line TRL2 and the capacitor C25.

[0080] On the other hand, the RF signal, which is divided equally by the branch circuit 51 and whose phase is adjusted by the matching circuit based on C23, L12, and C29, is further phase-adjusted by the phase adjustment circuit 61 (inductors L15, L16, and capacitor C32), and reaches the lower layer 10 via the via 61a, and goes to the peak amplifier 64.

[0081] The RF signal arriving at the lower layer 10 is input to the gate of the peak amplifier 64 via the input matching circuit 63 (inductor L7, capacitors C16-19). The gate bias is supplied from the power supply Vg through inductor L8. Capacitor C20 is the bypass capacitor for the power supply Vg, and resistor R5 is the adjustment resistor.

[0082] The drain output of peak amplifier 64 is supplied to the Dougherty network 66 on the peak amplifier side via capacitor C28 for DC cutoff. Drain bias is supplied from power supply Vd via inductor L10. Capacitor C22 is a bypass capacitor for power supply Vd.

[0083] The Dougherty network 66 on the peak amplifier side consists of an output matching circuit 65 and a transmission line TRL4. The output matching circuit 65 consists of a two-segment structure of capacitors C27 and C10 and a transmission line TRL3.

[0084] Comparing the outputs of the aforementioned amplifiers, it can be assumed that the current consumption or power consumption, and the resulting heat generation, increase in the order of drive amplifier 40, carrier amplifier 54, and peak amplifier 64. In the high-frequency amplifier 1 of this embodiment, a structure is provided to address the higher heat generation of the peak amplifier 64 and carrier amplifier 54 using a second heat dissipation path with better heat dissipation efficiency, while the drive amplifier 40, which generates less heat, is addressed using a first heat dissipation path. With this structure, the high-frequency amplifier 1 can provide a compact high-frequency amplifier with good heat dissipation.

[0085] Since the high-frequency amplifier 1 utilizes the second heat dissipation path to address the peak amplifier 64 and carrier amplifier 54, and the drive amplifier 40 utilizes the first heat dissipation path, therefore... Figure 1 As shown, the RF signal input to the input terminal RFin (signal via 13a) passes through the lower layer 10 from the base component La4, and through... Figure 1 The signal vias 13a, 13b, and 13c shown are not connected to any part of the lower layer 10. Figure 3 Let's look at the input from the lower left corner of the upper layer 20. Additionally, the RF signal distributed by the branch circuit 51 is input to the peak amplifier 64 and carrier amplifier 54 located in the lower layer 10, thus... Figure 1 The signal paths of the signal vias 14a and 14b shown are the same. Through these signal paths, the high-frequency amplifier 1 can provide a small and well-heated high-frequency amplifier.

[0086] The embodiments disclosed herein should be considered illustrative rather than restrictive in all respects. The scope of this disclosure is defined not by the foregoing meaning, but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0087] Explanation of reference numerals in the attached figures

[0088] 1…High-frequency amplifier, 10…Lower layer, 11…First dielectric layer, 12…Second dielectric layer, 13a, 13b, 13c, 14a, 14b, 16a, 17a…Signal vias, 15a, 15b, 15c, 15d…Heat dissipation vias, 20…Upper layer, 23…Third dielectric layer, 24…Fourth dielectric layer, 25…Cover material, 30…Input matching circuit, 40…Drive amplifier, 40a…Surface, 40b…Back side, 41…Output matching circuit, 49…Curved pattern, 50…Dougherty amplifier, 51…Branch circuit, 52…Curved pattern, 52a…via, 53…Input matching circuit, 54…Carrier amplifier, 54a…Surface, 54b…Back side, 55…Output matching circuit, 56, 66…Multiple Erti network, 56a…90° transmission line, 61…phase adjustment circuit, 61a…via, 63…input matching circuit, 64…peak amplifier, 64a…surface, 64b…back side, 65…output matching circuit, 100…printed substrate, 101a, 101b…wiring on printed substrate, La0…zero wiring layer (heat sink), La1…first wiring layer, La2…second wiring layer, La3…third wiring layer, La4…base component, RFin…input terminal, RFout…output terminal, L, L1~L12, L15, L16…inductors, C, C1~C29, C31, C32…capacitors, R1, R3~R5…resistors, TRL1~TRL4…transmission lines, Vd, Vg…power supply.

Claims

1. A high-frequency amplifier comprising: an asymmetric Doherty amplifier that amplifies an input high-frequency signal of a wavelength λ, and that includes a carrier amplifier and a peaking amplifier that starts an amplification operation when an output of the carrier amplifier reaches a saturation region and that has a saturation output different from that of the carrier amplifier; a driver amplifier that drives the asymmetric Doherty amplifier; a branching circuit that branches the high-frequency signal amplified by the driver amplifier into an input path to the peaking amplifier side and an input path to the carrier amplifier side; a phase adjustment circuit that is provided on either of the path to the peaking amplifier side and the path to the carrier amplifier side, and that delays either of a phase of an input signal to the peaking amplifier and a phase of an input signal to the carrier amplifier; a first substrate on which the carrier amplifier and the peaking amplifier are mounted; and a second substrate on which the driver amplifier, the branching circuit, and the phase adjustment circuit are mounted, wherein, when the second substrate is stacked on the first substrate in a superposed manner, an input terminal of the driver amplifier and an input terminal of the carrier amplifier are located at positions that project onto each other, and wherein, when n is set to an integer of 0 or more, an electrical length from the input terminal of the driver amplifier to an output terminal of the carrier amplifier is set in such a manner that a phase of (2n + 1) x π is obtained.

2. The high-frequency amplifier according to claim 1, wherein a phase difference between a high-frequency signal in the output terminal of the carrier amplifier and a high-frequency signal in an output terminal of the peaking amplifier is in a range of π / 2 to 3π / 2.

3. The high-frequency amplifier according to claim 1, wherein a metal layer to which a ground is applied is arranged between the first substrate and the second substrate.

4. The high-frequency amplifier according to claim 2, wherein a metal layer to which a ground is applied is arranged between the first substrate and the second substrate.

5. The high-frequency amplifier according to any one of claims 1 to 4, wherein the first substrate has a planar shape that projects onto the second substrate.

6. The high-frequency amplifier according to any one of claims 1 to 4, wherein the peaking amplifier is configured to have a saturation output larger than that of the carrier amplifier.

7. The high-frequency amplifier according to claim 5, wherein the peaking amplifier is configured to have a saturation output larger than that of the carrier amplifier. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

Images