Profile-layer-level parameter sets in video codecs

Abstract

Devices, systems, and methods for specifying syntax and semantics of decoding parameter sets (DPS) are described. An example method of video processing includes: for conversion between video and a bitstream of the video, determining that each output layer set (OLS) in a codec video sequence (CVS) in the bitstream conforms to at least one profile-layer-level (PTL) syntax structure included in a data structure associated with decoding parameter semantics in the bitstream; and performing the conversion based on the determination, wherein the PTL syntax structure indicates a profile, layer, and level of the bitstream.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is an application entering the Chinese national phase of International Patent Application No. PCT / US2020 / 067078 filed on December 26, 2020, which claims priority to U.S. Provisional Patent Application No. US 62 / 953,862 filed on December 26, 2019. The entire disclosure of the above application is incorporated by reference as part of the disclosure of this application. Technical Field

[0003] This patent document relates to video coding and decoding technology, systems and devices. Background Art

[0004] Digital video accounts for the largest use of bandwidth on the Internet and other digital communications networks. As the number of connected user devices capable of receiving and displaying video increases, bandwidth demand for digital video usage is expected to continue to grow. Summary of the invention

[0005] Devices, systems and methods related to digital video coding are described, including syntax and semantics for specifying a decoding parameter set (DPS). The described methods can be applied to existing video coding standards (e.g., High Efficiency Video Coding (HEVC) and / or Versatile Video Coding (VVC)) and future video coding standards or video codecs.

[0006] In one representative aspect, the disclosed technology may be used to provide a video processing method. The method includes: performing conversion between a video and a bitstream of the video, wherein the bitstream conforms to a format rule, wherein the format rule specifies excluding sub-layer level information from a plurality of profile-layer-level (PTL) syntax structures included in a decoding parameter set of the bitstream, wherein each of the plurality of PTL syntax structures indicates a profile, layer, and level of the bitstream, and wherein the decoding parameter set includes decoding capability information.

[0007] In another representative aspect, the disclosed technology can be used to provide a video processing method. The method includes: for conversion between a video and a bitstream of the video, determining that each output layer set (OLS) in a codec video sequence (CVS) in the bitstream conforms to at least one profile-layer-level (PTL) syntax structure, the syntax structure included in a data structure associated with decoding parameter semantics in the bitstream; and performing the conversion based on the determination, wherein the PTL syntax structure indicates the profile, layer and level of the bitstream.

[0008] In yet another representative aspect, the above method is embodied in the form of processor executable code and stored in a computer readable program medium.

[0009] In yet another representative aspect, a device is disclosed, the device being configured or operable to perform the above method. The device may include a processor programmed to implement the method.

[0010] In yet another representative aspect, a video decoder device may implement the method as described in the present disclosure.

[0011] The above and other aspects and features of the disclosed technology are described in more detail in the drawings, the description, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating an example video processing system in which the various techniques of this disclosure may be implemented.

[0013] Figure 2 is a block diagram of an example hardware platform for video processing.

[0014] Figure 3 A block diagram is provided to illustrate an example video codec system in which some embodiments of the present disclosure may be implemented.

[0015] Figure 4 A block diagram illustrating an example of an encoder in which some embodiments of the present disclosure may be implemented.

[0016] Figure 5 A block diagram illustrating an example of a decoder in which some embodiments of the present disclosure may be implemented.

[0017] Figure 6 A flow chart illustrating an example method of video processing.

[0018] Figure 7 A flow chart illustrating an example method of video processing. DETAILED DESCRIPTION

[0019] Video coding methods and techniques are ubiquitous in modern technology due to the increased demand for higher-precision video. Video codecs typically include electronic circuits or software that compress or decompress digital video, and are constantly being improved to provide greater coding efficiency. Video codecs convert uncompressed video into a compressed format and vice versa. There is a complex relationship between video quality, the amount of data used to represent the video (determined by the bitrate), the complexity of the encoding and decoding algorithms, sensitivity to data loss and errors, ease of editing, random access, and end-to-end delay (latency). The compression format typically conforms to a standard video compression specification, such as the High Efficiency Video Coding (HEVC) standard (also known as H.265 or MPEG-H Part 2), the yet-to-be-finalized Versatile Video Codec standard, or other current and / or future video codec standards.

[0020] Embodiments of the disclosed technology can be applied to existing video codec standards (e.g., HEVC, H.265) and future standards to improve runtime performance. It is particularly relevant to Merge mode in video codecs. Section headings are used in this document to improve readability of the description and do not in any way limit the discussion or embodiments (and / or implementation methods) to the corresponding section.

[0021] 1. Overview of Example Embodiments

[0022] Embodiments of the disclosed technology are directed to specifying the syntax and semantics of a decoding parameter set (DPS). It can be applied to any video codec standard or non-standard video codec that supports single-layer video codec and multi-layer video codec, such as Versatile Video Coding (VVC) under development. It can be applied to any video codec standard that supports segmenting a picture into slices and sub-pictures, such as Versatile Video Coding (VVC) under development, or any other video codec standard or video codec.

[0023] 2. List of abbreviations used in this document

[0024] APS (Adaptation Parameter Set)

[0025] AU (Access Unit)

[0026] AUD (Access Unit Delimiter) access unit delimiter

[0027] AVC (Advanced Video Coding) Advanced Video Codec

[0028] CLVS (Coded Layer Video Sequence) Coded Layer Video Sequence

[0029] CPB (Coded Picture Buffer) codec picture buffer

[0030] CRA (Clean Random Access) Clean Random Access

[0031] CTU (Coding Tree Unit)

[0032] CVS (Coded Video Sequence) codec video sequence

[0033] DPB (Decoded Picture Buffer) decoded picture buffer

[0034] DPS (Decoding Parameter Set) decoding parameter set

[0035] EOB (End Of Bitstream) bitstream ends

[0036] EOS (End Of Sequence) sequence ends

[0037] GDR (Gradual Decoding Refresh) Gradual Decoding Refresh

[0038] HEVC (High Efficiency Video Coding) High Efficiency Video Coding

[0039] IDR (Instantaneous Decoding Refresh) instant decoding refresh

[0040] JEM (Joint Exploration Model)

[0041] MCTS (Motion-Constrained Tile Sets)

[0042] NAL (Network Abstraction Layer) Network Abstraction Layer

[0043] OLS (Output Layer Set) output layer set

[0044] PH (Picture Header)

[0045] PPS (Picture Parameter Set) Picture Parameter Set

[0046] PTL (Profile, Tier and Level)

[0047] PU (Picture Unit)

[0048] RBSP (Raw Byte Sequence Payload) Raw Byte Sequence Payload

[0049] SEI (Supplemental Enhancement Information)

[0050] SPS (Sequence Parameter Set)

[0051] VCL (Video Coding Layer) video coding layer

[0052] VPS (Video Parameter Set) video parameter set

[0053] VTM (VVC Test Model) VVC Test Model

[0054] VUI (Video Usability Information) video availability information

[0055] VVC (Versatile Video Coding) multi-functional video codec

[0056] 3. Preliminary discussion

[0057] Video codec standards have evolved primarily through the well-known ITU-T and ISO / IEC standards. ITU-T developed H.261 and H.263, ISO / IEC developed MPEG-1 and MPEG-4 Vision, and the two organizations jointly developed the H.262 / MPEG-2 Video standard, the H.264 / MPEG-4 Advanced Video Codec (AVC) standard, and the H.265 / HEVC standard. Starting with H.262, video codec standards are based on a hybrid video codec structure, which uses temporal prediction plus transform codec. In order to explore future video codec technologies beyond HEVC, VCEG and MPEG jointly established the Joint Video Exploration Team (JVET) in 2015. Since then, JVET has adopted many new methods and put them into reference software called the Joint Exploration Model (JEM). JVET meetings are held simultaneously every quarter, and the goal of the new codec standard is to reduce the bit rate by 50% compared to HEVC. The new video codec standard was officially named Versatile Video Codec (VVC) at the JVET meeting in April 2018, and the first version of the VVC Test Model (VTM) was released at that time.

[0058] 3.1 Parameter Set

[0059] AVC, HEVC, and VVC specify parameter sets. Types of parameter sets include SPS, PPS, APS, VPS, and DPS. SPS and PPS are supported in all AVC, HEVC, and VVC. VPS was introduced since HEVC and is included in both HEVC and VVC. APS and DPS are not included in AVC or HEVC, but are included in the latest VVC draft text.

[0060] SPS is designed to carry sequence-level header information, and PPS is designed to carry picture-level header information that does not change frequently. With SPS and PPS, there is no need to repeat information that does not change frequently for each sequence or picture, so redundant signaling of this information can be avoided. In addition, the use of SPS and PPS enables out-of-band transmission of important header information, which not only avoids the need for redundant transmission but also improves error resilience.

[0061] VPS is introduced to carry sequence level header information common to all layers in a multi-layer bitstream.

[0062] APS was introduced to carry such picture-level or slice-level information, which requires quite a few bits to encode and decode, can be shared by multiple pictures, and can have many different variations in a sequence.

[0063] DPS is introduced to carry bitstream level information indicating the highest capability required for decoding the entire bitstream.

[0064] 3.2 Tiers, layers and levels

[0065] Video codec standards usually specify profiles and levels. Some video codec standards also specify layers, such as HEVC and VVC, which is being developed.

[0066] Profiles, tiers, and levels specify constraints on a bitstream, and therefore the capabilities required to decode the bitstream. Profiles, tiers, and levels can also be used to indicate points of interoperability between various decoder implementations.

[0067] Each profile specifies a subset of algorithmic features and restrictions that all decoders conforming to that profile should support. Note that encoders are not required to use all codecs or features supported in a profile, but decoders conforming to a profile are required to support all codecs or features.

[0068] Each level of the layers specifies a set of constraints on the values ​​that bitstream syntax elements can take. The same set of layer and level definitions are typically used for all profiles, but separate implementations may support different layers and different levels within a layer for each supported profile. For any given profile, the level of the layers typically corresponds to a specific decoder processing load and memory capabilities.

[0069] The capabilities of video decoders that conform to the video codec specification are specified based on the constraints that the ability to decode video streams conform to the profiles, layers, and levels specified in the video codec specification. When expressing the capabilities of a decoder for a specified profile, the layers and levels supported by the profile should also be expressed.

[0070] 3.3 Syntax and Semantics of Decoding Parameter Set (DPS) in VVC

[0071] In the latest VVC draft text in JVET-P2001-v14, which is publicly available here: http: / / phenix.int-evry.fr / jvet / doc_end_user / documents / 16_Geneva / wg11 / JVET-P2001-v14.zip, the DPS is specified as follows.

[0072] 7.3.2.1 Decoding Parameter Set Syntax

[0073]

[0074] 7.4.3.1 Decoding parameter set RBSP semantics

[0075] The DPS RBSP shall be available for the decoding process before being referenced, and shall be included in at least one AU with TemporalId equal to 0 or provided by external means.

[0076] NOTE 1 – The DPS NAL unit needs to be available to the decoding process (either in the bitstream or by external means) before being referenced. However, the information contained in the DPS RBSP is not necessary for the operation of the decoding process specified in clauses 2 to 9 of this specification.

[0077] dps_decoding_parameter_set_id identifies the DPS for reference by other syntax elements. The value of dps_decoding_parameter_set_id shall not be equal to 0.

[0078] dps_max_sublayers_minus1 plus 1 specifies the maximum number of temporal sublayers that can be present in each CVS involving the DPS. The value of dps_max_sublayers_minus1 shall be in the range of 0 to 6, inclusive.

[0079] dps_reserved_zero_5bits shall be equal to 0 in bitstreams conforming to this version of this specification. Other values ​​of dps_reserved_zero_5bits are reserved for future use by ITU-T | ISO / IEC.

[0080] dps_num_ptls_minus1 plus 1 specifies the number of profile_tier_level() syntax structures in DPS.

[0081] When multiple profile_tier_level() syntax structures exist in the DPS, bitstream conformance requires that each CVS in the bitstream conform to at least one of the profile_tier_level() syntax structures.

[0082] dps_extension_flag equal to 0 specifies that the dps_extension_data_flag syntax element is not present in the DPS RBSP syntax structure. dps_extension_flag equal to 1 specifies that the dps_extension_data_flag syntax element is present in the DPS RBSP syntax structure.

[0083] The dps_extension_data_flag may have any value. Its presence and value do not affect the conformance of a decoder to the profiles specified in Annex A. Decoders conforming to this version of this specification shall ignore all dps_extension_data_flag syntax elements.

[0084] 3.4 Syntax and Semantics of Profiles, Layers and Levels (PTL) in VVC

[0085] In the latest VVC draft text in JVET-P2001-v14, the syntax and semantics of the profile_tier_level() syntax structure (one or more instances of which may be included in a DPS) are specified as follows.

[0086] 7.3.3.1 Common profile, layer and level syntax

[0087]

[0088] 7.4.4.1 General profile, layer and level semantics

[0089] The profile_tier_level() syntax structure provides level information and optionally profile, tier, sub-profile and general constraint information.

[0090] When the profile_tier_level() syntax structure is included in the DPS, OlsInScope is the OLS of all layers in the entire bitstream that references the DPS. When the profile_tier_level() syntax structure is included in the VPS, OlsInScope is one or more OLSs specified by the VPS. When the profile_tier_level() syntax structure is included in the SPS, OlsInScope is the OLS that only includes the lowest layer among the layers that reference the SPS, and the lowest layer is an independent layer.

[0091] general_profile_idc indicates that OlsInScope conforms to the profile specified in Annex A. The bitstream shall not contain values ​​of general_profile_idc other than those specified in Annex A. Other values ​​of general_profile_idc are reserved for future use by ITU-T | ISO / IEC.

[0092] general_tier_flag specifies the tier context for the interpretation of general_level_idc specified in Annex A.

[0093] general_level_idc indicates that OlsInScope conforms to the level specified in Annex A. The bitstream shall not contain values ​​of general_level_idc other than those specified in Annex A. Other values ​​of general_level_idc are reserved for future use by ITU-T | ISO / IEC.

[0094] NOTE 1 – A larger value of general_level_idc indicates a higher level. The maximum level signaled in DPS for OlsInScope may be higher than the level signaled in SPS for CVS contained in OlsInScope.

[0095] NOTE 2 – When OlsInScope conforms to multiple profiles, general_profile_idc shall indicate the profile that provides the preferred decoding results or preferred bitstream identification, as determined by the encoder (in a manner not specified in this specification).

[0096] NOTE 3 – When the profile_tier_level() syntax structure is included in the DPS and CVS of OlsInScope compliant with different profiles, general_profile_idc and level_idc shall indicate the profile and level of the decoder capable of decoding OlsInScope.

[0097] num_sub_profiles specifies the number of general_sub_profile_idc[i] syntax elements.

[0098] general_sub_profile_idc[i] indicates the i-th interoperability metadata registered according to Rec.ITU-T T.35. The content of Rec.ITU-T T.35 is not specified in this specification.

[0099] sublayer_level_present_flag[i] equal to 1 specifies that level information is present in the profile_tier_level() syntax structure of the sublayer representation with TemporalId equal to i. sublayer_level_present_flag[i] equal to 0 specifies that level information is not present in the profile_tier_level() syntax structure of the sublayer representation with TemporalId equal to i.

[0100] ptl_alignment_zero_bits shall be equal to 0.

[0101] The semantics of the syntax element sublayer_level_idc[i], except for the absence of specification of an inferred value, is the same as for the syntax element general_level_idc, but applies to sublayer representations with TemporalId equal to i.

[0102] When not present, the value of sublayer_level_idc[i] is inferred as follows:

[0103] – infer sublayer_level_idc[maxNumSubLayersMinus1] to be equal to general_level_idc of the same profile_tier_level() structure,

[0104] – For i from maxNumSubLayersMinus1–1 to 0 (in decreasing order of the value of i, inclusive), sublayer_level_idc[i] is inferred to be equal to sublayer_level_idc[i+1].

[0105] 4. Disadvantages of existing implementation methods

[0106] The existing DPS design in VVC has the following problems:

[0107] (1) The DPS applies to the entire bitstream, and all SPSs referenced by codec pictures in the bitstream should reference the same DPS. However, there is no constraint requiring that all DPS NAL units in a bitstream should have the same content.

[0108] (2) Since the entire bitstream references the same DPS, the DPS ID referenced by the SPS is actually useless.

[0109] (3) In the latest VVC draft text, the DPS can appear in any AU. However, while it is useful to have a DPS at the beginning of the bitstream or in any AU that can be used as a random access point, for example, an AU containing IRAP pictures and GDR pictures, the presence of a DPS NAL unit in an AU that does not contain randomly accessible pictures or slices is useless. A randomly accessible slice is a slice with either the IRAP NAL unit type or the GDR NAL unit type.

[0110] (4) Since the DPS indicates the highest capability required to decode the entire bitstream, the profile_tier_level() syntax structure included in the DPS does not need to contain sublayer level information, which is carried by instances of the sublayer_level_idc[i] syntax element.

[0111] (5) When the profile_tier_level() syntax structure is included in a DPS, OlsInScope (i.e., the OLS to which the DPS applies) is defined as the OLS that includes all layers in the entire bitstream that references the DPS. However, there may not be an OLS that includes all layers in the entire bitstream.

[0112] 5. Example embodiments of the disclosed technology

[0113] The following detailed embodiments should be considered as examples to explain the general concept. These embodiments should not be interpreted narrowly. In addition, these embodiments can be combined in any way.

[0114] 1) To solve the first problem, it is required that all DPS NAL units with a specific value of dps_decoding_parameter_set_id in the bitstream should have the same content.

[0115] a. Alternatively, there is an additional requirement that all DPS NAL units in the bitstream should have the same dps_decoding_parameter_set_id value.

[0116] b. Alternatively, it is required (not an additional requirement) that all DPS NAL units in a bitstream should have the same dps_decoding_parameter_set_id value.

[0117] c. Alternatively, it is required that all DPS NAL units in the bitstream should have the same content.

[0118] 2) To solve the second problem, the DPS ID (i.e., the dps_decoding_parameter_set_id syntax element) is removed from the DPS syntax, and therefore the reference to the DPS ID in the SPS syntax (sps_decoding_parameter_set_id) is removed from the SPS syntax. In fact, the DPS then becomes an independent NAL unit instead of a parameter set. Therefore, the name of the DPS can be changed to "decoding parameter NAL unit". And it is required that all decoding parameter NAL units in the bitstream must have the same content.

[0119] a. Alternatively, the DPS information is signaled in a new SEI message, for example, named "decoding parameter SEI message", and it is required that when the SEI NAL unit contains the decoding parameter SEI message, it should not contain any other SEI message. And it is required that all decoding parameter SEI messages in the bitstream must have the same content.

[0120] 3) To solve the third problem, the following constraints are specified:

[0121] When present in the bitstream, the DPS NAL unit shall be present in the first AU of the bitstream, and may be present in any AU that has at least one codec slice NAL unit whose nal_unit_type is in the range from IDR_W_RADL to GDR_NUT (this NAL unit is an IRAP or GDR VCL NAL unit), inclusive, and shall not be present in any other AU.

[0122] Alternatively, replace the above “in any AU with at least one codec slice NAL unit whose nal_unit_type is in the range from IDR_W_RADL to GDR_NUT (the NAL unit is an IRAP or GDR VCL NAL unit), including IDR_W_RADL and GDR_NUT” with “in any AU with at least one IRAP or GDR picture”.

[0123] Alternatively, in either of the above two alternatives, the above “from IDR_W_RADL to GDR_NUT, including IDR_W_RADL and GDR_NUT” is replaced with “from IDR_W_RADL to RSV_IRAP_12, including IDR_W_RADL and RSV_IRAP_12”, i.e., further including the reserved IRAP NAL unit type.

[0124] Alternatively, the same constraints (any of the above alternatives) are specified for the decoding parameters NAL unit by replacing the above "DPS NAL unit" with a "decoding parameters NAL unit".

[0125] Alternatively, the same constraints are specified for the SEI NAL unit containing the decoding parameters SEI message (any of the above alternatives) by replacing the above "DPS NAL unit" with "SEI NAL unit containing the decoding parameters SEI message".

[0126] 4) To solve the fourth problem, ensure that each profile_tier_level() syntax structure included in the DPS does not contain sub-tier level information.

[0127] a. This purpose can be achieved by adding an input parameter to the PTL syntax structure to control whether sub-layer level information is signaled. For DPS, this parameter is 0 (ie, no sub-layer level information), and for VPS and SPS, this parameter is 1.

[0128] b. Alternatively, this purpose is achieved by requiring sublayer_level_present_flag[i] to be equal to 0 for each i in each PTL syntax structure in the DPS (or decoding parameter NAL unit, or SEI NAL unit containing a decoding parameter SEI message).

[0129] 5) To solve the fifth problem, the following constraints are specified:

[0130] Each OLS in the CVS in the bitstream shall conform to at least one PTL syntax structure in the DPS (as part of the DPS semantics).

[0131] And accordingly, the semantics of the PTL syntax structure regarding OlsInScope is changed: "When the profile_tier_level() syntax structure is included in the DPS, OlsInScope is one or more unidentified OLSs in one or more unidentified CVSs in the bitstream."

[0132] Note that the DPS does not need to contain the optimal PTL information for all OLSs. For example, when there are OLSs of levels 3, 4, and 5, assuming that the other PTL information of the OLSs is the same, it is sufficient to include only one PTL syntax structure indicating level 5 in the DPS, because an OLS that correctly complies with a particular level also complies with any higher level.

[0133] The same constraints also apply to the alternative of replacing the DPS with a decoding parameter NAL unit or a decoding parameter SEI message.

[0134] 6. Additional Example Embodiments

[0135] Below are some example embodiments that may be applied to the VVC specification. The changed text is based on the latest VVC text in JVET-P2001-v14. New additions, modifications, and the most relevant parts are double underlined. There are also some other changes that are editorial in nature and are therefore not shown or marked as different.

[0136] 6.1 First Embodiment

[0137] 6.1.1DPS Syntax and Semantics

[0138] 7.3.2.1 Decoding Parameter Set Syntax

[0139]

[0140]

[0141] 7.4.3.1 Decoding parameter set RBSP semantics

[0142] The DPS RBSP shall be available for the decoding process before being referenced, and shall be included in at least one AU with TemporalId equal to 0 or provided by external means.

[0143] NOTE 1 – The DPS NAL unit needs to be available to the decoding process (either in the bitstream or by external means) before being referenced. However, the information contained in the DPS RBSP is not necessary for the operation of the decoding process specified in clauses 2 to 9 of this specification.

[0144]

[0145] dps_decoding_parameter_set_id identifies the DPS for reference by other syntax elements. The value of dps_decoding_parameter_set_id should be greater than 0.

[0146] dps_max_sublayers_minus1 plus 1 specifies the maximum number of temporal sublayers that can be present in a layer in the bitstream. The value of dps_max_sublayers_minus1 shall be in the range of 0 to 6, inclusive.

[0147] dps_reserved_zero_5bits shall be equal to 0 in bitstreams conforming to this version of this specification. Other values ​​of dps_reserved_zero_5bits are reserved for future use by ITU-T | ISO / IEC.

[0148] dps_num_ptls_minus1 plus 1 specifies the number of profile_tier_level() syntax structures in DPS.

[0149]

[0150]

[0151] dps_extension_flag equal to 0 specifies that the dps_extension_data_flag syntax element is not present in the DPS RBSP syntax structure. dps_extension_flag equal to 1 specifies that the dps_extension_data_flag syntax element is present in the DPS RBSP syntax structure.

[0152] The dps_extension_data_flag may have any value. Its presence and value do not affect the conformance of a decoder to the profiles specified in Annex A. Decoders conforming to this version of this specification shall ignore all dps_extension_data_flag syntax elements.

[0153] 6.1.2PTL Syntax and Semantics

[0154] 7.3.3.1 Common profile, layer and level syntax

[0155]

[0156]

[0157] 7.4.4.1 General profile, layer and level semantics

[0158] The profile_tier_level() syntax structure provides level information and optionally profile, tier, sub-profile and general constraint information.

[0159] When the VPS contains the profile_tier_level() syntax structure, OlsInScope is one or more OLSs specified by the VPS. When the SPS contains the profile_tier_level() syntax structure, OlsInScope is the OLS that only contains the lowest layer among the layers that reference the SPS, and the lowest layer is an independent layer. ...

[0160] 7. Example Implementation of the Disclosed Technology

[0161] Figure 1 A block diagram of an example video processing system 1000 is shown, which can implement various techniques of the present disclosure. Various embodiments may include some or all of the components of system 1000. System 1000 may include an input 1002 for receiving video content. The video content may be received in a raw or uncompressed format (e.g., 8 or 10-bit multi-component pixel values), or may be received in a compressed or encoded format. Input 1002 may represent a network interface, a peripheral bus interface, or a storage interface. Examples of network interfaces include wired interfaces such as Ethernet, passive optical networks (PONs), and wireless interfaces such as Wi-Fi or cellular interfaces.

[0162] System 1000 may include a codec component 1004 that may implement various codecs or encoding methods described in this document. Codec component 1004 may reduce the average bit rate of the video from input 1002 to the output of codec component 1004 to generate a codec representation of the video. Therefore, codec technology is sometimes referred to as video compression or video transcoding technology. The output of codec component 1004 may be stored or transmitted via a connected communication, as shown in component 1006. The bitstream (or codec) representation of the storage or transmission of the video received at input 1002 may be used by component 1008 to generate pixel values ​​or displayable video sent to display interface 1010. The process of generating user-visible video from a bitstream is sometimes referred to as video decompression. In addition, although some video processing operations are referred to as "codec" operations or tools, it should also be recognized that codec tools or operations are used for encoders, and corresponding decoding tools or operations that reverse the codec results will be performed by decoders.

[0163] Examples of peripheral bus interfaces or display interfaces may include Universal Serial Bus (USB) or High Definition Multimedia Interface (HDMI) or Display Port, etc. Examples of storage interfaces include SATA (Serial Advanced Technology Attachment), PCI, IDE interfaces, etc. The technology described in this document may be embodied in various electronic devices, such as mobile phones, laptop computers, smart phones, or other devices capable of performing digital data processing and / or video display.

[0164] Figure 2 2000 is a block diagram of a video processing device 2000. The device 2000 may be used to implement one or more methods described in this document. The device 2000 may be embodied in a smart phone, a tablet computer, a computer, an Internet of Things (IoT) receiver, etc. The device 2000 may include one or more processors 2002, one or more memories 2004, and video processing hardware 2006. The processor 2002 may be configured to implement one or more methods described in this document (e.g., Figure 6-Figure 7 ). Memory 2004 may be used to store data and code for implementing the methods and techniques described herein. In hardware circuits, video processing hardware 2006 may be used to implement some of the techniques described in this document.

[0165] Figure 3 1 is a block diagram illustrating an example video encoding and decoding system 100 that may utilize the techniques of the present disclosure. Figure 3As shown, the video codec system 100 may include a source device 110 and a target device 120. The source device 110 generates encoded video data, which may be referred to as a video encoding device. The target device 120 may decode the encoded video data generated by the source device 110, which may be referred to as a video decoding device. The source device 110 may include a video source 112, a video encoder 114, and an input / output (I / O) interface 116.

[0166] The video source 112 may include a source such as a video capture device, an interface for receiving video data from a video content provider, and / or a computer graphics system for generating video data, or a combination of these sources. The video data may include one or more pictures. The video encoder 114 encodes the video data from the video source 112 to generate a bit stream. The bit stream may include a bit sequence that forms a codec representation of the video data. The bit stream may include a codec picture and associated data. The codec picture is a codec representation of the picture. The associated data may include a sequence parameter set, a picture parameter set, and other grammatical structures. The I / O interface 116 may include a modulator / demodulator (modem) and / or a transmitter. The encoded video data may be directly sent to the target device 120 via the network 130a via the I / O interface 116. The encoded video data may also be stored on a storage medium / server 130b for access by the target device 120.

[0167] Target device 120 may include an I / O interface 126 , a video decoder 124 , and a display device 122 .

[0168] The I / O interface 126 may include a receiver and / or a modem. The I / O interface 126 may obtain encoded video data from the source device 110 or the storage medium / server 130b. The video decoder 124 may decode the encoded video data. The display device 122 may display the decoded video data to the user. The display device 122 may be integrated with the target device 120, or may be external to the target device 120, which is configured to interface with an external display device.

[0169] The video encoder 114 and the video decoder 124 may operate according to a video compression standard, such as the High Efficiency Video Codec (HEVC) standard, the Versatile Video Codec (VVC) standard, and other current and / or future standards.

[0170] Figure 4 To illustrate a block diagram of an example of a video encoder 200, the video encoder 200 may be as follows: Figure 3 The video encoder 114 in the system 100 is shown.

[0171] Video encoder 200 may be configured to perform any or all of the techniques of this disclosure. Figure 4In the example of , video encoder 200 includes multiple functional components. The techniques described in this disclosure can be shared among various components of video encoder 200. In some examples, a processor can be configured to perform any or all of the techniques described in this disclosure.

[0172] The functional components of the video encoder 200 may include a segmentation unit 201, a prediction unit 202 (which may include a mode selection unit 203, a motion estimation unit 204, a motion compensation unit 205 and an intra-frame prediction unit 206), a residual generation unit 207, a transform unit 208, a quantization unit 209, an inverse quantization unit 210, an inverse transform unit 211, a reconstruction unit 212, a buffer 213 and an entropy coding unit 214.

[0173] In other examples, the video encoder 200 may include more, fewer, or different functional components. In one example, the prediction unit 202 may include an intra block copy (IBC) unit. The IBC unit may perform prediction in an IBC mode, where at least one reference picture is a picture where the current video block is located.

[0174] Furthermore, some components such as the motion estimation unit 204 and the motion compensation unit 205 may be highly integrated but are shown for the purpose of explanation. Figure 4 In the example, they are represented separately.

[0175] The partitioning unit 201 may partition a picture into one or more video blocks. The video encoder 200 and the video decoder 300 may support various video block sizes.

[0176] The mode selection unit 203 may select one of the coding modes (intra or inter, e.g., based on the error result), and provide the resulting intra or inter coded block to the residual generation unit 207 to generate residual block data, and to the reconstruction unit 212 to reconstruct the coded block for use as a reference picture. In some examples, the mode selection unit 203 may select a combined intra and inter prediction (CIIP) mode, where the prediction is based on an inter prediction signal and an intra prediction signal. In the case of inter prediction, the mode selection unit 203 may also select the precision of the motion vector (e.g., sub-pixel or integer pixel precision) for the block.

[0177] In order to perform inter-frame prediction on the current video block, the motion estimation unit 204 may generate motion information of the current video block by comparing the current video block with one or more reference frames from the buffer 213. The motion compensation unit 205 may determine a predicted video block of the current video block based on the motion information of pictures other than the picture associated with the current video block from the buffer 213 and decoded samples.

[0178] Motion estimation unit 204 and motion compensation unit 205 may perform different operations on the current video block, eg, depending on whether the current video block is in an I slice, a P slice, or a B slice.

[0179] In some examples, the motion estimation unit 204 may perform unidirectional prediction for the current video block, and the motion estimation unit 204 may search the reference pictures of list 0 or list 1 to find the reference video block of the current video block. The motion estimation unit 204 may then generate a reference index indicating the reference picture containing the reference video block in list 0 or list 1 and a motion vector indicating the spatial displacement between the current video block and the reference video block. The motion estimation unit 204 may output the reference index, the prediction direction indicator, and the motion vector as the motion information of the current video block. The motion compensation unit 205 may generate a predicted video block of the current block based on the reference video block indicated by the motion information of the current video block.

[0180] In other examples, the motion estimation unit 204 may perform bidirectional prediction for the current video block, and the motion estimation unit 204 may search for a reference video block of the current video block in the reference pictures in list 0, and may also search for another reference video block of the current video block in the reference pictures in list 1. The motion estimation unit 204 may then generate a reference index indicating the reference pictures in list 0 and list 1, which include a reference video block and a motion vector indicating a spatial displacement between the reference video block and the current video block. The motion estimation unit 204 may output the reference index and the motion vector of the current video block as the motion information of the current video block. The motion compensation unit 205 may generate a predicted video block of the current video block based on the reference video block indicated by the motion information of the current video block.

[0181] In some examples, motion estimation unit 204 may output a complete set of motion information for use in a decoding process by a decoder.

[0182] In some examples, motion estimation unit 204 may not output a complete set of motion information for the current video. Instead, motion estimation unit 204 may reference motion information of another video block to signal motion information for the current video block. For example, motion estimation unit 204 may determine that the motion information of the current video block is sufficiently similar to the motion information of a neighboring video block.

[0183] In one example, motion estimation unit 204 may indicate a value in a syntax structure associated with the current video block that indicates to video decoder 300 that the current video block has the same motion information as another video block.

[0184] In another example, the motion estimation unit 204 may identify another video block and a motion vector difference (MVD) in a syntax structure associated with the current video block. The motion vector difference represents the difference between the motion vector of the current video block and the motion vector of the indicated video block. The video decoder 300 may use the motion vector of the indicated video block and the motion vector difference to determine the motion vector of the current video block.

[0185] As described above, the video encoder 200 may predictively signal motion vectors. Two examples of predictive signaling techniques that may be implemented by the video encoder 200 include advanced motion vector prediction (AMVP) and merge mode signaling.

[0186] The intra prediction unit 206 may perform intra prediction on the current video block. When the intra prediction unit 206 performs intra prediction on the current video block, the intra prediction unit 206 may generate prediction data for the current video block based on decoded samples of other video blocks in the same picture. The prediction data for the current video block may include a prediction video block and various syntax elements.

[0187] The residual generation unit 207 can generate residual data of the current video block by subtracting (e.g., indicated by a minus sign) the predicted video block of the current video block from the current video block. The residual data of the current video block may include a residual video block corresponding to different sample components of samples in the current video block.

[0188] In other examples, there may be no residual data for the current video block, such as in skip mode, and the residual generation unit 207 may not perform a subtraction operation.

[0189] Transform processing unit 208 may generate one or more transform coefficient video blocks for the current video block by applying one or more transforms to the residual video block associated with the current video block.

[0190] After transform processing unit 208 generates a transform coefficient video block associated with the current video block, quantization unit 209 may quantize the transform coefficient video block associated with the current video block based on one or more quantization parameter (QP) values ​​associated with the current video block.

[0191] The inverse quantization unit 210 and the inverse transform unit 211 may apply inverse quantization and inverse transform to the transform coefficient video block, respectively, to reconstruct a residual video block from the transform coefficient video block. The reconstruction unit 212 may add the reconstructed residual video block to corresponding samples from one or more prediction video blocks generated by the prediction unit 202 to generate a reconstructed video block associated with the current block for storage in the buffer 213.

[0192] After the reconstruction unit 212 reconstructs the video block, a loop filtering operation may be performed to reduce video block artifacts in the video block.

[0193] The entropy coding unit 214 may receive data from other functional components of the video encoder 200. When the entropy coding unit 214 receives the data, the entropy coding unit 214 may perform one or more entropy coding operations to generate entropy-coded data and output a bitstream including the entropy-coded data.

[0194] Figure 5 To illustrate an example block diagram of a video decoder 300, the video decoder 300 may be Figure 3 1. The video decoder 114 in the system 100 is shown in FIG.

[0195] Video decoder 300 may be configured to perform any or all of the techniques of this disclosure. Figure 5 In the example of , video decoder 300 includes multiple functional components. The techniques described in this disclosure can be shared between various components of video decoder 300. In some examples, a processor can be configured to perform any or all of the techniques described in this disclosure.

[0196] exist Figure 5 In the example of FIG. 3 , the video decoder 300 includes an entropy decoding unit 301, a motion compensation unit 302, an intra-frame prediction unit 303, an inverse quantization unit 304, an inverse transform unit 305, a reconstruction unit 306, and a buffer 307. In some examples, the video decoder 300 can perform operations generally related to the video encoder 200 (e.g., Figure 4 ) describes the encoding pass corresponding to the decoding pass.

[0197] The entropy decoding unit 301 may retrieve an encoded bitstream. The encoded bitstream may include entropy-encoded video data (e.g., encoded video data blocks). The entropy decoding unit 301 may decode the entropy-encoded video data, and based on the entropy-decoded video data, the motion compensation unit 302 may determine motion information including motion vectors, motion vector precision, reference picture list index, and other motion information. For example, the motion compensation unit 302 may determine the information by performing AMVP and merge modes.

[0198] The motion compensation unit 302 may generate a motion compensated block, possibly performing interpolation based on an interpolation filter. An identifier of the interpolation filter used with sub-pixel precision may be included in the syntax element.

[0199] Motion compensation unit 302 may calculate interpolation of sub-integer pixels of a reference block using interpolation filters used by video encoder 20 during encoding of the video block. Motion compensation unit 302 may determine the interpolation filters used by video encoder 200 according to received syntax information and use the interpolation filters to produce a prediction block.

[0200] The motion compensation unit 302 can use some syntax information to determine the size of blocks used to encode frames and / or slices of the encoded video sequence, partitioning information describing how each macroblock of the pictures of the encoded video sequence is partitioned, a mode indicating how each partition is encoded, one or more reference frames (and reference frame lists) for each inter-frame coded block, and other information for decoding the encoded video sequence.

[0201] The intra prediction unit 303 may form a prediction block from spatially neighboring blocks using, for example, an intra prediction mode received in the bitstream. The inverse quantization unit 303 inversely quantizes, i.e., dequantizes, the quantized video block coefficients provided in the bitstream and decoded by the entropy decoding unit 301. The inverse transform unit 303 applies an inverse transform.

[0202] The reconstruction unit 306 may add the residual block to the corresponding prediction block generated by the motion compensation unit 202 or the intra prediction unit 303 to form a decoded block. If necessary, a deblocking filter may also be applied to filter the decoded block to remove blocky artifacts. The decoded video block is then stored in a buffer 307, which provides reference blocks for subsequent motion compensation / intra prediction and also produces decoded video for presentation on a display device.

[0203] Figure 6 to Figure 7 An example method for implementing the above technical solution is shown. For example, Figures 1 to 5 Shown in.

[0204] Figure 6 A flow chart of an example method 600 of video processing is shown. The method 600 includes: at operation 610, performing conversion between a video and a bitstream of the video, the bitstream conforming to a format rule that specifies excluding sub-layer level information from a plurality of profile-layer-level (PTL) syntax structures included in a decoding parameter set of the bitstream.

[0205] Figure 7A flow chart of an example method 700 for video processing is shown. The method 700 includes: at operation 710, for conversion between a video and a bitstream of the video, determining that each output layer set (OLS) in a codec video sequence (CVS) in the bitstream conforms to at least one profile-layer-level (PTL) syntax structure included in a data structure associated with decoding parameter semantics in the bitstream.

[0206] The method 700 includes, at operation 720 , performing a conversion based on the determination.

[0207] The following is a list of preferred solutions for some embodiments.

[0208] 1. A video processing method, comprising: performing conversion between a video and a bitstream of the video, wherein the bitstream complies with a format rule, wherein the format rule specifies excluding sub-layer level information from a plurality of profile-layer-level (PTL) syntax structures included in a decoding parameter set of the bitstream, wherein each of the plurality of PTL syntax structures indicates a profile, layer, and level of the bitstream, and wherein the decoding parameter set includes decoding capability information.

[0209] 2. The method of solution 1, wherein the PTL syntax structure includes a single bit input parameter that controls the sub-layer level information.

[0210] 3. The method of solution 2, wherein for the decoding parameter set, a single bit is 0.

[0211] 4. The method of solution 2, wherein for a video parameter set (VPS) or a sequence parameter set (SPS) of a bitstream, a single bit is 1.

[0212] 5. The method as described in solution 1, wherein the PTL syntax structure includes a flag indicating that sub-layer level information is included.

[0213] 6. The method as described in solution 5, wherein the flag is sublayer_level_present_flag.

[0214] 7. A method as described in solution 5 or 6, wherein the flag is 0 for a PTL syntax structure in a DPS, a decoding parameter network abstraction layer (NAL) unit, or a SEI NAL unit including a decoding parameter supplemental enhancement information (SEI) message.

[0215] 8. A video processing method, comprising: for conversion between a video and a bitstream of the video, determining that each output layer set (OLS) in a codec video sequence (CVS) in the bitstream conforms to at least one profile-layer-level (PTL) syntax structure, which is included in a data structure associated with decoding parameter semantics in the bitstream; and performing conversion based on the determination, wherein the PTL syntax structure indicates the profile, layer and level of the bitstream.

[0216] 9. A method as described in solution 8, wherein the data structure is a decoding parameter set, a decoding parameter network abstraction layer (NAL) unit, or a SEI NAL unit including a decoding parameter supplemental enhancement information (SEI) message, and wherein the decoding parameter set includes decoding capability information.

[0217] 10. A method as described in any of solutions 1 to 9, wherein the conversion includes decoding the video from a bitstream.

[0218] 11. A method as described in any one of solutions 1 to 9, wherein the conversion includes encoding the video into a bitstream.

[0219] 12. A method for storing a bitstream representing a video to a computer-readable recording medium, comprising: generating a bitstream from a video according to any one or more of the methods described in Solutions 1 to 9; and writing the bitstream to a computer-readable recording medium.

[0220] 13. A video processing device, comprising a processor, wherein the processor is configured to implement any one or more of the methods described in solutions 1 to 12.

[0221] 14. A computer-readable medium having instructions stored thereon, which, when executed, cause a processor to implement the method as described in any one or more of solutions 1 to 12.

[0222] 15. A computer-readable medium storing a bitstream generated according to any one or more of solutions 1 to 12.

[0223] 16. A video processing device storing a bit stream, wherein the video processing device is configured to implement any one or more of the methods described in solutions 1 to 12.

[0224] Another list of preferred solutions for some embodiments is provided next.

[0225] P1. A video processing method, comprising: for a conversion between a current video segment of a video and a bitstream representation of the video, determining that each of a plurality of decoding parameter set (DPS) network abstraction layer (NAL) units including a syntax element having a first value has common content; and performing the conversion based on the determination.

[0226] P2. A video processing method, comprising: for a conversion between a current video segment of a video and a bitstream representation of the video, determining that a syntax element of each of a plurality of decoding parameter sets (DPS) network abstraction layer (NAL) units includes a common value; and performing the conversion based on the determination.

[0227] P3. A method as described in solution P1 or P2, wherein the syntax element in the bitstream representation is dps_decoding_parameter_set_id.

[0228] P4. A video processing method, comprising: for a conversion between a current video segment of a video and a bitstream representation of the video, determining that each of a plurality of decoding parameter set (DPS) network abstraction layer (NAL) units includes common content; and performing the conversion based on the determination.

[0229] P5. A method as described in any of solutions P1 to P4, wherein a decoding parameter set (DPS) is applied to the entire bitstream representation.

[0230] P6. A video processing method, comprising: for a conversion between a current video segment of a video and a bitstream representation of the video, making a decision to exclude a first syntax element from a decoding parameter set (DPS) in the bitstream representation and thereby excluding a second syntax element from a sequence parameter set (SPS) in the bitstream representation; and performing the conversion based on the decision.

[0231] P7. The method as described in solution P6, wherein the first syntax element and the second syntax element are dps_decoding_parameter_set_id and sps_decoding_parameter_set_id respectively.

[0232] P8. A method as described in solution P6 or P7, wherein DPS is called a decoding parameter network abstraction layer (NAL) unit.

[0233] P9. A method as described in solution P8, wherein each decoding parameter NAL unit in the bitstream representation includes common content.

[0234] P10. A video processing method, comprising: for a conversion between a current video segment of a video and a bitstream representation of the video, configuring the bitstream representation to include a supplemental enhancement information (SEI) message, the SEI message including information associated with a decoding parameter; determining that an SEI network abstraction layer (NAL) unit including the SEI message does not include other SEI messages; and performing the conversion using the SEI NAL unit.

[0235] P11. The method of solution P10, wherein each of the plurality of SEI messages including information associated with decoding parameters includes common content.

[0236] P12. A video processing method, comprising: for a bitstream representation of a video including a decoding parameter set (DPS) network abstraction layer (NAL) unit, determining that the DPS NAL unit is in a first access unit (AU) of the bitstream representation, wherein the first AU is located at the beginning of the bitstream representation; and based on the determination, performing conversion between a current video segment of the video and the bitstream representation.

[0237] P13. The method of solution P12, wherein the DPS NAL unit is in a second AU, the second AU comprising at least one codec slice NAL having a nal_unit_type within a predetermined range.

[0238] P14. A method as described in solution P13, wherein the predetermined range is from IDR_W_RADL to GDR_NUT.

[0239] P15. A method as described in solution P13, wherein the predetermined range is from IDR_W_RADL to RSV_IRAP_12.

[0240] P16. A video processing method, comprising: for conversion between a current video segment of a video and a bitstream representation of the video, determining that a profile tier layer (PTL) syntax structure included in a decoding parameter set (DPS) in the bitstream representation does not include sub-layer level information; and performing conversion based on the determination.

[0241] P17. A method as described in solution P16, wherein the determination is based on a single bit input parameter in the PTL syntax structure.

[0242] P18. A method as described in solution P17, wherein for DPS, a single bit is 0.

[0243] P19. A method as described in solution P17, wherein for a video parameter set (VPS) and a sequence parameter set (SPS) in the bitstream representation, a single bit is 1.

[0244] P20. A video processing method, comprising: for conversion between a current video segment of a video and a bitstream representation of the video, determining that each output layer set (OLS) in a codec video sequence (CVS) in the bitstream representation conforms to at least one profile layer (PTL) syntax structure included in a decoding parameter set (DPS) in the bitstream representation; and performing conversion based on the determination.

[0245] P21. A method as described in any of solutions P1 to P20, wherein the conversion generates the current video fragment from a bitstream representation.

[0246] P22. A method as described in any of solutions P1 to P20, wherein the conversion generates a bitstream representation from the current video fragment.

[0247] P23. A method as described in any one of solutions P1 to P22, wherein the current video fragment is a current strip, a current block, a current slice or a current sub-picture.

[0248] P24. A video processing device, comprising a processor, wherein the processor is configured to implement the method described in any one or more of solutions P1 to P23.

[0249] P25. A computer-readable recording medium having recorded thereon a program including codes, the program being used for a processor to execute a method as described in any one of solutions P1 to P23.

[0250] P26. A computer program product stored on a non-transitory computer-readable medium, the computer program product comprising a program code for executing a method as described in any one of solutions P1 to P23.

[0251] In this document, the term "video processing" may refer to video encoding, video decoding, video compression, or video decompression. For example, a video compression algorithm may be applied during conversion from a pixel representation of a video to a corresponding bitstream, or vice versa. The bitstream for the current video block may, for example, correspond to bits that are co-located or distributed at different locations within the bitstream, as defined by the syntax. For example, a macroblock may be encoded based on error residual values ​​from a transform and a codec, and may also use bits in the header and other fields in the bitstream.

[0252] The disclosed and other solutions, examples, embodiments, modules and functional operations described in this document may be implemented in digital electronic circuits or computer software, firmware or hardware, including the structures disclosed in this document and their structural equivalents, or a combination of one or more thereof. The disclosed and other embodiments may be implemented as one or more computer program products, i.e., one or more computer program instruction modules encoded on a computer-readable medium, which are executed or controlled by a data processing device. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, a material composition that affects a machine-readable propagated signal, or a combination of one or more thereof. The term "data processing device" covers all devices, equipment and machines that process data, including, for example, a programmable processor, a computer or multiple processors or computers. In addition to hardware, the device may also include code that creates an execution environment for the computer program in question, for example, code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more thereof. A propagated signal is an artificially generated signal, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information for transmission to a suitable receiver device.

[0253] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language (including compiled or interpreted languages) and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or portions of code). A computer program may be deployed to execute on one computer or on multiple computers located at one location or distributed over multiple locations and interconnected by a communications network.

[0254] The processes and logic flows described in this document may be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows may also be performed by, and may also be implemented as, special purpose logic circuits, such as FPGAs (field programmable gate arrays) or ASICs (application specific integrated circuits).

[0255] Processors suitable for executing computer programs include general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory, or both. The basic elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include or be operatively coupled to one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, to receive data from them, or to transfer data to one or more mass storage devices, or both. However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD ROM and DVD-ROM disks. The processor and memory may be supplemented by or incorporated into a dedicated logic circuit.

[0256] Although this patent document contains many details, these details should not be interpreted as limitations on any invention or the scope of protection that may be claimed, but rather as descriptions of features that may be specific to a particular embodiment of a particular invention. Certain features described in this patent document in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although the features may be described above as working in certain combinations and even initially claimed as such, in some cases one or more features in the claimed combination may be excluded from the combination, and the claimed combination may involve a sub-combination or a variant of a sub-combination.

[0257] Similarly, although operations are depicted in a particular order in the drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a continuous order, or that all of the operations shown be performed to achieve the desired effect. In addition, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0258] Only a few implementations and examples are described, and other implementations, enhancements, and variations may be made based on what is described and shown in this patent document.

Claims

1. A video processing method, comprising: performing conversion between videos and bitstreams of said videos, wherein the bitstream includes a decoding capability information syntax structure, wherein the decoding capability information syntax structure comprises a plurality of profile-layer-level (PTL) syntax structures, wherein each of the plurality of PTL syntax structures indicates a profile, a layer and a level of the bitstream, wherein the bit stream complies with the format rules, The format rule specifies that sub-layer level information is excluded from the plurality of PTL syntax structures included in the decoding capability information syntax structure of the bitstream.

2. The method according to claim 1, wherein: The plurality of PTL syntax structures are included in a raw byte sequence payload of a Network Abstraction Layer (NAL) unit including decoding capability information.

3. The method according to claim 2, wherein: The PTL syntax structure includes a flag indicating inclusion or exclusion of the sub-layer level information.

4. The method according to claim 3, wherein: For the PTL syntax structure included in the raw byte sequence payload of the NAL unit including the decoding capability information, the flag is 0.

5. The method according to claim 1, wherein: Each output layer set (OLS) in a codec video sequence (CVS) in the bitstream conforms to at least one of the plurality of PTL syntax structures.

6. The method according to claim 1, wherein: The converting includes decoding the video from the bitstream.

7. The method according to claim 1, wherein: The converting includes encoding the video into the bitstream.

8. A video data processing apparatus comprising a processor and a non-transitory memory having instructions thereon, wherein: The instructions, when executed by the processor, cause the processor to: performing conversion between videos and bitstreams of said videos, wherein the bitstream includes a decoding capability information syntax structure, wherein the decoding capability information syntax structure comprises a plurality of profile-layer-level (PTL) syntax structures, wherein each of the plurality of PTL syntax structures indicates a profile, a layer and a level of the bitstream, wherein the bit stream complies with the format rules, The format rule specifies that sub-layer level information is excluded from the plurality of PTL syntax structures included in the decoding capability information syntax structure of the bitstream.

9. The device according to claim 8, wherein: The plurality of PTL syntax structures are included in a raw byte sequence payload of a Network Abstraction Layer (NAL) unit including decoding capability information.

10. The device according to claim 9, wherein: The PTL syntax structure includes a flag indicating inclusion or exclusion of the sub-layer level information.

11. The device according to claim 10, wherein: For the PTL syntax structure included in the raw byte sequence payload of the NAL unit including the decoding capability information, the flag is 0.

12. The device according to claim 8, wherein: Each output layer set (OLS) in a codec video sequence (CVS) in the bitstream conforms to at least one of the plurality of PTL syntax structures.

13. A non-transitory computer-readable storage medium having stored therein instructions that cause a processor to: performing conversion between videos and bitstreams of said videos, wherein the bitstream includes a decoding capability information syntax structure, wherein the decoding capability information syntax structure comprises a plurality of profile-layer-level (PTL) syntax structures, wherein each of the plurality of PTL syntax structures indicates a profile, a layer and a level of the bitstream, in, The bitstream complies with the format rules, The format rule specifies that sub-layer level information is excluded from the plurality of PTL syntax structures included in the decoding capability information syntax structure of the bitstream.

14. The non-transitory computer-readable storage medium of claim 13, wherein: The plurality of PTL syntax structures are included in a raw byte sequence payload of a Network Abstraction Layer (NAL) unit including decoding capability information.

15. The non-transitory computer-readable storage medium of claim 14, wherein: The PTL syntax structure includes a flag indicating inclusion or exclusion of the sub-layer level information.

16. The non-transitory computer-readable storage medium of claim 15, wherein: For the PTL syntax structure included in the raw byte sequence payload of the NAL unit including the decoding capability information, the flag is 0.

17. A non-transitory computer-readable recording medium storing a bit stream of a video generated by a method executed by a video processing device, wherein: The method comprises: generating the bitstream of the video, wherein the bitstream includes a decoding capability information syntax structure, wherein the decoding capability information syntax structure comprises a plurality of profile-layer-level (PTL) syntax structures, wherein each of the plurality of PTL syntax structures indicates a profile, a layer and a level of the bitstream, wherein the bit stream complies with the format rules, The format rule specifies that sub-layer level information is excluded from the plurality of PTL syntax structures included in the decoding capability information syntax structure of the bitstream.

18. The non-transitory computer-readable recording medium according to claim 17, wherein: The plurality of PTL syntax structures are included in a raw byte sequence payload of a Network Abstraction Layer (NAL) unit including decoding capability information.

19. The non-transitory computer-readable recording medium according to claim 18, wherein: The PTL syntax structure includes a flag indicating inclusion or exclusion of the sub-layer level information.

20. The non-transitory computer-readable recording medium according to claim 19, wherein For the PTL syntax structure included in the raw byte sequence payload of the NAL unit including the decoding capability information, the flag is 0.

21. A method for storing a bit stream of a video, comprising: generating the bitstream of the video, and storing the bitstream in a non-transitory computer-readable storage medium, wherein the bitstream includes a decoding capability information syntax structure, wherein the decoding capability information syntax structure comprises a plurality of profile-layer-level (PTL) syntax structures, wherein each of the plurality of PTL syntax structures indicates a profile, a layer and a level of the bitstream, wherein the bit stream complies with the format rules, The format rule specifies that sub-layer level information is excluded from the plurality of PTL syntax structures included in the decoding capability information syntax structure of the bitstream.

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