Single event upset cross section test method and device, electronic equipment and storage medium

Abstract

The application discloses a single event upset cross section test method and device, electronic equipment and storage medium, which are applied to three-dimensional integrated static random access memory (SRAM). The method comprises the following steps: obtaining a structure model of a target SRAM, wherein the structure model comprises a plurality of stacked layers; performing particle irradiation simulation on the structure model to obtain the energy deposited by incident particles in each stacked layer of the structure model and the particle ionization radius, wherein the particle ionization radius is the radius of a track generated when the particles are incident on each stacked layer; determining the size of a sensitive region of each stacked layer; obtaining a target SRAM simulation model according to the structure model of the target SRAM and the size of the sensitive region of each stacked layer; performing particle irradiation simulation on the target SRAM simulation model to determine the number i of flipped bits of the target SRAM under particle irradiation and the number of i-bit flip events, and obtaining the size of a single event upset cross section of the target SRAM based on the number i of flipped bits and the number of i-bit flip events.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a single event upset cross section test method and device, an electronic device and a storage medium. BACKGROUND

[0002] In the past few decades, the world integrated circuit industry has been developing rapidly under the guidance of Moore's Law. However, when the process feature size develops to the deep submicron era, the way of improving performance by further reducing the feature size and the line width of the interconnection line of the integrated circuit will be greatly limited by the CMOS (Complementary Metal Oxide Semiconductor) device preparation process and the physical properties of the material. And the balance between the improvement of device performance and the reduction of size and the preparation cost is also gradually broken, and the traditional Moore's Law has been difficult to continue to develop. With the continuous development of technology, multiple chips are integrated to obtain a three-dimensional packaged integrated circuit, which greatly improves the transistor density on a unit chip area, shortens the wire length, reduces signal delay, loss, and thermal stress of the chip, and also realizes the integration of heterogeneous materials, technologies, and functional elements, and improves the chip functionality.

[0003] However, due to the complex radiation environment in space, among many radiation effects, single event effect is the most common radiation effect that induces abnormality and failure of space devices. Single event upset (SEU) effect refers to that a single high-energy charged particle is incident to a semiconductor device and interacts with it to deposit electric charges, and when the device sensitive area collects enough electric charges, the logic state of the device will change. The sensitivity of the device to the single event upset effect is generally represented by the single event upset cross section, which refers to the area of the region where the device will have a soft error under the bombardment of a high-energy particle with a certain linear energy transfer (LET) value. During the bombardment of the chip, the LET of the particle will change with the incident depth. When studying the single event effect of a planar integrated circuit, we consider that the LET value of the particle is constant when it passes through the chip because the thickness of the planar integrated circuit is relatively thin. However, the three-dimensional integrated circuit is relatively thick, and the ion may have different LET values in each sensitive area, and the particle track may also change greatly.

[0004] Therefore, the existing technology also has the problem of inaccurate test regarding the single event upset cross section test method of the three-dimensional integrated SRAM. SUMMARY

[0005] The embodiment of the application provides a single event upset cross section test method, a device, an electronic equipment and a storage medium, so that the size of the single event upset cross section of a three-dimensional integrated SRAM can be more accurately tested, and the radiation characteristics of the three-dimensional integrated SRAM are facilitated to be understood, and the anti-radiation reinforcement of the three-dimensional integrated SRAM is realized.

[0006] In a first aspect, an embodiment of the application provides the following technical scheme:

[0007] A single event upset cross section test method is applied to a three-dimensional integrated static random access memory (SRAM), and the method comprises the following steps:

[0008] A structure model of a target SRAM is acquired, the structure model comprises a plurality of stacked layers; particle irradiation simulation is performed on the structure model, so that the energy deposited by incident particles in each stacked layer of the structure model and a particle ionization radius are obtained, wherein the particle ionization radius is the radius of a track generated when the particles are incident on each stacked layer; the size of a sensitive region of each stacked layer is determined based on the energy deposited by the incident particles and the particle ionization radius; a target SRAM simulation model is obtained according to the structure model of the target SRAM and the size of the sensitive region of each stacked layer; particle irradiation simulation is performed on the target SRAM simulation model, so that the number i of upset bits of the target SRAM under particle irradiation and the number of events of i-bit upset are determined, and the size of the single event upset cross section of the target SRAM is obtained based on the number i of upset bits and the number of events of i-bit upset.

[0009] Preferably, the target SRAM is an SRAM integrated based on a through silicon via (TSV) adapter plate technology.

[0010] Preferably, the size of the single event upset cross section of the target SRAM is obtained based on the number i of upset bits and the number of events of i-bit upset, and the size of the single event upset cross section of the target SRAM is obtained based on the number i of upset bits and the number of events of i-bit upset, which comprises the following steps: acquiring the storage capacity and the number of stacked layers of the target SRAM; obtaining the total number of upset bits based on the number i of upset bits and the number of events of i-bit upset; acquiring the particle flux used for irradiation simulation on the target SRAM simulation model; and obtaining the size of the single event upset cross section of the target SRAM based on the total number of upset bits, the number of stacked layers, the storage capacity and the particle flux.

[0011] Preferably, the structure model of the target SRAM is acquired by the following steps: controlling a scanning electron microscope to scan the target SRAM to obtain all characteristic information of the target SRAM, wherein the characteristic information comprises material information and thickness information; and establishing the structure model of the target SRAM based on all the characteristic information of the target SRAM.

[0012] Preferably, the particle irradiation simulation on the structure model is performed to obtain the energy deposited by incident particles in each stack layer in the structure model and the particle ionization radius, comprising: based on the target SRAM, dividing a plurality of stack layers contained in the structure model, and dividing each stack layer into a plurality of regions; determining a simulation region based on one of the regions, performing particle irradiation simulation on the simulation region, so that a simulation particle is incident from a surface of the simulation region, and the energy deposited by the incident particle in each stack layer and the particle ionization radius are obtained.

[0013] Preferably, the particle irradiation simulation on the simulation region based on one of the regions comprises: selecting one of the regions as a target region; determining a first simulation region and a second simulation region in the target region, wherein the first simulation region is located in a region corresponding to a through silicon via, and the second simulation region is located in a region not corresponding to a through silicon via; and performing particle irradiation simulation on the first simulation region and the second simulation region respectively to obtain the energy deposited by incident particles in each stack layer in the structure model and the particle ionization radius.

[0014] Preferably, the particle irradiation simulation on the target SRAM simulation model is performed to determine the number i of flipped bits of the target SRAM under particle irradiation and the number of i-bit flip events, and based on the number i of flipped bits and the number of i-bit flip events, the single event upset cross section size of the target SRAM is obtained, comprising: based on the first target SRAM simulation model, performing particle irradiation simulation to determine the first number i1 of flipped bits of the first target SRAM under particle irradiation and the first number of i1-bit flip events, wherein the first target SRAM simulation model is constructed based on the particle irradiation simulation result of the first simulation region;

[0015] based on the second target SRAM simulation model, performing particle irradiation simulation to determine the second number i2 of flipped bits of the second target SRAM under particle irradiation and the second number of i2-bit flip events, wherein the second target SRAM simulation model is constructed based on the particle irradiation simulation result of the second simulation region;

[0016] based on the first number i1 of flipped bits, the first number of i1-bit flip events, the second number i2 of flipped bits, the second number of i2-bit flip events, and the area ratio between the first simulation region and the second simulation region, the single event upset cross section size of the target SRAM is determined.

[0017] In a second aspect, an embodiment of the present application provides the following technical solutions:

[0018] A single event upset cross section testing device applied to a three-dimensional integrated static random access memory (SRAM), the device comprising:

[0019] An acquisition module configured to acquire a structure model of a target SRAM, the structure model comprising a plurality of stacked layers;

[0020] A first simulation module configured to perform particle irradiation simulation on the structure model to obtain energy deposited by incident particles in each stacked layer of the structure model and a particle ionization radius, wherein the particle ionization radius is a radius of a track generated when the particles are incident on each stacked layer;

[0021] A second simulation module configured to determine a sensitive region size of each stacked layer based on the energy deposited by the incident particles in each stacked layer and the particle ionization radius;

[0022] A simulation model establishment module configured to obtain a target SRAM simulation model according to the structure model of the target SRAM and the sensitive region size of each stacked layer;

[0023] A third simulation module configured to perform particle irradiation simulation on the target SRAM simulation model to determine a number of flipped bits i of the target SRAM under particle irradiation and a number of events of i-bit flipping, and obtain a single event upset cross section size of the target SRAM based on the number of flipped bits i and the number of events of i-bit flipping.

[0024] In a third aspect, an embodiment of the present application provides the following technical scheme:

[0025] An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the program: acquiring a structure model of a target SRAM, the structure model comprising a plurality of stacked layers; performing particle irradiation simulation on the structure model to obtain energy deposited by incident particles in each stacked layer of the structure model and a particle ionization radius, wherein the particle ionization radius is a radius of a track generated when the particles are incident on each stacked layer; determining a sensitive region size of each stacked layer based on the energy deposited by the incident particles in each stacked layer and the particle ionization radius; obtaining a target SRAM simulation model according to the structure model of the target SRAM and the sensitive region size of each stacked layer; performing particle irradiation simulation on the target SRAM simulation model to determine a number of flipped bits i of the target SRAM under particle irradiation and a number of events of i-bit flipping, and obtaining a single event upset cross section size of the target SRAM based on the number of flipped bits i and the number of events of i-bit flipping.

[0026] The one or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0027] The single event upset cross section testing method provided by the embodiment of the present application can fully consider the different sensitivities of each stack layer in the target SRAM and the interaction between the stack layers. The method can more accurately test the single event upset cross section size in the three-dimensional integrated SRAM, thereby facilitating the understanding of the radiation characteristics of the three-dimensional integrated SRAM and realizing the anti-radiation reinforcement of the three-dimensional integrated SRAM. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0029] Figure 1 The flow chart of the single event upset cross section testing method provided by the embodiment of the present application;

[0030] Figure 2 The structural schematic diagram of an exemplary target SRAM provided by the embodiment of the present application;

[0031] Figure 3 The stack layer simulation area schematic diagram of an exemplary target SRAM provided by the embodiment of the present application;

[0032] Figure 4 The simulation longitudinal section schematic diagram of the stack layer of the target SRAM provided by the embodiment of the present application;

[0033] Figure 5 The structural schematic diagram of the single event upset cross section testing device provided by the embodiment of the present application;

[0034] Figure 6 The structural schematic diagram of the electronic device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0035] The present application inventors have long studied the single event upset cross section test problem in three-dimensional integrated static random access memory (SRAM). The existing single event upset cross section test method mainly calculates the single event upset cross section of each stack layer of the three-dimensional integrated SRAM separately, and regards the sensitive region size of each stack layer SRAM cell as the same.

[0036] However, it is found through research that the LET and particle track size of particles in each stack layer are different due to different incident depths, and the three-dimensional integrated SRAM includes materials connecting chips, and different materials greatly affect the linear energy transfer (LET) and particle track size of particles in each stack layer, resulting in that the sensitive region size of each stack layer SRAM cell is not the same. If it is assumed that the sensitive region size of each stack layer SRAM cell is the same, it will greatly affect the single event upset cross section test of the three-dimensional integrated SRAM. And the single event upset cross section of each stack layer of the three-dimensional integrated SRAM is calculated separately, which will ignore the correlation between the stack layers, and also affect the single event upset cross section test of the three-dimensional integrated SRAM.

[0037] The embodiments of the present application can more accurately test the single event upset cross section size in the three-dimensional integrated SRAM, thereby facilitating the understanding of the radiation characteristics of the three-dimensional integrated SRAM, and realizing the anti-radiation reinforcement of the three-dimensional integrated SRAM, by providing a single event upset cross section test method, device, electronic equipment and storage medium.

[0038] The technical solutions of the embodiments of the present application are to solve the above technical problems, and the general idea is as follows:

[0039] A single event upset cross section test method, device, electronic equipment and storage medium are applied to a three-dimensional integrated static random access memory (SRAM), and the method comprises: obtaining a structure model of a target SRAM, the structure model comprising a plurality of stack layers; performing particle irradiation simulation on the structure model to obtain the energy deposited by incident particles in each stack layer of the structure model and the particle ionization radius, wherein the particle ionization radius is the radius of the track generated when the particles are incident to each stack layer; determining the sensitive region size of each stack layer based on the energy deposited by each stack layer and the particle ionization radius; obtaining a target SRAM simulation model according to the structure model of the target SRAM and the sensitive region size of each stack layer; performing particle irradiation simulation on the target SRAM simulation model to determine the number i of upset bits of the target SRAM under particle irradiation and the number of events of i-bit upset, and obtaining the single event upset cross section size of the target SRAM based on the number i of upset bits and the number of events of i-bit upset.

[0040] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0041] Firstly, embodiments of the present invention provide a method for testing single-particle flip-off cross-sections. Specifically, as follows: Figure 1 As shown, the method includes the following steps S101 to S105.

[0042] Step S101: Obtain the structural model of the target SRAM, which includes multiple stacked layers.

[0043] It should be noted that the target SRAM refers to a three-dimensional integrated SRAM used for single-event flip-flop (SIF) cross-sectional testing. In one application scenario, the target SRAM provided in this embodiment can be integrated based on through-silicon via (TSV) adapter technology. This TSV adapter technology enables multiple chips to be interconnected laterally and vertically through the adapter, thereby achieving three-dimensional integration. Of course, other technologies can also be used to integrate the chips, which will not be discussed here.

[0044] like Figure 2 The diagram shown is a schematic representation of an exemplary target SRAM provided in this embodiment. The target SRAM includes four stacked layers, each of which includes two SRAMs 201, a cover layer 202, and an adapter board 203. The adapter board 203 is provided with multiple TSVs 204. The cover layer 202 has lines connecting the chips distributed on it.

[0045] In one optional embodiment, the target SRAM can be scanned using a scanning electron microscope to obtain all its feature information. Then, based on this feature information, a structural model of the target SRAM is established. The feature information may include information such as the material and thickness of each layer in the target SRAM.

[0046] Specifically, the target SRAM's structural model includes multiple stacked layers, each containing an adapter board and multiple SRAMs, with each SRAM containing multiple SRAM cells. Each SRAM cell is used to store 1 bit of data.

[0047] Step S102: Perform particle irradiation simulation on the structural model to obtain the energy deposited by the incident particles in each stacked layer of the structural model and the particle ionization radius, where the particle ionization radius is the radius of the trace generated when the particle is incident on each stacked layer.

[0048] Specifically, the particle ionization radius refers to the radius of a track generated by a particle with a certain energy incident into a target SRAM, directly interacting with the outer electrons of the atomic nucleus of the target SRAM material, and generating ionization. The radius of the track generated by the particle incident into each stack layer is the particle ionization radius. For example, it can be assumed that the corresponding track after the particle incident is a cylinder, and the particle ionization radius is the radius of the cylinder. In addition, the type of particle here can be selected in multiple ways, such as ions, for example, Xe ions, Kr ions, Fe ions, Ar ions, Ne ions, N ions, and the like.

[0049] In an optional embodiment, since the LET and the particle track size of the particle in each stack layer are different due to different incident depths, in order to accurately obtain the LET and the particle track size of each stack layer, the structure model can be divided into multiple stack layers. By vertically incident a large number of particles from the surface of the structure model, Monte Carlo simulation is performed for each stack layer of the structure model, that is, the probability of a specific event is estimated by a large number of random experiments, and the device parameter variation simulation is performed for each stack layer, so as to obtain the energy deposited by the particle in each stack layer and the particle ionization radius. The Monte Carlo simulation can be realized by using reliable software tools for simulating the interaction between radiation particles and matter, for example, Geant4 and the like, and the specific software is not limited here.

[0050] Further, in order to realize fast simulation of the structure model, the multiple stack layers contained in the structure model can be divided based on the target SRAM, and each stack layer can be divided into multiple regions. A simulation region is determined based on one of the regions, and particle irradiation simulation is performed for the simulation region, so that the simulation particles are incident from the surface of the simulation region, and the energy deposited by the particle in each stack layer and the particle ionization radius are obtained.

[0051] In an application scenario, the two-dimensional planar SRAM array and the TSV array in the TSV adapter plate are regular array structures. In an optional embodiment, the SRAM array contained in each stack layer can be uniformly divided to obtain multiple divided regions. One of the regions is selected as a simulation region, and particle irradiation simulation is performed for the region. Each of the multiple divided regions can contain one SRAM cell or a region of multiple SRAM cells.

[0052] For example, as shown in FIG. 3A, the SRAM contained in each stack layer can be uniformly divided into 16 regions, so that the two-dimensional planar SRAM of each stack layer obtains 16 regions with the same area. One of the regions is selected as a simulation region, for example, the simulation region 301 in FIG. 3B. Particle irradiation simulation is performed for the region, and the energy deposited by the particle in each stack layer and the particle ionization radius are obtained. Figure 3 Figure 3 For example, as shown in FIG. 3A, the SRAM contained in each stack layer can be uniformly divided into 16 regions, so that the two-dimensional planar SRAM of each stack layer obtains 16 regions with the same area. One of the regions is selected as a simulation region, for example, the simulation region 301 in FIG. 3B. Particle irradiation simulation is performed for the region, and the energy deposited by the particle in each stack layer and the particle ionization radius are obtained.​

[0053] It should be noted that, due to the TSV adapter plate in the three-dimensional integrated SRAM, the different materials of the TSV layer in the TSV adapter plate will greatly affect the LET and particle ionization radius of particles in each stack layer, resulting in different sensitive area sizes of the SRAM unit in each stack layer. Therefore, in order to accurately obtain the sensitive area size of each stack layer in different regions, for determining the simulation region based on one of the regions, the particle irradiation simulation for the simulation region can further include: selecting one region as a target region from the plurality of regions; determining a first simulation region and a second simulation region in the target region, wherein the first simulation region is located in a region corresponding to the through silicon via, and the second simulation region is located in a region not corresponding to the through silicon via; and performing particle irradiation simulation on the first simulation region and the second simulation region respectively to obtain the energy deposited by the incident particles in each stack layer of the structure model and the particle ionization radius.

[0054] Specifically, in one application scenario, as shown in the target region shown in Figure 3 , a place in the region corresponding to the through silicon via is selected as the first simulation region 302, and particle irradiation simulation is performed to obtain the energy deposited by each stack layer and the particle ionization radius. And a place in the region not corresponding to the through silicon via is selected as the second simulation region 303, and particle irradiation simulation is performed to obtain the energy deposited by each stack layer and the particle ionization radius. Thus, the energy deposited by the region corresponding to the through silicon via in each stack layer and the energy deposited by the region not corresponding to the through silicon via in each stack layer are obtained.

[0055] Further, in order to more accurately obtain and model the particle track, when obtaining the energy deposited by each stack layer and the particle ionization radius, the sensitive area of each stack layer can be selected at intervals to obtain several regions, and then the particle ionization radius and LET value of particles in each region are calculated.

[0056] For example, Figure 4 shows a longitudinal sectional view of one stack layer, specifically showing the sensitive region 402 and other regions 401 arranged in layers. The sensitive region 402 of the stack layer can be cut transversely at intervals to select the first region 403, the second region 404 and the third region 405 as shown in Figure 4 , and the particle ionization radius and LET value of particles in each region are calculated respectively. Of course, as another optional embodiment, only one region can be selected for calculation to obtain the particle ionization radius and LET value of particles in the region, thereby obtaining the energy deposited by the particles in each stack layer and the particle ionization radius.

[0057] Step S103, based on the energy deposited by each stack layer and the particle ionization radius, the sensitive region size of each stack layer is determined.

[0058] Specifically, based on the obtained energy deposited by each stack layer and the particle ionization radius, as input information of simulation conditions, through the semiconductor process simulation and the single particle module of the device simulation tool (Technology Computer Aided Design, TCAD), the sensitive region size of the particles in each stack layer of the target SRAM, i.e. the soft error region size of each stack layer of the target SRAM, is obtained.

[0059] Further, in order to accurately obtain the sensitive region size of each stack layer, based on the energy deposited by the first simulation region in each stack layer and the particle ionization radius, and the energy deposited by the second simulation region and the particle ionization radius, as input information of simulation conditions, through the semiconductor process simulation and the single particle module of the TCAD, the sensitive region size of the particles in each stack layer of the target SRAM corresponding to the through silicon via region and the sensitive region size not corresponding to the through silicon via region are obtained.

[0060] Step S104, according to the structure model of the target SRAM and the sensitive region size of each stack layer, the target SRAM simulation model is obtained.

[0061] Specifically, the sensitive region model of the target SRAM can be established in combination with the sensitive region size and the structure framework contained in the target SRAM. Based on the structure model of the target SRAM and the sensitive region model, the final target SRAM modeling is realized through the modeling software such as Geant4, and the target SRAM simulation model is obtained.

[0062] Step S105, the particle irradiation simulation is performed on the target SRAM simulation model, the number of flipped bits i of the target SRAM under particle irradiation is determined, and the number of events of i-bit flipping is determined. Based on the number of flipped bits i and the number of events of i-bit flipping, the single particle flip cross section size of the target SRAM is obtained.

[0063] Specifically, in the particle irradiation simulation process of the target SRAM simulation model, the flip events of the sensitive area size of each stack layer are counted. It is assumed that the flip event involves i flip bits, and the number of flip events of i flip bits is counted. It can be understood that i is a positive integer, and the specific value range can be determined according to the actual application scenario, for example, there are 1-bit flip events, 2-bit flip events, and 3-bit flip events, and i can take 1 to 3. The flip bit number refers to the number of bits that cause soft errors due to particle impact on the target SRAM. The number of i-bit flip events refers to the number of events that cause the corresponding number of soft error bits. For example, if particle impact on the target SRAM causes 10 2-bit flip events, then when i is 2, the number of i-bit flip events is 10.

[0064] In an optional embodiment, the number of stack layers of the storage capacity of the target SRAM can be obtained, and then based on the flip bit number i and the number of i-bit flip events, the total flip bit number can be obtained. The particle flux of the particle irradiation simulation of the target SRAM simulation model is obtained. Based on the total flip bit number, the number of stack layers, the storage capacity, and the particle flux, the single event upset cross section size of the target SRAM is obtained.

[0065] Specifically, the basic structure information of the target SRAM such as the storage capacity and the number of stack layers of the target SRAM can be obtained through the structure model in the target SRAM simulation model. Then based on the sensitive area model contained in the target SRAM simulation model, the flip bit number i caused by the single event upset effect within the sensitive area size and the number of i-bit flip events are obtained. Based on the flip bit number i and the number of i-bit flip events, the total flip bit number occurring in the target SRAM is obtained. The particle flux obtained by the total number of incident particles divided by the area covered by the incident particles is obtained by irradiating the target SRAM simulation model. Thus, according to the relationship between the total flip bit number occurring in the target SRAM and the storage capacity, the number of stack layers, and the particle flux of the target SRAM, the single event upset cross section size of the target SRAM is obtained.

[0066] For example, the single event upset cross section size of the target SRAM can be obtained by the following formula:

[0067]

[0068] In the formula, σ SEU represents the single event upset cross section of the target SRAM, i represents the flip bit number of the flip event; N i-bit represents the number of i-bit flip events; N capacity represents the storage capacity of the target SRAM; k represents the number of stack layers of the target SRAM; and Φ represents the incident ion flux, wherein,

[0069]

[0070] N represents the total number of incident ions, and A represents the area covered by the incident ions.

[0071] In an optional embodiment, the target SRAM simulation model is simulated under particle irradiation to determine the number of flipped bits i of the target SRAM under particle irradiation and the number of events of i-bit flipping, and based on the number of flipped bits i and the number of events of i-bit flipping, the single-event upset cross section size of the target SRAM is obtained, and can further include:

[0072] The first target SRAM simulation model is simulated under particle irradiation to determine the first number of flipped bits i1 of the first target SRAM under particle irradiation and the first number of events of i1-bit flipping, wherein the first target SRAM simulation model is constructed based on the particle irradiation simulation result of the first simulation area; the second target SRAM simulation model is simulated under particle irradiation to determine the second number of flipped bits i2 of the second target SRAM under particle irradiation and the second number of events of i2-bit flipping, wherein the second target SRAM simulation model is constructed based on the particle irradiation simulation result of the second simulation area; and based on the first number of flipped bits i1, the first number of events, the second number of flipped bits i2, the second number of events, and the area ratio between the first simulation area and the second simulation area, the single-event upset cross section size of the target SRAM is determined.

[0073] The single event upset cross section of the target SRAM is obtained by calculating the single event upset cross section of the target SRAM according to the area proportion of the region corresponding to the through silicon via and the region not corresponding to the through silicon via in the target SRAM. Specifically, the total number of flipped bits under the first target SRAM simulation model (all regions corresponding to the through silicon via in the target SRAM) is obtained based on the first number of flipped bits i1 and the number of events of i1-bit flipping, and the total number of flipped bits under the second target SRAM simulation model (all regions not corresponding to the through silicon via in the target SRAM) is obtained based on the second number of flipped bits i2 and the number of events of i2-bit flipping. Based on the obtained total number of flipped bits, the known number of stacked layers, the storage capacity, and the particle flux, the single event upset cross section of the region corresponding to the through silicon via in the target SRAM and the single event upset cross section of the region not corresponding to the through silicon via in the target SRAM are obtained. Here, it is assumed that the area size of the region corresponding to the through silicon via in the target SRAM is σ1, and the area size of the region not corresponding to the through silicon via in the target SRAM is σ2, then the single event upset cross section of the target SRAM is the sum of the single event upset cross section under the first target SRAM simulation model multiplied by σ1 / (σ1+σ2) and the single event upset cross section under the second target SRAM simulation model multiplied by σ2 / (σ1+σ2).

[0074] For example, the single event upset cross section of the target SRAM can be obtained by the following formula:

[0075]

[0076] In the formula, σ1 represents the area size of the region corresponding to the through silicon via in the target SRAM; σ2 represents the area size of the region not corresponding to the through silicon via in the target SRAM; σ SEU represents the single event upset cross section of the target SRAM; i1 represents the first number of flipped bits of the flipping event; represents the number of events of i1-bit flipping; i2 represents the second number of flipped bits of the flipping event; represents the number of events of i2-bit flipping; N capacity represents the storage capacity of the target SRAM; k represents the number of stacked layers of the target SRAM; Φ represents the incident ion flux, wherein,

[0077]

[0078] N represents the total number of incident ions, and A represents the area covered by the incident ions.

[0079] In summary, the single event upset cross section test method provided by the embodiment of the application can more accurately test the single event upset cross section size of the three-dimensional integrated SRAM, thereby facilitating the understanding of the radiation characteristics of the three-dimensional integrated SRAM and achieving the radiation hardening of the three-dimensional integrated SRAM.

[0080] In a second aspect, based on the same inventive concept, the embodiment provides a single event upset cross section test device, as shown in the accompanying drawings, comprising: Figure 5

[0081] The acquisition module 501 is configured to acquire a structure model of the target SRAM, and the structure model comprises a plurality of stacked layers.

[0082] The first simulation module 502 is configured to perform particle irradiation simulation on the structure model to obtain the energy deposited by incident particles in each stacked layer of the structure model and the particle ionization radius, wherein the particle ionization radius is the radius of the track generated when the particles are incident on each stacked layer.

[0083] The second simulation module 503 is configured to determine the size of the sensitive region of each stacked layer based on the energy deposited by each stacked layer and the particle ionization radius.

[0084] The simulation model establishment module 504 is configured to obtain a target SRAM simulation model according to the structure model of the target SRAM and the size of the sensitive region of each stacked layer.

[0085] The third simulation module 505 is configured to perform particle irradiation simulation on the target SRAM simulation model to determine the number i of flipped bits of the target SRAM under particle irradiation and the number of i-bit flip events, and obtain the single event upset cross section size of the target SRAM based on the number i of flipped bits and the number of i-bit flip events.

[0086] As an optional embodiment, the third simulation module 505 specifically comprises:

[0087] The feature information acquisition sub-module is configured to acquire the storage capacity and the number of stacked layers of the target SRAM.

[0088] The total flip bit number determination sub-module is configured to obtain the total flip bit number based on the number i of flipped bits and the number of i-bit flip events.

[0089] The particle flux acquisition sub-module is configured to acquire the particle flux used for the irradiation simulation on the target SRAM simulation model.

[0090] The calculation sub-module is configured to obtain the single event upset cross section size of the target SRAM based on the total flip bit number, the number of stacked layers, the storage capacity, and the particle flux.

[0091] ​As an optional embodiment, the acquisition module 501 specifically comprises:

[0092] The scanning submodule is configured to control the scanning electron microscope to scan the target SRAM, and obtain all feature information of the target SRAM, wherein the feature information comprises material information and thickness information.

[0093] The structure model construction submodule is configured to establish a structure model of the target SRAM based on all feature information of the target SRAM.

[0094] As an optional embodiment, the first simulation module 502 specifically comprises:

[0095] The division submodule is configured to divide a plurality of stacked layers contained in the structure model based on the target SRAM, and divide each stacked layer into a plurality of regions.

[0096] The region simulation submodule is configured to determine a simulation region based on one of the regions, perform particle irradiation simulation on the simulation region, so that simulation particles are incident from a surface of the simulation region, and obtain energy deposited by each stacked layer and a particle ionization radius.

[0097] As an optional embodiment, the region simulation submodule is specifically configured to: select one region as a target region from the plurality of regions; determine a first simulation region and a second simulation region in the target region, wherein the first simulation region is located in a region corresponding to a through silicon via, and the second simulation region is located in a region not corresponding to the through silicon via; and perform particle irradiation simulation on the first simulation region and the second simulation region respectively, to obtain energy deposited by each stacked layer in the structure model and a particle ionization radius of incident particles.

[0098] As an optional embodiment, the third simulation module 505 further comprises:

[0099] The first determination submodule is configured to perform particle irradiation simulation based on the first target SRAM simulation model, to determine a first number i1 of flipped bits of the first target SRAM under particle irradiation, and a first number of events of i1-bit flipping, wherein the first target SRAM simulation model is constructed based on a particle irradiation simulation result of the first simulation region.

[0100] The second determination submodule is configured to perform particle irradiation simulation based on the second target SRAM simulation model, to determine a second number i2 of flipped bits of the second target SRAM under particle irradiation, and a second number of events of i2-bit flipping, wherein the second target SRAM simulation model is constructed based on a particle irradiation simulation result of the second simulation region.

[0101] The percentage calculation submodule determines the single-particle flip cross-section size of the target SRAM based on the first flip bit number i1, the first event number, the second flip bit number i2, the second event number, and the ratio of the area between the first simulation region and the second simulation region.

[0102] Each of these modules can be implemented using software code, in which case they can be stored in the memory of the control electronic device. Alternatively, each of these modules can be implemented using hardware, such as integrated circuit chips.

[0103] The single-particle flip-section testing device provided in this embodiment of the invention has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0104] Thirdly, based on the same inventive concept, such as Figure 6 As shown, this embodiment provides an electronic device 800, including one or more of the following components: a processing component 802, a memory 804, a power supply component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0105] Processing component 802 typically controls the overall operation of electronic device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the single-event rollover section testing method provided in the first aspect above. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

[0106] Memory 804 is configured to store various types of data to support the operation of electronic device 800. Examples of this data include instructions for any application or method operating on electronic device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0107] The power component 806 provides power to the various components of the electronic device 800. The power component 806 can include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the electronic device 800.

[0108] The multimedia component 808 includes a screen providing an output interface between the electronic device 800 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes the touch panel, the screen can be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense a touch, a slide, and a gesture on the touch panel. The touch sensor can not only sense a boundary of a touching or a sliding action, but also detect duration and pressure related to the touching or sliding action. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0109] The audio component 810 is configured to output and / or input an audio signal. For example, the audio component 810 includes a microphone (MIC) configured to receive an external audio signal when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting an audio signal.

[0110] The I / O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which can be a keypad, a click wheel, buttons, and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0111] The sensor component 814 includes one or more sensors for providing status assessments for various aspects of the electronic device 800. For example, the sensor component 814 can detect an open / closed position of the electronic device 800, relative positioning of components, such as a display and a keypad of the electronic device 800, a change in position of the electronic device 800 or a component of the electronic device 800, presence or absence of user contact with the electronic device 800, orientation or acceleration / deceleration / g-force and temperature of the electronic device 800. The sensor component 814 can include an optical sensor for detecting ambient light, a proximity sensor for detecting the presence of nearby objects without any physical touch, a CMOS or CCD image sensor for use in imaging applications, or an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor in some embodiments.

[0112] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a corresponding communication standard, such as WiFi, 2G, or 3G, or a combination thereof. In an example embodiment, the communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an example embodiment, the communication component 816 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) techniques, infrared data association (IrDA) techniques, ultra-wideband (UWB) techniques, Bluetooth (BT) techniques, and other techniques.

[0113] In an example embodiment, the electronic device 800 can be implemented using one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic components, for performing the above-described methods.

[0114] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, a system, or a computer program product. Accordingly, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) embodying computer-readable program code.

[0115] In a fourth aspect, based on the same inventive concept, the embodiments of the present application also provide a computer readable storage medium, having stored thereon a computer program, which, when executed by a processor, implements the steps of any of the embodiments of the single event latch-up cross section test method provided in the first aspect above.

[0116] The present application is described in reference to the flowchart and / or block diagrams of the method, apparatus (system) and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagrams, and the combination of flows and / or blocks in the flowchart and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus generate a means for implementing the functions specified in the flowchart and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 a module for performing the functions specified in one or more flows and / or blocks.

[0117] These computer program instructions can also be stored in a computer readable storage medium that can direct the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer readable storage medium produce a product including instruction modules, which implement the functions specified in the flowchart and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 a module for performing the functions specified in one or more flows and / or blocks.

[0118] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable data processing apparatus to produce a computer implemented process, so that the instructions executed on the computer or other programmable data processing apparatus provide a means for implementing the functions specified in the flowchart and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 a module for performing the functions specified in one or more flows and / or blocks.

[0119] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all the preferred embodiments and all the changes and modifications falling within the scope of the present application.

[0120] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for testing single-particle flip-over cross-sections, characterized in that, The method, applied to three-dimensional integrated static random access memory (SRAM), includes: Obtain the structural model of the target SRAM, the structural model including multiple stacked layers; Particle irradiation simulation was performed on the structural model to obtain the energy deposited by the incident particles in each stacked layer of the structural model and the particle ionization radius, wherein the particle ionization radius is the radius of the track generated when the particle is incident on each stacked layer; The size of the sensitive region of each stacked layer is determined based on the energy deposited in each stacked layer and the particle ionization radius. Based on the structural model of the target SRAM and the sensitive area size of each stacked layer, a simulation model of the target SRAM is obtained; The target SRAM simulation model is subjected to particle irradiation simulation to determine the number of flipped bits i in the target SRAM under particle irradiation and the number of events in which i-bit flips occur. Based on the number of flipped bits i and the number of events in which i-bit flips occur, the single-particle flip cross-section size of the target SRAM is obtained. The step of performing particle irradiation simulation on the structural model to obtain the energy deposited by incident particles in each stacked layer of the structural model and the particle ionization radius includes: dividing the multiple stacked layers contained in the structural model based on the target SRAM, and dividing each stacked layer into multiple regions; determining a simulation region based on one of the regions, and performing particle irradiation simulation on the simulation region, so that the simulated particles are incident from the surface of the simulation region, and obtaining the energy deposited by each stacked layer and the particle ionization radius. The step of determining a simulation region based on one of the regions and performing particle irradiation simulation on the simulation region includes: selecting one region from the plurality of regions as a target region; determining a first simulation region and a second simulation region in the target region, wherein the first simulation region is located in the region corresponding to a through-silicon via (TSV), and the second simulation region is located in the region without a corresponding TSV; performing particle irradiation simulation on the first simulation region and the second simulation region respectively to obtain the energy deposited by the incident particles in each stacked layer of the structural model and the particle ionization radius.

2. The method as described in claim 1, characterized in that, The target SRAM is an SRAM integrated based on through-silicon via (TSV) adapter board technology.

3. The method as described in claim 1, characterized in that, The method of obtaining the single-particle flip cross-section size of the target SRAM based on the number of flip bits i and the number of events in which i-bit flips occur includes: Obtain the storage capacity and stacking layer number of the target SRAM; The total number of flipped bits is obtained based on the number of flipped bits i and the number of events in which i-bit flips occur; Obtain the particle flux used in the irradiation simulation of the target SRAM simulation model; The single-particle flip cross-section size of the target SRAM is obtained based on the total number of flip bits, the number of stacked layers, the storage capacity, and the particle flux.

4. The method as described in claim 1, characterized in that, The process of obtaining the structural model of the target SRAM includes: The scanning electron microscope is controlled to scan the target SRAM to obtain all feature information of the target SRAM, including material information and thickness information. Based on all the feature information of the target SRAM, a structural model of the target SRAM is established.

5. The method as described in claim 1, characterized in that, The process involves performing particle irradiation simulation on the target SRAM simulation model to determine the number of flipped bits i in the target SRAM under particle irradiation, as well as the number of events resulting in i-bit flips. Based on the number of flipped bits i and the number of events resulting in i-bit flips, the single-particle flip cross-section size of the target SRAM is obtained, including: Particle irradiation simulation is performed based on the first target SRAM simulation model to determine the first flip bit i1 of the first target SRAM under particle irradiation and the number of first events in which i1 bit flips occur. The first target SRAM simulation model is constructed based on the particle irradiation simulation results of the first simulation region. Particle irradiation simulation was performed based on the second target SRAM simulation model to determine the second flip bit i2 of the second target SRAM under particle irradiation and the number of second events in which i2 bit flips occurred. The second target SRAM simulation model was constructed based on the particle irradiation simulation results of the second simulation region. The single-particle flip cross-section size of the target SRAM is determined based on the first flip bit number i1, the first number of events, the second flip bit number i2, the second number of events, and the ratio of the area between the first simulation region and the second simulation region.

6. A single-particle flip-over cross-section testing device, characterized in that, The device, applied to a three-dimensional integrated static random access memory (SRAM), comprises: An acquisition module is used to acquire the structural model of the target SRAM, the structural model including multiple stacked layers; The first simulation module is used to perform particle irradiation simulation on the structure model to obtain the energy deposited by the incident particle in each stacked layer of the structure model and the particle ionization radius, wherein the particle ionization radius is the radius of the track generated when the particle is incident on each stacked layer; The second simulation module is used to determine the size of the sensitive region of each stacked layer based on the energy deposited in each stacked layer and the particle ionization radius. The simulation model building module is used to obtain the simulation model of the target SRAM based on the structural model of the target SRAM and the sensitive area size of each stacked layer; The third simulation module is used to perform particle irradiation simulation on the target SRAM simulation model, determine the number of flipped bits i in the target SRAM under particle irradiation, and the number of events in which i-bit flips occur. Based on the number of flipped bits i and the number of events in which i-bit flips occur, the size of the single-particle flip cross section of the target SRAM is obtained. The first simulation module specifically includes: a partitioning submodule, used to partition the multiple stacked layers contained in the structural model based on the target SRAM, and to divide each stacked layer into multiple regions; and a region simulation submodule, used to determine a simulation region based on one of the regions, and to perform particle irradiation simulation on the simulation region, so that the simulated particles are incident from the surface of the simulation region, and to obtain the energy deposited in each stacked layer and the particle ionization radius. The region simulation submodule is specifically used for: selecting one region from the plurality of regions as the target region; determining a first simulation region and a second simulation region in the target region, wherein the first simulation region is located in the region corresponding to the through-silicon via, and the second simulation region is located in the region without a corresponding through-silicon via; performing particle irradiation simulation for the first simulation region and the second simulation region respectively, to obtain the energy deposited by the incident particles in each stacked layer in the structural model and the particle ionization radius.

7. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory being coupled to the processor, the memory storing instructions that, when executed by the processor, cause the electronic device to perform the method of any one of claims 1-5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method described in any one of claims 1-5.

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