Method and device for realizing physical interface of logic system design based on virtual interface

Abstract

The present disclosure provides a method and apparatus for implementing a physical interface of a logical system design based on a virtual interface. The method includes: determining whether a physical interface exists in a module of the logical system design, the physical interface including at least one physical signal; in response to the existence of the physical interface in the module, generating a virtual interface based on a description of the physical interface, the virtual interface including at least one variable corresponding to the physical signal; initializing the virtual interface to associate it with the physical interface; and simulating the logical system design based on the virtual interface.

Description

Technical Field

[0001] The present disclosure relates to the field of chip verification technology, and in particular to a method and device for implementing a physical interface of a logic system design based on a virtual interface. Background Art

[0002] During the logic system design process, the logic system design needs to be tested and verified. The logic system design being tested and verified can be called the device under test (DUT). As the complexity of the DUT increases, the connection and communication between the testbench and the design becomes more complex.

[0003] Currently, users use Verilog port descriptions to establish signal connections between testbenches and designs. To simplify inter-module communication, SystemVerilog introduces the concept of physical interfaces. Some simulator vendors implement physical interfaces based on cross-module references (XMRs). However, when simulating a design, the XMR processing module must add a processing interface as part of the physical interface processing logic, violating the single responsibility principle of the XMR processing module. Furthermore, the XMR processing module must store information such as interface member references in files during compilation and load (patch) it at runtime, increasing time consumption. Summary of the Invention

[0004] In view of this, the present disclosure proposes a method, device, and storage medium for implementing a physical interface of a logical system design based on a virtual interface.

[0005] In a first aspect of the present disclosure, a method for implementing a physical interface of a logic system design based on a virtual interface is provided, comprising: determining whether a physical interface exists in a module of the logic system design, the physical interface including at least one physical signal; in response to the existence of the physical interface in the module, generating a virtual interface according to a description of the physical interface, the virtual interface including at least one variable corresponding to the physical signal; initializing the virtual interface to associate the virtual interface with the physical interface; and simulating the logic system design based on the virtual interface.

[0006] In a second aspect of the present disclosure, a device is provided for implementing a physical interface designed for a logical system based on a virtual interface, comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device performs the method described in the first aspect.

[0007] According to a third aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, wherein the non-transitory computer-readable storage medium stores a set of instructions for an electronic device, where the set of instructions is used to enable the electronic device to execute the method according to the first aspect.

[0008] This disclosure provides a method and device for implementing the physical interface of a logical system design based on a virtual interface. By using virtual interfaces to connect modules, the interface processing module does not need to add a new processing interface when simulating the design using a simulation tool, thus adhering to the single responsibility principle of the design. The simulation tool also does not need to load information such as interface member references reserved during compilation, which improves the execution speed. Furthermore, the one-to-one correspondence between virtual interfaces and physical interfaces enables a certain degree of code reuse. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the present disclosure or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only for the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0010] Figure 1 A schematic structural diagram of an exemplary device according to an embodiment of the present disclosure is shown.

[0011] Figure 2 A schematic diagram of an exemplary simulation tool according to an embodiment of the present disclosure is shown.

[0012] Figure 3A A schematic diagram showing part of the code of an exemplary logic system design according to an embodiment of the present disclosure is shown.

[0013] Figure 3B A schematic diagram of an exemplary method for generating a mirror class definition according to an embodiment of the present disclosure is shown.

[0014] Figure 3C A schematic diagram of exemplary codes including a virtual interface according to an embodiment of the present disclosure is shown.

[0015] Figure 4 A schematic diagram showing exemplary codes of continuous assignment statements according to an embodiment of the present disclosure is shown.

[0016] Figure 5A A schematic diagram showing exemplary code including references to nested interface instances according to an embodiment of the present disclosure is shown.

[0017] Figure 5B A schematic diagram showing part of exemplary code of a virtual interface involving references to nested interface instances according to an embodiment of the present disclosure is shown.

[0018] Figure 6A A schematic diagram of an exemplary implementation method according to an embodiment of the present disclosure is shown.

[0019] Figure 6B A flowchart of an exemplary implementation method according to an embodiment of the present disclosure is shown.

[0020] Figure 6C A flowchart of an exemplary processing method for continuous assignment statements according to an embodiment of the present disclosure is shown.

[0021] Figure 6D A flowchart of an exemplary processing method involving references to nested interface instances according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0022] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0023] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0024] In logic system design, as the complexity of the design under test (DUT) increases, the communication between the testbench and the design becomes increasingly complex. Conventional technology often uses Verilog port descriptions to establish signal connections between the testbench and the design. This connection approach faces challenges such as the large number of connected signals and the susceptibility to errors. To address these issues, the SystemVerilog Language Reference Manual (LRM) introduces the concept of a physical interface. A physical interface encapsulates hardware port signals and related functionality, using a high-level abstraction approach to simplify the interconnection between modules.

[0025] As mentioned above, when simulating a design, the way of connecting modules using the physical interface implemented based on XMR will destroy the single responsibility principle of the design and increase the time consumption.

[0026] In view of the above problems, the present disclosure provides a method and device for implementing a physical interface designed for a logical system based on a virtual interface.

[0027] This disclosure provides a method and device for implementing the physical interface of a logical system design based on a virtual interface. By using virtual interfaces to connect modules, the interface processing module does not need to add a new processing interface when simulating the design using a simulation tool, thus adhering to the single responsibility principle of the design. The simulation tool also does not need to load information such as interface member references reserved during compilation, which improves the execution speed. Furthermore, the one-to-one correspondence between virtual interfaces and physical interfaces enables a certain degree of code reuse.

[0028] Figure 1 FIG. 1 is a schematic structural diagram of an exemplary device 100 according to an embodiment of the present disclosure.

[0029] Device 100 may be, for example, a host computer and may include a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Processor 102, memory 104, network interface 106, and peripheral interface 108 may be communicatively coupled to each other within device 100 via bus 110.

[0030] The processor 102 may be a central processing unit (CPU), an image processor, a neural network processor, a microcontroller, a programmable logic device, a digital signal processor, an application-specific integrated circuit (ASIC), or one or more integrated circuits. The processor 102 may be used to perform functions related to the technology described in this disclosure. In some embodiments, the processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0031] The memory 104 may be configured to store data (eg, instruction sets, computer code, intermediate data, etc.). Figure 1As shown, the stored data may include program instructions (e.g., program instructions for implementing the techniques of the present disclosure) and data to be processed (e.g., memory 104 may store temporary code generated by a compilation process). Processor 102 may also access the stored program instructions and data and execute the program instructions to operate on the data to be processed. Memory 104 may include non-transitory computer-readable storage media, such as volatile memory devices or non-volatile memory devices. In some embodiments, memory 104 may include random access memory (RAM), read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), flash memory, a memory stick, etc.

[0032] The network interface 106 can be configured to enable the device 100 to communicate with one or more other external devices via a network. The network can be any wired or wireless network capable of transmitting and / or receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near-field communication (NFC)), a cellular network, the Internet, or a combination thereof. It will be appreciated that the type of network is not limited to the specific examples above. In some embodiments, the network interface 106 can include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.

[0033] The peripheral interface 108 can be configured to connect the device 100 to one or more peripheral devices to enable information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touchpad, a touch screen, a microphone, and various sensors, and output devices such as a display, a speaker, a vibrator, and an indicator light.

[0034] The bus 110 may be configured to transmit information between various components of the device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), and may be, for example, an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0035] In some embodiments, in addition to Figure 1 In addition to the processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110 shown and described above, the device 100 may also include one or more other components required for normal operation and / or one or more other components required for implementing the solutions of the embodiments of the present disclosure. In some embodiments, the device 100 may not include Figure 1 One or more components shown in .

[0036] It should be noted that although the above-mentioned electronic device 100 architecture only shows the processor 102, memory 104, network interface 106, peripheral interface 108 and bus 110, in a specific implementation, the architecture of the electronic device 100 may also include other components necessary for normal operation. In addition, those skilled in the art will understand that the architecture of the electronic device 100 may also include only the components necessary to implement the embodiments of the present disclosure, and does not necessarily include all the components shown in the figure.

[0037] Figure 2 FIG. 2 is a schematic diagram of an exemplary simulation tool 200 according to an embodiment of the present disclosure. The simulation tool 200 may be a computer program running on the electronic device 100 .

[0038] In the field of chip design, a design is usually simulated using a simulation tool, such as the GalaxSim simulation tool produced by Xinhuazhang Technology Co., Ltd. Figure 2 The exemplary simulation tool 200 shown may include a compiler 210 and a simulator 220. The compiler 210 may receive source code 204 (e.g., a hardware description language such as VHDL, Verilog, SystemVerilog, etc.) and compile it into executable code 206 (e.g., machine code, assembly code, software code, etc.). The simulator 220 may perform simulation based on the executable code 206 and output simulation results 208. For example, the simulation tool 200 may output the simulation results 208 via Figure 1 The peripheral interface 108 outputs the data to an output device (eg, displayed on a display).

[0039] In some embodiments, after receiving the source code 204 , the simulation tool 200 detects the existence of a physical interface in the module description, and then generates a virtual interface corresponding to the physical interface according to the description of the physical interface.

[0040] Figure 3A A schematic diagram showing a portion of code of an exemplary logic system design 300 according to an embodiment of the present disclosure is shown.

[0041] In some embodiments, a logical system design 300 may include a definition 301 of a physical interface "bus_if," a definition 302 of a module "test," a definition 303 of a module "dut," and a definition 304 of a top-level module "top." The definition 301 of the physical interface "bus_if" may include physical signals req and gnt. The definition 302 of the module "test" may include a port declaration 3021 of the interface bus, as well as write and read operations 3022 for interface members. The definition 303 of the module "dut" may include a declaration 3031 of the interface bus. The definition 304 of the top-level module "top" may include instantiation declarations 3041 of two modules. The interface instance i0 is connected and exchanges data in a port manner.

[0042] In some embodiments, the virtual interface may be implemented by a mirror class.

[0043] Figure 3B A schematic diagram of an exemplary method 310 for generating image class definitions according to an embodiment of the present disclosure is shown.

[0044] In some embodiments, the simulation tool 200 can generate a mirror class definition 340 for a physical interface 320. The attributes 340a, 340b, and 340n of the mirror class definition 340 can correspond one-to-one with the variable members 320a, 320b, and 320n of the physical signal in the physical interface 320. The mirror class definition 340 can also record additional information 342 related to the virtual interface. This additional information 342 can include the actual addresses of the variable members in the physical interface description, signal value change propagation record table information, and so on.

[0045] Figure 3C FIG. 3 is a schematic diagram showing an exemplary code 320 including a virtual interface according to an embodiment of the present disclosure.

[0046] In some embodiments, after receiving the exemplary logical system design 300, simulation tool 200 may process it using techniques such as lexical, syntactic, and semantic analysis to obtain node information of an abstract syntax tree. By traversing this node information, simulation tool 200 detects the presence of physical interface declarations 3021 and 3031 in the definition 302 of module "test" and the definition 303 of module "dut." Simulation tool 200 may rewrite physical interface code 302 and 303 to obtain virtual interface code 362 and 363. Virtual interface code 362 and 363 includes rewriting the physical interface into a virtual interface based on the data type of declarations 3021 and 3031, and modifying the port direction to input, thereby obtaining port declarations 3621 and 3631 for the virtual interfaces. Simulation tool 200 may add modifier keywords such as "input" and "virtual" before virtual interface declarations 3621 and 3631 to indicate that the port is a virtual interface and that the virtual interface is an input parameter. The virtual interface code 362 may include variables “req” and “gnt” corresponding to the physical signals req and gnt in the physical interface code 301 .

[0047] Thus, the physical interface can be rewritten as a virtual port, and its data type has also undergone significant changes. In some embodiments, the virtual interface name can remain unchanged, or it can be modified to an interface name that is uniquely corresponding to the physical interface name.

[0048] In some embodiments, the description of a physical interface in a module may involve a continuous assignment statement. The continuous assignment statement may involve a reference to a variable member of the physical interface. Regarding the continuous assignment statement in the physical interface, embodiments of the present application provide further improvements when rewriting the virtual interface.

[0049] Figure 4 A schematic diagram of exemplary code 400 of a continuous assignment statement according to an embodiment of the present disclosure is shown.

[0050] In some embodiments, exemplary code 400 may include a definition 401 of a physical interface "bus_if" and a definition 402 of a module "test2." The definition 402 of the module "test2" may include a physical interface bus, a continuous assignment statement 4021 involving a reference to the interface member bus.req, and a modification operation 4022 on the interface member value.

[0051] After the physical interface bus is rewritten as a virtual interface, a continuous assignment statement also exists in the description of the rewritten virtual interface, wherein the continuous assignment statement may involve a reference to a variable of the virtual interface.

[0052] Unlike the static physical interface processing logic, virtual interfaces are dynamic and cannot appear in static connection assignment statements. Therefore, when interface member references are used as right-hand values (loads) in continuous assignments, the following processing can be performed to ensure the normal operation of the continuous assignment statement.

[0053] In some embodiments, the simulation tool 200 can parse the rewritten continuous assignment statement, analyze the virtual interface variable in the expression containing the interface member reference through its abstract syntax tree node information, and record the continuous assignment information of the interface member reference in the continuous assignment into the continuous assignment load list of the virtual interface variable. The continuous assignment information may include the left value, right value, delay, and at least one of the modules of the continuous assignment statement.

[0054] Based on the continuous assignment load list for the virtual interface variable, simulation tool 200 can register a propagation function. When simulation tool 200 executes a non-continuous assignment statement to modify the virtual interface variable, it can call the registered propagation function and execute the continuous assignment statement. Based on the information in the continuous assignment load list, the right value can be assigned to the left value.

[0055] In some embodiments, after generating the virtual interface, the simulation tool 200 may initialize the virtual interface to associate the virtual interface with a physical interface.

[0056] In some embodiments, the initialization of the virtual interface can be performed by connecting the port of the module instance. Figure 3A The physical interface bus in code 302 is used as a high-conn, and the physical interface instance can be assigned to the virtual interface object; Figure 3C The virtual interface bus in code 362 acts as a low-level connection (low-conn) and can receive an interface instance to be assigned. Initialization operations may include allocating memory resources for the virtual interface object, recording the mapping relationship between mirrored class attributes and variable members in the physical interface description, obtaining the actual address of the variable members in the physical interface description, and maintaining a signal value change propagation record table.

[0057] In SystemVerilog, physical interfaces are inherently static, while virtual interfaces are dynamic. Therefore, during module instantiation, non-physical interface signals may trigger signal value propagation due to changes in their signal values when ports are connected. These non-physical interface signals can include common signals of register type (e.g., reg type), wire type, memory type, and so on. At this point, the virtual interface, after being rewritten according to the port declaration order, may not yet have established an association with the physical interface (i.e., initialization of the virtual interface), resulting in uninitialized virtual interfaces.

[0058] For avoiding this problem, in certain embodiments, simulation tool 200 can adjust the connection order of physical interface in the port list when processing port connection.For example, simulation tool 200 can determine whether the connection order of physical interface takes precedence over this non-physical interface in the description of module.If the connection order of this physical interface does not take precedence over this non-physical interface, simulation tool 200 can adjust the connection order of this physical interface in the port list so, so that this physical interface is set to the connection that takes precedence over described non-physical interface.Like this, simulation tool 200 can preferentially set up the port connection for the physical interface in the port list, so that set up the association of virtual interface and physical interface fast.Simulation tool 200 can, after finishing the connection of physical interface in this module, connect non-physical interface again.

[0059] In some embodiments, the module description may also include references to nested interface instances—that is, references to interface instance members of other interface types within the physical interface. Due to their static nature, physical interface instances cannot be instantiated within a class (mirror class); however, a virtual interface is a data type that can be instantiated within a class. Therefore, simulation tool 200 can process the nested interface instance to initialize the virtual interface. Based on this virtual interface, simulation tool 200 can complete communication between the nested interface instance and the design under test.

[0060] Figure 5A A schematic diagram of exemplary code 500 including references to nested interface instances according to an embodiment of the present disclosure is shown.

[0061] In some embodiments, exemplary code 500 may include a definition 501 of a physical interface "a_m_if," a definition 502 of a physical interface "a_if," a definition 503 of a module "dut_1," a definition 504 of a module "dut_2," and a definition 505 of a top-level module "top." The definition 502 of the physical interface "a_if" may include a physical interface instance "m_if" of the interface "a_m_if" type and a declaration 5021. The definition 503 of the module "dut_1" and the definition 504 of the module "dut_2" may include references 5032 and 5042 to nested interface instances.

[0062] Figure 5B A schematic diagram illustrating a portion of exemplary code 510 of a virtual interface involving a reference 500 of a nested interface instance according to an embodiment of the present disclosure is shown.

[0063] In some embodiments, the reference to the nested interface instance can establish an association between the virtual interface and the physical interface instance by setting the initial value of the virtual interface variable to the interface instance member. The simulation tool 200 can create a virtual interface variable "_xepic_vi_intfInst_m_if" pointing to the physical interface instance "m_if" in the definition 512 of the interface "a_if" (as shown in code 5121). And the simulation tool 200 can rewrite Figure 5A The ports 5031 and 5041 in the module "dut_1" and the module "dut_2" are declared as virtual interfaces 5131 and 5141 to generate virtual interfaces vaif in the modules "dut_1" and "dut_2" respectively.

[0064] The simulation tool 200 may generate a mapping table between the virtual interface vaif in the code 513 and the physical interface vaif in the code 503. The mapping table may include the physical interface vaif in the code 503, the virtual interface vaif in the code 513, the physical signal req in the code 503, the variable "req" in the code 513, the mapping relationship between the physical interface vaif and the virtual interface vaif, and the mapping relationship between the physical signal req and the variable "req".

[0065] The simulation tool 200 may also generate a mapping table between the virtual interface vaif in the code 514 and the physical interface vaif in the code 504 .

[0066] According to the mapping relationship in the mapping table, the simulation tool 200 can use the virtual interfaces 513 and 514 to replace the physical interfaces 503 and 504, so as to convert the references 5032 and 5042 of the nested interface instance into references 5132 and 5142 of the nested class object based on the virtual interface. Thereafter, based on the virtual interface vaif, the simulation tool 200 can complete the communication between the nested interface instance and the design under test.

[0067] After the virtual interface is associated with the physical interface, in some embodiments, the simulation tool 200 can also determine the physical operations associated with the physical interface based on the description of the physical interface. The physical operations may include reading, writing, evaluation of trigger conditions in a sensitive list, continuous assignment, gate-level connection, etc. Figure 3A and Figure 3C As shown, the simulation tool 200 can generate system functions to convert the read and write operations of the physical interface represented by code 3022 into read and write operations of the virtual interface represented by code 3622. The operation of the simulation tool 200 on the virtual interface object member can affect the physical interface instance member associated with the virtual interface.

[0068] It is understandable that the simulation tool 200 may also convert the physical operations of the physical interface into virtual operations of the virtual interface through other logic processing codes (eg, C++ codes).

[0069] In some embodiments, the simulation tool 200 may compile the virtual operations of the virtual interface into an execution code 206 , and based on the execution code 206 , may simulate the logical system design.

[0070] Thus, the disclosed embodiment connects modules using virtual interfaces, reducing the logical complexity of the interface processing module. During runtime, the simulation tool 200 no longer needs to load information such as interface member references that were reserved during compilation, thereby improving runtime speed. Furthermore, the virtual interfaces in the disclosed embodiment correspond one-to-one with the physical interfaces, enabling a certain degree of code reuse.

[0071] Figure 6A A schematic diagram of an exemplary implementation method according to an embodiment of the present disclosure is shown.

[0072] In some embodiments, when the test platform 620 and the design under test 640 are connected and communicated through the physical interface 320, the simulation tool 200 can create a virtual interface 660 corresponding to the physical interface 320. The simulation tool 200 can use the interface instance of the physical interface 320 to initialize the virtual interface 660 to establish an association between the virtual interface 660 and the physical interface 320. After the association is established, the simulation tool 200's operations such as reading (load) or writing (driver) on the members of the virtual interface 660 object correspond to the operations such as reading or writing on the corresponding members of the physical interface 320 instance. Thereafter, the virtual interface object no longer points to other new interface instances, and each physical interface uniquely corresponds to one virtual interface.

[0073] In other embodiments, the test platform 620 or the design under test 640 may also be connected and communicated via the physical interface 320. The simulation tool 200 may also create a virtual interface 660 corresponding to the physical interface 320. That is, the present disclosure is applicable not only to the implementation of the interface between the test platform and the design under test, but also to the implementation of the interface within the test platform or the design under test.

[0074] Figure 6B 6 shows a flow chart of an exemplary implementation method 600 according to an embodiment of the present disclosure. The method 600 may be performed by, for example Figure 1 The method 600 may be executed by the device 100, more specifically, by the simulation tool 200 running on the device 100. The method 600 may include the following steps.

[0075] In step S602, the simulation tool 200 may determine the following in the logic system design (eg, Figure 3A Whether there is a physical interface (e.g., Figure 3A In code 301 ), the physical interface includes at least one physical signal (eg, Figure 3A req and gnt in the code 301).

[0076] In step S604, in response to the existence of a physical interface (eg, Figure 3A The simulation tool 200 can generate a virtual interface (eg, bus) according to the description of the physical interface. Figure 3C The virtual interface may include at least one variable corresponding to the physical signal (eg, Figure 3C "req" and "gnt" in code 362).

[0077] In some embodiments, the virtual interface can be implemented by a mirror class. The simulation tool 200 can generate a virtual interface that is similar to the physical interface (e.g., Figure 3BThe mirror class definition corresponding to the physical interface 320 in Figure 3B The mirror class definition 340 in the figure). The mirror class definition may include variable members related to the physical signal (e.g., Figure 3B Variable members 320a, 320b and 320n) have one-to-one corresponding attributes (for example, Figure 3B At the same time, the mirror class definition may also include additional information related to the virtual interface (for example, Figure 3B The simulation tool 200 receives the additional information 342 in the logic system design (e.g., Figure 3A After the logical system design 300), the physical interface description can be modified (e.g., Figure 3A 3021 and 3031 in the ) to generate a virtual interface (for example, Figure 3C Statements 3621 and 3631 in the text).

[0078] In some embodiments, the description of the physical interface may involve continuous assignment statements (e.g., Figure 4 The continuous assignment statement 4021 in ). The continuous assignment statement can reference an interface member (for example, Figure 4 bus.req in code 4021). Accordingly, the description of the virtual interface, obtained by rewriting the description of the physical interface, also includes a continuous assignment statement, which may reference a variable of the virtual interface. To ensure the normal operation of continuous assignment statements in dynamic virtual interfaces, these continuous assignment statements can be converted into a continuous assignment processing flow.

[0079] Figure 6C FIG6 is a flowchart of an exemplary processing method 610 for continuous assignment statements according to an embodiment of the present disclosure. It is understood that the processing method 610 can be executed as an independent method or as part of the method 600.

[0080] In step S612, based on the continuous assignment statement, the simulation tool 200 may determine the continuous assignment information as an element in the load list of the variable of the virtual interface. The continuous assignment information may include at least one of the left value, right value, delay, and module of the continuous assignment statement.

[0081] In step S614, the simulation tool 200 may register a propagation function according to the load list. When the continuous assignment statement is activated, the propagation function may assign the right value to the left value according to the continuous assignment information in the load list.

[0082] Back to Figure 6BIn step S606, the simulation tool 200 may initialize the virtual interface to associate the virtual interface with the physical interface. In some embodiments, the initialization of the virtual interface may be performed through a port connection of a module instance.

[0083] For avoiding the problem that virtual interface is not initialized, in some embodiments, simulation tool 200 can adjust the connection order of physical interface in port list when processing the port connection in module.For example, simulation tool 200 can determine whether the connection order of this physical interface takes precedence over non-physical interface in the description of module.In response to the connection order of this physical interface not taking precedence over this non-physical interface, simulation tool 200 can adjust the connection order of physical interface in the description of module, so that this physical interface is set to take precedence over this non-physical interface connection.

[0084] In some embodiments, the module description may also include nested interface instances (e.g., Figure 5A The reference to the interface instance "m_if") in code 502. The virtual interface involving the reference to the nested interface instance can be further processed.

[0085] Figure 6D FIG6 is a flowchart of an exemplary processing method 620 for nested interface instance references according to an embodiment of the present disclosure. It is understood that the processing method 620 can be executed as an independent method or as part of the method 600.

[0086] In step S622, the simulation tool 200 may generate a mapping table between the virtual interface and the physical interface. The mapping table may include the physical interface (eg, Figure 5A The physical interface vaif in code 503), the virtual interface (for example, Figure 5B The virtual interface vaif in the code 513), at least one physical signal of the physical interface (for example, Figure 5A The signal req in the code 503), at least one variable of the virtual interface (for example, Figure 5B The variable "req" in the code 513), the mapping relationship between the physical interface and the virtual interface, and the mapping relationship between the at least one physical signal and the at least one variable, etc.

[0087] In step S624, the simulation tool 200 may check whether there is a reference to a nested interface instance in the module description (eg, Figure 5A The reference to the interface instance "m_if" in codes 5032 and 5042), and the nested interface instance can relate to the physical interface.

[0088] In step S626, in response to the presence of a reference to a nested interface instance, the simulation tool 200 may determine a virtual interface according to the mapping table, and use the virtual interface (eg, Figure 5B Codes 513 and 514 in the ) replace the physical interface (for example, Figure 5A Codes 503 and 504 in ).

[0089] In some embodiments, the simulation tool 200 may also be configured based on the description of the physical interface (eg, Figure 3A The code 3022 in the example 3020 determines a physical operation (eg, a read or write operation) associated with the physical interface. The simulation tool 200 may convert the physical operation into a virtual operation (eg, a read or write operation) of the virtual interface. Figure 3C The virtual operation can be implemented by generating a system function by the simulation tool 200.

[0090] Back to Figure 6B In step S608, the simulation tool 200 may simulate the logic system design based on the virtual interface. In some embodiments, the simulation tool 200 may compile the virtual operations of the virtual interface into an execution code 206, and based on the execution code 206, may simulate the logic system design.

[0091] The present disclosure also provides a device for implementing a physical interface of a logical system design based on a virtual interface. The device may be Figure 1 The simulation tool 200 may be configured to execute a computer program stored in the memory 104 to implement a method consistent with the present disclosure for implementing a physical interface of a logical system design based on a virtual interface, such as one of the exemplary methods described above (e.g., Figure 6B The method 600 shown in or Figure 6C The method 610 shown or Figure 6D The method 620 is shown in FIG. 6 . The details will not be described here.

[0092] The present disclosure also provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores a computer program. When executed by the simulation tool 200, the computer program causes the debugging tool to implement a method consistent with the present disclosure for implementing a physical interface of a logical system design based on a virtual interface, such as the exemplary method described above (e.g., Figure 6B The method 600 shown in or Figure 6C The method 610 shown or Figure 6D The method 620 is shown in FIG. 6 . The details will not be described here.

[0093] The computer-readable media of this embodiment includes permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0094] The foregoing description describes specific embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0095] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Within the scope of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0096] Additionally, to simplify the description and discussion, and to avoid obscuring the present disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided figures. Furthermore, devices may be shown in block diagram form to avoid obscuring the present disclosure, and this also takes into account the fact that the implementation details of these block diagram devices are highly dependent on the platform on which the present disclosure will be implemented (i.e., such details should be fully understood by those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it will be apparent to those skilled in the art that the present disclosure can be implemented without or with variations in these specific details. Accordingly, these descriptions should be considered illustrative rather than restrictive.

[0097] Although the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may utilize the discussed embodiments.

[0098] The present disclosure is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method for implementing a physical interface of a logical system design based on a virtual interface, comprising: determining whether a physical interface exists in a module of the logic system design, the physical interface comprising at least one physical signal; In response to the physical interface existing in the module, generating a virtual interface according to a description of the physical interface, the virtual interface including at least one variable corresponding to the physical signal; Initializing the virtual interface to associate the virtual interface with the physical interface; as well as simulating the logic system design based on the virtual interface; The step of generating a virtual interface according to the description of the physical interface further includes: generating a mirror class definition corresponding to the physical interface, the mirror class definition including attributes corresponding to the physical signal; modifying the description of the physical interface to generate the virtual interface; Wherein, modifying the description of the physical interface to generate the virtual interface further comprises: determining whether there are consecutive assignment statements referencing a variable of the virtual interface in the description of the module; In response to the presence of the continuous assignment statement in the description of the module, converting the continuous assignment statement into a continuous assignment processing flow; The method further comprises: determining a physical operation associated with the physical interface according to a description of the physical interface; The physical operation is converted into a virtual operation of the virtual interface, where the virtual operation is implemented by a system function.

2. The method according to claim 1, wherein Initializing the virtual interface to associate the virtual interface with the physical interface further comprises: determining whether the physical interface is prioritized over non-physical interfaces in a description of the module; and In response to the physical interface not having a connection order that takes precedence over the non-physical interface, adjusting the connection order of the physical interface in the description of the module to set the physical interface to be connected in priority over the non-physical interface.

3. The method according to claim 1, wherein The continuous assignment processing flow includes: Determining, according to the continuous assignment statements, a left value, an right value, a delay of the continuous assignment statements, and an element in a load list of at least one of the modules as a variable of the virtual interface; and A propagation function is registered according to the load list, and the propagation function assigns the right value to the left value according to the load list when the continuous assignment statement is activated.

4. The method according to claim 1 or 2, wherein: Initializing the virtual interface to associate the virtual interface with the physical interface further comprises: Generate a mapping table between the virtual interface and the physical interface, the mapping table including the physical interface, the virtual interface, the at least one physical signal of the physical interface, the at least one variable of the virtual interface, a mapping relationship between the physical interface and the virtual interface, and a mapping relationship between the at least one physical signal and the at least one variable.

5. The method according to claim 4, further comprising: determining whether a nested interface instance exists in the description of the module, the nested interface instance relating to the physical interface; In response to the presence of the nested interface instance in the description of the module, the physical interface is replaced with the virtual interface, where the virtual interface is determined according to the mapping table.

6. An electronic device that implements a physical interface of a logical system design based on a virtual interface, comprising: a memory for storing a set of instructions; as well as At least one processor is configured to execute the set of instructions so that the electronic device performs the method according to any one of claims 1 to 5.

7. A non-transitory computer-readable storage medium storing a set of instructions for an electronic device, wherein when the set of instructions is executed, the electronic device executes the method according to any one of claims 1 to 5.

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