Programmable Logic Device, Prototype Verification System, Method, Device and Storage Medium

Abstract

Embodiments of the present disclosure provide a programmable logic device, a prototype verification system, a method, a device, and a storage medium. The programmable logic device is embedded with a coprocessor and a memory; the memory pre-stores configuration information related to the chip under test and test cases of the chip under test; the coprocessor is configured to, in response to a start interrupt signal sent by a main processor, load the configuration information from the memory, configure the programmable logic device by using the configuration information, and start the configured programmable logic device; the programmable logic device is configured to, after being started, load the test cases from the memory, and perform prototype verification on the chip under test simulated by the configured programmable logic device through the test cases. This embodiment is beneficial to improving the configuration efficiency.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip design, and in particular, to a programmable logic device, a prototype verification system, a method, a device, and a storage medium. Background Art

[0002] A prototype verification system is an indispensable tool for an integrated circuit design company in the chip verification stage. The prototype verification system can prototype and debug a chip design including one or more modules. The chip design can be, for example, a design for an Application Specific Integrated Circuit (ASIC) or a System-On-Chip (SOC) for a specific application. In the prototype verification system, the chip design under test can also be referred to as the Design Under Test (DUT), and the logic hardware for testing the DUT constitutes the prototype verification system.

[0003] The prototype verification system can include one or more programmable logic devices (for example, a Field Programmable Gate Array (FPGA)). The prototype verification system can configure these programmable logic devices to simulate the chip under test, and based on these configured programmable logic devices, the functions of each module in the chip design under test can be tested and verified before manufacturing.

[0004] However, with the continuous development of chip technology, the chip scale becomes more complex (such as an increase in chip area and computational complexity), and the amount of data required to configure the programmable logic device gradually increases. However, the configuration efficiency of the prototype verification system in the related art for configuring the programmable logic device cannot meet the requirements of large-scale chip design. Summary of the Invention

[0005] The present disclosure provides a programmable logic device, a prototype verification system, a method, a device, and a storage medium.

[0006] According to a first aspect of an embodiment of the present disclosure, there is provided a programmable logic device for prototype verification of a chip under test; a coprocessor and a memory are embedded in the programmable logic device; wherein, the memory pre-stores configuration information related to the chip under test and test cases of the chip under test;

[0007] The coprocessor is configured to, in response to a start interrupt signal sent by a main processor, load the configuration information from the memory, configure the programmable logic device by using the configuration information, and start the configured programmable logic device;

[0008] The programmable logic device is configured to, after being started, load the test case from the memory and perform prototype verification on the device under test simulated by the configured programmable logic device using the test case.

[0009] Optionally, the coprocessor, the memory, and the programmable logic device are connected via a bus.

[0010] Optionally, the configuration information and the test case are stored in the memory by the main processor before sending the start interrupt signal.

[0011] Optionally, the programmable logic device is further configured to, after being started, process the loaded test case, obtain a processing result and store it in the memory; and after processing the test case, generate a completion interrupt signal to be sent to the main processor; wherein the completion interrupt signal is used to trigger the main processor to read the processing result from the memory and obtain the prototype verification result of the device under test based on the difference between the processing result and the actual result of the test case.

[0012] Optionally, the coprocessor is further configured to initialize and configure the programmable logic device using the configuration information and start the initialized programmable logic device.

[0013] The programmable logic device is further configured to, after being started, feedback a first status signal to the coprocessor during the process of processing the test case; the first status signal characterizes the processing progress of the test case.

[0014] The coprocessor is further configured to configure the programmable logic device based on the information in the configuration information related to the first status signal.

[0015] Optionally, the coprocessor is further configured to periodically send a second status signal to the main processor; wherein the second status signal indicates the working status of the coprocessor; the second status signal is used to trigger the main processor to monitor the working status of the coprocessor.

[0016] Optionally, the programmable logic device is further configured to feedback a first status signal to the main processor during the process of processing the test case; wherein the first status signal is used to trigger the main processor to configure the programmable logic device based on the preset configuration information related to the first status signal when the second status signal indicates that the coprocessor is abnormal; and discard the first status signal when the second status signal indicates that the coprocessor is operating normally.

[0017] Optionally, the programmable logic device further includes a programmable logic module;

[0018] The configuration information includes first configuration information for the chip under test and second configuration information for the programmable logic device;

[0019] The coprocessor is further configured to configure the programmable logic module by using the first configuration information, so that the configured programmable logic unit has the same function as the chip under test at the behavioral level; and configure other components in the programmable logic device except the programmable logic module by using the second configuration information, so that the configured other components can cooperate with the configured programmable logic module in the process of processing the test case.

[0020] Optionally, the programmable logic device and the main processor are communicatively connected based on the PCI-e protocol or the USB protocol.

[0021] Optionally, the programmable logic device further includes a communication module and an interrupt control module; the start interrupt signal is sent from the main processor to the communication module and forwarded to the coprocessor via the interrupt control module; and / or, the completion interrupt signal generated after the programmable logic device processes the test case is forwarded by the interrupt control module to the communication module and sent by the communication module to the main processor.

[0022] Optionally, the configuration information related to the chip under test is encapsulated into a firmware file; the firmware file is obtained by the following method: after compiling a high-level language programming file into a binary file by a compiler, saving it in a format supported by the coprocessor.

[0023] Optionally, the main processor includes an ARM processor, the coprocessor includes an MCU, and the programmable logic device includes an FPGA.

[0024] According to a second aspect of the embodiments of the present disclosure, there is provided a prototype verification system, including a main processor and the programmable logic device according to any one of the first aspect.

[0025] According to a third aspect of the embodiments of the present disclosure, there is provided an electronic device, including the prototype verification system according to the second aspect.

[0026] According to a fourth aspect of the embodiments of the present disclosure, there is provided a prototype verification method, which is applied to the programmable logic device according to any one of the first aspect; the method is executed by a coprocessor embedded in the programmable logic device, and the method includes:

[0027] In response to the startup interrupt signal sent by the main processor, load the pre-stored configuration information related to the chip under test from the memory;

[0028] Configure the programmable logic device by using the configuration information, and start the configured programmable logic device; wherein, the started programmable logic device is used to load the pre-stored test cases of the chip under test from the memory, and verify the prototype of the chip under test simulated by the configured programmable logic device through the test cases.

[0029] According to the fifth aspect of the embodiments of the present disclosure, there is provided a computer-readable storage medium, on which computer instructions are stored, and when the computer instructions are executed by a processor, the steps of the method described in the second aspect are implemented.

[0030] In the embodiments of the present disclosure, it should be understood that the coprocessor is embedded in the programmable logic device, so that the communication efficiency between the coprocessor and the programmable logic device is higher than the communication efficiency between the main processor and the programmable logic device. And a firmware file related to the chip under test is pre-stored in the memory of the programmable logic device. The coprocessor responds to the startup interrupt signal sent by the main processor, loads the firmware file from the memory to configure the programmable logic device. This on-chip configuration method can achieve a faster chip configuration process, improve the chip configuration efficiency, thus effectively accelerating the chip R & D cycle, and this on-chip configuration method also effectively reduces the load of the main processor.

[0031] The above general description and the following detailed description are only exemplary and explanatory, and do not limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings herein are incorporated into the specification and form a part of this specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0033] Figure 1 It is a schematic structural diagram of the first prototype verification system according to the embodiments of the present disclosure.

[0034] Figure 2 It is a schematic structural diagram of the second prototype verification system according to the embodiments of the present disclosure.

[0035] Figure 3 It is a schematic structural diagram of the third prototype verification system according to the embodiments of the present disclosure.

[0036] Figure 4 It is a schematic structural diagram of the fourth prototype verification system according to the embodiments of the present disclosure.

[0037] Figure 5It is a schematic structural diagram of a prototype verification method according to an embodiment of the present disclosure. Detailed implementation manners

[0038] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present disclosure. On the contrary, they are merely examples of apparatuses and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0039] The terms used in the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The singular forms "a", "the", and "said" used in the present disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items. In addition, the term "at least one" herein represents any one of a plurality or any combination of at least two of a plurality.

[0040] It should be understood that although the terms first, second, third, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0041] In order to enable those skilled in the art of the present technology to better understand the technical solutions in the embodiments of the present disclosure and to make the above-mentioned objects, features, and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0042] The working principle of prototype verification is to map the system function model of the chip design onto a programmable logic device for implementation, and then let the software part in the chip design run on the real hardware to achieve co-verification of software and hardware. The prototype verification system may include one or more programmable logic devices. For example, a Field Programmable Gate Array (FPGA for short). The prototype verification system can load the verification data corresponding to the chip under test to configure the programmable logic device, so that the function of the programmable logic device after configuration is consistent with the function of the chip under test at the behavioral level. Thus, the chip under test can be verified through the configured programmable logic device, including performing various operations of the chip under test, and testing and verifying the functions of each module in the chip design under test before manufacturing.

[0043] A prototype verification system in the related art includes a processor and a programmable logic device. The processor and the programmable logic device are communicatively connected. The processor sends the verification data corresponding to the chip under test to the programmable logic device to configure the programmable logic device. However, with the continuous development of chip technology, the chip scale becomes more complex (such as the increase in chip area, the increase in computational complexity, etc.), and the amount of data required to configure the programmable logic device also gradually increases. The configuration efficiency of the prototype verification system with the above structure cannot meet the requirements of large-scale chip design.

[0044] Based on the problems in the related art, please refer to Figure 1 , an embodiment of the present disclosure provides a prototype verification system, the system includes a main processor 10 and a programmable logic device 30; the programmable logic device 30 can be communicatively connected with the main processor 10; wherein, a coprocessor 20 and a memory 31 are embedded in the programmable logic device 30; the memory 31 pre-stores configuration information related to the chip under test and test cases of the chip under test.

[0045] The main processor 10 is configured to send a start interrupt signal to the coprocessor 20.

[0046] The coprocessor 20 is configured to, in response to the start interrupt signal sent by the main processor 10, load the configuration information from the memory 31, configure the programmable logic device 30 by using the configuration information, and start the configured programmable logic device 30; wherein, the configured programmable logic device is used to simulate the chip under test.

[0047] The programmable logic device 30 is configured to, after being started, load the test cases from the memory 31, and perform prototype verification on the chip under test simulated by the configured programmable logic device through the test cases.

[0048] In the prototype verification system provided in this embodiment, the coprocessor 20 is embedded in the programmable logic device 30, so that the communication efficiency between the coprocessor 20 and the programmable logic device 30 is higher than that between the main processor 10 and the programmable logic device 30. And configuration information related to the chip under test is pre-stored in the memory 31 of the programmable logic device. The coprocessor 20 responds to the startup interrupt signal sent by the main processor 10 and loads the configuration information from the memory 31 to configure the programmable logic device 30. This on-chip configuration method can achieve a faster chip configuration process, improve the chip configuration efficiency, effectively accelerate the chip R & D cycle, and this on-chip configuration method also effectively reduces the load of the main processor 10.

[0049] Exemplarily, the main processor 10 includes but is not limited to an ARM processor, a field programmable logic device 30 (FPGA), an application specific integrated circuit, or a microcontroller, etc. The coprocessor 20 includes a microprocessor (MCU), and the programmable logic device 30 includes a field programmable logic device 30 (FPGA) or a generic array logic (GAL). The memory 31 can be a random access memory 31 (such as a DDR memory 31) or a static random access memory 31, etc.

[0050] Exemplarily, the configuration information related to the chip under test is encapsulated into a firmware file. Exemplarily, the firmware file can be obtained in the following way: developed using a high-level programming language (such as C language or C++ language), program the configuration information related to the chip under test into a high-level language programming file (C language programming file or C++ language programming file), and then after compiling the high-level language programming file into a binary file by a compiler, save it in the format supported by the coprocessor 20. In this embodiment, the configuration information related to the chip under test is encapsulated into a firmware file, so as to realize the automatic configuration of the programmable logic device 30 by the coprocessor 20 based on the firmware file without the participation of the main processor 10, which is beneficial to improving the configuration efficiency and reducing the load of the main processor 10.

[0051] In an exemplary implementation manner, the coprocessor 20, the memory 31, and the programmable logic device 30 are connected by a bus, then the coprocessor 20 can load the configuration information through the bus to configure the programmable logic device 30. It can be understood that the specific type of the bus can be specifically set according to the actual application scenario, and this embodiment does not make any limitation on this. Exemplarily, the bus includes but is not limited to an AXI bus, a PCI bus, or an RS485 bus, etc.

[0052] It is understandable that the present disclosure embodiments do not impose any restrictions on the specific communication method between the programmable logic device 30 and the main processor 10, and can be specifically set according to the actual application scenario. In an exemplary embodiment, the programmable logic device 30 and the main processor 10 are communicatively connected based on PCI-e or USB; among them, the communication efficiency based on PCI-e is higher than that based on USB. In an example, the main processor 10 provides a PCIe Gen3 x16 general expansion slot and communicates with the programmable logic device 30 through PCI-e, which is beneficial to improving the communication efficiency.

[0053] In some embodiments, when it is necessary to perform prototype verification on the chip under test, the main processor 10 may first obtain the configuration information related to the chip under test and the test cases of the chip under test, and store them in the built-in memory of the main processor 10. Before sending the start interrupt signal, the main processor 10 may move the configuration information related to the chip under test and the test cases of the chip under test stored in the built-in memory to the memory 31. After determining that the configuration information and the test cases are stored in the memory 31 in the programmable logic device 30, the main processor 10 may send a start interrupt signal to the coprocessor 20 to inform the coprocessor 20 to configure and start the programmable logic device 30.

[0054] In some exemplary embodiments, please refer to Figure 2 , the programmable logic device 30 includes a communication module 32 and a relay control module 33. Exemplarily, the communication module 32, the relay control module 33, the coprocessor 20, and the memory 31 can be connected by a bus. The communication module 32 is configured to receive the configuration information and the test cases sent by the main processor 10 and store them in the specified address of the memory 31; and receive the start interrupt signal sent by the main processor 10 and send it to the relay control module 33. The relay control module 33 is responsible for the functions of receiving, forwarding, and processing the interrupt signal. After receiving the start interrupt signal, the relay control module 33 forwards it to the coprocessor 20. In an example, after receiving the start interrupt signal, if the format of the start interrupt signal is a format that cannot be read by the coprocessor 20, the relay control module 33 may first convert the format of the start interrupt signal into a format supported by the coprocessor 20 and then forward it to the coprocessor 20.

[0055] In some embodiments, the coprocessor 20, in response to the start interrupt signal forwarded by the relay control module 33, loads the configuration information from the memory 31, configures the programmable logic device 30 by using the configuration information, and starts the configured programmable logic device 30; the configured programmable logic device 30 has the same function as the chip under test at the behavioral level, implementing the hardware part of the simulated chip under test. The programmable logic device 30 is further configured to, after being started, load the test case from the memory 31, and perform prototype verification on the chip under test simulated by the configured programmable logic device by using the test case; specifically, the configured programmable logic device 30 can process the loaded test case, obtain a processing result and store it in the memory 31; and after processing the test case, generate a completion interrupt signal sent to the main processor 10. Wherein, the test case is a software test case to implement simulation verification of the software part of the chip under test.

[0056] Exemplarily, the programmable logic device 30 can send the generated completion interrupt signal to the relay control module 33, and the interrupt processing module forwards it to the communication module 32, and then the communication module 32 sends it to the main processor 10. In one example, the programmable logic device 30 and the main processor 10 are communicatively connected based on PCI-e. After receiving the completion interrupt signal, the relay control module 33 can process the completion interrupt signal into an MSIX interrupt signal supported by PCI-e, so as to send the processed completion interrupt signal to the main processor 10 via the communication module 32.

[0057] The main processor 10, in response to the completion interrupt signal, reads the processing result from the memory 31 of the programmable logic device 30, compares the processing result with the actual result of the test case, and obtains the prototype verification result of the chip under test according to the difference between the processing result and the actual result of the test case. Exemplarily, if the processing result is the same as the actual result or the difference between the two is less than a preset difference, it indicates that there is no problem with the functional design of the chip under test; on the contrary, if the difference between the processing result and the actual result is greater than the preset difference, it indicates that there is a problem with the functional design of the chip under test and the functional design of the chip under test needs to be readjusted; it can be understood that the preset difference can be specifically set according to the actual application scenario. In this embodiment, since the chip configuration task is executed by the coprocessor, the main processor 10 only needs to compare and verify based on the processing result and the actual result, reducing the load of the main processor 10, which is beneficial to improving the processing efficiency of the main processor 10.

[0058] In some embodiments, please refer toFigure 3 The programmable logic device 30 further includes a programmable logic module 34. The programmable logic device 30 is composed of a look-up table (LUT) and a register. The look-up table completes pure combinational logic functions. The co-processor 20 can configure the programmable logic module 34 according to the configuration information related to the chip under test, so that the configured programmable logic module 34 has the same function as the chip under test at the behavioral level, realizing the simulation of the chip under test. Exemplarily, the co-processor 20 can configure the registers in the programmable logic device 30. For example, the register can be configured as a flip-flop with synchronous / asynchronous reset and set, clock enable, or can also be configured as a latch. Exemplarily, the programmable logic device 30 includes an FPGA, and the programmable logic module 34 includes one or more configurable logic blocks (CLBs). The CLB is the main bearer of the programmable ability of the FPGA. By configuring these CLBs, the FPGA can simulate the chip under test, so that the FPGA has the same function as the chip under test at the behavioral level.

[0059] In some embodiments, considering that the chip under test may need to cooperate with other hardware or software during actual application, the programmable logic module 34 of the simulated chip under test may require the cooperation of other hardware or software during the process of processing test cases; or, in the prototype verification system, it is necessary to collect the processing results obtained by the programmable logic module 34 processing test cases for verification and analysis, while the programmable logic module 34 of the simulated chip under test does not have the function of collecting processing results for verification and analysis. Therefore, in addition to configuring the programmable logic module 34, the embodiments of the present disclosure also need to configure other components in the programmable logic device 30 to ensure the stable progress of the prototype verification process. The above configuration information related to the chip under test includes first configuration information for the chip under test and second configuration information for the programmable logic device 30. The coprocessor 20 is further configured to configure the programmable logic module 34 using the first configuration information, so that the configured programmable logic unit has the same function as the chip under test at the behavioral level; and configure other components in the programmable logic device 30 except the programmable logic module 34 using the second configuration information, so that the configured other components can cooperate with the configured programmable logic module 34 in the process of processing the test cases. In one example, for instance, the configured other components can simulate the hardware and software cooperating with the chip under test during the process of the configured programmable logic module 34 processing test cases, and send relevant excitation information to the programmable logic module 34. In another example, for instance, the configured other components can collect relevant processing data after the configured programmable logic module 34 finishes processing the test cases for subsequent verification and analysis.

[0060] Other components in the programmable logic device 30 except the programmable logic module 34 include but are not limited to the communication module 32, the relay control module 33, the memory 31, the coprocessor 20, and so on. Exemplarily, the second configuration information includes at least one or more of the following: drive configuration information for the coprocessor 20, interrupt processing configuration information for the relay control module 33, storage configuration information for the memory 31, and communication configuration information for the communication module 32, and so on. In one example, the configured relay control module 33 can respond to the completion interrupt signal sent by the configured programmable logic module 34 and send the completion interrupt signal to the main processor 10. In another example, for instance, the configured coprocessor 20 can respond to the first status signal sent by the programmable logic module 34 during the process of processing test cases and execute relevant processing logic based on the first status signal; wherein, the first status signal represents the processing progress of the test cases.

[0061] In some embodiments, please refer toFigure 4 , the programmable logic device 30 further includes a storage control module 35, and the storage control module 35 is used to control other components to read and write the memory 31. For example, the main processor 10 can write configuration information and test cases related to the chip under test into the memory 31 through the storage control module 35; for example, the coprocessor 20 can read the configuration information from the memory 31 through the storage control module 35 to configure the programmable logic module 34 and other components; for example, the configured programmable logic module 34 can read test cases from the memory 31 through the storage control module 35 for processing. Exemplarily, as Figure 4 shown, the communication module 32, the relay control module 33, the programmable logic module 34, the storage control module 35, and the coprocessor 20 can be connected through a bus. The programmable logic module 34 can be directly connected to the storage control module 35, which is beneficial to improving the efficiency of the programmable logic module 34 to read or write data from the memory 31.

[0062] In some embodiments, considering that as the scale of chip design expands, the computing complexity of the chip also gradually increases. For example, the chip under test may need to be used in cooperation with other hardware or software during actual application. Then, when the programmable logic device 30 simulating the chip under test processes test cases, it also needs the cooperation of other hardware or software. In the prototype verification system, the coprocessor 20 is further used to initialize and configure the programmable logic device 30 by using the configuration information, and start the initialized programmable logic device 30; the programmable logic device 30 is further used to, after being started, feedback a first status signal to the coprocessor 20 during the process of processing the test cases, and the first status signal represents the processing progress of the test cases; the coprocessor 20 is further used to configure the programmable logic device 30 based on the information related to the first status signal in the configuration information. In this embodiment, accurate configuration of the programmable logic device 30 is achieved through the status feedback during the test case processing process, so as to ensure the stable progress of the prototype verification process of the chip under test.

[0063] Exemplarily, please refer to Figure 3 and Figure 4, after the programmable logic module 34 in the programmable logic device 30 is initialized and configured and started, it can read the test cases of the chip under test pre-stored in the memory 31, process the test cases, and feedback a first status signal to the coprocessor 20 during the process of processing the test cases. Among them, the first status signal can reflect the working status of the programmable logic module 34 during the processing process. For example, the first status signal characterizes the processing progress of the test cases. The coprocessor 20 is also used to, after receiving the first status signal, configure the programmable logic module 34 based on the information related to the first status signal in the configuration information, so as to simulate the cooperation effect of other hardware or software in the actual application process and ensure the stable progress of the prototype verification process. Exemplarily, the configuration information may include the configurable information corresponding to different status signals.

[0064] In one example, assume that the chip under test is used to process a video frame sequence, such as performing face detection on video frames. The function of the chip under test is to perform face detection on images, but which image to perform face detection on needs to be determined by other hardware or software according to the face detection result of the chip under test for the previous frame image. The test case can be the video frame sequence to be processed. The test cases are pre-stored in the memory 31. After the programmable logic module 34 is initialized and configured and started, it can read the first frame image in the video frame sequence from the memory 31, perform face detection processing on the first frame image, and after the processing is completed, store the processing result of the first frame image in the memory 31 and feedback a first status signal indicating that the processing of the first frame image is completed to the coprocessor 20; the first status signal indicates that the processing of the first frame image is completed, and the coprocessor can read the processing result of the first frame image from the memory 31. For example, in the case where a face is detected in the first frame image, skip the second frame image in the video frame sequence and directly process the third frame image in the video frame sequence. In the case where no face is detected in the first frame image, the second frame image in the video frame sequence needs to be processed next. In the actual application process, the chip under test needs to receive the processing signal sent by other hardware or software according to the first status signal, and this processing signal indicates which frame image in the video frame sequence the chip under test should process next.

[0065] During the prototype verification process, the coprocessor 20 can configure the programmable logic module 34 based on the information related to the first status signal in the configuration information. The information related to the first status signal in the configuration information can simulate the cooperation effect of other hardware or software in the actual application process. For example, the information related to the first status signal in the configuration information can include an excitation signal for simulating the above cooperation effect, and the excitation signal indicates which frame of image the configured programmable logic module 34 should process next. Then, the configured programmable logic module 34 can read the second frame image or the third image in the video frame sequence from the memory 31 for face detection. After the processing is completed, the processing result is stored in the memory 31, and a first status signal indicating the completion of the processing is fed back to the coprocessor 20, and so on until the programmable logic module 34 finishes processing the video frame sequence. In another example, the function of the chip under test is to perform speech recognition on a speech signal, but when to stop the speech recognition needs to be determined by other hardware or software. For example, when other hardware or software determines that there is a preset vocabulary in the speech recognition result of the chip under test, it can notify the chip under test to stop the speech recognition.

[0066] The test case can be a speech segment to be processed, and the test case is pre-stored in the memory 31. During the prototype verification process, after the programmable logic module 34 is initialized and configured and started, it can read the speech segment from the memory 31 for speech recognition, store the recognition result in the memory 31, and feed back a first status signal to the coprocessor 20 every time it finishes recognizing a speech signal of a preset duration. The coprocessor 20 can obtain the speech recognition result of the speech signal of the preset duration from the memory according to the first status signal. If it is determined that the speech recognition result includes a preset vocabulary, the coprocessor 20 can configure the programmable logic module 34 based on the information related to the first status signal in the configuration information, so that the configured programmable logic module 34 stops recognizing the next speech signal. If the speech recognition result does not include a preset vocabulary, the programmable logic module 34 is not configured, so that the programmable logic module 34 continues to recognize the speech signal.

[0067] In some embodiments, the coprocessor 20 is further configured to periodically send a second status signal to the main processor 10, where the second status signal indicates the working status of the coprocessor 20; the main processor 10 is further configured to monitor the working status of the coprocessor 20 according to the second status signal, so as to ensure the stable progress of the verification process of the chip under test. Exemplarily, when the second status signal includes a first preset field, the main processor 10 determines that the coprocessor 20 is running normally; when the second status signal includes a second preset field, the main processor 10 determines that the coprocessor 20 is abnormal. Wherein, the specific values of the first preset field and the second preset field can be specifically set according to the actual application scenario, and this embodiment does not make any restrictions on this, for example, the first preset field is 1 and the second preset field is 0.

[0068] Exemplarily, when the main processor 10 determines that the coprocessor 20 is abnormal, it can output an abnormal prompt message to prompt the user to check the coprocessor 20, so as to ensure the stable progress of the configuration and verification process of the chip under test.

[0069] In a possible implementation manner, during the process of the programmable logic device 30 processing the test case, in addition to feeding back the first status signal to the coprocessor 20, it can also feed back the first status signal to the main processor 10. The main processor 10 is further configured to discard the first status signal when the second status signal indicates that the coprocessor 20 is running normally, and at this time, the coprocessor 20 continues to configure the programmable logic device 30; and when the second status signal indicates that the coprocessor 20 is abnormal, configure the programmable logic device 30 based on the preset configuration information related to the first status signal. This embodiment provides a remedial measure in the case of an abnormal coprocessor 20. In the case of an abnormal coprocessor 20, the main processor 10 can continue to execute the chip configuration task, so as to ensure the stable progress of the prototype verification process of the chip under test.

[0070] Exemplarily, the first status signal is sent by the programmable logic module 34 in the programmable logic device 30 to the coprocessor 20 and the main processor 10. When the coprocessor 20 is running normally, the coprocessor 20 continues to configure the programmable logic module 34 based on the first status signal; when the coprocessor 20 is abnormal, the main processor 10 continues to configure the programmable logic module 34 based on the first status signal, so as to ensure the stable progress of the prototype verification process of the chip under test.

[0071] In an exemplary embodiment, during the specific verification and debugging process of the prototype verification system, it is mainly divided into two stages: "compilation" and "runtime" (hereinafter, the programmable logic device 30 is used as an FPGA for exemplary illustration):

[0072] In the "compilation" stage: (1) All synthesizable hardware description source files, including components such as coprocessor 20, communication module 32, bus, relay control module 33, storage control module 35, memory 31, and programmable logic module 34, are synthesized and implemented in a dedicated FPGA integrated compilation environment, and finally a netlist database of the hardware circuit is obtained, generating a dedicated FPGA bitstream file. (2) Developed using a high-level programming language (such as C language or C++ language), the configuration information related to the chip under test is programmed into a C language programming file or a C++ language programming file. Then, after the C language programming file or the C++ language programming file is compiled into a binary file by a compiler, it is saved in the format supported by the coprocessor 20 to obtain a firmware file.

[0073] In the "runtime" stage:

[0074] 1. Download the FPGA bitstream file completed in the compilation stage to the FPGA through a preset tool.

[0075] 2. The built-in memory of the main processor 10 stores the test cases and firmware files of the chip under test.

[0076] 3. The main processor 10 is communicatively connected to the FPGA based on PCI-e. The main processor 10 sends the test cases and firmware files in the built-in memory to the communication module 32 in the FPGA, and the communication module 32 moves them to the specified address of the memory 31 on the FPGA.

[0077] 4. The main processor 10 sends a start interrupt signal to the communication module 32, which is then forwarded to the coprocessor 20 through the relay control module 33. The coprocessor 20 loads the firmware file in the memory 31 to implement the configuration of the programmable logic module 34 and other components on the FPGA, and starts the programmable logic module 34 after the configuration.

[0078] 5. After being started, the programmable logic module 34 parses the instructions, then fetches the required test cases from the memory 31 on the FPGA for chip calculation, and the output processing result is still stored back in the memory 31 on the FPGA. After the calculation is completed, a completion interrupt signal is sent to the relay control module 33.

[0079] 6. The relay control module 33 receives the completion interrupt signal from the programmable logic module 34. On the one hand, it sends it to the coprocessor 20 for interrupt processing, and on the other hand, it converts the completion interrupt signal into a dedicated MSIX interrupt of PCIe and sends it to the main processor 10 through the communication module 32.

[0080] 7. In response to the completion of the interrupt signal, the main processor 10 transfers the processing result data of the test case from the memory 31 on the FPGA to the built-in memory of the main processor 10 through the communication module 32, and compares and verifies based on the actual result of the test case and the processing result.

[0081] It should be noted that, without conflict, the solutions described in the above embodiments can be combined, which are not enumerated one by one in the embodiments of the present disclosure.

[0082] Correspondingly, please refer to Figures 1 to 4 , the embodiments of the present disclosure further provide a programmable logic device for prototype verification of a chip under test; the programmable logic device is embedded with a coprocessor and a memory; wherein, the memory pre-stores configuration information related to the chip under test and test cases of the chip under test.

[0083] The coprocessor is configured to, in response to a start interrupt signal sent by the main processor, load the configuration information from the memory, configure the programmable logic device using the configuration information, and start the configured programmable logic device;

[0084] The programmable logic device is configured to, after being started, load the test cases from the memory, and perform prototype verification on the chip under test simulated by the configured programmable logic device through the test cases.

[0085] In some embodiments, the coprocessor, the memory, and the programmable logic device are connected through a bus.

[0086] In some embodiments, the configuration information and the test cases are stored in the memory by the main processor before sending the start interrupt signal.

[0087] In some embodiments, the programmable logic device is further configured to, after being started, process the loaded test cases, obtain a processing result and store it in the memory; and after processing the test cases, generate a completion interrupt signal sent to the main processor; wherein, the completion interrupt signal is used to trigger the main processor to read the processing result from the memory, and obtain the prototype verification result of the chip under test according to the difference between the processing result and the actual result of the test case.

[0088] In some embodiments, the coprocessor is further configured to initialize and configure the programmable logic device using the configuration information, and start the initialized programmable logic device; the programmable logic device is further configured to, after being started, when performing the

[0089] During the processing, a first status signal is fed back to the coprocessor; the first status signal characterizes the processing progress of the test case; the coprocessor is further configured to configure the programmable logic device based on the information related to the first status signal in the configuration information.

[0090] In some embodiments, the coprocessor is further configured to periodically send a second status signal to the main processor; wherein, the second status signal indicates the working status of the coprocessor; the second status signal is used to trigger the main processor to monitor the working status of the coprocessor.

[0091] In some embodiments, the programmable logic device is further configured to feed back a first status signal to the main processor during the processing of the test case; wherein, the first status signal is used to trigger the main processor to configure the programmable logic device based on the preset configuration information related to the first status signal when the second status signal indicates that the coprocessor is abnormal; and, when the second status signal indicates that the coprocessor is operating normally, discard the first status signal.

[0092] In some embodiments, the programmable logic device further includes a programmable logic module; the configuration information includes first configuration information for the device under test and second configuration information for the programmable logic device; the coprocessor is further configured to configure the programmable logic module with the first configuration information so that the configured programmable logic unit has the same function as the device under test at the behavioral level; and, configure other components in the programmable logic device except the programmable logic module with the second configuration information so that the configured other components can cooperate with the configured programmable logic module in the processing of the test case.

[0093] In some embodiments, the programmable logic device and the main processor are communicatively connected based on the PCI-e protocol or the USB protocol.

[0094] In some embodiments, the programmable logic device further includes a communication module and an interrupt control module; the start interrupt signal is sent from the main processor to the communication module and forwarded to the coprocessor via the interrupt control module; and / or, the completion interrupt signal generated by the programmable logic device after processing the test case is forwarded to the communication module by the interrupt control module and sent to the main processor by the communication module.

[0095] In some embodiments, the configuration information related to the chip under test is encapsulated into a firmware file; the firmware file is obtained by the following method: after compiling a high-level language programming file into a binary file by a compiler, saving it in a format supported by the coprocessor.

[0096] In some embodiments, the main processor includes an ARM processor, the coprocessor includes an MCU, and the programmable logic device includes an FPGA.

[0097] Among them, the specific description of the above programmable logic device can refer to the description in the above system embodiment and will not be elaborated here. Correspondingly, please refer to Figure 5 , the embodiments of the present disclosure further provide a prototype verification method, which is applied to the above programmable logic device; the method is executed by a coprocessor embedded in the programmable logic device, and the method includes:

[0098] In step S101, in response to a startup interrupt signal sent by the main processor, load the pre-stored configuration information related to the chip under test from the memory.

[0099] In step S102, configure the programmable logic device by using the configuration information, and start the configured programmable logic device; wherein, the started programmable logic device is used to load the pre-stored test cases of the chip under test from the memory, and perform prototype verification on the chip under test simulated by the configured programmable logic device through the test cases.

[0100] In some embodiments, the coprocessor, the memory, and the programmable logic device are connected through a bus. The configuration information and the test cases are stored in the memory by the main processor before sending the startup interrupt signal.

[0101] In some embodiments, the started programmable logic device is used to process the loaded test cases, obtain a processing result and store it in the memory; and after processing the test cases, generate a completion interrupt signal sent to the main processor; wherein, the completion interrupt signal is used to trigger the main processor to read the processing result from the memory, and obtain the prototype verification result of the chip under test according to the difference between the processing result and the actual result of the test case.

[0102] In some embodiments, configuring the programmable logic device using the configuration information and starting the configured programmable logic device includes: initializing and configuring the programmable logic device using the configuration information and starting the programmable logic device after the initialization configuration; receiving a first status signal fed back by the programmable logic device during the process of processing the test case, where the first status signal characterizes the processing progress of the test case; and configuring the programmable logic device based on the information related to the first status signal in the configuration information.

[0103] In some embodiments, it further includes: periodically sending a second status signal to the main processor; where the second status signal indicates the working status of the coprocessor; and the second status signal is used to trigger the main processor to monitor the working status of the coprocessor.

[0104] In some embodiments, the programmable logic device is further configured to feed back a first status signal to the main processor during the process of processing the test case; where the first status signal is used to trigger the main processor to configure the programmable logic device based on preset configuration information related to the first status signal when the second status signal indicates that the coprocessor is abnormal; and to discard the first status signal when the second status signal indicates that the coprocessor is operating normally.

[0105] In some embodiments, the programmable logic device further includes a programmable logic module; the configuration information includes first configuration information for the chip under test and second configuration information for the programmable logic device. Configuring the programmable logic device using the configuration information includes: configuring the programmable logic module using the first configuration information so that the configured programmable logic unit has the same function as the chip under test at the behavioral level; and configuring other components in the programmable logic device except the programmable logic module using the second configuration information so that the configured other components can cooperate with the configured programmable logic module in the process of processing the test case.

[0106] In some embodiments, the configuration information related to the chip under test is encapsulated into a firmware file; the firmware file is obtained by the following method: after compiling a high-level language programming file into a binary file by a compiler, saving it in a format supported by the coprocessor.

[0107] Specific steps of the above prototype verification method can refer to the description in the above system embodiments and will not be elaborated here.

[0108] Furthermore, an embodiment of the present disclosure also provides an electronic device, including the above prototype verification system.

[0109] Exemplarily, the electronic device includes, but is not limited to, devices such as a computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, or a server.

[0110] An embodiment of the present disclosure also provides a computer-readable storage medium, on which computer instructions are stored, and when the computer instructions are executed by a processor, the method described in any of the foregoing embodiments is implemented.

[0111] Computer-readable media includes both permanent and non-permanent, removable and non-removable media and can be implemented by any method or technology for storing information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media such as modulated data signals and carrier waves.

[0112] From the description of the above embodiments, those skilled in the art can clearly understand that the embodiments of the present disclosure can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the embodiments of the present disclosure, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disc, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the method described in each of the embodiments or some parts of the embodiments of the present disclosure.

[0113] The systems, apparatuses, modules or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, and the specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email transceiver device, a game console, a tablet computer, a wearable device, or a combination of any several of these devices.

[0114] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the method embodiments. The apparatus embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separated. When implementing the solutions of the embodiments of the present disclosure, the functions of the various modules can be implemented in one or more software and / or hardware. It is also possible to select some or all of the modules according to actual needs to achieve the purpose of the solutions of this embodiment. Those of ordinary skill in the art can understand and implement without creative efforts.

[0115] The above are only the specific implementation manners of the embodiments of the present disclosure. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principles of the embodiments of the present disclosure, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the embodiments of the present disclosure.

Claims

1. A programmable logic device, characterized in that, For prototype verification of the chip under test; the programmable logic device is embedded with a coprocessor and a memory; wherein, the memory pre-stores configuration information related to the chip under test and test cases of the chip under test; the configuration information is encapsulated in a format supported by the coprocessor; The coprocessor is configured to, in response to a start interrupt signal sent by the main processor, load the configuration information from the memory, configure the programmable logic device by using the configuration information, and start the configured programmable logic device; The programmable logic device is configured to, after being started, load the test cases from the memory, and perform prototype verification on the chip under test simulated by the configured programmable logic device through the test cases.

2. The programmable logic device according to claim 1, wherein The coprocessor, the memory, and the programmable logic device are connected through a bus.

3. The programmable logic device according to claim 1, wherein The configuration information and the test cases are stored in the memory by the main processor before sending the start interrupt signal.

4. The programmable logic device according to claim 1, wherein The programmable logic device is further configured to, after being started, process the loaded test cases, obtain a processing result and store it in the memory; and after processing the test cases, generate a completion interrupt signal sent to the main processor; Wherein, the completion interrupt signal is used to trigger the main processor to read the processing result from the memory, and obtain the prototype verification result of the chip under test according to the difference between the processing result and the actual result of the test case.

5. The programmable logic device according to claim 1, wherein The coprocessor is further configured to initialize and configure the programmable logic device by using the configuration information, and start the initialized programmable logic device; The programmable logic device is further configured to, after being started, feedback a first status signal to the coprocessor during the process of processing the test cases; the first status signal characterizes the processing progress of the test cases; The coprocessor is further configured to configure the programmable logic device based on the information related to the first status signal in the configuration information.

6. The programmable logic device according to any one of claims 1 to 5, wherein The coprocessor is further configured to periodically send a second status signal to the main processor; Wherein, the second status signal indicates the working status of the coprocessor; the second status signal is used to trigger the main processor to monitor the working status of the coprocessor.

7. The programmable logic device according to claim 6, wherein The programmable logic device is further configured to feedback a first status signal to the main processor during the process of processing the test cases; Wherein, the first status signal is used to trigger the main processor to configure the programmable logic device based on preset configuration information related to the first status signal when the second status signal indicates an exception of the coprocessor; and, when the second status signal indicates that the coprocessor is operating normally, discard the first status signal.

8. The programmable logic device according to claim 1, characterized in that, The programmable logic device further includes a programmable logic module; The configuration information includes first configuration information for the chip under test and second configuration information for the programmable logic device; The coprocessor is further configured to configure the programmable logic module using the first configuration information, so that the configured programmable logic unit has the same function as the chip under test at the behavioral level; and, configure other components in the programmable logic device other than the programmable logic module using the second configuration information, so that the configured other components can cooperate with the configured programmable logic module for the processing process of the test case.

9. The programmable logic device according to claim 1, wherein The programmable logic device and the main processor are communicatively connected based on the PCI-e protocol or the USB protocol.

10. The programmable logic device according to claim 1, characterized in that, The programmable logic device further includes a communication module and an interrupt control module; The start interrupt signal is sent from the main processor to the communication module and forwarded to the coprocessor via the interrupt control module; and / or, The completion interrupt signal generated by the programmable logic device after processing the test case is forwarded by the interrupt control module to the communication module and sent by the communication module to the main processor.

11. The programmable logic device according to claim 1, wherein The configuration information related to the chip under test is encapsulated into a firmware file; The firmware file is obtained by the following method: after compiling a high-level language programming file into a binary file by a compiler, save it in a format supported by the coprocessor.

12. The programmable logic device according to claim 1, wherein, The main processor includes an ARM processor, the coprocessor includes an MCU, and the programmable logic device includes an FPGA.

13. A prototype verification system, characterized in that, Including a main processor and the programmable logic device according to any one of claims 1 to 12.

14. An electronic device, characterized in that, Including the prototype verification system according to claim 13.

15. A prototype verification method, characterized in that, Applied to the programmable logic device according to any one of claims 1 to 12; the method is executed by a coprocessor embedded in the programmable logic device, and the method includes: In response to the start interrupt signal sent by the main processor, load the pre-stored configuration information related to the chip under test from the memory; the configuration information is encapsulated in a format supported by the coprocessor; Configure the programmable logic device using the configuration information and start the configured programmable logic device; wherein, the started programmable logic device is used to load the pre-stored test case of the chip under test from the memory and perform prototype verification on the chip under test simulated by the configured programmable logic device through the test case.

16. A computer-readable storage medium having computer instructions stored thereon, characterized in that, When the computer instruction is executed by a processor, the steps of the method according to claim 15 are implemented.

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