A DDS board and control system for an ion trap quantum computer

Abstract

The present invention discloses a DDS board for an ion trap quantum computer, comprising a CPLD circuit module, a DDS circuit module and a data communication circuit module; wherein the data communication circuit module is electrically connected to a control device of the ion trap quantum computer and the CPLD circuit module, and is used to receive a control signal sent by the control device of the ion trap quantum computer and forward it to the CPLD circuit module; the CPLD circuit module is used to generate a digital signal after delaying and amplifying the control signal, and to send the digital signal to the DDS circuit module, so that the DDS circuit module converts the digital signal into an analog signal and sends it to the ion trap quantum computer. The present invention can convert the control signal sent by the control device of the ion trap quantum computer received into an analog signal to control the ion trap quantum computer, and has the characteristics of multi-channel, high speed, short delay, etc. The present invention also provides an ion trap quantum computer control system.

Description

Technical Field

[0001] The invention relates to an ion trap quantum computer, in particular to a DDS board card of an ion trap quantum computer and an ion trap quantum computer control system. Background Art

[0002] When operating an ion trap quantum computer, the 369-nanometer laser of the ion trap quantum computer based on ytterbium ions needs to be modulated and the quantum logic gates need to be operated through the board. However, the existing boards are increasingly unable to meet people's needs in terms of communication speed, delay, number of channels, phase synchronization accuracy, etc. Therefore, there is an urgent need for a control circuit with fast communication speed, low delay, large number of channels, and high phase synchronization accuracy to meet the needs of ion trap quantum computers. Summary of the invention

[0003] In order to overcome the deficiencies of the prior art, one of the purposes of the present invention is to provide a DDS board for an ion trap quantum computer, which can solve the problems of slow speed and long delay in the control board of the ion trap quantum computer in the prior art.

[0004] The second object of the present invention is to provide an ion trap quantum computer control system that can solve the problems of slow speed and long delay in the ion trap quantum computer control board in the prior art.

[0005] One of the purposes of the present invention is achieved by the following technical solution:

[0006] A DDS board for an ion trap quantum computer, characterized in that the DDS board comprises a CPLD circuit module, a DDS circuit module and a data communication circuit module; wherein the input end of the data communication circuit module is communicatively connected to a control device of the ion trap quantum computer, and the output end is electrically connected to the CPLD circuit module, and is used to receive a control signal sent by the control device of the ion trap quantum computer and forward it to the CPLD circuit module;

[0007] The CPLD circuit module is electrically connected to the ion trap quantum computer through the DDS circuit module, and is used to delay and amplify the control signal to generate a digital signal, and send the digital signal to the DDS circuit module, so that the DDS circuit module converts the digital signal into an analog signal and sends it to the ion trap quantum computer.

[0008] Furthermore, the input end of the data communication circuit module is communicatively connected to the control device of the ion trap quantum computer through an LVDS signal line, and the output end is electrically connected to the CPLD circuit module through an LVDS signal interface.

[0009] Furthermore, the data communication circuit module adopts a half-duplex four-channel LVDS signal transceiver; wherein the LVDS signal transceiver is electrically connected to the LVDS signal line through an IDC socket, is used to receive the LVDS differential signal, and converts the LVDS differential signal into a single-ended control signal and sends it to the CPLD circuit module.

[0010] Furthermore, the data communication circuit module includes a first chip with model number SN65MLVD040RGZT and a plug connector; wherein the first chip is communicatively connected to a control device of an ion trap quantum computer via the plug connector, and is used to receive the LVDS differential signal; the first chip is communicatively connected to a CPLD circuit module, and is used to generate a single-ended control signal from the received LVDS differential signal and send it to the CPLD circuit module.

[0011] Furthermore, there are multiple DDS circuit modules; the CPLD circuit module is used to generate multiple digital signals according to the control signal, and forward each digital signal to the corresponding DDS circuit module; each DDS circuit module is used to convert the corresponding received digital signal into an analog signal and send it to the corresponding channel of the ion trap quantum computer.

[0012] Furthermore, the DDS board also includes a clock circuit module; wherein the clock circuit module and the CPLD circuit module are used to provide a clock synchronization signal for the CPLD circuit module.

[0013] Furthermore, the DDS board also includes a power supply module; wherein the power supply module is electrically connected to the CPLD circuit module, the data communication circuit module, and the DDS circuit module, and is used to convert the connected external power supply into a corresponding power supply and provide it to the CPLD circuit module, the data communication circuit module, and the DDS circuit module.

[0014] Further, the power supply module includes a first power conversion module, a second power conversion module and a third power conversion module; wherein the first power conversion module is used to connect to an external power supply and convert the external power supply into a first power supply and a second power supply; the second power conversion module is used to convert the first power supply into a third power supply; the third power conversion module is used to convert the second power supply into a fourth power supply;

[0015] The first power conversion module includes a buck chip and a temperature sensor chip, wherein the power input end of the buck chip is connected to an external power supply through an IDC socket, the first power output end outputs a first power supply, and the second power output end outputs a second power supply; the temperature sensor chip is electrically connected to the control end of the buck chip, and is used to control the buck chip to stop outputting the power supply when the temperature of the DDS board exceeds a preset value;

[0016] The second power conversion module and the third power conversion module both include a linear regulator chip, which is used to convert the first power supply into the third power supply and convert the second power supply into the third power supply, respectively.

[0017] Further, the DDS circuit module includes a second chip, a power filter module, a resistor R112, a resistor R88, a resistor R10, a resistor R40, a resistor R41, a capacitor C26 and a capacitor C87; wherein one end of the power filter module is electrically connected to port 2 of the second chip, and the other end is connected to a 1.8V power supply; the power filter module includes a resistor R90, a resistor R92, a capacitor C72, a capacitor C99 and a capacitor C112; one end of the resistor R90 is electrically connected to port 2 of the second chip, and the other end is connected to a 1.8V power supply through the resistor R92 and the capacitor C72; one end of the capacitor C112 is electrically connected to port 2 of the second chip, and the other end is connected to a 1.8V power supply; one end of the capacitor C99 is connected between the capacitor C72 and the capacitor C112, and the other end is connected between the resistor R92 and the capacitor C72;

[0018] Port 68, port 67, port 69, port 70, and port 59 of the second chip are electrically connected to the CPLD circuit module to receive a control signal sent by the CPLD circuit module;

[0019] The port 68 of the second chip is grounded through a resistor R41 and a capacitor C26, and the port 67 is grounded through a resistor R40 and a capacitor C87;

[0020] Ports 90 and 91 of the second chip are electrically connected to the ion trap quantum computer, and are used to output the generated analog signal to the ion trap quantum computer; ports 90 and 91 of the second chip are also electrically connected via a resistor R10;

[0021] Port 7, port 8, port 9 and port 10 of the second chip are electrically connected to the CPLD circuit module;

[0022] The second chip is also connected to a 3.3V power supply and a 1.8V power supply; the port 84 of the second chip is also grounded through a resistor R112, and the port 95 is grounded through a resistor R88;

[0023] The model of the second chip is AD9910BSVZ.

[0024] The second object of the present invention is achieved by adopting the following technical solution:

[0025] An ion trap quantum computer control system comprises a control board, an ion trap quantum computer and a DDS board of the ion trap quantum computer used as one of the purposes of the present invention; wherein the input end of the DDS board of the ion trap quantum computer is electrically connected to the control board, and the output end is electrically connected to the ion trap quantum computer, and is used for converting a control signal sent by the control board into an analog signal, and sending the analog signal to the ion trap quantum computer, so as to control the operation of the ion trap quantum computer.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The present invention provides a DDS board for an ion trap quantum computer, which can realize data communication between a control board of the ion trap quantum computer and the ion trap quantum computer, and realizes control of the ion trap quantum computer by receiving a control signal sent by the control board and converting it into an analog signal to send to the ion trap quantum computer. The present invention also has the characteristics of low delay, high speed, and multi-channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A module diagram of a DDS board for an ion trap quantum computer provided by the present invention;

[0029] Figure 2 A circuit diagram of a signal transceiver and a power filter module of a data communication circuit module;

[0030] Figure 3 A circuit diagram of a plug connector for a data communication circuit module;

[0031] Figure 4 One of the circuit diagrams of the CPLD chip of the CPLD circuit module;

[0032] Figure 5 The second circuit diagram of the CPLD chip of the CPLD circuit module;

[0033] Figure 6 This is the circuit diagram of the DDS circuit module;

[0034] Figure 7 is a circuit diagram of a clock circuit module;

[0035] Figure 8 is a circuit diagram of a first power conversion module;

[0036] Fig. 9 is a circuit diagram of a second power conversion module;

[0037] Fig.10 is a circuit diagram of a third power conversion module;

[0038] Fig.11 is a circuit diagram of a fourth power conversion module. DETAILED DESCRIPTION

[0039] The present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, under the premise of no conflict, the various embodiments or technical features described below can be arbitrarily combined to form a new embodiment.

[0040] The present invention provides a DDS board card for an ion trap quantum computer, such as Figure 1 As shown, it includes a CPLD circuit module, a DDS circuit module and a data communication circuit module.

[0041] The input end of the data communication circuit module is connected to the control device of the ion trap quantum computer in communication, and the output end is electrically connected to the CPLD circuit module, so as to realize data interaction between the control device of the ion trap quantum computer and the CPLD circuit module. That is, the data communication circuit module is used to receive various instructions and data issued by the control device of the ion trap quantum computer, and forward them to the CPLD circuit module.

[0042] More specifically, the input end of the data communication circuit module is electrically connected to the control board of the ion trap quantum computer through a long-distance high-speed LVDS signal line, and the output end is connected to the CPLD circuit module through an LVDS signal interface, which is used to realize data communication between the control board and the CPLD circuit module through a long-distance high-speed LVDS signal line and an LVDS signal interface, and realize signal reception and output. Furthermore, the data communication circuit module in the present invention adopts a half-duplex four-channel LVDS signal transceiver, which is used to receive the LVDS differential signal sent by the control board through an IDC socket, and convert it into a single-ended signal and send it to the CPLD circuit module to realize signal transmission. Among them, the chip of the data communication circuit module is implemented by a high-speed signal transceiver, which can process data signals of up to 250MHz, or clock synchronization signals of 125MHz, and meet the index requirements of the system's 125MHz frequency data signal communication.

[0043] More specifically, Figure 2 and Figure 3 As shown, the signal transceiver of the present invention is implemented by a chip of model SN65MLVD040RGZT. Specifically, the data communication circuit module includes a chip IC1, a chip IC6, a plug connector J1 and a power filter module.

[0044] Among them, the plug connector J1 is electrically connected to the LVDS signal line, and is used to send the received LVDS differential signal to the chip IC1 and the chip IC6 of the data communication circuit module. The chip IC1 and the chip IC6 convert the received LVDS differential signal into a single-ended control signal and send it to the CPLD circuit module. At the same time, the chip IC1 and the chip IC6 are also electrically connected to the CPLD circuit module, and are used to receive the configuration parameters of the CPLD circuit module, so as to realize the configuration of data transmission and reception, and specifically realize the configuration through the DE port, D port, R port and RE port of the chip IC1 and the chip IC6.

[0045] In addition, the power filter module includes a parallel circuit composed of multiple capacitors, which are connected between the 3.3V power supply and the chip IC1, and between the 3.3V power supply and the chip IC6 to ensure the stability of the power supply of the chip IC1 and the chip IC6. Specifically, the power filter module includes a parallel circuit composed of capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8 and capacitor C9.

[0046] More specifically, port 26 of the plug connector J1 is also electrically connected to port 3 (SDA terminal) of chip IC8, and port 27 is electrically connected to port 1 (SCL terminal) of chip IC8. Port 4 (VCC terminal) of chip IC8 is electrically connected, port 2 (VSS) is grounded, and port 4 is grounded through capacitor C10. Among them, the model of chip IC8 is 24AA02E48T. Power supply is provided to plug connector J1 through chip IC8.

[0047] The CPLD circuit module is used to delay and amplify the received control signal to generate a digital signal. The CPLD circuit module in the present invention includes a CPLD chip and a peripheral configuration circuit. The CPLD chip also stores configuration data by software burning. In this way, when powered on, the CPLD chip will automatically complete the hardware reset process and automatically use the burned software to configure the internal circuit before starting to work. Specifically, the model of the CPLD chip in the present invention is XC2C256-6FTG256CCoolRunner-II; the peripheral configuration circuit is electrically connected to the corresponding configuration pins of the CPLD chip to control the various configuration pins of the CPLD chip, so that the CPLD chip is in the correct working state and ensures the normal operation of the CPLD chip. Specifically, the various pins of the CPDL chip IC10 of the CPLD circuit module in the present invention are as follows Figure 4 and Figure 5 shown.

[0048] In addition, the CPLD chip in the present invention adopts a low voltage of 1.8V for power supply, and has low power consumption; at the same time, it has 256 macro unit circuits inside, and is rich in resources; its working clock frequency can reach up to 256MHz, which can meet the system working frequency requirement of 125MHz. The CPLD chip also has a short internal processing delay, and the input delay and the single macro unit processing delay are both in the nanosecond level, and the whole can be easily completed within the microsecond level. During production, the FTG256 standard small package is adopted, with a maximum of 184 available I / 0 pins, and the pin resources are rich, meeting the system requirements.

[0049] Furthermore, the CPLD circuit module is electrically connected to the DDS circuit module to send the generated digital signal to the DDS circuit module, so that the DDS circuit module generates an analog signal from the digital signal and sends the generated analog signal to the ion trap quantum computer to achieve control of the ion trap quantum computer.

[0050] The present invention has the characteristics of high speed and low delay, and can quickly convert instructions or data sent by the control board of the ion trap quantum computer into control signals of the ion trap quantum computer, thereby controlling the ion trap quantum computer.

[0051] Furthermore, the DDS circuit modules in the present invention are multiple. Each DDS circuit module is used to control a channel of an ion trap quantum computer. Each DDS circuit module is electrically connected to the CPLD circuit module, and is used to receive a digital signal sent by the CPLD circuit module, and convert the corresponding digital signal into an analog signal and then send it to the corresponding channel of the ion trap quantum computer, so as to realize multi-channel control of the ion trap quantum computer.

[0052] The DDS circuit module in the present invention is composed of a digital frequency synthesizer DDS chip of model AD9910BSVZ. The CPLD chip is also electrically connected to the digital frequency synthesizer DDS chip through a serial I / O port to encode the internal control register of the digital frequency synthesizer DDS chip to control the digital frequency synthesizer DDS chip.

[0053] Further, the multiple DDS circuit modules of the present invention can realize the synchronous input and output of multiple DDS circuit modules by using the SYNC_IN+ port / SYNC_IN- port / SYNC_OUT+ port / SYNC_OUT- port of the DDS chip, and can realize signal synchronization between multiple DDS chips, and the synchronization accuracy can reach nanosecond level. Specifically, the CPDL chip can be electrically connected to the SYNC_IN+ port, SYNC_IN- port, SYNC_OUT+ port, and SYNC_OUT- port of each DDS chip to send a synchronization signal to each DDS chip, thereby realizing signal synchronization of multiple DDS chips.

[0054] Specifically, Figure 6 As shown, the DDS circuit module includes a chip IC2, a filter module, a resistor R112, a resistor R88, a resistor R10 and an RC circuit. Among them, one end of the filter module is electrically connected to port 2 of the chip IC2, and the other end is connected to a 1.8V power supply to ensure the stability of the power supply connected to the chip IC2. Specifically, the filter module includes a resistor R90, a resistor R92, a capacitor C72, a capacitor C99 and a capacitor C112. One end of the resistor R90 is electrically connected to port 2 of the chip IC2, and the other end is connected to a 1.8V power supply through a resistor R92 and a capacitor C72. One end of the capacitor C112 is electrically connected to port 2 of the chip IC2, and the other end is connected to a 1.8V power supply. One end of the capacitor C99 is connected between the capacitor C72 and the capacitor C112, and the other end is connected between the resistor R92 and the capacitor C72.

[0055] Port 68, port 67, port 69, port 70, and port 59 of chip IC2 are all I / O ports, which are electrically connected to the CPLD circuit module to receive the control signal sent by the CPLD circuit module to realize the control of the DDS circuit module. For example, after the CPLD chip is powered on and started and initialized, it will send a start signal to the DDS circuit module to start the work of chip IC2; at the same time, it can also send a control signal to the DDS circuit module to control the digital-to-analog conversion of the DDS circuit module.

[0056] The RC circuit includes a resistor R40, a resistor R41, a capacitor C26 and a capacitor C87. Port 68 of the chip IC2 is grounded through the resistor R41 and the capacitor C26 in sequence, and port 67 is grounded through the resistor R40 and the capacitor C87 in sequence. The RC circuit is used to filter the IO signal sent by the CPDL circuit module.

[0057] Ports 90 and 91 of chip IC2 are electrically connected to the ion trap quantum computer, and are used to output the generated analog signals (DDS_CLKB_P, DDS_CLKB_N) to the ion trap quantum computer to control the ion trap quantum computer. Ports 90 and 91 of chip IC2 are also electrically connected via resistor R10.

[0058] Port 7, port 8, port 9 and port 10 of the chip IC2 are electrically connected to the CPLD circuit module and are used to receive the synchronous control signal sent by the CPLD circuit module to realize the synchronous input and output of multiple DDS circuit modules.

[0059] In addition, the chip IC2 is also connected to a 3.3V power supply and a 1.8V power supply to ensure normal power supply of the chip. Port 84 of the chip IC2 is also grounded through a resistor R112, and port 71 is connected to a reset signal I / O_RESET to achieve reset initialization of the chip. Port 95 of the chip IC2 is grounded through a resistor R88.

[0060] Furthermore, the present invention also includes a clock circuit module. The clock circuit module is electrically connected to the CPLD circuit module, and is used to provide a clock synchronization signal for the CPLD circuit module to ensure the clock synchronization of each signal in the system, that is, to ensure that the multi-channel digital signals generated by the CPLD circuit module remain highly synchronized. Among them, the clock circuit module in the present invention is a high-speed precision clock circuit module, which can provide an accurate 100MHz high-speed clock signal for the CPLD circuit module. Optionally, the clock circuit module of the present invention uses an ultra-low noise oscillator of model CCHD-950-25-100.000 to generate a 100MHz clock signal. Among them, the impedance of the transmission line of the clock signal is 50 ohms, which ensures signal integrity. The oscillator used in the present invention has the following advantages: a maximum rise and fall time of 3ns, and a phase noise of 40 femtoseconds, which can meet the picosecond output signal jitter requirements of the system; at the same time, its frequency stability is less than 3ppm per year, which can ensure the long-term stability of the operation of this scheme. At the same time, the present invention also uses a 100MHz external clock signal to input into the differential pin of the CPLD, which can improve the anti-interference ability of the signal. The input clock of the DDS chip of the present invention can reach up to 2 GHz, and the internal working clock frequency can reach up to 1 GSPS, which can meet the 100 MHz requirement of the external input clock of the present solution; at the same time, its output signal can reach up to 400 MHz, which meets the system requirements.

[0061] Specifically, Figure 7As shown, the clock circuit module includes MOS tube T1, inductor L9, capacitor C101, capacitor C102, resistor R167, resistor R168, capacitor C145, chip OSC1 and resistor R117. Among them, the model of MOS tube T1 is BBS84LT1G. The model of chip OSC1 is CCHD-950-25-100.000.

[0062] Among them, port 4 (power supply terminal VDD) of chip OSC1 is connected to a 3.3V power supply through inductor L9, port 2 (ground terminal GND) is grounded, and port 3 (output terminal OUT) is electrically connected to the CPLD circuit module through resistor R117, for outputting a clock synchronization signal to the CPLD circuit module.

[0063] Port 1 (NC end) of chip OSC1 is also grounded through capacitor C145. Resistor R167, resistor R168, capacitor C101, and capacitor C102 are used to filter the power supply connected to chip OSC1 to ensure stable power supply. Among them, one end of capacitor C101 and capacitor C102 are both grounded, and the other end is connected between inductor L9 and chip OSC1. One end of resistor R168 is grounded, and the other end is electrically connected to port 4 of chip OSC1 through resistor R167. Port 1 of chip OSC1 is also connected between resistor R167 and resistor R168.

[0064] The MOS transistor T1 is connected between the 3.3V power supply and the inductor L9, and the power supply of the chip OSC1 is controlled by the MOS transistor T1. The G terminal of the MOS transistor T1 is electrically connected to the port B6 (OSC_ENn) of the CPLD chip to receive the start-up signal of the CPLD chip IC10, thereby controlling the startup of the chip OSC1 of the clock circuit module.

[0065] Furthermore, the present invention also includes a power supply module, which is used to convert the connected external power supply into a corresponding internal power supply for use by the CPLD circuit module, the DDS circuit module, the data communication circuit module, etc. More specifically, the connected external power supply of the present invention is 12V, and the corresponding internal power supply is 3.6V power supply, 3.3V power supply, 2.1V power supply and 1.8V power supply, so as to provide corresponding working power supply for each circuit module and ensure the stable operation of the circuit module.

[0066] Furthermore, the power module includes a first power conversion module, a second power conversion module and a third power conversion module.

[0067] The first power conversion module is used to convert the connected external power into the first power supply and the second power supply. Specifically, the external power supply is 12V, the first power supply is 3.6V, and the second power supply is 2.1V.

[0068] The second power conversion module is used to convert the first power supply into a third power supply, wherein the third power supply is a 3.3V power supply.

[0069] The third power conversion module is used to convert the second power supply into a fourth power supply, wherein the fourth power supply is a 1.8V power supply.

[0070] Furthermore, the first power conversion module uses a step-down chip of model LTM4622AEV#PBF to convert the external 12V power supply to 3.6V and 2.1V power. At the same time, a digital temperature sensor chip of model LM75AIMM / NOPB is used to monitor the temperature of the entire DDS board. Once the temperature of the DDS board is detected to be too high, the step-down chip stops working and the power supply of the entire DDS board is cut off to protect the various devices on the DDS board, thereby improving safety.

[0071] Furthermore, the second power conversion module and the third power conversion module both use a low-noise linear regulator chip of model TPS74901RGWT to convert a 3.6V power supply into 3.3V and convert a 2.1V power supply into a 1.8V power supply.

[0072] Specifically, Figure 8 As shown, the first power conversion module includes a step-down chip IC15, a first power filter module, a second power filter module, a third power filter module, a second inductor L2, a third inductor L3, a capacitor C67, a resistor R55, a resistor R82, a resistor R53, a diode LD7, a resistor R84, and a resistor R87. Among them, the port A2, the port B3, the port D3, and the port E2 (input terminal VIN_1, input terminal VIN_2, input terminal VIN_3, and input terminal VIN_4) of the step-down chip IC15 are connected to a 12V power supply, the port D1 and the port E1 (output terminal VOUT1_1 and output terminal VOUT1_2) output a 3.6V power supply through the second inductor L2, and the port A1 and the port B1 (output terminal VOUT2_1 and output terminal VOUT2_2) output a 2.1V power supply through the third inductor L3.

[0073] The first power supply filter module includes a capacitor C73, a capacitor C75, a capacitor C74, a resistor R5 and a diode LD1. Among them, one end of the capacitor C73 is grounded, and the other end is connected between the first end of the second inductor L2 and the buck chip IC15. One end of the capacitor C75 and the capacitor C74 are both grounded, and the other end is electrically connected to the second end of the second inductor L2. The first end of the second inductor L2 is electrically connected to the buck chip IC15. One end of the resistor R5 is electrically connected to the second end of the second inductor L2, and the other end is grounded through the diode LD1.

[0074] The second power supply filter module includes a capacitor C161, a capacitor C163 and a capacitor C76. Among them, one end of the capacitor C161 is grounded, and the other end is connected to the buck chip IC15 and electrically connected to the first end of the third inductor L3. One end of the capacitor C163 and the capacitor C76 are both grounded, and the other end is electrically connected to the second end of the third inductor L3. The first end of the third inductor L3 is electrically connected to the buck chip IC15.

[0075] Port E4 of the step-down chip IC15 is grounded through a circuit connected in parallel by resistors R55 and R82, port B4 is grounded through diode LD7, connected to a 7.5V power supply through resistor R53, and grounded through resistors R84 and R87, port E3 and port A3 are grounded through capacitor C67, port B5, port C1, port C2, and port D5 (ground terminal GND_1, ground terminal GND_2, ground terminal GND_3, ground terminal GND_4) are grounded, and port C5 is grounded.

[0076] Further, the temperature detection circuit includes a temperature sensor chip IC12, a resistor R120, a resistor R121, a resistor R122, a resistor R123, a resistor R124, a resistor R125, a resistor R126, a resistor R127, a resistor R128, a capacitor C48, a resistor R143 and a diode LD7.

[0077] Port 1 of the temperature sensor chip IC12 is electrically connected to the temperature probe through resistor R124, port 2 is electrically connected to the temperature probe through resistor R125, and port 3 is electrically connected to port D2 and port B2 of the buck chip IC15 through resistor R123, and is used to control the buck chip IC15 to stop outputting power when the temperature exceeds a preset threshold.

[0078] Port 4 of the temperature sensor chip IC12 is grounded, port 5 is grounded through resistor R126, port 6 is grounded through resistor R127, port 7 is grounded through resistor R128, and port 8 is connected to a 3.3V power supply. Port 1 of the temperature sensor chip IC12 is also connected to a 3.3V power supply through resistor R121, and port 2 is connected to a 3.3V power supply through resistor R122.

[0079] One end of the resistor R120 is connected to a 3.3V power supply, and the other end is connected between the resistor R123 and the step-down chip IC15.

[0080] One end of the resistor R143 is connected to a 3.3V power supply, and the other end is connected between the temperature sensor chip IC12 and the resistor R123 through the diode LD7.

[0081] like Fig. 9As shown, the second power conversion module includes a first linear regulator chip IC11, capacitors C160, C165, C166, resistors R118 and R119. Ports 5, 6, 7 and 8 (power input IN) of the first linear regulator chip IC11 are connected to a 3.6V power supply.

[0082] One end of the capacitor C160 is grounded, and the other end is electrically connected to the port 5 , the port 6 , the port 7 , and the port 8 of the first linear regulator chip IC11 .

[0083] Port 1, port 18, port 19, and port 20 (output terminal OUT) of the first linear regulator chip IC11 output 3.3V power.

[0084] Ports 11 and 10 of the first linear regulator chip IC11 are connected to a 5.0V power supply, and port 11 is also grounded through a capacitor C165.

[0085] The ports 12 and 21 of the first linear regulator chip IC11 are grounded.

[0086] One end of the resistor R118 is electrically connected to the port 1, port 18, port 19, and port 20 of the first linear regulator chip IC11, and the other end is grounded through the resistor R119. One end of the capacitor C166 is electrically connected to the port 1, port 18, port 19, and port 20 of the first linear regulator chip IC11, and the other end is grounded. Port 16 of the first linear regulator chip IC11 is connected between the resistor R118 and the resistor R119.

[0087] Similarly, the circuit structure of the third power conversion module is the same as that of the second power conversion module. Fig.10 As shown, the third power conversion module includes a second linear regulator chip IC18, capacitors C167, C168, C169, resistors R130 and R129. Among them, ports 5, 6, 7 and 8 (power input terminals IN) of the second linear regulator chip IC18 are connected to a 2.1V power supply.

[0088] One end of the capacitor C167 is grounded, and the other end is electrically connected to the port 5 , the port 6 , the port 7 , and the port 8 of the second linear regulator chip IC18 .

[0089] Ports 1, 18, 19, and 20 (output terminals OUT) of the second linear regulator chip IC18 output 1.8V power. Ports 11 and 10 of the second linear regulator chip IC18 are connected to a 5.0V power supply. One end of the capacitor C168 is grounded, and the other end is electrically connected to ports 11 and 10 of the second linear regulator chip IC18. Ports 12 and 21 of the second linear regulator chip IC18 are grounded.

[0090] One end of the resistor R129 is electrically connected to the port 1, port 18, port 19, and port 20 of the second linear regulator chip IC18, and the other end is grounded through the resistor R130. One end of the capacitor C169 is grounded, and the other end is electrically connected to the port 1, port 18, port 19, and port 20 of the second linear regulator chip IC18. Port 16 of the second linear regulator chip IC18 is connected between the resistor R129 and the resistor R130.

[0091] Further, the present invention also includes a fourth power supply module, which is used to convert the external power supply into a fifth power supply, a sixth power supply, and a seventh power supply. Among them, the fifth power supply is a 7.5V power supply, the sixth power supply is a 7.0V power supply, and the seventh power supply is a 5.0V power supply. Specifically, the fourth power conversion module first uses a switching regulator with a model number of TPS62148RGX to convert a 12V power supply into a 7.5V power supply, and then uses a low-noise linear voltage regulator chip with a model number of LT3045EDD#PBF to convert the 7.5V power supply into a 7.0V power supply, and then uses a low-noise LDO with a model number of LT1761ES5-BYP#TRMPBF to convert the 7.5V power supply into a 5.0V power supply to provide power supply for other chips. For example, the EN terminal and the BIAS terminal of the chip IC of the second power conversion module are both connected to a 5.0V power supply. The present invention provides a variety of power supplies to ensure the normal operation of each chip.

[0092] Specifically, Fig.11 As shown, the fourth power conversion module includes chip IC22, chip IC20, chip IC21, capacitor C181, capacitor C182, resistor R166, capacitor C139, fourth inductor L4, resistor R136, resistor R134, capacitor C178, capacitor C179, capacitor C211, fifth inductor L5, capacitor C156, capacitor C183, capacitor C171, capacitor C170, resistor R131, resistor R132, capacitor C79, capacitor C173, diode C139, diode LD9, capacitor C132, resistor R176, resistor R177, capacitor C174, capacitor C155, capacitor C177, resistor R133, and resistor R135.

[0093] Port 1 and port 8 (VIN terminal and EN terminal) of chip IC22 are connected to a 12V power supply, port 4 and port 3 are grounded, port 11 is grounded, port 9 is grounded through capacitor C139, and port 5 is grounded through resistor R136.

[0094] The port 2 of the chip IC22 outputs a 7.5V power supply through the fourth inductor L4 , the port 6 is electrically connected to the second end of the fourth inductor L4 , and the first end of the fourth inductor L4 is electrically connected to the port 2 of the chip IC22 .

[0095] One end of the resistor R134 is electrically connected to the second end of the fourth inductor L4 , and the other end of the resistor R134 is grounded via the resistor R136 , and the port 5 of the chip IC22 is connected between the resistor R134 and the resistor R136 .

[0096] One end of the capacitor C178 is electrically connected to the second end of the fourth inductor L2, and the other end is grounded. One end of the capacitor C179 is electrically connected to the second end of the fourth inductor L2, and the other end is grounded. One end of the capacitor C211 is electrically connected to the second end of the fourth inductor L4, and the other end is grounded.

[0097] One end of the resistor R166 is electrically connected to the port 1 and the port 8 of the chip IC22, and the other end is electrically connected to the port 10 of the chip IC22. One end of the capacitor C181 and the capacitor C182 are both grounded, and the other end are both electrically connected to the port 1 and the port 8 of the chip IC22.

[0098] Port 2 of chip IC22 is also electrically connected to the first end of the fifth inductor L5 through the fourth inductor L4. The second end of the fifth inductor L5 is electrically connected to port 1 of chip IC20. One end of capacitor C71 is electrically connected to port 1 of chip IC20, and the other end is grounded. One end of capacitor C183 is grounded, and the other end is connected between the second end of the fifth inductor L5 and port 1 of chip IC20.

[0099] The port 2 of the chip IC20 is grounded, and the port 3 is electrically connected to the port 5 of the chip IC20. The port 5 of the chip IC20 outputs a 5.0V power supply.

[0100] Port 4 of chip IC20 is grounded through resistor R132. One end of resistor R131 is grounded through resistor R132, and the other end is electrically connected to port 5 of chip IC20. Port 4 of chip IC20 is connected between resistor R131 and resistor R132.

[0101] The negative electrode of the capacitor C79 is grounded, and the positive electrode is electrically connected to the port 5 of the chip IC20. One end of the capacitor C173 is grounded, and the other end is electrically connected to the port 5 of the chip IC20.

[0102] Ports 1, 2, and 3 of the chip IC21 are all electrically connected to the second end of the fifth inductor L5, and ports 9 and 10 output 7.0V power. The negative electrode of the capacitor C156 is grounded, and the positive electrode is electrically connected to the second end of the fifth inductor L5. One end of the capacitor C132 is grounded, and the other end is electrically connected to the second end of the fifth inductor L5.

[0103] Port 5 of chip IC21 is grounded, port 6 is grounded through resistor R176, ports 8 and 11 are grounded, port 7 is grounded through capacitor C174, and port 7 is grounded through resistor R33 and resistor R135. One end of capacitor C55 is grounded, and the other end is electrically connected to ports 9 and 10 of chip IC21. One end of capacitor C177 is grounded, and the other end is electrically connected to ports 9 and 10 of chip IC21.

[0104] One end of the resistor R177 is grounded through the resistor R176 , and the other end is electrically connected to the port 9 and the port 10 of the chip IC21 .

[0105] The present invention provides high-precision 0.25Hz frequency resolution, 400MHz high-speed output signal, nanosecond synchronization accuracy, and microsecond low-delay analog signal to drive the control of the ion trap quantum computer. The host computer or the control board of the ion trap quantum computer can directly control the ion trap quantum computer through the DDS board card provided by the present invention, without the need for other circuit modules, thereby simplifying the operation mode of the ion trap quantum computer. At the same time, the present invention can also realize the control of multi-channel ion trap quantum computers, with the characteristics of low delay and high synchronization accuracy.

[0106] Based on the DDS board of the ion trap quantum computer provided by the present invention, the present invention also provides another embodiment, an ion trap quantum computer control system, comprising a control board, an ion trap quantum computer and the DDS board of the aforementioned ion trap quantum computer. Among them, the input end of the DDS board of the ion trap quantum computer is electrically connected to the control board, and the output end is electrically connected to the ion trap quantum computer, and is used to convert the control signal sent by the control board into an analog signal for controlling the ion trap quantum computer, so as to realize the control of the ion trap quantum computer. Through the present invention, there is no need for additional control equipment, and the host computer, control board and other equipment can realize the control of the ion trap quantum computer.

[0107] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. A DDS board for an ion trap quantum computer. It is characterized in that The DDS board includes a CPLD circuit module, a DDS circuit module and a data communication circuit module; wherein the input end of the data communication circuit module is communicatively connected to the control device of the ion trap quantum computer, and the output end is electrically connected to the CPLD circuit module, and is used to receive the control signal sent by the control device of the ion trap quantum computer and forward it to the CPLD circuit module; The CPLD circuit module is electrically connected to the ion trap quantum computer through the DDS circuit module, and is used to delay and amplify the control signal to generate a digital signal, and send the digital signal to the DDS circuit module, so that the DDS circuit module converts the digital signal into an analog signal and sends it to the ion trap quantum computer; The DDS circuit module includes a second chip, a power filter module, a resistor R112, a resistor R88, a resistor R10, a resistor R40, a resistor R41, a capacitor C26 and a capacitor C87; wherein one end of the power filter module is electrically connected to the port 2 of the second chip, and the other end is connected to a 1.8V power supply; the power filter module includes a resistor R90, a resistor R92, a capacitor C72, a capacitor C99 and a capacitor C112; one end of the resistor R90 is electrically connected to the port 2 of the second chip, and the other end is connected to the 1.8V power supply through the resistor R92 and the capacitor C72; one end of the capacitor C112 is electrically connected to the port 2 of the second chip, and the other end is connected to the 1.8V power supply; one end of the capacitor C99 is connected between the capacitor C72 and the capacitor C112, and the other end is connected between the resistor R92 and the capacitor C72; Port 68, port 67, port 69, port 70, and port 59 of the second chip are electrically connected to the CPLD circuit module to receive a control signal sent by the CPLD circuit module; The port 68 of the second chip is grounded through a resistor R41 and a capacitor C26, and the port 67 is grounded through a resistor R40 and a capacitor C87; Ports 90 and 91 of the second chip are electrically connected to the ion trap quantum computer, and are used to output the generated analog signal to the ion trap quantum computer; ports 90 and 91 of the second chip are also electrically connected via a resistor R10; Port 7, port 8, port 9 and port 10 of the second chip are electrically connected to the CPLD circuit module; The second chip is also connected to a 3.3V power supply and a 1.8V power supply; port 84 of the second chip is also grounded through a resistor R112, and port 95 is grounded through a resistor R88.

2. The DDS board of the ion trap quantum computer according to claim 1, It is characterized in that The input end of the data communication circuit module is connected to the control device of the ion trap quantum computer through an LVDS signal line, and the output end is electrically connected to the CPLD circuit module through an LVDS signal interface.

3. The DDS board of the ion trap quantum computer according to claim 2, It is characterized in that The data communication circuit module adopts a half-duplex four-channel LVDS signal transceiver; wherein the LVDS signal transceiver is electrically connected to the LVDS signal line through an IDC socket, is used to receive LVDS differential signals, and converts the LVDS differential signals into single-ended control signals and then sends them to the CPLD circuit module.

4. The DDS board of the ion trap quantum computer according to claim 3, It is characterized in that The data communication circuit module includes a first chip with model number SN65MLVD040RGZT and a plug connector; wherein the first chip is communicatively connected to a control device of an ion trap quantum computer via the plug connector, and is used to receive the LVDS differential signal; the first chip is communicatively connected to a CPLD circuit module, and is used to generate a single-ended control signal from the received LVDS differential signal and send it to the CPLD circuit module.

5. The DDS board of the ion trap quantum computer according to claim 1, It is characterized in that There are multiple DDS circuit modules; the CPLD circuit module is used to generate multiple digital signals according to the control signal and forward each digital signal to the corresponding DDS circuit module; each DDS circuit module is used to convert the received corresponding digital signal into an analog signal and send it to the corresponding channel of the ion trap quantum computer.

6. The DDS board of the ion trap quantum computer according to claim 1, It is characterized in that The DDS board also includes a clock circuit module; wherein the clock circuit module is electrically connected to the CPLD circuit module and is used to provide a clock synchronization signal for the CPLD circuit module.

7. The DDS board of the ion trap quantum computer according to claim 1, It is characterized in that The DDS board also includes a power supply module; wherein the power supply module is electrically connected to the CPLD circuit module, the data communication circuit module, and the DDS circuit module, and is used to convert the connected external power supply into a corresponding power supply and provide it to the CPLD circuit module, the data communication circuit module, and the DDS circuit module.

8. The DDS board of the ion trap quantum computer according to claim 7, It is characterized in that The power supply module includes a first power conversion module, a second power conversion module and a third power conversion module; wherein the first power conversion module is used to connect to an external power supply and convert the external power supply into a first power supply and a second power supply; the second power conversion module is used to convert the first power supply into a third power supply; the third power conversion module is used to convert the second power supply into a fourth power supply; The first power conversion module includes a buck chip and a temperature sensor chip, wherein the power input end of the buck chip is connected to an external power supply through an IDC socket, the first power output end outputs a first power supply, and the second power output end outputs a second power supply; the temperature sensor chip is electrically connected to the control end of the buck chip, and is used to control the buck chip to stop outputting the power supply when the temperature of the DDS board exceeds a preset value; The second power conversion module and the third power conversion module both include linear regulator chips, which are used to convert the first power supply into the third power supply and convert the second power supply into the fourth power supply, respectively.

9. The DDS board of the ion trap quantum computer according to claim 1, It is characterized in that The model of the second chip is AD9910BSVZ.

10. An ion trap quantum computer control system, It is characterized in that The invention comprises a control board, an ion trap quantum computer and a DDS board of an ion trap quantum computer as claimed in any one of claims 1 to 9; wherein the input end of the DDS board of the ion trap quantum computer is electrically connected to the control board, and the output end is electrically connected to the ion trap quantum computer, and is used for converting the control signal sent by the control board into an analog signal, and sending the analog signal to the ion trap quantum computer, so as to control the operation of the ion trap quantum computer.

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