Control Circuit, Read Switch Driving Circuit, and Control Method

Abstract

This application describes circuits and methods for controlling a bit line precharge circuit. For example, the control circuit includes a first latch circuit and a second latch circuit. The first latch circuit is configured to receive a first shallow sleep signal. The first latch circuit generates a second shallow sleep signal based on a clock signal. The second latch circuit is configured to receive the second shallow sleep signal. The second latch circuit generates a third shallow sleep signal based on a sense amplifier enable signal. The second latch circuit provides the third shallow sleep signal to a bit line read switch, thereby cutting off the bit line of the read switch after the sense amplifier is enabled. Embodiments of this application also provide a control circuit, a read switch driving circuit, and a method for controlling a bit line precharge circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to a control circuit, a read switch driving circuit, and a method of controlling a bit line precharge circuit. Background Art

[0002] A static random access memory (SRAM) is a type of semiconductor memory that stores each bit in a memory array using bistable latch circuits. SRAM stores data in the memory array without the need to refresh upon power-up, but is still volatile, such that data will eventually be lost when the memory is not powered. Power gating and voltage holding techniques are commonly used in the memory array to reduce power consumption. For example, power gating can be used to turn off memory peripherals in deep sleep mode and to turn off peripherals and the memory array in the off mode. When the memory exits the off mode, power gating is used to boost the internal supply voltage of the memory. This results in a large wake-up surge current. Summary of the Invention

[0003] According to one aspect of embodiments of the present application, a control circuit is provided, including: a first latch circuit configured to receive a first shallow sleep signal, wherein the first latch circuit generates a second shallow sleep signal according to a clock signal; and a second latch circuit configured to receive the second shallow sleep signal, wherein the second latch circuit generates a third shallow sleep signal according to a sense amplifier enable signal, wherein the second latch circuit provides the third shallow sleep signal to a bit line read switch, so as to cut off the bit line of the read switch after the sense amplifier is enabled.

[0004] According to another aspect of embodiments of the present application, a read switch driving circuit is provided, including: a latch circuit configured to receive a sleep signal and a sense amplifier enable signal; the latch circuit is configured to delay an activation signal of a read switch located between a memory and a bit line of a sense amplifier, such that the sense amplifier enable signal is before the read switch activation signal.

[0005] According to still another aspect of embodiments of the present application, a method of controlling a bit line precharge circuit is provided, including: providing a sense amplifier enable signal to a latch to delay a first activation signal, such that the first activation signal is asserted after a sense amplifier signal, wherein the first activation signal is provided to a read switch; delaying the first activation signal to generate a second activation signal, wherein the second activation signal activates the bit line precharge circuit only after the first activation signal is provided to the read switch. Brief Description of the Drawings

[0006] As will be best understood by reference to the following detailed description when read in conjunction with the accompanying drawings, various aspects of the present invention will be best understood. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be increased or decreased arbitrarily.

[0007] Corresponding numbers and symbols in different figures generally refer to corresponding parts, unless otherwise specified. The drawings are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0008] Figure 1 is a block diagram illustrating an example memory device in accordance with various embodiments of the present disclosure.

[0009] Figure 2 is a block diagram illustrating another example memory device in accordance with various embodiments of the present disclosure.

[0010] Figure 3 is a block diagram illustrating an example memory device in accordance with various embodiments of the present disclosure.

[0011] Figure 4 is a circuit schematic diagram illustrating an example shallow sleep latch circuit coupled to a latch circuit.

[0012] Figure 5 is illustrating various waveforms associated with a memory device in accordance with various embodiments of the present disclosure Figure 3 in an example timing diagram.

[0013] Figure 6 is a block diagram illustrating an example memory device in accordance with various embodiments of the present disclosure.

[0014] Figure 7 is a block diagram illustrating an example delay structure in accordance with various embodiments of the present disclosure.

[0015] Figure 8 is a block diagram illustrating another example delay structure in accordance with various embodiments of the present disclosure.

[0016] Figure 9 is illustrating various waveforms associated with a memory device 600 in accordance with various embodiments of the present disclosure Figure 6 in an example timing diagram.

[0017] Figure 10 is a circuit schematic diagram illustrating another example delay structure in accordance with various embodiments of the present disclosure.

[0018] Figure 11 is a process flow diagram illustrating a method of controlling a bit line precharge circuit. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0021] Some embodiments of the present disclosure are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the stages described may be replaced or eliminated. Additional features may be added to the semiconductor device. For different embodiments, some of the features described below may be replaced or eliminated. Although some embodiments discuss operations performed in a specific order, these operations may be performed in another logical order.

[0022] Electronic circuits are often composed of various subcomponents that each undertake a specific set of functions. Some of those functions may not be applicable to all circuit operating modes. Subcomponents of a circuit can be selectively activated or deactivated based on the current or future state of the circuit (e.g., the desired next state of the circuit). By deactivating subcomponents, certain power savings can be achieved.

[0023] As the demand for circuit speed performance increases, the tolerance for circuit operation hysteresis that facilitates subcomponent activation / deactivation decreases. Circuits may be designed to begin activating / deactivating components in anticipation of the next operating cycle while the current operating cycle is still ongoing. However, speed performance gains that may be achieved through aggressive power management may be undesirable if such power management has an adverse effect on operation in the current operating cycle.

[0024] The circuits and methods described herein provide a power management control circuit that ensures that the power management control state of the next operation cycle does not impair the circuit operation in the current operation cycle. In an embodiment, certain latch circuits are provided that ensure that the bit line read switch (which may take the form of a read-transfer-transistor in an embodiment) is not disabled before the sense amplifier is enabled. Without such a latch circuit, a sleep signal that is intended to deactivate certain sub-components in the next operation cycle may cut off the bit line read switch before the sense amplifier is enabled, isolating the bit lines before the sense amplifier can output the result of a read operation. In some cases, such isolation may result in an incorrect data output for the read operation in the current operation cycle.

[0025] Figure 1 is a block diagram illustrating an example memory device 100 in accordance with various embodiments of the present disclosure. The memory device 100 is formed of many electronic components and, among other things, the memory device 100 includes a memory array 110 and a local control circuit 120, such as those described in more detail in Figure 2 The memory array 110 includes a plurality of memory cells (also referred to as bit cells) configured to store information in the form of "0" or "1". The process of storing information into the memory array 110 is referred to as "writing". The process of reading the information stored on the memory array 110 is referred to as "reading". Reading and writing are example functions of the memory device 100. To perform these functions, some of the electronic components that make up the memory device 100 need power and need to be turned on. However, not all electrical components need to be powered during these functions and can be temporarily turned off (e.g., enter a sleep mode). The process of turning on or off certain electronic components in the memory device is referred to as power management. The power management of the memory device 100 uses a series of power management signals sent to the electrical components to tell them whether to be turned on or off. When the power is turned off or minimized, some electrical components take some time to turn on or wake up. To enable functions such as reading and writing to operate smoothly, the components performing a particular operation should be kept powered with minimal or no impact, while other electrical components are turned on or off.

[0026] The latch circuit 122 and the delay circuit 124 (e.g., a first delay circuit) of the local control circuit 120 can be used to assist in the operation of the power management signals and the smooth transition of turning on / off components within the memory device. The latch circuit 122 and the delay circuit 124 work together, as described in more detail in Figure 3 to generate power management signals (such as a sleep signal) to turn on / off specific electronic components without affecting the read or write functions of the memory device 100.

[0027] Figure 2is a block diagram illustrating another example memory device 200 in accordance with various embodiments of the present disclosure. Similar to the memory device 100, the memory device 200 can be a random access memory, such as a static random access memory (SRAM) device or other types of memory devices, such as a dynamic random access memory (DRAM) device. As Figure 2 shown, the memory device 200 includes at least one memory array 110 and a plurality of peripheral circuits, such as word line (WL) driver circuits 220, local input / output (IO) circuits 230, local control circuits 120, global IO circuits 250, global control circuits 260, and a power control circuit or power controller 270. The memory device 200 may include Figure 2 other components not shown in

[0028] The memory array 110 includes bit cells arranged in a matrix of rows and columns. Each memory cell of the memory array 110 is used to store one bit of information. For example, in some SRAM implementations, each memory cell uses six transistors connected between an upper reference potential and a lower reference potential (usually ground), such that one of two storage nodes can be occupied by the information to be stored and complementary information is stored at the other storage node.

[0029] The memory array 110 includes a plurality of word lines and a plurality of bit line pairs. Each memory cell of the memory array 110 is connected to a word line and a bit line pair. The word lines are used to activate access to the memory cells of the row connected to the word line. The bit line pairs are used to access the information stored or to be stored in the memory cells activated by the word line. Although, for ease of discussion, the memory device 200 is shown as including only one memory array 110, the memory device 200 may include a plurality of memory arrays 110.

[0030] The peripheral devices include circuits that provide various functions of the memory device 200 associated with the memory array 110. For example, the word line driver circuit 220 of the memory device 200 is used to select a word line of the memory array 110 and charge the selected word line to a logic high. The logic high is approximately equal to a first predetermined potential. In an example embodiment, the word line driver circuit 220 is a decoder circuit that includes a plurality of logic operators to decode the potential on the address lines to identify the word line to be activated. The address lines are charged to a logic high (i.e., approximately equal to the first potential) or a logic low (i.e., approximately equal to the second potential). In an example embodiment, the second predetermined potential is approximately equal to the ground potential or zero volts. The logic high is represented by a bit 1 and the logic low is represented by a bit 0.

[0031] The local IO circuit 230 of the memory device 200 is used to read data from the memory array 110 and write data into the memory array 110. For example, the local IO circuit 230 is used to sense the potentials at a plurality of bit line pairs and compare the potentials of each pair. In an exemplary embodiment, when the potential of the first bit line of the bit line pair is greater than the potential of the second bit line, the local IO circuit 230 reads the output as logic 1. In addition, when the potential of the first bit line of the bit line pair is less than the potential of the second bit line, the local IO circuit 230 reads the output as logic 0.

[0032] The local control circuit 120 of the memory device 200 is used to control the local IO circuit 230. For example, the local control circuit 120 is used to configure the local IO circuit 230 into a read mode to read information from the memory array 110 or into a write mode to write information into the memory array 110. In addition, the local control circuit 120 is used to enable the local IO circuit 230 in a hold mode where no data is read from or written to the memory array 110.

[0033] The global IO circuit 250 of the memory device 200 is used to combine the input / output from the local IO circuit 230. For example, the memory device 200 may include a plurality of memory arrays 110, each memory array 110 having its own local IO circuit 230. The global IO circuit 250 is used to combine the information from the plurality of local IO circuits 230 into the global IO of the memory device 200. For example, the local IO circuit 230 is used to store the output from the memory array 110 in a shift register, and the global IO circuit 250 is used to read data from the shift register and provide the data as the output of the memory device 200.

[0034] The global control circuit 260 of the memory device 200 is used to control the global IO circuit 250. For example, the global control circuit 260 is used to configure the global IO circuit 250 to select one or more local IO circuits 230 to read data or write data. In another example, the global control circuit 260 is used to configure the read sequence of the global IO circuit 250 to read data from one or more local IO circuits 230, or the write sequence to write data into one or more local IO circuits 230.

[0035] The power control circuit 270 is used to control and manage the power supply of one or more components of the memory device 200. In some embodiments, for example, the power control circuit 270 is used to selectively connect one or more components of the memory device 200 to a voltage terminal. The power control circuit 270 includes a plurality of logic gates or power gates. Each of the plurality of power gates is used to power on or power off the associated component of the memory device 200. The power gates are enabled by signals. For example, a first signal enables the power gate to power on the component, and a second signal enables the power gate to power off the component.

[0036] Figure 3 is a block diagram illustrating an example memory device 300 according to various embodiments of the present disclosure. The memory device 300 shows additional components that can be implemented in either the memory device 100 Figure 1 or the memory device 200 Figure 2 . The memory device 300 is configured to receive a plurality of signals that facilitate operation, including a shallow sleep signal (LSLP), a write enable signal (WE), a clock signal (CLK), and a clock enable signal (CE). In addition, the memory device 300 receives address signals. The global control circuit 260 includes a shallow sleep latch circuit 302, a write enable latch circuit 304, a clock generator 306, and an address latch and column decoder component 308. The shallow sleep latch circuit 302 receives the shallow sleep signal (LSLP) (a binary logic signal) from an external input. The shallow sleep latch circuit 302 generates a second shallow sleep signal (LLSLP) that is provided to the local control circuit 120. The second shallow sleep signal (LLSLP) is generated using two inputs: the shallow sleep signal (LSLP) and an internal clock signal (ICLK) generated by the clock generator 306. When the LSLP signal is logic high (e.g., "1") and the internal clock signal (ICLK) transitions to logic low (e.g., "0"), the output of the shallow sleep latch circuit 302 (e.g., the second shallow sleep signal (LLSLP)) is logic high (e.g., "1"). Further details regarding these signals are described in the timing diagram 500 Figure 5 .

[0037] The Light Sleep Signal (LSLP) is a signal for enabling the light sleep mode. When the light sleep mode is enabled, all supply voltages to the word lines and bit lines within the memory device 300 are turned off. More specifically, the write enable latch circuit 304 receives a write enable signal (WE) from an external input and generates an internal clock signal (ICLK) by the clock generator 306. The write enable latch circuit 304 generates a light write enable signal (LWE) based on these two inputs. For example, when the write enable signal (WE) is logic high (e.g., "1"), the write enable latch circuit 304 outputs a light write enable signal (LWE) that is also logic high (e.g., "1") to the local control circuit 120. When the write enable signal is logic high (e.g., "1"), the memory device 300 performs a write operation. When the write enable signal (WE) is logic low (e.g., "0"), the light write enable signal is also logic low (e.g., "0") and the memory device 300 performs a read operation. The clock generator 306 receives a clock signal (CLK) and a clock enable signal (CE). The clock enable signal (CE) drives the operation of the memory device 300. When the clock enable signal (CE) is logic high (e.g., "1"), the memory device 300 is operable and generates an internal clock signal (ICLK). When the clock enable signal (CE) is logic low (e.g., "0"), the memory device 300 is inoperable and does not generate an internal clock signal (ICLK). The clock generator 306 outputs the internal clock signal (ICLK) to the local control circuit 120. The address latch and column address decoder 308 receive an address and output the decoded address to the local control circuit 120.

[0038] The local control circuit 120 includes a latch circuit 122, a delay element 124, a word line / bit line tracking delay component 310, logic gates 312, 314, and an inverter 316. The local control circuit 120 receives a second shallow sleep signal (LLSLP), a shallow write enable signal (LWE), an internal clock signal (ICLK), and a decoded address from the global control circuit. More specifically, the latch circuit 122 receives the second shallow sleep signal (LLSLP). The latch circuit 122 generates a third shallow sleep signal (LLSLP_SAE) based on the sense amplifier enable signal (SAE) it receives from the output of the word line / bit line tracking delay component 310, and this signal is fed back to the latch circuit 122. More specifically, the sense amplifier enable signal (SAE) is generated by the word line / bit line tracking delay component 310. When the memory device 300 switches from performing a read operation to a write operation, the sense amplifier enable signal (SAE) is logic high (e.g., "1"). When the sense amplifier enable signal (SAE) goes high, the latch circuit 122 holds the previous value of the second shallow sleep signal (LLSLP). Alternatively, when the sense amplifier enable (SAE) signal is logic low (e.g., "0"), the current value of the second shallow sleep signal (LLSLP) is output as the third shallow sleep signal (LLSLP_SAE). Further details of these signals are described with respect to Figure 5 the timing diagram 500.

[0039] The latch circuit 122 provides the third shallow sleep signal (LLSLP_SAE) to the logic gate 312. The logic gate 312 evaluates the presence of the third shallow sleep signal (LLSLP_SAE) and the shallow write enable signal (LWE). Figure 3The illustrated logic gate 312 is a NAND gate. When both the third light sleep signal (LLSLP_SAE) and the light write enable signal (LWE) are logic low (e.g., “0”), the output of the logic gate 312 (the read bit signal (READB)) is logic high. When both the third light sleep signal (LLSLP_SAE) and the light write enable signal (LWE) are logic high (e.g., “1”), the output of the logic gate 312 is logic low. The read bit signal (READB) is coupled to the bit line read switches of the local input / output 230 (e.g., transistors 318RBL and transistor 320RBLB). Based on the read bit signal (READB), the bit lines of the read switches are disconnected after the sense amplifier 322 is enabled. For example, when the sense amplifier enable signal (SAE) is logic high (e.g., “1”), after a time delay, the read bit signal (READB) is also logic high (e.g., “1”). This occurs due to the comparison performed by the logic gate 312. Based on the logical comparison (e.g., OR comparison) between the third light sleep signal (LLSLP_SAE), the light write enable signal (LWE), and the sense amplifier enable signal (SAE), the sense amplifier 322 outputs a data signal to the output latch circuit 350 of the global input / output circuit 250.

[0040] Logic gate 314 evaluates the presence of both the third sleep signal (LLSLP_SAE) and the internal clock signal (ICLK). In Figure 3 the example, logic gate 314 is a NAND gate. When both the third light sleep signal (LLSLP_SAE) and the internal clock signal (ICLK) are logic low (e.g., “0”), the output of logic gate 314, the bit line precharge signal (BLPCH), is logic high. When both the third light sleep signal (LLSLP_SAE) and the internal clock signal (ICLK) are logic high (e.g., “1”), the output of logic gate 314 is logic low. The bit line precharge signal (BLPCHB) drives the operation of the precharge circuit 340. When the memory device 300 is placed in the light sleep mode using the light sleep signal (LSLP), all bit lines are disconnected from their respective power supplies. This occurs when the bit line precharge signal (BLPCH) is logic low (e.g., “0”).

[0041] The local input / output circuit 230 includes a plurality of transistors 324, 326, 328, 330, 332, 334, 336, 338, bit line read switches 318, 320, a sense amplifier 322, and a precharge circuit 340. The transistors 324, 326, 328, 330, 332, 334, 338 receive address input / output from the inverter 316. The inverter 316 inverts the decoded address received from the address latch and column address decoder circuit 308. Each of the transistors 324, 326, 328, 330, 332, 334, 338 is coupled to a bit line BL / BLB. The gates of the transistors 324, 326, 328, 330, 332, 334, 338 are each coupled to the output of the inverter 316 and receive an inverted version of a portion of the decoded address. For example, the transistors 324, 338 receive the address portion of the bit line pair (e.g., BL0 / BLB0) to which they are coupled. The transistors 326, 336 receive the address portion of the bit line pair (e.g., BL1 / BLB1) to which they are coupled. The transistors 328, 334 receive the address portion of the bit line pair (e.g., BL2 / BLB2) to which they are coupled. The transistors 330, 332 receive the address portion of the bit line pair (e.g., BL3 / BLB3) to which they are coupled. When the address portion for the gate of one or more of the transistors 324, 326, 328, 330, 332, 334, 338 is logic low (e.g., "0"), the corresponding transistor conducts. Alternatively, when the address is logic high (e.g., "1") for the address portion of the gate of one or more of the transistors 324, 326, 328, 330, 332, 334, 338, the corresponding transistor is cut off, and the voltage coupled to the source / drain terminal of that transistor passes through that transistor. This operation is Figure 10 explained in more detail in

[0042] The power supply of the word line driver 220 is managed using the logic gate 342. The logic gate 242 generates a word line sleep signal (SLP_WL) based on an input shallow sleep delay signal (LSD), a second shallow sleep signal (LLSLP) output from the shallow sleep latch circuit 302, and a shallow sleep delay signal (LDSLP). The word line sleep signal (SLP_WL) is provided to the gate terminal of the transistor 344. When the transistor 344 is closed, the drive voltage VDD is provided to the word line driver 220. The word line driver 220 operates the 6TSRAM cells 346, 348. Figure 3 WLTOP in Figure 3WL0 therein represents the first row within the memory device 300. To enable the word lines within the memory device 300, the complementary bit line pair BL3 / BLB3 should be cut off. This occurs when the address portion is logic high (e.g., "1"). This in turn discharges the read bit line pair (e.g., RBL / RBLB) and as a result the 6TSRAM cells 346, 348 store logic high (e.g., "1").

[0043] Figure 4FIG. 0 is a circuit schematic diagram showing an example shallow sleep latch circuit 302 coupled to a latch circuit 120. The shallow sleep latch circuit 302 includes inverters 402, 412, 438 and a plurality of transistors 404, 406, 408, 410, 440, 442, 444, 446. The shallow sleep latch circuit 302 receives a shallow sleep signal (LSLP) that drives PMOS transistor 410 and NMOS transistor 404. The shallow sleep latch circuit 302 outputs a second shallow sleep signal (LLSLP) to the latch circuit 122 of the local control circuit 120. The latch circuit 122 includes a logic gate 414 that evaluates a sense amplifier enable signal (SAE) and a delayed internal clock signal (ICLKD) and outputs a signal (e.g., ICLKD_OR_SAE) based on a logical comparison. When the sense amplifier enable signal (SAE) or the delayed internal clock signal (ICLKD) is logic high (e.g., “1”), the output signal (e.g., ICLKD_OR_SAE) is logic high (e.g., “1”). When both the sense amplifier enable signal (SAE) and the delayed internal clock signal (ICLKD) are logic low (e.g., “0”), the output signal (e.g., ICKD_OR_SAE) of the logic gate 414 is logic low (e.g., “0”). The latch circuit 122 also includes a plurality of inverters 422, 426, 430 and a plurality of transistors 416, 418, 420, 424, 428, 432, 434 and 436. The gate terminals of transistor 416 and transistor 424 both receive the second shallow sleep signal (LLSLP). When the second shallow sleep signal (LLSLP) is logic high (e.g., “1”), transistor 416 turns off and transistor 424 operates. Alternatively, when the second shallow sleep signal (LLSLP) is logic low (e.g., “0”), transistor 424 turns off and transistor 416 operates. The gate terminal of transistor 418 receives the output signal (e.g., ICLKD_OR_SAE) of the logic gate 414. The gate terminal of transistor 420 is coupled to the output of inverter 422. Inverter 422 inverts the output (e.g., ICLKD_OR_SAE) of the logic gate 414. When the output (e.g., ICLKD_OR_SAE) of the logic gate 414 is logic high (e.g., “1”), transistors 418, 420 turn off. When the output (e.g., ICLKD_OR_SAE) of the logic gate 414 is logic low (e.g., “0”), transistors 418, 420 operate. Transistors 428, 432, 434, 436 operate in a similar manner.Inverter 426 outputs a third shallow sleep signal (LLSLP_SAE) that delays the activation signal (e.g., READB) to a read switch (e.g., transistors 318, 320) located between the bit line and sense amplifier 322 of memory 300, so that the sense amplifier enable signal (SAE) precedes the read switch activation signal (READB).

[0044] Figure 5 is a diagram illustrating various embodiments according to the present disclosure Figure 3 An example timing diagram 500 of various waveforms associated with the memory device 300 is shown. Figure 5 As shown, LLSLP is latched by latch circuit 122 using the internal clock signal (ICLK) and the sense amplifier enable signal (SAE) to generate a third sleep signal (LLSLP_SAE). Figure 3 As explained in , the latch circuit 122 generates the third shallow sleep signal (LLSLP_SAE) according to the sense amplifier enable signal (SAE) received from the output of the word line / bit line tracking delay component 310, and the sense amplifier enable signal (SAE) is fed back to the latch circuit 122. More specifically, the sense amplifier enable signal (SAE) is generated by the word line / bit line tracking delay component 310. When the memory device 300 switches from performing a read operation to a write operation, the sense amplifier enable signal (SAE) is logic high (e.g., "1"). When the sense amplifier enable signal (SAE) becomes high, the latch circuit 122 maintains the previous value of the second shallow sleep signal (LLSLP). Alternatively, when the sense amplifier enable (SAE) signal is logic low (e.g., "0"), the current value of the second shallow sleep signal (LLSLP) is output as the third shallow sleep signal (LLSLP_SAE). Therefore, after the sense amplifier enable signal (SAE) rises to a logic high (e.g., "1"), the third sleep signal (LLSLP_SAE) rises to a logic high (e.g., "1"). The bit line read signal (READB) is controlled by the third shallow sleep signal (LLSLP_SAE). The logic gate 312 evaluates the presence of the third shallow sleep signal (LLSLP_SAE) and the shallow write enable signal (LWE). Figure 3The illustrated logic gate 312 is a NAND gate. When both the third shallow sleep signal (LLSLP_SAE) and the shallow write enable signal (LWE) are logic low (e.g., "0"), the output of the logic gate 312, the read bit signal (READB), is logic high. When both the third shallow sleep signal (LLSLP_SAE) and the shallow write enable signal (LWE) are logic high (e.g., "1"), the output of the logic gate 312 is logic low. Thus, after the sense amplifier enable (SAE) rises to logic high (e.g., "1"), the bit line read signal (READB) also rises to logic high (e.g., "1"), which ensures that the sense amplifiers 322 are enabled before their inputs are disconnected from the bit lines BL / BLB. Thus, the voltages on the bit lines BL and BLB have sufficient time to discharge, and the Q output by the sense amplifiers 322 is accurate.

[0045] Figure 6 is a block diagram illustrating an example memory device 600 in accordance with various embodiments of the present disclosure. Figure 6 The components of Figure 3 are similar to those Figure 6 described in Figure 3 The memory device 600 differs from the memory device 300 of Figure 3 in that it includes an additional delay component 602. The delay component 602 is coupled between the latch circuit 122 and the logic gate 314. The delay component 602 delays the third shallow sleep signal generated by the latch circuit 122. In some cases, a race condition exists between the read bit line signal (READB) and the bit line precharge signal (BLPCHB). For the memory device 600 to operate in the shallow sleep mode, the read bit line signal (READB) must become logic high (e.g., "1") before the bit line precharge signal (BLPCHB). The delay component 602 injects a delay into the third shallow sleep signal (LLSLP_SAE) such that the output of the logic gate 314 (e.g., BLPCHB) is delayed in time and the read bit line signal (READB) output from the logic gate 312 goes to logic high (e.g., "1") faster. All other operations of the previously described memory device 300 apply to the memory device 600.

[0046] Figure 7 is a block diagram illustrating an example delay configuration 700 in accordance with various embodiments of the present disclosure. As Figure 7As shown, an additional delay component 602 is placed within the local control circuit 120. The delay component 602 further delays the signal to the delay component 702 of the local input / output circuit 230. The delay component 602 delays the third shallow sleep signal generated by the latch circuit 122. In some cases, there is a race condition between the read bit line signal (READB) and the bit line precharge signal (BLPCHB). For the memory device 600 to operate in the shallow sleep mode, the read bit line signal (READB) must go logic high (e.g., "1") before the bit line precharge signal (BLPCHB). More specifically, the delay component 602 injects a delay into the third shallow sleep signal (LLSLP_SAE) such that the output of the logic gate 314 (e.g., BLPCHB) is delayed in time and the read bit line signal (READB) output from the logic gate 312 goes logic high (e.g., "1") faster. Figure 7 The configuration shown is an RC circuit with a delay (e.g., a series of buffers). The delay 702 injects an additional time delay to further delay the output of the logic gate 314 (e.g., the bit line precharge signal (BLPCHB)).

[0047] Figure 8 is a block diagram illustrating another example delay configuration 800 in accordance with various embodiments of the present disclosure. The delay configuration 800 is similar to Figure 7 the delay configuration. The delay component 602 delays the third shallow sleep signal generated by the latch circuit 122. In some cases, there is a race condition between the read bit line signal (READB) and the bit line precharge signal (BLPCHB). For the memory device 600 to operate in the shallow sleep mode, the read bit line signal (READB) must go logic high (e.g., "1") before the bit line precharge signal (BLPCHB). The delay component 602 injects a delay into the third shallow sleep signal (LLSLP_SAE) such that the output of the logic gate 314 (e.g., BLPCHB) is delayed in time and the read bit line signal (READB) output from the logic gate 312 goes logic high (e.g., "1") faster. The difference in the delay configuration is that Figure 8 there is no additional delay component in the local input / output circuit 230 in

[0048] Figure 9 is a diagram illustrating various waveforms associated with the memory device 600 in accordance with various embodiments of the present disclosure Figure 6 The timing diagram 900 has features similar to those previously discussed in Figure 5 Using the additional delay component 602, the third sleep signal (LLSLP_SAE) is delayed even more in time than the delay shown in the timing diagram 500 of Figure 5

[0049] Figure 10 FIG. 1000 is a circuit schematic showing another example time delay configuration in accordance with various embodiments of the present disclosure. As Figure 10 shown, the precharge circuit 340 includes transistor pairs 1018, 1020 coupled to the bit line pair BL / BLB. The transistor pairs 1018, 1020 are coupled to Figure 3 the transistors 330, 332 described in. The transistors 330, 332 are coupled to the read transistors 318, 320. The read transistors 318, 320 are coupled to the sense amplifier precharge circuit 1004, which in turn is coupled to the sense amplifier 1002. In this example, a second delay circuit (e.g., delay 602) is also applied to the bit line precharge (BLPCHB). The second delay circuit (e.g., delay 602) injects a time delay to delay the output of the logic gate 314. Thus, after the third sleep signal (LLSLP_SAE) goes logic high (e.g., “1”), the read bit line (READB) goes logic high (e.g., “1”) first before the bit line precharge (BLPCHB) goes logic high (e.g., “1”). In some cases, this can avoid precharging the bit line pair BL and BLB from the SA precharge circuit (SAPCHB) 1004. In other words, the read bit line (READB) goes logic high before the bit line precharge (BLPCHB) goes logic high, so the bit line pair BL and BLB are first disconnected from the sense amplifier circuit 1002.

[0050] The circuit schematic diagram includes transistors 1018 and 1020. When the memory devices 300 and 600 are in the sleep state (e.g., no read / write operation), the bit line precharge signal (BLPCHB) is at a low logic level (e.g., 0). With the bit line precharge signal (BLPCHB) being at a logic low (e.g., "0"), transistor 1018 operates and BL3 and BLB3 are precharged to the supply voltage coupled to the source / drain terminals of transistors 1018 and 1020. When a read / write operation occurs in the memory devices 300 and 600, the bit line precharge signal (BLPCHB) is at a logic high (e.g., "1"). When the bit line precharge signal (BLPCHB) is at a logic high (e.g., "1"), transistors 1018 and 102 are turned off and any voltage on BL3 / BLB3 will be transferred to transistors 330 and 332. If a partial selection of YB[3] in the memory devices 300 and 600 using the decoded address is made, then the gate inputs of transistors 330 and 332 are at a logic low (e.g., "0"). When the gate inputs of transistors 330 and 332 are at a logic low (e.g., "0"), then transistors 330 and 332 operate. With transistors 330 and 332 operating, any voltage on the bit lines is propagated to the read bit line pair (RBL / RBLB). Additionally, when the memory devices 300 and 600 are placed in the shallow sleep mode, the bit line precharge signal (BLBCHB) is at a logic high (e.g., "1"), thereby disconnecting the bit lines from their respective power supplies.

[0051] Figure 11 FIG. 1100 is a process flow diagram illustrating a method of controlling a bit line precharge circuit. For ease of understanding, although described herein with reference to the previously described structure Figure 11 it should be understood that the method is also applicable to many other structures. The sense amplifier enable signal (SAE) is provided to a latch circuit (e.g., latch circuit 122) to delay a first activation signal (e.g., the bit line precharge signal (BLPCHB)) such that the first activation signal is asserted after the sense amplifier signal (e.g., step 1110). The first activation signal is provided to a read switch (e.g., transistors 318 and 320). The first activation signal is delayed to generate a second activation signal (e.g., step 1120). Only after the first activation signal is provided to the read switch (e.g., transistors 318 and 320), the second activation signal activates the bit line precharge circuit. This in turn allows the word lines and bit lines to be turned off during the shallow sleep mode such that they are disconnected from their respective power supplies and the total leakage current of the memory devices 300 and 600 is minimized.

[0052] The use of the various circuits and methods described herein can provide many advantages. For example, introducing a latch circuit in a local control circuit facilitates the operation of various memory devices (such as the execution of tasks, DFT, and pipelining) without generating timing effects due to power management assertions in the same cycle. In addition, the introduction of the latch circuit has a minimal impact on the memory device (e.g., about 1%).

[0053] In one embodiment, the control circuit includes a first latch circuit and a second latch circuit. The first latch circuit is configured to receive a first shallow sleep signal. The first latch circuit generates a second shallow sleep signal based on a clock signal. The second latch circuit is configured to receive the second shallow sleep signal. The second latch circuit generates a third shallow sleep signal based on a sense amplifier enable signal. The second latch circuit provides the third shallow sleep signal to a bit line read switch, thereby cutting off the bit line of the read switch after the sense amplifier is enabled.

[0054] In the above control circuit, the second latch circuit is configured to modify the power supply of the memory device coupled to the memory device without interrupting the read operation or write operation of the memory device.

[0055] In the above control circuit, the second latch circuit includes: a logic gate configured to compare the third shallow sleep signal and the clock signal; a first inverter coupled to the output of the logic gate and configured to invert the output; a first group of transistors coupled to the output of the first inverter and the input of a second inverter, the first group of transistors being configured to send a fourth shallow sleep signal; and a second inverter coupled to the output of the first group of transistors and configured to output the third shallow sleep signal by inverting the fourth shallow sleep signal.

[0056] In the above control circuit, the first group of transistors includes at least four transistors coupled in series, and the at least four transistors include two transistors of a first type and two transistors of a second type.

[0057] In the above control circuit, the second group of transistors includes at least four transistors coupled in series, and the at least four transistors include two transistors of a first type and two transistors of a second type. The second group of transistors is configured to receive the clock signal or the sense amplifier enable signal.

[0058] In the above control circuit, the memory device includes a plurality of peripheral circuits, and the plurality of peripheral circuits include a local input / output circuit, a global input / output circuit, a local input / output controller, and a global input / output controller.

[0059] In another embodiment, the read switch drive circuit includes a latch circuit. The latch circuit is configured to receive a sleep signal and a sense amplifier enable signal. The latch circuit is further configured to delay an activation signal to a read switch located between a memory and a bit line of a sense amplifier such that the sense amplifier enable signal is before the read switch activation signal.

[0060] In the above read switch drive circuit, the latch circuit is configured to modify the power supply of a memory device coupled to the memory device without interrupting a read operation or a write operation of the memory device.

[0061] In the above read switch drive circuit, the latch circuit includes: a logic gate configured to compare a third shallow sleep signal and a clock signal; a first inverter coupled to an output of the logic gate and configured to invert the output; a first group of transistors coupled to the output of the first inverter and an input of a second inverter, the first group of transistors being configured to send a fourth shallow sleep signal; and the second inverter coupled to an output of the first group of transistors and configured to output the third shallow sleep signal by inverting the fourth shallow sleep signal.

[0062] In the above read switch drive circuit, the first group of transistors includes at least four transistors coupled in series, the at least four transistors including two transistors of a first type and two transistors of a second type.

[0063] In the above read switch drive circuit, the second group of transistors includes at least four transistors coupled in series, the at least four transistors including two transistors of a first type and two transistors of a second type, and the second group of transistors is configured to receive a clock signal or a sense amplifier enable signal.

[0064] In the above read switch drive circuit, the memory device includes a plurality of peripheral circuits, and the peripheral circuits include a local input / output circuit, a global input / output circuit, a local input / output controller, and a global input / output controller.

[0065] In yet another embodiment, a method of controlling a bit line precharge circuit includes: providing a sense amplifier enable signal to a latch to delay a first activation signal such that the first activation signal is asserted after a sense amplifier signal. The first activation signal is provided to a read switch. The method further includes delaying the first activation signal to generate a second activation signal. The second activation signal activates the bit line precharge circuit only after the first activation signal is provided to the read switch.

[0066] In the above method, a latch circuit is used to delay the first activation signal.

[0067] In the above method, the latch circuit is configured to modify the power supply of the memory device coupled to the memory device without interrupting the read operation or write operation of the memory device.

[0068] In the above method, the latch circuit includes: a logic gate configured to compare a third shallow sleep signal and a clock signal; a first inverter coupled to the output of the logic gate and configured to invert the output; a first group of transistors coupled to the output of the first inverter and the input of a second inverter, the first group of transistors being configured to send a fourth shallow sleep signal; and a second inverter coupled to the output of the first group of transistors and configured to output the third shallow sleep signal by inverting the fourth shallow sleep signal.

[0069] In the above method, the first group of transistors includes at least four transistors coupled in series, the at least four transistors including two transistors of a first type and two transistors of a second type.

[0070] In the above method, the second group of transistors includes at least four transistors coupled in series, the at least four transistors including two transistors of a first type and two transistors of a second type, the second group of transistors being configured to receive a clock signal or a sense amplifier enable signal.

[0071] In the above method, the memory device includes a plurality of peripheral circuits, the plurality of peripheral circuits including a local input / output circuit, a global input / output circuit, a local input / output controller, and a global input / output controller.

[0072] In the above method, it further includes operating the memory device in a first power management mode, and operating the memory device in the first power management mode includes removing power from a part of the peripheral circuits.

[0073] The above outlines the features of several embodiments so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as those introduced in the embodiments herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present invention, and they can be variously changed, substituted, and altered in the present invention without departing from the spirit and scope of the present invention.

Claims

1. A control circuit, comprising: A first latch circuit configured to receive a first shallow sleep signal, wherein the first latch circuit generates a second shallow sleep signal according to a clock signal; and A second latch circuit configured to receive the second shallow sleep signal, wherein the second latch circuit generates a third shallow sleep signal according to a sense amplifier enable signal, Wherein the second latch circuit provides the third shallow sleep signal to a bit line read switch, thereby cutting off the bit line read switch after the sense amplifier is enabled.

2. The control circuit according to claim 1, wherein, The second latch circuit is configured to modify the power supply of a memory device coupled to the memory device without interrupting a read operation or a write operation of the memory device.

3. The control circuit according to claim 1, wherein The second latch circuit comprises: A logic gate configured to compare the sense amplifier enable signal and the clock signal; A first inverter coupled to the output of the logic gate and configured to invert the output; A first group of transistors coupled to the output of the first inverter and the input of a second inverter, the first group of transistors being configured to send a fourth shallow sleep signal; and A second inverter coupled to the output of the first group of transistors, the second inverter being configured to output the third shallow sleep signal by inverting the fourth shallow sleep signal.

4. The control circuit according to claim 3, wherein, The first group of transistors comprises at least four transistors coupled in series, the at least four transistors comprising two transistors of a first type and two transistors of a second type.

5. The control circuit according to claim 2, wherein, A second group of transistors comprises at least four transistors coupled in series, the at least four transistors comprising two transistors of a first type and two transistors of a second type, the second group of transistors being configured to receive the clock signal or the sense amplifier enable signal.

6. The control circuit according to claim 2, wherein, The memory device comprises a plurality of peripheral circuits, the plurality of peripheral circuits comprising a local input / output circuit, a global input / output circuit, a local input / output controller, and a global input / output controller.

7. A read switch driving circuit, comprising: A latch circuit configured to receive a sleep signal and a sense amplifier enable signal; The latch circuit is configured to delay an activation signal that reaches a read switch located between a bit line and a sense amplifier of a memory, such that the sense amplifier enable signal arrives before the activation signal, and The latch circuit is configured to modify the power supply of a memory device coupled to the memory device without interrupting a read operation or a write operation of the memory device.

8. The read switch driving circuit according to claim 7, wherein, The memory device is a random access memory.

9. The read switch driving circuit according to claim 7, wherein The latch circuit comprises: A logic gate configured to compare a sense amplifier enable signal and a clock signal; A first inverter coupled to the output of the logic gate and configured to invert the output; A first group of transistors coupled to the output of the first inverter and the input of a second inverter, the first group of transistors being configured to send a fourth shallow sleep signal; and A second inverter coupled to the output of the first group of transistors, the second inverter being configured to output the third shallow sleep signal by inverting the fourth shallow sleep signal.

10. The read switch driving circuit according to claim 9, wherein, The first set of transistors includes at least four transistors coupled in series, the at least four transistors including two transistors of a first type and two transistors of a second type.

11. The read switch driving circuit according to claim 7, wherein, The second set of transistors includes at least four transistors coupled in series, the at least four transistors including two transistors of a first type and two transistors of a second type, the second set of transistors being configured to receive a clock signal or the sense amplifier enable signal.

12. The read switch driving circuit according to claim 7, wherein, The memory device includes a plurality of peripheral circuits, the peripheral circuits including a local input / output circuit, a global input / output circuit, a local input / output controller, and a global input / output controller.

13. A method of controlling a bit line precharge circuit, comprising: Providing a sense amplifier enable signal to a latch to delay a first activation signal such that the first activation signal is asserted after the sense amplifier enable signal, wherein the first activation signal is provided to a read switch, and wherein a latch circuit is used to delay the first activation signal, the latch circuit being configured to modify a power supply of a memory device coupled to the memory device without interrupting a read operation or a write operation of the memory device; Delaying the first activation signal to generate a second activation signal, wherein the second activation signal activates the bit line precharge circuit only after the first activation signal is provided to the read switch.

14. The method according to claim 13, wherein, The memory device includes at least one memory array and a plurality of peripheral circuits.

15. The method according to claim 13, wherein, The memory device is a random access memory.

16. The method according to claim 14, wherein, The latch circuit includes: A logic gate configured to compare the sense amplifier enable signal and a clock signal; A first inverter coupled to an output of the logic gate and configured to invert the output; A first set of transistors coupled to the output of the first inverter and an input of a second inverter, the first set of transistors being configured to send a fourth shallow sleep signal; and A second inverter coupled to the output of the first set of transistors and configured to output a third shallow sleep signal by inverting the fourth shallow sleep signal.

17. The method according to claim 16, wherein The first set of transistors includes at least four transistors coupled in series, the at least four transistors including two transistors of a first type and two transistors of a second type.

18. The method according to claim 17, wherein, The second set of transistors includes at least four transistors coupled in series, the at least four transistors including two transistors of a first type and two transistors of a second type, the second set of transistors being configured to receive the clock signal or the sense amplifier enable signal.

19. The method according to claim 15, wherein The memory device includes a plurality of peripheral circuits, the plurality of peripheral circuits including a local input / output circuit, a global input / output circuit, a local input / output controller, and a global input / output controller.

20. The method of claim 19, further comprising operating the memory device in a first power management mode, operating the memory device in the first power management mode including removing power from a portion of the peripheral circuits.

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