Memory device and control method thereof

Abstract

The present invention discloses a memory device and a control method thereof. The memory device includes a memory cell array, a current detector and a controller. The memory cell array has a plurality of memory cell strings coupled to a shared source line. The current detector detects the current flowing through the shared source line or the power supply terminal of the page buffer of the memory cell array during a reading operation. The controller is used to: in a programming operation, perform a first programming operation according to a first programming verification voltage for a plurality of first memory cells corresponding to logic 0, and perform a second programming operation according to a second programming verification voltage for a plurality of second memory cells corresponding to logic 1, wherein the first programming verification voltage is different from the second programming verification voltage; and, in a reading operation, provide a read voltage to the memory cell string to sense the current flowing through based on a read current reference value.

Description

Technical Field

[0001] The present invention relates to a memory device and a control method thereof, and in particular to a memory device that can be used as an in-memory operator and a control method thereof. Background Art

[0002] As artificial intelligence is advancing, providing chips with high-efficiency multiplication and addition capabilities in integrated circuits has become an important issue. In today's technology, it has become a mainstream to perform multiplication and addition operations by setting up memory devices.

[0003] In the prior art, the digital sum of all the page data in the memory can be used to generate the calculation result. This method has relatively high accuracy, but requires relatively long calculation time. In addition, the prior art also provides an analog method to detect the sum of the current on the source line to obtain the calculation result. However, although this method can reduce the calculation time, it cannot provide a high-accuracy calculation result. Summary of the invention

[0004] The invention provides a memory device and a control method thereof, which can improve the accuracy of current summing operation.

[0005] The memory device of the present invention includes a memory cell array, a current detector and a controller. The memory cell array has a plurality of memory cell strings. The memory cell strings are coupled to a shared source line. The current detector detects the current flowing through the shared source line or the power supply terminal of the page buffer of the memory cell array during a read operation. The controller is coupled to the memory cell string to: in a programming operation, perform a first programming operation according to a first programming verification voltage for a plurality of first memory cells corresponding to logic 0, and perform a second programming operation according to a second programming verification voltage for a plurality of second memory cells corresponding to logic 1, wherein the first programming verification voltage is greater than the second programming verification voltage; and, in a reading operation, provide a read voltage to the memory cell string to sense the current flowing through based on a read current reference value.

[0006] The control method of the memory device of the present invention includes: detecting the current flowing on the power supply terminal of the shared source line or the page buffer of the memory cell array during the reading action, wherein the memory cell array has a plurality of memory cell strings, and the memory cell strings are coupled to the shared source line; in the programming action, performing a first programming action according to a first programming verification voltage for a plurality of first memory cells corresponding to logic 0, and performing a second programming action according to a second programming verification voltage for a plurality of second memory cells corresponding to logic 1, wherein the first programming verification voltage is different from the second programming verification voltage; and providing a read voltage to the memory cell string during the reading action to sense the current flowing based on a read current reference value.

[0007] Based on the above, the memory cells corresponding to logic 0 and logic 1 are programmed to different degrees to improve the distribution of the memory cells corresponding to logic 0 and logic 1. In this way, the accuracy of the sensed current provided by the memory cell array can be improved, thereby improving the accuracy of the calculation result. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram of a memory device according to an embodiment of the present invention is shown.

[0009] Figure 2 A schematic diagram of a threshold voltage distribution state of a memory cell during a programming operation of the memory cell according to an embodiment of the present invention is shown.

[0010] Figure 3 FIG. 4 is a flowchart showing an operation of executing a programming operation in a memory device according to an embodiment of the present invention.

[0011] Figure 4A as well as Figure 4B A current-voltage relationship diagram of a memory cell corresponding to a program verification voltage and a read voltage according to an embodiment of the present invention is shown.

[0012] Figure 5 A schematic diagram of a memory device according to another embodiment of the present invention is shown.

[0013] FIG. 6A to FIG. 6D Schematic diagrams are respectively shown showing implementations of a voltage regulator and a current detector in a memory device according to an embodiment of the present invention.

[0014] Fig. 7A as well as Figure 7B Schematic diagrams showing different implementation structures of a memory device according to an embodiment of the present invention.

[0015]

Explanation of symbols

[0016] 100, 500, 701, 702: Memory devices

[0017] 110, 510, 721-1, 721-2: Memory cell array

[0018] 120, 520, 520-1~520-4, 712, 722-1, 722-2: Current detector

[0019] 130: Controller

[0020] 140: Page Buffer

[0021] 141: Latch

[0022] 150: Drive

[0023] 210, 220, 221: Distribution status

[0024] 410: Distribution range

[0025] 550, 550-1~550-4: Voltage regulator

[0026] 710: Memory Cell Array

[0027] BL1~BL4, MBL0~MBL2: bit lines

[0028] BLSW1~BLSW4: bit line switch

[0029] CSL, CSL0, CSL1: shared source line

[0030] GND: reference ground

[0031] Icell_1~Icell_3: current

[0032] ICT: Circulating Current

[0033] IDET: Detection Information

[0034] M1~M5:Transistor

[0035] MIDET: Adjusted detection information

[0036] MS1~MS4: storage unit string

[0037] OP1, OP2: Amplifier

[0038] PV_0, PV_1, PV1: Programming verification voltage

[0039] RD: Read voltage

[0040] S310~S330: Steps of programming action

[0041] VR1: Reference voltage

[0042] VR2, VB: bias voltage

[0043] VCSL: Source voltage

[0044] W2, W1: Width

[0045] WL: Word Line DETAILED DESCRIPTION

[0046] Please refer to Figure 1 , Figure 1A schematic diagram of a memory device according to an embodiment of the present invention is shown. The memory device 100 includes a memory cell array 110, a current detector 120, a controller 130, a page buffer 140, and a driver 150. The memory cell array 110 has a plurality of memory cell strings MS1-MS4, wherein the memory cell strings MS1-MS4 may be flash memory cell strings. The memory cell strings MS1-MS4 may be arranged in a two-dimensional manner. The memory cell strings MS1-MS4 are coupled to a shared source line CSL. The memory cell strings MS1-MS4 are coupled to the driver 150 through a word line WL. The driver 150 sends a word line signal through the word line WL to control the access actions of the plurality of memory cells on the memory cell strings MS1-MS4. The memory cell strings MS1-MS4 are also coupled to the bit lines BL1-BL4, respectively. The page buffer 140 includes a latch 141 and a plurality of bit line switches BLSW1-BLSW4. The bit line switches BLSW1-BLSW4 are respectively coupled to the bit lines BL1-BL4 and are controlled by a plurality of outputs of the latch 141. The bit line switches BLSW1-BLSW4 transmit a plurality of input signals to the bit lines BL1-BL4 according to their on or off states. In this embodiment, the memory device 100 can be used as an in-memory computation device.

[0047] On the other hand, the current detector 120 is coupled to the shared source line CSL and is used to detect the current flowing on the shared source line CSL during a read operation. In the present embodiment, the memory cell strings MS1 to MS4 may provide weight values, perform multiplication and addition operations with the received input signals, and generate operation results on the shared source line CSL. The current detector 120 obtains the above-mentioned operation results by detecting the current flowing on the shared source line CSL. In the read operation, a read voltage (for example, provided by the controller 130) may be applied to the word line of the memory cell to be read on the memory cell strings MS1 to MS4, and the current detector 120 may sense the current flowing on the shared source line CSL based on a preset read current reference value.

[0048] It is worth mentioning that the current detector 120 can also be coupled to the power terminal of the page buffer 140 and obtain the above-mentioned flow current by detecting the current on the power terminal of the page buffer 140. In this way, the current detector 120 can also obtain the calculation result generated by the memory device 100.

[0049] It is worth noting that the controller 130 is coupled to the memory cell strings MS1-MS4. The controller 130 is used to perform a first programming operation on a plurality of first memory cells corresponding to logic 0 according to a first programming verification voltage, and to perform a second programming operation on a plurality of second memory cells corresponding to logic 1 according to a second programming verification voltage in performing a programming operation on the memory cells in the memory cell strings MS1-MS4. In this embodiment, the first programming verification voltage is different from (e.g., greater than) the second programming verification voltage. Please refer to Figure 1 as well as Figure 2 ,in Figure 2 A schematic diagram of the threshold voltage distribution state of the memory cell in the programming operation of the memory cell according to an embodiment of the present invention is shown. In the initial state, all the memory cells are in the erased state and have a distribution state 210. When performing the programming operation of the memory cell, the controller 130 can first find out a plurality of first memory cells corresponding to logic 0 in all the memory cells, and find out a plurality of second memory cells corresponding to logic 1 in all the memory cells. Then, the controller 130 enables the plurality of first memory cells corresponding to logic 0 to perform a first programming operation according to the first programming verification voltage PV_0. In addition, the controller 130 enables the plurality of second memory cells corresponding to logic 1 to perform a second programming operation according to the second programming verification voltage PV_1. After the first programming operation and the second programming operation are completed, the first memory cells corresponding to logic 0 have a distribution state 220, and the second memory cells corresponding to logic 1 have a distribution state 221.

[0050] In this embodiment, the controller 130 may be a processor with computing capabilities. Alternatively, the controller 130 may be a hardware circuit designed by a hardware description language (HDL) or any other digital circuit design method known to those skilled in the art, and implemented by a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC).

[0051] On the other hand, the current detector 120 may perform a reading operation of the current flowing on the common source line CSL according to the reading voltage RD.

[0052] Please note that in the embodiment of the present invention, whether it is the first memory cell corresponding to logic 0 or the second memory cell corresponding to logic 1, the controller 130 will perform different degrees of programming actions according to different programming verification voltages. In this way, after the programming action, the width W1 of the distribution state 220 of the first memory cell and the width W2 of the distribution state 221 of the second memory cell can be set to a range. In other words, the current magnitudes provided by each memory cell on the memory cell string MS1-MS4 can be effectively concentrated, and the current detector 120 can read the flowing current more accurately.

[0053] Please refer to the following Figure 3 , Figure 3 The flowchart of the memory device of the embodiment of the present invention is shown. When the memory device performs the programming action, in step S310, the controller can input the write data, and in step S320, the memory cell corresponding to the logic 0 and the memory cell corresponding to the logic 1 performs different degrees of programming actions. In step S330, the controller can decide whether to continue to execute step S320 based on whether the programming verification is passed. If step S330 determines that the programming verification has not passed, step S320 is executed again; conversely, if step S330 determines that the programming verification has passed, the programming action is terminated.

[0054] Please refer to the following Figure 4A as well as Figure 4B , Figure 4A as well as Figure 4B A current-voltage relationship diagram of a memory cell corresponding to a programming verification voltage and a reading voltage according to an embodiment of the present invention is shown. Figure 4A , 4B In the figure, the horizontal axis of the curve is the bias voltage of the memory cell on the character line, and the vertical axis of the curve is the current generated by the memory cell. Figure 4A In the memory cell corresponding to logic 1, when the provided read voltage RD is greater than the second programming verification voltage PV_1, it can be found that the current provided by the plurality of memory cells has a distribution range 410, and the distribution range 410 can be, for example, between 80nA (nanoamperes) and 100nA. This distribution range 410 will cause a certain error when performing the current detection operation. Based on the above, in the embodiment of the present invention, when performing the programming voltage for the memory cell corresponding to logic 1, the second programming verification voltage PV_1 can be increased by an offset value to obtain the offset second programming verification voltage PV1, such as Figure 4B The second program verification voltage PV1 after shifting is not greater than the read voltage RD.

[0055] exist Figure 4BIn the embodiment of the present invention, the second programming verification voltage PV1 after the offset can be equal to the read voltage RD. And the current generated by the memory cell based on the read voltage RD can be, for example, concentrated at 80nA. Further, in the read operation, the current detector can synchronously increase the read current reference value by an offset value (for example, from 20nA to 80nA). In this way, the accuracy of the current detection operation performed by the current detector can be further improved.

[0056] Please refer to Figure 5 , Figure 5 A schematic diagram of a memory device according to another embodiment of the present invention is shown. The memory device 500 includes a memory cell array 510, a current detector 520, a voltage regulator 550, and a plurality of sense amplifiers SA0-SA2. The memory cell array 510 has a plurality of memory cell strings MS1-MS3 arranged in a three-dimensional manner, one end of the memory cell strings MS1-MS3 is respectively coupled to the bit lines MBL0-MBL2; the other end of the memory cell strings MS1-MS3 is commonly coupled to a shared source line CSL. In addition, the current detector 520 and the voltage regulator 550 are both coupled to the shared source line CSL.

[0057] In the read operation, the sense amplifiers SA0-SA2 can provide multiple bias voltages to be applied to the bit lines MBL0-MBL2. At the same time, the voltage regulator 550 can provide another bias voltage to the shared source line CSL. At this time, the memory cell strings MS1-MS3 can generate currents Icell_1-Icell_3 respectively. The currents Icell_1-Icell_3 are provided to the shared source line CSL to generate the flow current ICT. The current detector 520 can detect the flow current ICT and obtain the current size of the flow current ICT.

[0058] In this embodiment, the memory cell strings MS1 ˜ MS3 may be NAND flash memory cell strings.

[0059] Please refer to the following FIG. 6A to FIG. 6D , FIG. 6A to FIG. 6D Schematic diagrams of implementation of a voltage regulator and a current detector in a memory device according to an embodiment of the present invention are respectively shown. Figure 5 Based on the implementation example, Fig. 6AIn the embodiment, the voltage regulator 550-1 and the current detector 520-1 are coupled to the shared source line CSL of the memory cell array 510. The voltage regulator 550-1 includes an amplifier OP1 and a transistor M1. The positive input terminal of the amplifier OP1 is coupled to the shared source line CSL, the negative input terminal of the amplifier OP1 receives the reference voltage VR1, and the output terminal of the amplifier OP1 is coupled to the control terminal of the transistor M1. In addition, the first terminal of the transistor M1 is coupled to the shared source line CSL, and the second terminal of the transistor M1 is coupled to the reference ground terminal GND. The voltage regulator 550-1 can generate a source voltage VCSL according to the reference voltage VR1, and provide the source voltage VCSL to the shared source line CSL. When performing a read operation, the current ICT flowing on the shared source line CSL flows through the transistor M1. The amplifier OP1 also generates a bias voltage VB at the output terminal according to the source voltage VCSL on the positive and negative input terminals and the reference voltage VR1, and the bias voltage VB can be provided to the control terminal of the transistor M1.

[0060] In addition, the current detector 520-1 includes a transistor M2. The control terminal of the transistor M2 receives the bias voltage VB, and the second terminal of the transistor M2 is coupled to the reference ground terminal GND. The transistor M2 can mirror the current ICT flowing through the transistor M1 to generate the detection information IDET at its first terminal. In this embodiment, by making the channel width-to-length ratio of the transistor M2 1 / k times the channel width-to-length ratio of the transistor M1, the current value of the detection information IDET can be 1 / k times the current ICT flowing through. Wherein k is a real number greater than 1.

[0061] exist Figure 6B In the embodiment of the present invention, the voltage regulator 550-2 and the current detector 520-2 are coupled to the shared source line CSL of the memory cell array 510 and are used to detect the current ICT flowing on the shared source line CSL. Fig. 6A The circuit structure of the voltage regulator 550-1 in the embodiment is the same, and will not be described in detail here. Fig. 6A Differently, the current detector 520-2 further includes a transistor M3. The second end of the transistor M3 is coupled to the first end of the transistor M2, the control end of the transistor M3 receives the bias voltage VR2, and the first end of the transistor M3 generates the detection information IDET. In this embodiment, the detection information IDET can be a current signal or a voltage signal, without specific limitation.

[0062] In addition, Figure 6CIn the implementation mode, the voltage regulator 550-3 and the current detector 520-3 are coupled to the common source line CSL of the memory cell array 510, and are used to detect the current ICT flowing on the common source line CSL. The implementation mode of the voltage regulator 550-3 is the same as the implementation mode of the voltage regulator 550-1, and will not be described in detail below. In terms of the current detector 520-3, unlike the current detector 520-2, the current detector 520-2 in this implementation mode further includes an amplifier OP2 for generating a bias voltage VR2. Among them, the positive input terminal of the amplifier OP2 is coupled to the common source line CSL, the negative input terminal of the amplifier OP2 is coupled to the coupling end points of the transistors M3 and M2, and the output terminal of the amplifier OP2 generates the bias voltage VR.

[0063] exist Fig.6D In the implementation mode, the voltage regulator 550-4 and the current detector 520-4 are coupled to the shared source line CSL of the memory cell array 510, and are used to detect the current ICT flowing on the shared source line CSL. Similarly, the implementation mode of the voltage regulator 550-4 is the same as the implementation mode of the voltage regulator 550-1, and will not be described in detail below. In terms of the current detector 520-4, unlike the current detector 520-2, the current detector 520-4 in this implementation mode further includes a current mirror composed of transistors M4 and M5. The current mirror is used to mirror the detection information IDET provided by the transistor M3 and generate the adjusted detection information MIDET. In this embodiment, the adjusted detection information MIDET can be a current signal or a voltage signal, without specific limitations. In this embodiment, the current mirror ratio of the current mirror formed by the transistors M4 and M5 may be 1:1. When the adjusted detection information MIDET is a current signal, the ratio of the adjusted detection information MIDET to the value of the flowing current ICT may be 1:k.

[0064] Please refer to Fig. 7A as well as Figure 7B , Fig. 7A as well as Figure 7B Schematic diagrams showing different implementation architectures of a memory device according to an embodiment of the present invention. Fig. 7A In the memory device 701, the memory cell array includes all memory cell arrays 710 in a memory device. The memory cell array 710 has a shared source line CSL. The current detector 712 is coupled to the shared source line CSL of the memory cell array 710, and obtains the multiplication and addition result of the memory device 701 by detecting the current flowing on the shared source line CSL.

[0065] exist Figure 7BIn the memory device 702, the memory cell arrays 721-1 and 721-2 are two partial memory cell arrays in a memory device. The memory cell arrays 721-1 and 721-2 have shared source lines CSL0 and CSL1, respectively. The current detectors 722-1 and 722-2 are coupled to the shared source lines CSL0 and CSL1, respectively. The current detectors 722-1 and 722-2 obtain the multiplication and addition operation results of the corresponding memory cell arrays 721-1 and 721-2 by detecting the current flowing on the shared source lines CSL0 and CSL1, respectively.

[0066] Of course, in the above embodiments, a single memory device may include a greater number of memory cell arrays. Fig. 7A , 7B The drawings are merely illustrative examples and are not intended to limit the scope of protection of the present invention.

[0067] Another embodiment of the present invention provides a control method for a memory device. In this embodiment, in one step, the memory device can detect the current flowing through the power supply terminal of the shared source line or the page buffer of the memory cell array during a read operation, wherein the memory cell array has a plurality of memory cell strings, and the memory cell strings are coupled to the shared source line. In another step, the memory device can perform a first programming operation according to a first programming verification voltage for a plurality of first memory cells corresponding to logic 0 in a programming operation, and perform a second programming operation according to a second programming verification voltage for a plurality of second memory cells corresponding to logic 1 in a programming operation, wherein the first programming verification voltage is different from the second programming verification voltage. In addition, in another step, the memory device can provide a read voltage to the memory cell string during a read operation to sense the current flowing through the memory device based on a read current reference value.

[0068] The implementation details of the steps of the above actions have been described in detail in the aforementioned embodiments and will not be repeated here.

[0069] In summary, the present invention allows the memory cells corresponding to logic 0 and 1 to perform programming operations to different degrees, so that the distribution width of the threshold voltage of the memory cells corresponding to logic 0 and 1 can be limited to a certain preset value. In this way, when performing the reading operation of the memory cell, the current range provided by the memory cell can have a higher uniformity, which can improve the accuracy of the reading operation.

[0070] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.

[0071] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory device, wherein: include: A memory cell array has a plurality of memory cell strings, and the memory cell strings are coupled to a shared source line; a current detector for detecting a current flowing through the shared source line or a power supply terminal of a page buffer of the memory cell array during a read operation; as well as A controller is coupled to the memory cell strings to: In a programming operation, different programming voltages are applied to different logic values ​​to be written to perform programming operations so that the current magnitudes provided by each memory cell can be effectively concentrated, wherein a first programming operation is performed according to a first programming verification voltage for a plurality of first memory cells to be written with logic 0, and a second programming operation is performed according to a second programming verification voltage for a plurality of second memory cells to be written with logic 1, wherein the first programming verification voltage is greater than the second programming verification voltage; as well as During the reading operation, a reading voltage is provided to the memory cell strings, and the flowing current is sensed based on a reading current reference value.

2. The memory device according to claim 1, wherein: The controller makes the second programming verification voltage not greater than the reading voltage in the second programming action.

3. The memory device according to claim 1, wherein: Also includes: A voltage regulator is coupled to the common source line and provides a source voltage to the common source line.

4. The memory device according to claim 3, wherein: The voltage regulator includes: a first amplifier having a positive input terminal coupled to the shared source line, a negative input terminal of the first amplifier receiving a reference voltage, and an output terminal of the first amplifier coupled to the positive input terminal of the first amplifier; and A first transistor has a first terminal coupled to the output terminal of the first amplifier, a control terminal of the first transistor coupled to the output terminal of the first amplifier, and a second terminal of the first transistor coupled to a reference ground terminal.

5. The memory device according to claim 4, wherein: The current detector includes: A second transistor has a first terminal for generating a detection information, a control terminal of the second transistor is coupled to the control terminal of the first transistor, and a second terminal of the second transistor is coupled to the reference ground terminal.

6. The memory device according to claim 5, wherein: The channel width-to-length ratio of the second transistor is 1 / k of the channel width-to-length ratio of the first transistor, where k is a real number greater than 1.

7. The memory device according to claim 5, wherein: The current detector includes: A third transistor has a first terminal for generating the detection information, a second terminal of the third transistor is coupled to the first terminal of the second transistor, and a control terminal of the third transistor receives a bias voltage.

8. The memory device according to claim 7, wherein: The current detector further comprises: A second amplifier has a positive input terminal coupled to the shared source line, a negative input terminal of the second amplifier coupled to the second terminal of the third transistor, and an output terminal of the second amplifier generates the bias voltage.

9. The memory device according to claim 7, wherein: The current detector further comprises: A current mirror is coupled to the first end of the third transistor and is used for mirroring the detection information to generate an adjusted detection information.

10. The memory device according to claim 1, wherein: Also includes: A plurality of bit line switches are respectively coupled to the plurality of bit lines of the memory cell strings, respectively receive a plurality of input signals, and respectively transmit the input signals to the bit lines.

11. The memory device according to claim 10, wherein: Also includes: A plurality of sense amplifiers are respectively coupled to the bit line switches.

12. The memory device according to claim 1, wherein: The memory cell array includes all or part of the memory cells in the memory device.

13. The memory device according to claim 1, wherein: The memory cell strings are arranged in a two-dimensional manner or a three-dimensional manner.

14. A method for controlling a memory device, wherein: include: Detecting a current flowing through a power supply terminal of a shared source line or a page buffer of a memory cell array during a read operation, wherein the memory cell array has a plurality of memory cell strings coupled to the shared source line; In a programming operation, different programming voltages are applied to different logic values ​​to be written to perform programming operations so that the current magnitudes provided by each memory cell can be effectively concentrated, wherein a first programming operation is performed according to a first programming verification voltage for a plurality of first memory cells to be written with logic 0, and a second programming operation is performed according to a second programming verification voltage for a plurality of second memory cells to be written with logic 1, wherein the first programming verification voltage is greater than the second programming verification voltage; as well as During the reading operation, a reading voltage is provided to the memory cell strings, and the flowing current is sensed based on a reading current reference value.

15. The control method according to claim 14, wherein: Also includes: In the second programming action, the second programming verification voltage is made not greater than the reading voltage.

16. The control method according to claim 14, wherein: Also includes: providing a plurality of bit line switches to be respectively coupled to a plurality of bit lines of the memory cell strings; The bit line switches are respectively configured to receive a plurality of input signals and respectively transmit the input signals to the bit lines.

17. The control method according to claim 14, wherein: Also includes: All or part of the memory cells in the memory device are selected to serve as the memory cell array.

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