Diffusion barrier liner for interconnects

Abstract

The present disclosure relates to diffusion barrier liners for interconnects. Representative embodiments of techniques and devices are used to reduce or prevent diffusion of conductive materials into insulating or dielectric materials bonded to a substrate. Due to overlap, misaligned conductive structures may directly contact dielectric portions of a substrate, especially when direct bonding techniques are employed. A barrier interface that can inhibit diffusion is typically provided between the conductive material and the dielectric at the overlap.

Description

[0001] Description of the case

[0002] This application is a divisional application of the Chinese invention patent application with application number 201880055006.5 and name “Diffusion Barrier Liner for Interconnection” filed on October 1, 2018.

[0003] CROSS-REFERENCE TO RELATED APPLICATIONS

[0004] This application claims the benefit of U.S. Non-Provisional Patent Application No. 16 / 143,850, filed on September 27, 2018, and U.S. Provisional Application No. 62 / 569,232, filed on October 6, 2017, which are incorporated herein by reference in their entirety. Technical Field

[0005] The following description relates to the processing of integrated circuits ("ICs"). More specifically, the following description relates to techniques for processing dies or wafers in preparation for bonding. Background Art

[0006] Dies or wafers, etc., may be stacked in a three-dimensional arrangement as part of various microelectronic packaging schemes. This may include stacking one or more dies or wafers on a larger base die or wafer, stacking multiple dies or wafers in a vertical arrangement, and various combinations of these. Dies may also be stacked on wafers, or wafers may be stacked on other wafers prior to singulation. Dies or wafers may be bonded in a stacked arrangement using a variety of bonding techniques, including direct dielectric bonding, non-adhesive techniques such as Directly combine technology or Hybrid bonding technology, both of which are available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), a subsidiary of XperiCorp (eg, see US Pat. Nos. 6,864,585 and 7,485,968, which are incorporated herein by reference in their entireties).

[0007] When using direct bonding technology to bond stacked dies or wafers, it is desirable that the surface of the die or wafer to be bonded is extremely flat and smooth. For example, the surface should have very small surface topological changes so that the surface can fit closely to form a lasting bond. It is also desirable that the surface is clean and free of impurities, particles and / or other residues. For example, the presence of undesirable particles can cause the bonding to be defective or unreliable at the location of the particles. For example, some particles and residues remaining on the bonding surface can create gaps at the bonding interface between the stacked dies.

[0008] The corresponding mating surfaces of the bonded dies or wafers typically include embedded conductive interconnect structures, etc. In some examples, the bonding surfaces are arranged and aligned so that the conductive interconnect structures from the respective surfaces are joined during bonding. The joined interconnect structures form a continuous conductive interconnect (for signals, power, etc.) between the stacked dies or wafers. However, due to the use of fine-pitch conductive interconnect structures, placement accuracy limitations of pick-and-place tools, contact grid patterns on the die or wafer surfaces, different pad sizes, etc., the conductive interconnect pads of one die or wafer may be offset, or partially cover the dielectric portion (e.g., silicon oxide, etc.) of the mating surface of another die or wafer, rather than being fully aligned with the corresponding conductive interconnect pads on the mating surface of the other die or wafer.

[0009] Misalignment such as this may cause the conductive material (e.g., copper, etc.) of the overlying interconnect pad to diffuse into the dielectric with which it contacts, potentially resulting in degraded performance of the microelectronic structure. For example, at higher temperatures (such as during annealing) and in electric fields, the barrier properties of silicon oxide may be significantly degraded (relative to silicon nitride, silicon oxynitride, silicon carbonitride, etc.), thereby promoting diffusion of conductive materials into silicon oxide. This may result in leakage, short circuits, etc. between interconnects. Performance degradation may be particularly problematic when it involves multiple conductive interconnect structures of a bonded stack of dies or wafers, which can adversely affect packaging yield and packaging performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The detailed description is set forth with reference to the accompanying drawings. In the figures, the leftmost digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numerals in different figures indicates similar or identical items.

[0011] For this discussion, the devices and systems shown in the figures are shown as having multiple components. As described herein, various embodiments of the devices and / or systems may include fewer components and still be within the scope of the present disclosure. Alternatively, other embodiments of the devices and / or systems may include additional components or various combinations of the described components and still be within the scope of the present disclosure.

[0012] Figure 1 is a profile view of a pair of stacked substrates, illustrating the misalignment of embedded conductive structures within the stacked substrates.

[0013] Figure 2 is a graphical flow chart illustrating an example process of forming a microelectronic assembly including a pair of substrates having embedded conductive structures.

[0014] Figure 3A and Figure 3B is a profile diagram illustrating an example barrier interface for use with a stacked substrate having an embedded conductive structure according to various embodiments.

[0015] FIG. 4A to FIG. 4E is a profile diagram illustrating an example barrier interface for use with a stacked substrate having embedded conductive structures according to additional embodiments.

[0016] Figure 4F is a plan view illustrating an example barrier interface having a plurality of embedded conductive structures according to an embodiment.

[0017] FIG. 5A to FIG. 5C is a profile diagram illustrating an example barrier interface for use with a stacked substrate having embedded conductive structures according to additional embodiments.

[0018] Figure 6 is a graphical flow chart illustrating an example process of forming a microelectronic assembly including a pair of substrates having embedded conductive structures with a barrier interface according to an embodiment.

[0019] Figure 7 is a graphical flow chart illustrating an example process for forming a microelectronic assembly including a pair of substrates having embedded conductive structures with a barrier interface according to another embodiment.

[0020] Figure 8 is a flow chart illustrating an example method for forming a microelectronic assembly including a pair of substrates having embedded conductive structures and a barrier interface according to various embodiments. Summary of the invention

[0021] Various embodiments of the apparatus and techniques reduce or prevent diffusion of conductive material into insulating materials or dielectrics of a bonding substrate. In particular, the apparatus and techniques disclosed herein mitigate undesired diffusion caused by misaligned conductive structures on a bonding surface of a substrate. Due to overlap, misaligned conductive structures may otherwise directly contact dielectric portions of a substrate surface, especially when direct bonding techniques are employed.

[0022] These devices and techniques involve the use of a barrier interface, typically disposed between a conductive material and a dielectric, which can inhibit diffusion of the conductive layer into the surrounding dielectric material.

[0023] The substrate may be a die, wafer, carrier, large planar panel, etc., made of semiconductor or non-semiconductor materials. Semiconductor materials may, for example, include direct bandgap semiconductors or indirect bandgap semiconductors and combinations thereof. Non-semiconductor materials may include, for example, dielectric materials such as glass, ceramics, silicon oxycarbide, silicon oxide, etc., or combinations thereof. The use of the term "substrate" herein is intended to include all of these and other similar examples.

[0024] In an embodiment, a microelectronic assembly may include at least a first substrate having a first substantially flat surface, the first substrate including, for example, an insulating material or a dielectric. The dielectric may be disposed on a base die or wafer of a semiconductor, an insulating material, or a conductive material. A second substrate has a first substantially flat surface, the second substrate also including, for example, an insulating material or a dielectric. The dielectric may be disposed on a base die or wafer of a semiconductor, an insulating material, or a conductive material. The material of the first substrate may be the same (or similar) material of the second substrate. However, in an alternative embodiment, the material of the first substrate is a material different from the material of the second substrate. The first surface of the second substrate is bonded to the first surface of the first substrate without an intermediate material such as an adhesive.

[0025] A first conductive interconnect structure is embedded in a first substrate (or in a layer of the first substrate), and a surface of the first conductive interconnect structure is exposed through a first surface of the first substrate to form a first interconnect pad. A second conductive interconnect structure is embedded in a second substrate (or in a layer of the second substrate), and a surface of the second conductive interconnect structure is exposed through a first surface of the second substrate to form a second interconnect pad. The first interconnect pad faces and can contact a portion of the first surface of the first substrate and the second interconnect pad faces and can contact a portion of the first surface of the second substrate. In one embodiment, the second interconnect pad is directly bonded to the first interconnect pad.

[0026] In various examples, the second interconnect pad may be misaligned relative to the first interconnect pad, resulting in some overlap of the first and / or second interconnect pads on the insulating material or dielectric of the opposing substrate.

[0027] In this embodiment, the first barrier interface is disposed on the first substrate and at least partially surrounds the periphery of the first interconnect pad. The first barrier interface includes a material different from the insulating material or dielectric material of the first substrate and is arranged to inhibit the material of the second conductive interconnect structure from diffusing into the first substrate. In this embodiment, the material of the first barrier interface is also a material different from the material of the second conductive interconnect structure. In one embodiment, the first barrier interface includes an air gap, a rough surface, etc.

[0028] In another embodiment, the microelectronic assembly further comprises a second barrier interface disposed on the second substrate. The second barrier interface at least partially surrounds the periphery of the second interconnect pad and comprises a material different from the insulating material or dielectric of the second substrate. The second barrier interface is arranged to inhibit the material of the first conductive interconnect structure from diffusing into the second substrate. In one embodiment, the second barrier interface comprises an air gap, a rough surface, etc.

[0029] In some embodiments, the first barrier interface and / or the second barrier interface may include multiple materials or may include multiple parts consisting of one or more materials. In other embodiments, the first barrier interface and / or the second barrier interface may include a combination of materials, air gaps, rough surfaces, etc.

[0030] In various embodiments, the first barrier interface or the second barrier interface may partially or completely surround a plurality of interconnect pads of its corresponding substrate. Alternatively, a plurality of barrier interfaces may partially or completely surround one or more interconnect pads of the first substrate or the second substrate.

[0031] In some embodiments, the first barrier interface or the second barrier interface can also mitigate or prevent dielectric erosion (eg, corner rounding), etc., that may occur at the perimeter of the conductive interconnect structure during planarization.

[0032] Some disclosed processes can be illustrated using block flow diagrams, including graphical flow diagrams and / or text flow diagrams. The order in which the disclosed processes are described is not intended to be interpreted as a limitation, and any number of described process blocks can be combined in any order to implement the process or an alternative process. In addition, without departing from the essence and scope of the subject matter described herein, individual blocks can be deleted from these processes. In addition, without departing from the scope of the subject matter described herein, the disclosed processes can be implemented in any suitable manufacturing or processing equipment or system together with any hardware, software, firmware, or a combination thereof.

[0033] The embodiments are explained in more detail below using a number of examples.Although various embodiments and examples are discussed here and below, other embodiments and examples are possible by combining features and elements of the various embodiments and examples. DETAILED DESCRIPTION

[0034] Overview

[0035] Figure 11 is a profile view of a pair of stacked substrates 102 and 104, showing the misalignment of embedded conductive structures 106 and embedded conductive structures 108 within the stacked substrates 102 and 104, respectively. Substrates 102 and 104 are composed of an insulating material or dielectric (e.g., silicon oxide, etc.) at least on the bonding surface of each substrate 102 and 104. For example, substrates 102 and 104 can represent a top insulating layer of a microelectronic component composed of a base layer (of an active semiconductor, such as silicon, etc.), with one or more metallization layers on top of the base layer within the associated insulating layer. In some cases, substrate 102 can be significantly larger than substrate 104. In one example, substrate 104 can include a die with a width of 1 to 30 mm or even larger, while substrate 102 can include another die (for example) that is larger than substrate 104, such as a flat panel, a 200 or 300 mm wafer, etc.

[0036] Prior to bonding, the portions of embedded conductive structures 106 and embedded conductive structures 108 exposed through the bonding surfaces of substrates 102 and 104 may form interconnect pads, etc. In an example, substrate 102 and substrate 104 are bonded on respective bonding surfaces, and conductive structures 106 and conductive structures 108 are electrically coupled and are also generally mechanically bonded to form a single (continuous) conductive structure. Bond lines 110 indicate where the bonding surfaces of substrate 102 and substrate 104 are joined.

[0037] In an example, substrate 102 and substrate 104 are bonded to form microelectronic assembly 100. For example, substrate 102 and substrate 104 may be directly bonded, including using a hybrid bonding technique, without using an intermediate material such as an adhesive. Prior to bonding, conductive structures 106 and conductive structures 108 may be slightly recessed below the surface of substrate 102 and substrate 104 to prepare for metal expansion. The surfaces of substrate 102 and substrate 104 may be bonded via direct bonding (e.g., via Zibond). TM ), dielectric to dielectric bonding at room temperature without the use of adhesives. Then, using a high temperature anneal (<350C), contact pads 106 and contact pads 108 expand and form a metal-to-metal bond, thereby creating an electrical connection. After the bonding operation, for example when substrate 102 and substrate 104 comprise wafers, the bonded assembly 100 can be tested against known good dies before segmentation to separate into various bonded substrates or dies.

[0038] like Figure 1As shown, due to one or more of the various reasons discussed above, including inaccuracies (or tolerances) of a pick and place tool used to bond substrate 104 to substrate 102, conductive structures 106 and conductive structures 108 may be misaligned when substrate 102 and substrate 104 are placed together and bonded. The misaligned offset 112 includes an overlap of interconnect pad 106 beyond the perimeter or edge of interconnect pad 108 and / or an overlap of interconnect pad 108 beyond the perimeter or edge of interconnect pad 106. Due to the offset 112, a portion of one or both of conductive structures 106 and conductive structures 108 may contact insulating materials of substrate 104 and substrate 102, respectively. As discussed above, due to such contact, the conductive material (e.g., copper or copper alloy, etc.) of one or both of conductive structures 106 and conductive structures 108 may diffuse into insulating materials or dielectrics of substrate 104 and substrate 102. Additionally, some process elements (such as high temperature annealing, for example) or operating parameters (such as high frequency electric fields, etc.) may exacerbate diffusion of conductive materials into insulating materials or dielectrics of substrate 104 and substrate 102, resulting in, for example, undesirable leakage in dielectric layers.

[0039] Figure 2 1 is a graphical flow chart showing an exemplary method 200 of forming a microelectronic assembly 100 according to an embodiment, the microelectronic assembly including a pair of substrates 102 and 104 having an embedded conductive structure 106 and an embedded conductive structure 108. In an example, a damascene structure is formed by substrate 102. At block (A), a conductive material 202 (e.g., copper, copper alloy, nickel or nickel-bearing conductor, etc.) is deposited on the surface of substrate 102, including deposition into a damascene cavity, filling the cavity. At block (B), the conductive material 202 is planarized (e.g., via chemical mechanical polishing (CMP), etching, etc.) to form conductive structure 106. The exposed portion of conductive structure 106 may include interconnect pads 204. In one embodiment, it may be preferred that interconnect pads 204 may be slightly recessed below the bonding surface of substrate 102. The bonding surface is prepared by a cleaning method to remove defects, residual organic materials, etc. that cause undesirable particles. (One or more) clean surfaces may be prepared by exposing one or more of the surfaces to a nitrogen plasma to prepare for the bonding process.

[0040] At block (C), a similar damascene structure is formed from another substrate 104, which includes a conductive structure 108 after planarization. The exposed portion of the conductive structure 108 may include an interconnect pad 206. The prepared bonding surface of the substrate 104 is placed on the substrate 102 and stacked thereon in preparation for bonding. The assembled substrate 102 and substrate 104 are then heat treated at a temperature below 350° C. and preferably below 250° C. for a sufficient time to permanently bond the bonding surfaces and couple the opposing conductive materials both mechanically and electrically.

[0041] Boxes (D), (E), and (F) illustrate three potential outcomes of bonding substrate 102 to substrate 104. Box (D) represents an ideal scenario, where conductive structure 106 and conductive structure 108 are well aligned without offset. Box (E) represents an average scenario, where there is an average misalignment of conductive structure 106 and conductive structure 108 based on the average inaccuracy (e.g., tolerance) of the placement tool used to bond substrate 104 to substrate 102. Box (F) represents an extreme scenario, where there is an extreme misalignment of conductive structure 106 and conductive structure 108 based on the maximum inaccuracy (e.g., tolerance) of the placement tool used to bond substrate 104 to substrate 102. In general, the higher the placement speed of a pick and place tool, the lower its placement accuracy, i.e., the greater the offset. For applications with extremely small interconnect pad sizes, the placement tool can be significantly slowed down to improve placement accuracy, which affects throughput.

[0042] As described above, offset 112 (shown at blocks (E) and (F)) provides an opportunity to diffuse the conductive material of conductive structures 106 and 108 into the insulating material or dielectric of substrates 104 and 102, respectively.

[0043] Example blocking interface

[0044] According to the present disclosure, in order to prevent copper from diffusing into the oxide, for example, a barrier interface 302 including a dielectric bonding layer, a conductive barrier layer, or other barrier may be applied around the interconnect pad 106 and / or the interconnect pad 108 to form a barrier against diffusion. The barrier interface 302 material is selected so that the diffusion rate of the conductive material (e.g., copper) of the conductive structure 106 and the conductive structure 108 into the barrier material is poorer than the insulating material or dielectric (e.g., silicon oxide) of the substrate 104 and the substrate 102. In various embodiments, the barrier material may include a conductive or non-conductive material having a preselected diffusion characteristic.

[0045] Figure 3A and Figure 3Bis a profile diagram illustrating an example of a barrier interface 302 used with a stacked substrate 102 and a stacked substrate 104 having an embedded conductive structure 106 and an embedded conductive structure 108 according to various embodiments. In an embodiment, the substrate 102 and the substrate 104 are directly bonded without an intermediate material, such as an adhesive, to form a microelectronic assembly 300. In an embodiment, the microelectronic assembly 300 includes the microelectronic assembly 100 as discussed above, and includes one or more barrier interfaces 302 on one or both of the substrate 102 and the substrate 104. In an alternative embodiment, the microelectronic assembly 300 includes more than two substrates, such as the substrate 102 and the substrate 104, in a bonded stack, wherein one or more of the substrates of the stack include one or more barrier interfaces 302. In another embodiment, the microelectronic assembly 300 includes two or more substrates, such as the substrate 102 and the substrate 104, that are separately bonded to another substrate or wafer, wherein two or more of the substrates include one or more barrier interfaces 302.

[0046] In an embodiment, the blocking interface(s) 302 of the assembly 300 are disposed at one or both of the substrate 102 and the substrate 104 and at least partially surround the perimeter of the interconnect pad 204 and / or the interconnect pad 206 and / or the embedded conductive structure 106 and the embedded conductive structure 108, respectively. Figure 3A As shown, the (multiple) barrier interface 302 may include one or more materials that are different from the insulating material or dielectric of the substrate 102 and / or the substrate 104. For example, the (multiple) barrier interface 302 may include a dielectric material that is different from the insulating material or dielectric of the substrate 102 and / or the substrate 104. In various embodiments, the (multiple) barrier interface 302 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, diamond, boron-doped glass or oxide, aluminum oxide, or similar diffusion-resistant materials. In other embodiments, the (multiple) barrier interface 302 includes nickel, nickel alloys, or one or more other conductive materials in various combinations.

[0047] Additionally, employing barrier interface 302 may include techniques to prevent diffusion by avoiding bonding at the associated bonding interface. For example, in various embodiments, respective conductive interconnect structures 106 and conductive interconnect structures 108 may be bonded but with little or no bonding to the immediately surrounding insulating material or dielectric. Figure 3BAs shown, one or more of the barrier interfaces 302 may include recesses, air gaps, or gas-filled cavities, etc. Likewise, the barrier interfaces 302 include a material that is different from the insulating material or dielectric of the substrate 102 and / or substrate 104. In various embodiments, the barrier interfaces 302 include an inert gas or fluid, a preselected gas or fluid (based on the desired properties), a vacuum, etc. The air gap barrier interfaces 302 may be formed by etching, making undercuts in the substrate 102 and / or substrate 104, recessing the substrate 102 and / or 104 via CMP, grinding, filleting of the substrate near the substrate, and the interconnect pad interface during CMP, etc.

[0048] See also Figure 3A and Figure 3B In an embodiment, the barrier interface(s) 302 are arranged to inhibit the diffusion of the materials of the conductive interconnect structure 106 and the conductive interconnect structure 108 into the substrate 104 and the substrate 102, respectively. For example, the materials of the barrier interface(s) 302 are selected so that the diffusion rate of the materials of the conductive interconnect structure 106 into the substrate 104 or the barrier interface(s) 302 of the substrate 102 or the diffusion rate of the materials of the conductive interconnect structure 108 into the substrate 104 or the barrier interface(s) 302 of the substrate 102 is less than the diffusion rate of the materials of the conductive interconnect structure 106 or the conductive interconnect structure 108 into the substrate 104 or the substrate 102 (e.g., silicon oxide).

[0049] In various embodiments, one or more of the blocking interfaces 302 may be arranged to completely surround or enclose the conductive structure 106 and / or the conductive structure 108 and / or their respective interconnect pads 204 and / or interconnect pads 206 (i.e., the mating surfaces of the conductive structure 106 and the conductive structure 108, respectively), or partially surround the conductive structure 106 and / or the conductive structure 108 and / or their respective interconnect pads 204 and / or interconnect pads 206, forming a barrier that blocks the diffusion of conductive material (e.g., copper) into the material (silicon oxide) of the substrate 102 and the substrate 104.

[0050] like Figure 3A and Figure 3B As shown, in various embodiments, the blocking interface 302 has a placement accuracy 306 (also indicated by Figure 1112 in FIG. 1 ). This thickness of barrier interface 302 ensures that the material of conductive structure 106 and conductive structure 108 will contact barrier interface 302 rather than substrate 104 or substrate 102 in the case of maximum placement misalignment. This ensures that any conductive material overlap occurs at barrier interface 302 rather than at substrate material (e.g., silicon oxide), thereby preventing diffusion. Additionally, this significantly relaxes the placement accuracy requirements of the pick and place tool, which can improve throughput, especially during die-to-die and die-to-wafer bonding processes.

[0051] Thus, in one embodiment, the relative lateral displacement of one interconnect pad 204 (of the conductive structure 106) from another interconnect pad 206 (of the conductive structure 108) is less than the width of one or more of the blocking interfaces 302. Further, in one embodiment, the width of one or more of the blocking interfaces 302 is at least 10% of the diameter of the conductive structure 106 and / or the interconnect pads 204 and / or 206 of the conductive structure 108. In other embodiments, the width of one or more of the blocking interfaces is at least 20% of the diameter of the interconnect pads 204 and / or the interconnect pads 206.

[0052] like Figure 3B As shown, in some embodiments, at least some portions of the pads 204 extend or protrude beyond the recessed surface of the insulating material of the substrate 102 on the microelectronic assembly 300 after bonding, and may extend beyond the bonding wires 110. This extension may be the result of forming the blocking interface 302, it may also be the result of dielectric erosion (i.e., rounding) on ​​the surface of the substrate 102 around the perimeter of the pads 204 due to planarization, or both, or other reasons, either separately or in combination. Similar extension or protrusion of at least some portions of the pads 206 past the recessed surface of the substrate 104 after bonding, and possibly extension past the bonding wires 110, may also exist in embodiments.

[0053] In any case, the extension of pad 204 and / or pad 206 results in an air gap (intentional or otherwise) at least partially surrounding pad 204 and / or pad 206. In some cases, when interconnect pad 204 and interconnect pad 206 are misaligned (e.g., Figure 3B As shown, in some embodiments, there may be only a partial extension or protrusion of pad 204 or pad 206 through at least some portions of bonding wire 110.

[0054] exist Figure 3AIn the embodiment, the relative lateral displacement of one interconnect pad 204 (of the conductive structure 106) and the other interconnect pad 206 (of the conductive structure 108) is less than the width of one or more of the barrier interfaces 302. During annealing, when the conductive pads 204 / 206 expand more than the substrate material 102 / 104 and the barrier interface material 302, this high mismatch between the thermal expansion coefficients may induce debonding of portions of the substrate 102 from the substrate 104 at locations where the pads 204 / 206 push the barrier interface 302. In an embodiment, the debonding may be mitigated (e.g., reduced or eliminated) by adjusting the annealing time and temperature. In an embodiment, the bonding surfaces may be heat treated at about 100-150° C. for 2 to 4 hours to form a strong bond between the substrate 102 and the substrate 104. The pads 204 and 206 may then be annealed at about 250-400° C. for 10 seconds to less than 300 seconds during a second thermal treatment using a pulse annealing technique. In an example, the pulse annealing time of the second thermal treatment is less than 10% of the heating time of the first thermal treatment. In an embodiment, the adjusted heating / annealing time is effective to reduce or eliminate mismatch stresses or loads of the bonded microelectronic assembly 300 .

[0055] Although Figure 3A and Figure 3B The conductive structures are shown extending through substrate 102 and substrate 104, but these structures may extend partially through the substrate or layers on the substrate. For simplicity, and to focus on the structures or portions of the structures at the bonding interface, the conductive structures are shown in FIGS. Figure 7 Specific details of the conductive connections on, in or through the substrate are not shown.

[0056] FIG. 4A to FIG. 4E 1 is a schematic diagram illustrating an additional example barrier interface 302 for use with stacked substrates 102 and 104 having embedded conductive structures 106 and embedded conductive structures 108 according to additional embodiments. Figure 3A and Figure 4A As shown, the blocking interface 302 may be embedded in one or more of the substrate 102 and / or the substrate 104. In an embodiment, as shown in FIG. Figure 3A and Figure 4A As shown, one or more blocking interfaces 302 are embedded in substrate 102 and / or substrate 104 and extend into substrate 102 and / or substrate 104 to a depth that is less than or equal to the depth of conductive structure 106 or conductive structure 108. In this configuration, substrate 102 and substrate 104 are protected from diffusion of conductive materials. Figure 3A and Figure 4AAs shown, the blocking interface 302 may be disposed (and may be exposed) on a bonding surface of the substrate 102 and / or the substrate 104 , and may extend a predetermined depth into the substrate 102 and / or the substrate 104 .

[0057] like Figure 4B As shown, when the conductive structure 106 and the conductive structure 108 are of different sizes, the blocking interface 302 can be used on one of the substrate 102 or the substrate 104. For example, the blocking interface 302 (at a favorable thickness) can be used on the smaller of the conductive structure 106 and the conductive structure 108 to prevent diffusion from the larger of the conductive structure 106 and the conductive structure 108 without exposing the overlap on the substrate 102 or the substrate 104. For example, in an embodiment, the width of the first interconnect pad 106 is less than the width of the second interconnect pad 108, and the blocking interface 302 is disposed at the first substrate 102, at least partially surrounding the perimeter of the first interconnect pad 106. The thickness / width of the blocking interface 302 is such that the combined width of the first interconnect pad 106 and the blocking interface 302 is greater than the width of the second interconnect pad 108. In other words, as in each of the embodiments, at least one of the peripheral edges of the second interconnect pad 108 is within the perimeter of the blocking interface 302. The other peripheral edge of the second interconnect pad 108 is also within the perimeter of the barrier interface 302 or within the perimeter of the first interconnect pad 106 (to prevent diffusion into the substrate material).

[0058] like Figure 4C As shown, the embedded barrier interface 302 may or may not be exposed on the bonding surface of the substrate 102 and the substrate 104. The barrier interface 302 may be disposed at a preselected distance below the bonding surface and may have various depths and thicknesses (i.e., widths or ranges). For example, in one embodiment, the barrier interface 302 may extend over the entire width of the substrate 102 or the substrate 104. The barrier interface 302 may abut the conductive structure 106 and / or the conductive structure 108, and the diffusion may be limited to the area of ​​the substrate 102 and the substrate 104 above the barrier interface 302, and the barrier interface 302 prevents diffusion below the barrier interface 302. In some embodiments, such a barrier interface 302 may be composed of a polymer layer or a similar material having desired diffusion characteristics.

[0059] like Figure 4DAs shown, the blocking interface 302 may include a rough area of ​​the bonding surface of the substrate 102 and / or substrate 104, which may include one or more gaps with a predetermined width in the bonding between the substrate 102 and the substrate 104. For example, a highly flat bonding surface with low variance in topology is usually prepared on both the substrate 102 and the substrate 104 so as to have a reliable direct bonding between the substrate 102 and the substrate 104. However, in an embodiment, the surface area of ​​the substrate 102 and / or substrate 104 that partially or entirely surrounds the conductive structure 106 and / or the conductive structure 108 may have a higher roughness (with a greater variation in surface topology) to produce an uneven or irregular surface between the substrate 102 and the substrate 104, thereby reducing or eliminating the bonding at this area of ​​the substrate 102 and the substrate 104. For example, the roughness may make the surface not smooth enough (or leave insufficient surface contact) to form a bond. The high roughness (e.g., a variation greater than 10nm) blocking interface 302 may be formed using etching, cutting, grinding, selective CMP, etc.

[0060] Similar to reference Figure 4B The described embodiments, such as Figure 4E As shown, when the conductive structures 106 and 108 are of different sizes, the blocking interface 302 can be used on one of the substrate 102 and the substrate 104. Figure 4E In the case of the barrier interface 302, the barrier interface 302 includes an air gap (or fluid-filled gap) used with the smaller of the conductive structure 106 and the conductive structure 108. When the barrier interface 302 is dimensioned advantageously, there is no overlap, and therefore no diffusion, of the conductive material with the substrate 102 or on the substrate 104. For example, the air gap barrier interface 302 is dimensioned such that any offset between the interconnect pad 204 and the interconnect pad 206 (effectively the edges of the interconnect pad 204 and the interconnect pad 206) falls within the barrier interface 302 and not at the material of the substrate 102 and the substrate 104.

[0061] In an implementation, the one or more blocking interfaces 302 include a combination of two or more of: a plurality of air gaps, one or more materials different from the insulating or dielectric material of the substrates 102 and 104 , and a roughened surface of a predetermined width.

[0062] like Figure 4F As shown in the plan view of FIG. 1 , in an embodiment, a plurality of conductive structures 106 (or interconnect pads 204) may be partially or completely surrounded or enclosed by a single barrier interface 302. In such embodiments, substrate 102 may be bonded to another substrate 104 having a plurality of conductive structures 108, or more than one substrate having conductive structures.

[0063] Alternatively, the plurality of blocking interfaces 302 may partially or completely surround one or more of the conductive structures 106, 108, or the interconnect pads 204, 206 of one or more of the substrates 102 and 104. For example, FIG. 5A to FIG. 5C As shown, the plurality of conductive structures 106 and conductive structures 108 are partially or fully surrounded by the blocking interface 302. For example, in an embodiment, the plurality of additional conductive interconnect structures 106 are embedded in the substrate 102, wherein the surface of each of the additional conductive interconnect structures 106 is exposed through the bonding surface of the substrate 102 to form the plurality of additional interconnect pads 204. The plurality of additional conductive interconnect structures 108 are embedded in the opposing substrate 104, and the surface of each of the additional conductive interconnect structures 108 is exposed through the bonding surface of the substrate 104 to form the plurality of additional interconnect pads 206.

[0064] The barrier interface 302 at least partially surrounds at least a subset of the pad group including the first interconnect pad 106 and the plurality of additional interconnect pads 106. Based on the position and composition of the barrier interface 302, the barrier interface 302 is arranged to inhibit the conductive material of the interconnect structure group including the conductive interconnect structure 108 and the plurality of additional conductive interconnect structures 108 from diffusing into the substrate 102. Further, the barrier interface(s) 302 may be arranged to inhibit the conductive material of the interconnect structure group including the conductive interconnect structure 106 and the plurality of additional conductive interconnect structures 106 from diffusing into the substrate 104.

[0065] like Figure 5A and Figure 5C As shown, each of the plurality of conductive structures 106 and 108 may include a barrier interface 302. For example, in an embodiment, one or more additional barrier interfaces 302 are disposed at the substrate 102 and / or the substrate 104, which interfaces at least partially surround the perimeter of the first interconnect pad 106 and the plurality of additional interconnect pads 106, and / or the second interconnect pad 108 and the plurality of additional interconnect pads 108. The one or more additional barrier interfaces 302 include a material different from the insulating material or dielectric of the substrate 102 and / or the substrate 104, and are arranged to inhibit diffusion of material of the interconnect structure group including the conductive interconnect structure 108 and the plurality of additional conductive interconnect structures 108 into the material of the substrate 102 based on the location and composition of the barrier interfaces 302. Further, the one or more additional barrier interfaces 302 may be arranged to inhibit diffusion of material of the interconnect structure group including the conductive interconnect structure 106 and the plurality of additional conductive interconnect structures 106 into the material of the substrate 104.

[0066] refer to FIG. 5A to FIG. 5CIn some embodiments, between each barrier interface 302 may be a gap 502, which may be a space between the barrier interfaces 302, a gap filled with a gas, etc. The gap 502 forms a physical separation between the bonding surfaces of the substrate 102 and the substrate 104 (at least around the perimeter of the conductive structure 106 and / or the conductive structure 108). In some embodiments, the combination of the barrier interface 302 and the gap(s) 502 prevents or reduces the diffusion of the conductive material of the conductive structure 106 and / or the conductive structure 108 and their respective interconnect pads 204 and interconnect pads 206 into the material of the substrate 104 and the substrate 102. In another embodiment, no such gap 502 is formed between the bonding surfaces of the substrates 102 and 104.

[0067] Alternatively, if Figure 5B As shown, a single conductive structure 106 and / or conductive structure 108 and a group of two or more conductive structures 106 and / or conductive structures 108 may be partially or completely surrounded by a single barrier interface 302. Between barrier interfaces 302, there may or may not be gaps 502, as described above. Through holes (e.g., TSVs) such as through hole 504 may be present in any of the embodiments discussed herein, including Figure 5B The through hole 504 may extend to the outer extent (eg, exposed surface) of one or both of the substrate 102 and the substrate 104 (and extend beyond it), or it may have some portions extending through the substrate 102 and / or the substrate 104.

[0068] Exemplary Methods

[0069] Figure 6 is a graphical flow chart illustrating an exemplary method 600 of forming a microelectronic assembly 300 including a pair of substrates 102 and 104 having embedded conductive structures 106 and 108 and one or more barrier interfaces 302 according to an embodiment.

[0070] At block A, the method includes forming a cavity 602 (or a plurality of cavities 602 and a cavity 603) in a surface of a substrate 102. Cavity 602 and cavity 603 may be formed by patterned etching, etc. In an embodiment, one of cavities 603 may extend to a depth less than 5% of the depth of the other cavity 602. At block B, a barrier layer 604 is formed on the surface of substrate 102 and within cavity 602. Barrier layer 604 may be, for example, made of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, diamond, boron-doped glass or oxide, aluminum oxide, or other suitable materials with poor diffusivity than silicon oxide, or combinations thereof. In other embodiments, barrier layer 604 may include a conductive material, such as titanium or tantalum or their corresponding nitrides, nickel and nickel alloys, or other conductive materials and combinations thereof.

[0071] At block C, the cavity 602 coated with the barrier layer 604 is filled with a conductive material 202, such as copper, a copper alloy, etc. This can be done, for example, using a dual damascene process. In some examples, it may be desirable for the conductive structure 106 to contact the bottom of the cavity 602 at the substrate 102 instead of the barrier layer 604. In these examples, portions of the barrier layer 604 may be removed from the bottom portion of the cavity 602 (and / or any other desired portion) to expose the substrate 102 before the cavity 602 is filled with the conductive material 202.

[0072] At block D, the excess conductive material 202 is removed by etching, CMP, etc. (stopping at the barrier layer 604) to form a conductive structure 106 (or multiple conductive structures 106) within the barrier layer 604. At block E, the conductive structure 106 and a portion of the barrier layer 604 are planarized via, for example, CMP to form a barrier interface 302 that partially or completely surrounds the interconnect pad 204 (which may have a very small recess) and a substantially planar surface (having a smooth surface topography with variations of no more than 10-20 nm) of the substrate 102.

[0073] In some embodiments, the barrier layer 604 or barrier interface 302 can be used to prevent or mitigate the erosion of the insulating material or dielectric of the substrate 102 that may occur during planarization (e.g., rounding). For example, the barrier layer 604 can extend beyond the predetermined range (i.e., width, diameter, etc.) of the conductive structure 106 and extend on the surface of the substrate 102 to protect the surface of the substrate 102 during planarization. In other words, the first barrier interface 302 is disposed on at least a portion of the substantially flat surface of the first substrate 102 and is arranged to protect the substantially flat surface from erosion caused by planarization or polishing of the substantially flat surface. With the barrier interface 302 in place, dielectric erosion (e.g., rounding) does not occur at the intersection of the conductive structure 106 and the substrate 102, or at the intersection of the barrier layer interface 302 and the substrate 102. In some examples, the barrier interface 302 can be used as an indicator for polishing the substrate 102, and in some examples, the barrier interface 302 can also be polished by a desired amount to obtain a flat, smooth bonding surface.

[0074] At block F, a similar microelectronic structure with the prepared substrate 104, conductive structure 108, and barrier layer 302 is placed onto substrate 102 for bonding. At block G, substrate 104 is directly bonded to substrate 102 without an intermediate material (such as an adhesive) to form microelectronic assembly 300. In particular, substrate 104 is bonded to a bonding surface of substrate 102 and barrier layer 302 on substrate 102, and substrate 102 is bonded to a bonding surface of substrate 104 and barrier layer 302 on substrate 104. In this step, conductive structure 106 from substrate 102 and conductive structure 108 from substrate 104 may be slightly recessed below bond wire 110 due to the CMP process and may not be in physical contact. In some cases, conductive structure 108 may be bonded to conductive structure 106 via heat annealing or the like. After annealing at high temperature as discussed above, conductive structure 108 mates with conductive structure 106 to form an electrical connection.

[0075] Any offset of conductive structure 106 from conductive structure 108 due to misalignment is located on barrier interface 302 rather than on substrate 102 and substrate 104. Thus, diffusion of conductive material (e.g., copper) into substrate 102 and / or substrate 104 material (e.g., silicon oxide) is reduced or eliminated due to barrier interface(s) 302.

[0076] In another embodiment, Figure 6After planarization at block E of , an additional layer is deposited on the interconnect pad 204 and the barrier layer 302, which is typically of the same type of material as the substrate 102 (e.g., silicon oxide). This is followed by another planarization process, such as CMP, to remove excess substrate material and obtain a surface in which the barrier layer 302 is flush with the surface of the substrate 102 surrounding it. The barrier layer 302 partially or completely surrounds the interconnect 204, and the substrate layer 102 completely or partially surrounds the barrier layer 302. In this embodiment, during block G, direct bonding of the bonding layers 102 and 104 occurs together with direct bonding of the barrier layer 302 of the substrate 102 to the barrier layer 302 of the substrate 104. This is followed by an annealing step, in which the conductive structure 108 can be bonded to the conductive structure 106 via a heat anneal or the like.

[0077] Figure 7 is a graphical flow chart illustrating an exemplary method 700 of forming a microelectronic assembly 300 including a pair of substrates 102 and 104 having embedded conductive structures 106 and embedded conductive structures 108 and one or more barrier interfaces 302 according to another embodiment.

[0078] At block A, the method includes depositing a barrier material 604 onto a surface of an oxide or other dielectric (e.g.) substrate 102. At block B, a portion of the barrier 604 and a portion of the dielectric of the substrate 102 are removed, and the resulting cavity 602 is filled with the conductive material 202 (at block C). In some embodiments, the method of forming the conductive material 602 in the cavity 202 may include coating a second barrier layer (not shown) on the surface of the first barrier 604 and the cavity 602 before filling the cavity 602 with the conductive material 202.

[0079] At block D, a conductive structure 106 having interconnect pads 204 surrounded by a barrier interface 302 is formed by planarizing the conductive material 202 and the second barrier layer (if present). In an embodiment, the barrier interface 302 is effective to prevent dielectric erosion of the substrate 102 at the intersection of the conductive structure 106 during planarization. In an embodiment, the structure 102 having the prepared barrier interface 302 and conductive structure 106 can be bonded to another similar structure, but without the barrier interface 302 on the other structure. In such an embodiment, the barrier layer 302 can act as a bonding surface for the other structure based on the material used for the barrier layer (e.g., silicon nitride, etc.).

[0080] At Block E, if desired, the blocking interface 302 may be altered to remove any undesired portions. A resist, mask, or other pattern 702 may be deposited, and the blocking interface 302 may be etched as desired (at Block F). Additional substrate material (such as silicon oxide, for example) may be deposited on the surface of the substrate 102 to prepare the surface for bonding. For example, the added material may be deposited while the mask 702 is still in place or after the mask 702 is removed. The surface of the substrate 102 is then planarized (via CMP, etc.) to obtain a flat, smooth surface (the flat, smooth surface includes the surface of the substrate 102 that is flush with the blocking interface 302) in preparation for bonding.

[0081] At block G, the fabricated substrate 102 is shown with the interconnect pad 204 having a partially or completely surrounding barrier interface 302. Two similarly fabricated substrates 102 and 104 may be stacked and bonded on their planarized surfaces to form a microelectronic structure 300, as shown at block H. Any overlap of conductive material occurs at the barrier interface(s) 302 rather than at the dielectric of the substrate 102 and / or substrate 104. The method may also be used to form a plurality of conductive interconnect structures 106, 108 having a barrier interface(s) 302 that partially or completely surrounds the plurality of conductive interconnect structures 106, 108.

[0082] In an alternative embodiment, conductive structure 106 and / or conductive structure 108 may include a conductive mechanical pad. In this embodiment, the mechanical pad mates with barrier layer 302 or substrate 102 / 104 to secure the mechanical pad to substrate 102 / 104.

[0083] Figure 8 8 is a flow chart describing an example process 800 of forming a microelectronic assembly (such as microelectronic assembly 300) according to an embodiment, the microelectronic assembly including a pair of substrates (such as, a pair of substrates 102 and 104) having embedded conductive structures (such as conductive structure 106 and conductive structure 108) and one or more blocking interfaces (such as, blocking interface 302).

[0084] At block 802, the process includes forming a first cavity (or a plurality of first cavities) in a surface of a first substrate (e.g., such as substrate 102). In an embodiment, the first substrate includes an insulating material or a dielectric (such as silicon oxide, etc.), which may be disposed on a semiconductor substrate having a circuit on, in, or through the substrate. At block 804, the process includes forming a first blocking interface (e.g., such as blocking interface 302) at the first substrate, and at least partially surrounding the periphery of the first cavity. In an embodiment, the process includes depositing a first barrier material onto at least a portion of the surface of the first cavity. The first barrier material may also be deposited on at least a portion of the surface of the first substrate, particularly partially or completely surrounding the first cavity. In an embodiment, the first blocking interface includes a material different from the insulating material or the dielectric, and is arranged to inhibit diffusion of conductive material into the first substrate.

[0085] At block 806, the process includes filling the first cavity with a conductive material. In various embodiments, the conductive material includes copper, a copper alloy, or a similar conductive material.

[0086] At block 808, the process includes planarizing at least a portion of the surface of the first substrate, the first barrier interface (including the first barrier layer material), and the conductive material to form a first conductive interconnect structure, wherein the first barrier interface at least partially surrounds the exposed surface of the first conductive interconnect structure. In an embodiment, the first barrier interface is formed to have a predetermined width.

[0087] In an alternative embodiment, the process includes depositing an additional layer of insulating material or dielectric (e.g., silicon oxide) onto the surface of the first substrate to improve the bonding surface of the substrate. For example, the deposition can be used to fill any gaps created during the previous planarization step so that the surface of the substrate is flush with the barrier interface. In an embodiment, after the deposition, the surface of the substrate is re-planarized to form a flat, smooth and flush bonding surface. The first barrier interface (at least partially) surrounds the conductive interconnect, and the insulating material or dielectric (at least partially) surrounds the first barrier interface.

[0088] In an embodiment, the process includes forming a second cavity in a surface of a second substrate (e.g., such as substrate 104), wherein the second substrate also includes an insulating material or a dielectric. The process includes forming a second blocking interface at the second substrate and at least partially surrounding a perimeter of the second cavity, wherein the second blocking interface includes a material different from the insulating material or dielectric of the second substrate. In an embodiment, the process includes depositing a second blocking layer material onto at least a portion of the surface of the second substrate and onto at least a portion of the surface of the second cavity.

[0089] The second barrier interface is arranged to inhibit the conductive material of the first conductive structure (embedded in the first substrate) from diffusing into the second substrate. In an embodiment, the process includes forming the first barrier interface and / or the second barrier interface to include a gap filled with air. In another embodiment, the process includes forming the first barrier interface and / or the second barrier interface to include a rough area on the surface of the first substrate and / or the second substrate, which inhibits bonding at the rough area. In other embodiments, the first barrier interface and / or the second barrier interface include one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, diamond, boron-doped glass or oxide, aluminum oxide, or similar diffusion-resistant materials.

[0090] In an embodiment, the process includes filling the second cavity with a conductive material and planarizing the second substrate, the second barrier interface, and at least a portion of the surface of the conductive material at the second substrate to form a second conductive interconnect structure (e.g., such as conductive structure 108), wherein the second barrier interface at least partially surrounds the exposed surface of the second conductive interconnect structure. In one example, the process includes forming the first barrier interface or the second barrier interface to have a width of at least 10% of the diameter of the second conductive interconnect structure. In another example, the process includes forming the first barrier interface or the second barrier interface to have a width of at least 20% of the diameter / width of the second conductive interconnect structure.

[0091] The process further includes directly bonding the surface of the second substrate to the surface of the first substrate without an adhesive material, and mating the second conductive interconnect structure to the first conductive interconnect structure such that when the second conductive interconnect structure and the first conductive interconnect structure are offset or misaligned, any portion of the second conductive interconnect structure contacts the first barrier interface without contacting the first substrate, and any portion of the first conductive interconnect structure contacts the second barrier interface without contacting the second substrate.

[0092] In an embodiment, the process includes bonding the exposed surface of the second conductive interconnect structure directly to the exposed surface of the first conductive interconnect structure. In an example, the process includes a high temperature anneal to bond the conductive structures into a single conductive interconnect.

[0093] Although various embodiments and examples are discussed herein, other embodiments and examples are possible by combining features and elements of individual embodiments and examples.

[0094] in conclusion

[0095] Although the embodiments of the present disclosure have been described using language specific to structural features and / or methodological acts, it should be understood that these embodiments are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as representative forms of implementing exemplary devices and techniques.

[0096] Each claim of this document constitutes a separate embodiment, and embodiments combining different claims and / or different embodiments are within the scope of the disclosure and will be apparent to those of ordinary skill in the art after reading this disclosure.

Claims

1. A microelectronic assembly comprising: A first substrate having a bonding surface, and comprising: a first insulating material having a first cavity and a second cavity, the first cavity and the second cavity extending at least partially through a thickness of the first insulating material, a first conductive interconnect structure, at least partially disposed in the first cavity, a second conductive interconnect structure, at least partially disposed in the second cavity, an embedded barrier interface embedded in the first substrate and extending horizontally from the first conductive interconnect structure to the second conductive interconnect structure, the embedded barrier interface having a thickness thinner than a thickness of the first conductive interconnect structure, and a bonding layer over the embedded barrier interface and at least partially defining the bonding surface of the first substrate, the bonding layer extending from the first conductive interconnect structure to the second conductive interconnect structure; and a second substrate having a bonding surface directly bonded to the bonding surface of the first substrate without an adhesive in between, the first substrate and the second substrate being vertically stacked, the second substrate comprising: a second insulating material having a third cavity extending at least partially through a thickness of the second insulating material, and A third conductive interconnect structure is at least partially disposed in the third cavity, the third conductive interconnect structure being directly bonded to the first conductive interconnect structure without an intervening adhesive, wherein the embedded barrier interface inhibits diffusion of material of the third conductive interconnect structure into the first insulating material. 2 . The microelectronic assembly of claim 1 , wherein the embedded barrier interface extends across the first substrate. 3 . The microelectronic assembly of claim 2 , wherein the embedded barrier interface extends across a thickness of the first substrate.

4. The microelectronic assembly of claim 2, wherein the embedded barrier interface surrounds and abuts a perimeter of a group of conductive interconnect structures, the group of conductive interconnect structures comprising a first conductive interconnect structure and a second conductive interconnect structure.

5. The microelectronic assembly of claim 2, wherein the embedded barrier interface extends across a conductive interconnect structure region of the first substrate and is surrounded by a region devoid of the embedded barrier interface. 6 . The microelectronic assembly of claim 1 , wherein the embedded barrier interface surrounds and abuts a perimeter of the first conductive interconnect structure.

7. A microelectronic assembly as claimed in claim 1, wherein the bonding surface of the first substrate comprises a nitrogen plasma treated surface.

8. A microelectronic assembly as claimed in claim 1, wherein the embedded barrier interface comprises a dielectric material that is different from the first insulating material and the bonding layer.

9. A microelectronic assembly as claimed in claim 1, wherein the first insulating material and the second insulating material comprise silicon oxide.

10. The microelectronic assembly of claim 1, wherein the width of the first conductive interconnect structure is narrower than the width of the third conductive interconnect structure.

11. The microelectronic assembly of claim 1, wherein the first insulating material comprises a silicon oxide material and the material of the third conductive interconnect structure comprises copper or a copper alloy.

12. A microelectronic assembly according to claim 1, wherein the second substrate further includes a second embedded barrier interface and a second bonding layer formed on the second embedded barrier interface, the second embedded barrier interface is below the bonding surface of the second substrate, the second embedded barrier interface has a thickness thinner than the third conductive interconnect structure, and the second bonding layer at least partially defines the bonding surface of the second substrate.

13. The microelectronic assembly of claim 12, wherein the second substrate further comprises a fourth conductive interconnect structure laterally spaced apart from the third conductive interconnect structure and the fourth conductive interconnect structure is directly bonded to the second conductive interconnect structure.

14. The microelectronic assembly of claim 13, wherein the second embedded barrier interface extends between the third conductive interconnect structure and the fourth conductive interconnect structure.

15. A microelectronic assembly as claimed in claim 1, wherein the embedded barrier interface is located closer to the bonding surface of the first substrate than to a backside of the first conductive interconnect structure.

16. A microelectronic assembly as claimed in claim 1, wherein the bonding layer comprises silicon and oxygen.

17. A substrate having a bonding surface, the substrate comprising: a first insulating material having a first cavity and a second cavity, the first cavity and the second cavity extending at least partially through a thickness of the first insulating material; a first conductive interconnect structure at least partially disposed in the first cavity, at least a portion of the first conductive interconnect structure comprising a first interconnect pad; a second conductive interconnect structure at least partially disposed in the second cavity, at least a portion of the second conductive interconnect structure comprising a second interconnect pad; and an embedded barrier interface embedded in the substrate and extending horizontally from the first conductive interconnect structure to the second conductive interconnect structure, the embedded barrier interface having a thickness thinner than a thickness of the first conductive interconnect structure, wherein the embedded barrier interface is spaced apart from the bonding surface and closer to the bonding surface than a back side of the first conductive interconnect structure, wherein the bonding surface of the substrate is prepared for direct bonding and includes a dielectric surface separated from the embedded barrier interface, the dielectric surface extending from the first conductive interconnect structure to the second conductive interconnect structure, and The embedded barrier interface inhibits diffusion of conductive material from the bonding surface into the first insulating material.

18. The substrate of claim 17, further comprising a bonding layer on the embedded barrier interface and defining the dielectric surface of the substrate.

19. The substrate of claim 17, wherein the embedded barrier interface extends across the substrate.

20. The substrate of claim 19, wherein the embedded barrier interface extends across a width of the substrate.

21. The substrate of claim 19, wherein the embedded barrier interface surrounds and abuts a perimeter of a group of conductive interconnect structures, the group of conductive interconnect structures comprising a first conductive interconnect structure and a second conductive interconnect structure.

22. The substrate of claim 19, wherein the embedded barrier interface extends across a conductive interconnect structure region of the substrate and is surrounded by a region devoid of the embedded barrier interface.

23. The substrate of claim 17, wherein the bonding surface of the substrate has a surface topography with a variance of no more than 20 nm.

24. The substrate of claim 23, wherein the bonding surface of the substrate has a surface topography with a variance of no more than 10 nm.

25. The substrate of claim 17, further comprising a third conductive interconnect structure laterally spaced apart from the first conductive interconnect structure and the second conductive interconnect structure.

26. The substrate of claim 25, wherein the embedded barrier interface extends between and abuts the second and third conductive interconnect structures.

27. The substrate of claim 17, wherein the embedded barrier interface includes a perimeter of the first conductive interconnect structure and a perimeter of the second conductive interconnect structure.

28. The substrate of claim 17, wherein the first conductive interconnect structure and the second conductive interconnect structure are recessed relative to the bonding surface of the substrate.

29. The substrate of claim 17, wherein the bonding surface of the substrate comprises a nitrogen plasma treated surface.

30. The substrate of claim 17, wherein the insulating material of the substrate comprises a silicon oxide material, and a material of the first conductive interconnect structure comprises copper or a copper alloy.

31. A bonding structure comprising the substrate of claim 17, and a second substrate having a second insulating material and a third conductive interconnect structure, the third conductive interconnect structure being directly bonded to the first conductive interconnect structure of the substrate without an intervening adhesive.

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