Method for preparing fin field-effect transistor

Abstract

A method for fabricating a fin field-effect transistor includes: providing a substrate and a plurality of fin structures spaced apart on a surface of the substrate; forming shallow trench isolation structures between adjacent fin structures; forming a stress layer on a side of the shallow trench isolation structure facing away from the substrate, the stress layer encapsulating portions of the plurality of fin structures facing away from the substrate; thermally treating the stress layer and the plurality of fin structures; and removing the stress layer. By providing a stress layer that completely encapsulates the upper ends of the narrow and elongated fin structures, a pulling force is applied from the edges of the plurality of fin structures toward the center, thereby strengthening the uprightness of each fin structure and preventing the fin structures from skewing or bending.

Description

Technical Field

[0001] The invention relates to a method for preparing a fin field effect transistor. Background Art

[0002] With the rapid advancement of semiconductor manufacturing technology, the size of semiconductor devices continues to shrink, and the gate size of planar transistors is also getting shorter and shorter. This weakens the ability of traditional planar transistors to control channel current, resulting in a short-channel effect (SCE) and leakage current, ultimately affecting the electrical performance of semiconductor devices. To overcome the SCE of planar transistors and suppress leakage current, three-dimensional multi-gate structures such as the Fin Field-Effect Transistor (FinFET) have been developed. The FinFET structure comprises: a fin located on the surface of a semiconductor substrate and a dielectric layer, the dielectric layer covering a portion of the fin's sidewalls and with a surface lower than the top of the fin; a gate structure located on the surface of the dielectric layer and on the top and sidewalls of the fin; and source and drain regions located within the fin on either side of the gate structure. This FinFET design significantly improves circuit control and reduces leakage current, leading to its widespread application. The fins of FinFETs are typically long and narrow, with a large aspect ratio. However, as the aspect ratio of the fin increases, the fins formed using existing fabrication processes are prone to skew and bowing, which can affect the performance of the FinFET. Summary of the Invention

[0003] In view of this, the present invention provides a method for preparing a fin field effect transistor, which can effectively ensure the uprightness of a narrow and long fin structure and prevent the problem of skewing and bending.

[0004] A method for preparing a fin field effect transistor comprises:

[0005] Providing a substrate and a plurality of fin structures spaced apart from each other on a surface of the substrate;

[0006] forming a shallow trench isolation structure between adjacent fin structures;

[0007] forming a stress layer on a side of the shallow trench isolation structure away from the substrate, wherein the stress layer wraps portions of the plurality of fin structures away from the substrate;

[0008] performing a thermal treatment on the stress layer and the plurality of fin structures; and

[0009] The stress layer is removed.

[0010] The method for preparing a fin field-effect transistor of the present invention provides a stress layer that completely wraps the upper end portion of a narrow and long fin structure, thereby producing an effect of applying a pulling force from the edges of the multiple fin structures to the middle of the multiple fin structures, thereby enhancing the upright effect of each fin structure and preventing the fin structure from being skewed or bent. In addition, after achieving this effect, the stress layer is removed, which does not affect the subsequent formation of other components on the fin structure, and can also effectively ensure that the fin structure can still maintain an upright effect in the subsequent steps of forming other components on the fin structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 4 is a flow chart of a method for preparing a fin field effect transistor according to an embodiment of the present invention.

[0012] Figure 2 FIG. 1 is a cross-sectional diagram of steps S1 to S2 of a method for fabricating a FinFET according to an embodiment of the present invention.

[0013] Figure 3 FIG. 1 is a cross-sectional diagram of steps S3 to S7 of a method for fabricating a FinFET according to an embodiment of the present invention.

[0014] Description of main component symbols

[0015] substrate 10

[0016] Fin structure 20

[0017] Groove 25

[0018] Shallow trench isolation structure 30

[0019] Part 121

[0020] Part 23

[0021] Stress layer 40

[0022] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be further described with reference to the above-mentioned drawings. DETAILED DESCRIPTION

[0023] While the accompanying drawings illustrate embodiments of the present invention, the present invention may be implemented in a variety of different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more comprehensive and complete disclosure of the present invention and to enable those skilled in the art to more fully understand the scope of the invention. In the drawings, the dimensions of layers and regions are exaggerated for clarity.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an overly idealized or overly formal sense unless explicitly defined herein.

[0025] The present invention describes an exemplary fabrication process for a FinFET. In certain embodiments of the present invention, the FinFET may be formed on a bulk silicon substrate. Alternatively, the FinFET may be formed on a silicon-on-insulator (SOI) substrate or, alternatively, a germanium-on-insulator (GOI) substrate. Furthermore, according to some embodiments, the silicon substrate may include other conductive layers or other semiconductor elements, such as transistors, diodes, and the like. The present invention is not limited in this context.

[0026] See also Figure 1 A preferred embodiment of the present invention provides a method for preparing a fin field effect transistor, including the following steps.

[0027] Step S1: providing a substrate and a plurality of fin structures spaced apart from each other on a surface of the substrate.

[0028] Step S2: forming a shallow trench isolation structure between adjacent fin structures.

[0029] Step S3: forming a stress layer on a side of the shallow trench isolation structure away from the substrate, wherein the stress layer wraps portions of the plurality of fin structures away from the substrate.

[0030] Step S4: performing heat treatment on the stress layer and the plurality of fin structures.

[0031] Step S5: removing the stress layer.

[0032] Figures 2 to 3 A cross-sectional schematic diagram of the preparation of a FinFET according to a preferred embodiment of the present invention.

[0033] like Figure 2 As shown, the connection between the multiple fin structures 20 and the substrate 10 is integrated. Step S1 may specifically include: providing a semiconductor substrate (not shown), forming a patterned mask layer (not shown) on the surface of the substrate, the patterned mask layer defining the position of the fin structures 20, and etching the substrate using an etching process to simultaneously form the substrate 10 and the multiple fin structures 20. The substrate may be a silicon substrate 10, or a substrate 10 doped with germanium, or silicon on an insulating layer, and may include various doped regions, buried layers, etc.

[0034] It is understandable that in other embodiments, a plurality of fin structures 20 arranged at intervals may be formed by depositing a fin structure material layer on the substrate 10 and then etching the fin structure material layer.

[0035] The fin structure 20 can also be doped with different impurity ions depending on the type of FinFET to be formed, to adjust the threshold voltage of the FinFET. When forming an N-type FinFET, the fin structure 20 is doped with P-type ions; when forming a P-type FinFET, the fin structure 20 is doped with N-type ions.

[0036] The multiple fin structures 20 are protruding from the same surface of the substrate 10. Each fin structure 20 is elongated and has a large aspect ratio. The height of the fin structure 20 is greater than the width of the fin structure 20. The width of each fin structure 20 ranges from 8 nm to 20 nm. The distance between adjacent fin structures 20 is from 20 nm to 50 nm.

[0037] A trench 25 is formed between each adjacent fin structure 20. The trench 25 is located where the substrate is removed during etching. In this embodiment, the width of the fin structure 20 gradually decreases along the height of the fin structure 20 (away from the substrate 10). The width of the trench 25 gradually increases as it moves away from the substrate 10.

[0038] like Figure 2 As shown, step S2 involves forming a shallow trench isolation structure 30 made of insulating material in the trench 25 between adjacent fin structures 20. The height of the shallow trench isolation structure 30 is lower than that of the fin structures 20. That is, the surface of the shallow trench isolation structure 30 away from the substrate 10 is lower than the end surface of the fin structure 20 away from the substrate 10, thereby exposing portions of the multiple fin structures 20. Specifically, the arrangement of the shallow trench isolation structure 30 divides each fin structure 20 into two portions: a first portion 21 and a second portion 23. The first portion 21 is connected between the substrate 10 and the second portion 23; the first portion 21 is in contact with the shallow trench isolation structure 30; and the second portion 23 is exposed relative to the shallow trench isolation structure 30. The shallow trench isolation structure 30 can be formed using a chemical vapor deposition process, a physical vapor deposition process, or a thermal oxidation growth process. Typically, a thick insulating material is first deposited to completely fill the grooves 25 between adjacent fin structures 20 , and then the insulating material is etched back using an etch back process until a portion of each fin structure 20 is exposed.

[0039] The shallow trench isolation structure 30 is used to electrically isolate adjacent fin structures 20. The material of the shallow trench isolation structure 30 includes an insulating material such as silicon oxide, silicon oxynitride, or silicon hydroxide. In this embodiment, the material of the isolation structure 210 is silicon oxide. The method for forming the shallow trench isolation structure 30 is a deposition process, such as an atomic layer deposition process, a low-pressure chemical vapor deposition process, or a plasma-enhanced chemical vapor deposition process. In this embodiment, the isolation structure material layer is formed using a plasma-enhanced chemical vapor deposition process.

[0040] During step S2 , the fin structure 20 is prone to bend or warp. Therefore, steps S3 - S5 are performed to reduce the occurrence and degree of the bend or warp of the fin structure 20 .

[0041] In step S3, the material of the stress layer 40 can be silicon nitride, silicon oxide, hafnium oxide, silicon, or silicon germanium. Figure 3 As shown, the stress layer 40 is disposed on the shallow trench isolation structure 30 and completely encapsulates the second portion 23 of each fin structure 20. The stress layer 40 can be deposited using a conventional film deposition process, such as an atomic layer deposition process, a low-pressure chemical vapor deposition process, or a plasma-enhanced chemical vapor deposition process. During the formation of the stress layer 40, the provision of the stress layer 40 has the effect of pulling the second portions 23 of the multiple fin structures 20 from the edges of the multiple fin structures 20 toward the center of the multiple fin structures 20, thereby preventing the fin structures 20 from being skewed or bent.

[0042] In step S4, the stress layer 40 is heat treated at a temperature of 400-800°C for 10-30 minutes. This heat treatment further solidifies the tensioning effect of the stress layer 40, thereby strengthening the ability of the multiple fin structures 20 to maintain their upright position. This step is not limited to heat treatment and can also include ultraviolet light exposure.

[0043] In step S5 , the stress layer 40 is removed in any manner, for example, by conventional etching or machining.

[0044] In this way, by disposing the stress layer 40 and performing heat treatment on it, the fin structure 20 can remain upright without bending.

[0045] The preparation method may further include the step of ion bombarding the fin structure 20 and the shallow trench isolation structure 30 after step S2 and before step S3. The purpose of this step is to soften the structures of the fin structure 20 and the shallow trench isolation structure 30 to a certain extent through ion bombardment, so as to better achieve a pulling effect when the stress layer 40 is subsequently formed.

[0046] After step S5 is completed, the preparation method further includes forming other component layers, such as forming a gate, source, and drain. For example, if the fin structure 20 extends along a first direction parallel to the substrate 10, a gate structure (not shown) needs to be formed across the fin structure 20. The gate structure extends along a second direction parallel to the substrate 10 and perpendicular to the first direction, and the gate structure covers the top and part of the sidewalls of the fin structure 20.

[0047] The method for preparing a fin field-effect transistor of the present invention provides a stress layer 40 that completely wraps the upper end portion of a narrow and long fin structure 20, thereby producing an effect of applying a pulling force from the edges of the multiple fin structures 20 to the middle of the multiple fin structures 20, thereby enhancing the upright effect of each fin structure 20 and preventing the fin structure 20 from being skewed or bent. In addition, after achieving this effect, the stress layer 40 is removed, which does not affect the subsequent formation of other components on the fin structure 20, and can also effectively ensure that the fin structure 20 can still maintain an upright effect during the subsequent steps of forming other components on the fin structure 20.

[0048] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. The up, down, left and right directions shown in the figures are only for ease of understanding. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for preparing a fin field-effect transistor, characterized in that: It includes: Providing a substrate and a plurality of fin structures spaced apart from each other on a surface of the substrate; forming a shallow trench isolation structure between adjacent fin structures, wherein the arrangement of the shallow trench isolation structure divides each fin structure into a first portion and a second portion, wherein the first portion is in contact with and connected to the shallow trench isolation structure, and the second portion is exposed relative to the shallow trench isolation structure, and the second portion includes a top surface facing away from the substrate and a side surface connected to the top surface; forming a stress layer on a side of the shallow trench isolation structure away from the substrate, wherein the stress layer completely wraps the top surface and side surfaces of the second portion; performing a heat treatment on the stress layer and the plurality of fin structures; as well as The stress layer is removed.

2. The method for preparing a fin field effect transistor according to claim 1, wherein: Providing the substrate and the plurality of fin structures includes providing a base plate, and etching the base plate using an etching process to simultaneously form the substrate and the plurality of fin structures.

3. The method for preparing a fin field effect transistor according to claim 1, wherein: The shallow trench isolation structure is made of insulating material.

4. The method for preparing a fin field effect transistor according to claim 1, wherein: The stress layer is made of silicon nitride, silicon oxide, hafnium oxide, silicon, or silicon germanium.

5. The method for preparing a fin field effect transistor according to claim 1, wherein: The heat treatment temperature is 400-800° C., and the heat preservation time is 10-30 minutes.

6. The method for preparing a fin field effect transistor according to claim 1, wherein: The heat treatment is replaced by ultraviolet light irradiation.

7. The method for preparing a fin field effect transistor according to claim 1, wherein: The preparation method further includes a step of performing ion bombardment on the fin structure and the shallow trench isolation structure after forming the shallow trench isolation structure and before forming the stress layer.

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