A transistor
By designing a ring gate structure and a self-aligned process for transistors, the performance and process compatibility issues of carbon nanotube transistors were solved, enabling high-performance, low-cost large-scale manufacturing and three-dimensional integration.
Patent Information
- Application Number
- CN202210535292.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-05-11
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2040-05-11
AI Technical Summary
Existing transistors using carbon nanotubes as channel materials suffer from problems such as poor actual performance, incompatibility between fabrication processes and large-scale manufacturing, and poor device uniformity.
A transistor structure was designed, including a substrate, a low-dimensional material layer, sidewalls, a source, a drain, and a gate structure. It adopts a ring gate structure and a self-aligned process. The sidewalls define the positions of the source, drain, and gate. The threshold and switching state are controlled by fixed charge or dipole. The low-dimensional material layer is protected by protective and insulating material layers, which simplifies the process flow.
It improves the overall performance of transistors, enhances process compatibility and device uniformity, reduces contact resistance and parasitic capacitance, and enables low-cost mass production and 3D integration.
Smart Images
Figure CN114914292B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular, to a carbon-based transistor. BACKGROUND
[0002] Carbon nanotube is an ideal transistor channel material, which has one-dimensional ultra-thin, high mobility, perfect lattice, high physical and chemical stability, high thermal conductivity and other excellent physical and chemical properties. The transistor with carbon nanotube as channel material has significant advantages in ultimate performance and energy utilization efficiency compared with traditional transistor, and has low process cost, high process compatibility, and is easy to realize three-dimensional integration.
[0003] However, the transistor with carbon nanotube as channel material and the manufacturing method thereof still need to be improved. SUMMARY
[0004] The present application is made based on the discovery and understanding of the inventors on the following facts and problems:
[0005] The inventors found that the transistor with carbon nanotube as channel material still has problems such as poor actual working performance, incompatible manufacturing process and scale manufacturing, poor device uniformity, etc.
[0006] The present application aims to at least partially alleviate or solve at least one of the above-mentioned problems.
[0007] In one aspect of the present application, a transistor is provided. The transistor comprises: a substrate and a low-dimensional material layer disposed above the substrate; a plurality of side walls disposed on a side of the low-dimensional material layer away from the substrate, and the plurality of side walls are spaced apart; a source and a drain disposed on a side of the low-dimensional material layer away from the substrate; a gate structure disposed on a side of the low-dimensional material layer away from the substrate, the gate structure is located between the source and the drain, the gate structure, the source and the drain are all spaced apart by the side wall, and the gate structure, the source and the drain are all in contact with the side wall. Therefore, the transistor has excellent comprehensive performance, high process compatibility, good device uniformity and other advantages.
[0008] According to an embodiment of the present application, a part of the sidewall is located between the low-dimensional material layer and the substrate, another part of the sidewall is located on a side of the low-dimensional material layer away from the substrate, the gate structure comprises a gate dielectric layer and a gate metal layer, the gate dielectric layer comprises a first part located between the low-dimensional material layer and the substrate and a second part located on a side of the low-dimensional material layer away from the substrate, a part of the gate metal layer is located between the first part and the substrate, another part of the gate metal layer is located on a side of the second part away from the substrate, a part of the source electrode is located between the low-dimensional material layer and the substrate, another part of the source electrode is located on a side of the low-dimensional material layer away from the substrate, a part of the drain electrode is located between the low-dimensional material layer and the substrate, another part of the drain electrode is located on a side of the low-dimensional material layer away from the substrate. Thus, the gate structure is a ring gate structure, which can further improve the gate control and make the transistor have better electrostatics, and the source electrode and the drain electrode form an embedded / surrounding contact with the low-dimensional material layer, which can reduce the contact resistance, improve the thermal stability of the source electrode and the drain electrode contact, eliminate the influence of the substrate on the contact, and the sidewall can fix the low-dimensional material layer, which can prevent the low-dimensional material layer from moving during the fabrication of the source electrode, the drain electrode and the gate structure.
[0009] According to an embodiment of the present application, the low-dimensional material layer comprises a plurality of sub-layers, and adjacent two of the sub-layers are filled with part of the sidewall, part of the source electrode, part of the drain electrode and part of the gate structure. Thus, the performance of the transistor can be further improved.
[0010] According to an embodiment of the present application, the material constituting the low-dimensional material layer comprises at least one of carbon nanotubes, nanowires and two-dimensional materials. Thus, the transistor has excellent performance when the above-mentioned materials are used as the channel material of the transistor.
[0011] According to an embodiment of the present application, the sidewall has fixed charges or dipoles. Thus, the threshold and the on-off state of the transistor can be well controlled.
[0012] According to an embodiment of the present application, the transistor further comprises a gate interconnection metal layer, which is located on a side of the gate structure away from the substrate and between the sidewalls. Thus, the interconnection between the gate structures is facilitated, and thus the voltage applied to the gate structure is facilitated.
[0013] According to an embodiment of the present invention, a source interconnect metal layer and a drain interconnect metal layer are disposed in the substrate, the source interconnect metal layer being connected to the source, and the drain interconnect metal layer being connected to the drain. This facilitates interconnection between the sources and between the drains, and the presence of the source interconnect metal layer and drain interconnect metal layer in the substrate also reduces parasitic capacitance between the source / drain and the gate, further improving transistor performance.
[0014] In another aspect, the present invention provides a method for fabricating a transistor. The method includes: forming a low-dimensional material layer over a substrate, and forming a plurality of sidewalls on a side of the low-dimensional material layer away from the substrate, the sidewalls being spaced apart; forming a source and a drain on the side of the low-dimensional material layer away from the substrate; and forming a gate structure on the side of the low-dimensional material layer away from the substrate, the gate structure being located between the source and the drain, the gate structure, the source, and the drain being spaced apart by the sidewalls, and the gate structure, the source, and the drain being in contact with the sidewalls to obtain the transistor. Therefore, this method has advantages such as low cost, simple process, scalability, and high compatibility, and can effectively improve the uniformity of the transistor.
[0015] According to an embodiment of the present invention, forming the sidewall includes: sequentially forming a protective material layer and an insulating material layer on the side of the low-dimensional material layer away from the substrate; sequentially patterning the insulating material layer and the protective material layer to form a plurality of spaced-apart first grooves, exposing a portion of the low-dimensional material layer; growing a sidewall material layer in the first grooves and on the side of the insulating material layer away from the substrate; and patterning the sidewall material layer to form the sidewall. Thus, a plurality of spaced-apart sidewalls can be easily formed. These sidewalls can serve as self-aligned masks in subsequent steps during the formation of the source / drain electrodes and the gate, enabling self-alignment, effectively controlling the positional relationship between the source / drain electrodes and the gate, reducing process complexity, and effectively controlling the size and morphology of the source / drain electrodes and the gate, thereby improving transistor uniformity.
[0016] According to an embodiment of the present invention, the sidewall material layer is grown by at least one of atomic layer deposition, chemical vapor deposition, and physical vapor deposition. This allows the material to fill the first groove with a high aspect ratio well without leaving voids in the first groove, thereby avoiding defects in the sidewall material layer.
[0017] According to an embodiment of the present invention, the patterning process of the sidewall material layer includes at least one of reactive ion etching and chemical mechanical polishing. Thus, the patterning of the sidewall material layer can be achieved using a simple method.
[0018] According to an embodiment of the present application, the insulating material layer comprises a plurality of insulating sub-layers stacked together, and the thickness of the insulating material layer is 100-3000 nm. In this way, the insulating material layer can facilitate the subsequent preparation of the sidewall, source / drain electrode and gate.
[0019] According to an embodiment of the present application, the deposition temperature of the insulating material layer is lower than 400°C. In this way, the insulating material layer can be deposited at a lower temperature, further improving the compatibility of the manufacturing process.
[0020] According to an embodiment of the present application, the deposition temperature of the protective material layer is lower than 400°C. In this way, the protective material layer can be deposited at a lower temperature, further improving the compatibility of the manufacturing process.
[0021] According to an embodiment of the present application, the patterning of the protective material layer comprises chemical etching of the protective material layer by a reactive solution or a reactive gas, and cleaning by water. In this way, the lattice structure of the low-dimensional material is not damaged when forming the groove, and the low-dimensional material layer is not damaged or contaminated.
[0022] According to an embodiment of the present application, the reactive solution comprises an acidic solution or an alkaline solution. In this way, the patterning of the protective material layer can be achieved by the reaction between the acidic solution or the alkaline solution and the protective material layer, and the process of the reaction between the acidic solution or the alkaline solution and the protective material layer does not damage the lattice structure of the low-dimensional material.
[0023] According to an embodiment of the present application, the acidic solution comprises at least one of hydrochloric acid, acetic acid, nitric acid, phosphoric acid and sulfuric acid. In this way, the reaction between the acidic solution and the protective material layer can remove part of the protective material layer, and the lattice structure of the low-dimensional material is not damaged.
[0024] According to an embodiment of the present application, the alkaline solution comprises at least one of potassium hydroxide, sodium hydroxide and tetramethylammonium hydroxide. In this way, the reaction between the alkaline solution and the protective material layer can remove part of the protective material layer, and the lattice structure of the low-dimensional material is not damaged.
[0025] According to an embodiment of the present application, the reactive gas comprises at least one of hydrogen chloride and hydrogen fluoride. In this way, the reaction between the reactive gas and the protective material layer can remove part of the protective material layer, and the lattice structure of the low-dimensional material is not damaged.
[0026] According to an embodiment of the present application, the material constituting the protective material layer comprises at least one of yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide, and aluminum oxide. Thus, in subsequent steps, the protective material layer can protect the low-dimensional material layer from damage and contamination when etching other film layers, and the crystal lattice structure of the low-dimensional material will not be damaged when etching the protective material layer formed of the above-mentioned materials, so that not only damage and contamination of the low-dimensional material layer are avoided, but also impurities and molecules adsorbed on the surface of the low-dimensional material layer are removed, so that the performance of the low-dimensional material layer is better.
[0027] According to an embodiment of the present application, the thickness of the protective material layer is 3-50 nm. Thus, the protective material layer can well protect the low-dimensional material layer, and meanwhile, when etching the protective material layer, adverse effects such as lateral etching caused by excessive thickness of the protective material layer can be alleviated.
[0028] According to an embodiment of the present application, before the protective material layer is formed on the side of the low-dimensional material layer away from the substrate, the method further comprises: forming the protective material layer between the substrate and the low-dimensional material layer. Thus, in subsequent steps, when etching the protective material layer, the low-dimensional material layer can be suspended, and finally a transistor with a ring gate structure is obtained, so that the gate control is further improved and the transistor has better electrostatics.
[0029] According to an embodiment of the present application, forming the source and the drain comprises: sequentially performing patterning treatment on the insulating material layer and the protective material layer located between two adjacent side walls to form a second recess, expose part of the low-dimensional material layer, and form the source and the drain in the second recess, so that the source and the drain are separated by the side walls. Thus, the side walls can be used as a self-aligned mask for forming the source and the drain, so that a self-aligned process is realized, the position of the source and the drain is well controlled, the process complexity is reduced, and the size and topography of the source and the drain can be well controlled, so that the uniformity of the transistor is improved.
[0030] According to an embodiment of the present application, forming the source and the drain in the second recess comprises: forming a metal material layer on the side of the side wall and the insulating material layer away from the substrate in the second recess; forming a dielectric protective material layer on the side of the metal material layer away from the substrate; performing patterning treatment on the dielectric protective material layer to expose the metal material layer on the side of the side wall and the insulating material layer away from the substrate; and removing the metal material layer on the side of the side wall and the insulating material layer away from the substrate to obtain the source and the drain. Thus, by arranging the dielectric protective material layer, damage to the source and the drain and the low-dimensional material layer caused by etching process can be avoided.
[0031] According to an embodiment of the present application, the forming of the metal material layer includes physical vapor deposition or atomic layer deposition. In this way, good deposition of the metal material can be achieved.
[0032] According to an embodiment of the present application, the forming of the dielectric protective material layer includes at least one of atomic layer deposition, chemical vapor deposition and physical vapor deposition. In this way, the material can be well filled into the second recess with high aspect ratio, without leaving voids in the second recess, so as to avoid formation of defects in the dielectric protective material layer.
[0033] According to an embodiment of the present application, the patterning of the dielectric protective material layer includes at least one of reactive ion etching and chemical mechanical polishing. In this way, the patterning of the dielectric protective material layer can be achieved by using a simple method.
[0034] According to an embodiment of the present application, the forming of the gate structure includes sequentially patterning the insulating material layer and the protective material layer between the two side walls between the source and the drain, forming a third recess, exposing part of the low-dimensional material layer, and forming the gate structure in the third recess. In this way, the side wall can be used as a self-aligned mask for forming the gate, a self-aligned process is achieved, the position of the gate is well controlled, the process complexity is reduced, and the size and topography of the gate can be well controlled, and the uniformity of the transistor is improved.
[0035] According to an embodiment of the present application, the gate dielectric layer and the gate metal layer are sequentially formed in the third recess to form the gate structure. The forming of the gate dielectric layer and the gate metal layer includes at least one of atomic layer deposition, chemical vapor deposition and physical vapor deposition. In this way, the gate structure can be formed, and for the case that the low-dimensional material layer is suspended, a ring gate structure can be formed, which can further improve the gate control and make the transistor obtain better electrostatics.
[0036] According to an embodiment of the present application, the low-dimensional material layer includes a plurality of sub-layers, and the protective material layer is arranged between two adjacent sub-layers. In this way, the performance of the transistor can be further improved.
[0037] According to an embodiment of the present application, after the forming of the first recess, the forming of the second recess and the forming of the third recess, the part of the low-dimensional material layer exposed outside is cleaned by using a wet cleaning method. In this way, impurities, molecules, polymers and the like on the surface of the low-dimensional material layer can be removed by using a simple method, so that the low-dimensional material layer obtains a clean surface, which is beneficial to better performance of the low-dimensional material layer.
[0038] According to an embodiment of the present invention, the sidewall has a fixed charge, and the low-dimensional material layer is electrostatically doped by the fixed charge in the sidewall; or, the sidewall has a dipole, and the low-dimensional material layer is electrostatically doped by the dipole. Thus, the threshold and switching state can be well controlled.
[0039] According to embodiments of the present invention, the materials constituting the low-dimensional material layer include at least one of carbon nanotubes, nanowires, and two-dimensional materials. Therefore, using the above materials as the channel material for transistors can enable transistors to exhibit excellent performance. Attached Figure Description
[0040] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:
[0041] Figure 1 A schematic diagram of a transistor structure according to an embodiment of the present invention is shown;
[0042] Figure 2 A schematic diagram of a transistor according to another embodiment of the present invention is shown;
[0043] Figure 3 A schematic diagram of a transistor according to yet another embodiment of the present invention is shown;
[0044] Figure 4 A flowchart illustrating a method for fabricating a transistor according to an embodiment of the present invention is shown;
[0045] Figure 5 A partial flowchart of a method for fabricating a transistor according to an embodiment of the present invention is shown;
[0046] Figure 6 A partial flowchart of a method for fabricating a transistor according to an embodiment of the present invention is shown;
[0047] Figure 7 A partial flowchart of a method for fabricating a transistor according to an embodiment of the present invention is shown;
[0048] Figure 8 A partial flowchart of a method for fabricating a transistor according to an embodiment of the present invention is shown;
[0049] Figure 9 A partial flowchart of a method for fabricating a transistor according to an embodiment of the present invention is shown;
[0050] Figure 10 A partial flowchart of a method for fabricating a transistor according to another embodiment of the present invention is shown;
[0051] Figure 11 shows a partial flowchart of a method of fabricating a transistor according to another embodiment of the present application;
[0052] Figure 12 shows a partial flowchart of a method of fabricating a transistor according to another embodiment of the present application;
[0053] Figure 13 shows a partial flowchart of a method of fabricating a transistor according to another embodiment of the present application;
[0054] Figure 14 shows a partial flowchart of a method of fabricating a transistor according to another embodiment of the present application;
[0055] Figure 15 shows a top view of a low-dimensional material layer and a protective material layer according to an embodiment of the present application.
[0056] BRIEF DESCRIPTION OF DRAWINGS
[0057] 100: substrate; 110: substrate; 120: insulating and heat-conductive layer; 200: low-dimensional material layer; 300: protective material layer; 300': protective layer; 400: insulating material layer; 400': insulating layer; 410: first sub-layer; 420: second sub-layer; 500: side wall; 510: side wall material layer; 520: side wall roughcast; 610: metal material layer; 620: source electrode; 630: drain electrode; 700: dielectric protective layer; 710: dielectric protective material layer; 720: dielectric protective layer roughcast; 800: gate structure; 810: gate dielectric layer; 811: first part; 812: second part; 820: gate metal layer; 10: first recess; 20: second recess; 30: third recess; 40: gate interconnection metal layer; 50: source interconnection metal layer; 60: drain interconnection metal layer. DETAILED DESCRIPTION
[0058] Embodiments of the present application are described in detail below with reference to the attached drawing figures, wherein the same or like reference numerals and letters throughout the figures denote the same or like elements or elements having the same or similar functionality. The embodiments described below are exemplary and are not intended to be limiting of the scope of the present application. Embodiments of the present application will be described with reference to the attached figures.
[0059] In one aspect of the present application, a transistor is provided. According to an embodiment of the present application, reference is made to Figure 1The transistor comprises a substrate 100, a low-dimensional material layer 200, a plurality of side walls 500, a source electrode 620, a drain electrode 630 and a gate structure 800. The low-dimensional material layer 200 is arranged above the substrate 100. The side walls 500 are arranged on a side of the low-dimensional material layer 200 away from the substrate 100, and the plurality of side walls 500 are arranged at intervals. The source electrode 620 and the drain electrode 630 are arranged on a side of the low-dimensional material layer 200 away from the substrate 100. The gate structure 800 is arranged on a side of the low-dimensional material layer 200 away from the substrate 100, and the gate structure 800 is located between the source electrode 620 and the drain electrode 630. The gate structure 800, the source electrode 620 and the drain electrode 630 are all spaced apart by the side walls 500, and the gate structure 800, the source electrode 620 and the drain electrode 630 all contact the side walls 500. Thus, the transistor has the advantages of uniform performance, low cost, scalable manufacturing, simple manufacturing process and strong process compatibility.
[0060] According to the embodiments of the present application, by arranging a plurality of side walls in the transistor, the positions of the source and drain electrodes and the gate are defined by the side walls. In the process of manufacturing the transistor, the side walls can be used as a self-aligned mask for forming the source and drain electrodes and the gate. The positional relationship between the source and drain electrodes and the gate can be well controlled, and the size and topography of the source and drain electrodes and the gate can be well controlled. The uniformity of the transistor is improved, the process difficulty is reduced, and the cost is reduced.
[0061] The structures of the transistor will be described in detail below according to specific embodiments of the present application.
[0062] According to the embodiments of the present application, the substrate 100 can comprise a substrate 110 and an insulating and heat-conducting layer 120 formed on the substrate 110. The constituent materials of the substrate and the insulating and heat-conducting layer are not particularly limited. For example, the material constituting the substrate can include, but is not limited to, a semiconductor, glass, a polymer, and the material constituting the insulating and heat-conducting layer can include nitride. Thus, the insulating and heat-conducting layer has good heat conductivity. In addition, the dense nitride can form a stable interface with the gate dielectric layer, and has good thermal stability and thermal kinetic stability during heat treatment.
[0063] According to the embodiments of the present application, the material constituting the low-dimensional material layer 200 can include at least one of a carbon nanotube, a nanowire and a two-dimensional material. The carbon nanotube can be a single carbon nanotube, a network carbon nanotube or an array of aligned carbon nanotubes. The two-dimensional material can include black phosphorus or molybdenum disulfide, etc. Thus, using the above-mentioned materials as the channel material of the transistor can make the transistor have excellent performance. According to the preferred embodiments of the present application, the material constituting the low-dimensional material layer can be a single-walled carbon nanotube. The single-walled carbon nanotube has higher mobility and fewer surface dangling bonds than other low-dimensional materials, so that the transistor has better performance.
[0064] According to the embodiments of the present application, referenceFigure 1 The transistor may further include a protective layer 300' and an insulating layer 400'. The protective layer 300' is disposed on the side of the low-dimensional material layer 200 away from the substrate 100, and the insulating layer 400' is disposed on the side of the protective layer 300' away from the substrate 100. Both the protective layer 300' and the insulating layer 400' are located on the side of the sidewall 500 away from the source 620 and on the side of the sidewall 500 away from the drain 630. The protective layer 300' and the insulating layer 400' are the remaining portions after the protective material layer and the insulating material layer formed on the low-dimensional material layer are patterned during the transistor fabrication process. During the transistor fabrication process, the protective material layer can protect the low-dimensional material layer from contamination and damage, and the insulating material layer facilitates the fabrication of the sidewall, source / drain, and gate structures.
[0065] According to an embodiment of the present invention, the insulating layer 400' may include a plurality of stacked insulating sublayers, for example, Figure 1 The first sublayer 410 and the second sublayer 420 shown herein, and the insulating layer 400', can have a thickness of 100-3000 nm, such as 100 nm, 500 nm, 800 nm, 1000 nm, 1500 nm, 1800 nm, 2000 nm, 2500 nm, 2800 nm, or 3000 nm. Therefore, during transistor fabrication, the insulating material layer facilitates the fabrication of sidewalls, source / drain electrodes, and gate electrodes. The specific materials constituting the insulating layer are not particularly limited, and those skilled in the art can design it based on commonly used insulating materials in transistors. For example, according to embodiments of the present invention, the materials constituting the insulating layer may include at least one of oxides, nitrides, and organic materials, and the multiple insulating sublayers may be used respectively as an anti-etching layer, a planarization layer, an anti-reflection layer, and a stop layer for chemical mechanical polishing (CMP) processes.
[0066] According to an embodiment of the present application, the material constituting the protective layer 300' satisfies that in the process of forming the protective layer 300', the material can be patterned by a non-destructive chemical etching method to remove part of the protective material, finally forming the protective layer 300', and the patterning process does not destroy the crystal lattice structure of the low-dimensional material, and does not cause pollution and damage to the low-dimensional material layer. The specific material constituting the protective layer 300' is not particularly limited, as long as it satisfies the above condition. For example, the material constituting the protective layer 300' can include at least one of yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide, and aluminum oxide. Thus, the above-mentioned material has good wettability with the low-dimensional material layer, and the deposition method does not damage the low-dimensional material layer. In the process of making a transistor, when etching other film layers, the protective material layer can protect the low-dimensional material layer from damage and pollution, and when etching the protective material layer formed by the above-mentioned material, not only does it not damage and pollute the low-dimensional material layer, but also removes impurities and molecules adsorbed on the surface of the low-dimensional material layer, so that the performance of the low-dimensional material layer can be better played.
[0067] According to an embodiment of the present application, the thickness of the protective layer 300' can be 3-50nm, preferably 3-20nm, such as 5nm, 8nm, 10nm, 15nm, 18nm, 20nm. Thus, in the process of making a transistor, the protective material layer can well protect the low-dimensional material layer, and at the same time, when etching the protective material layer, it can alleviate the adverse effects caused by the excessive thickness of the protective material layer, such as lateral etching.
[0068] According to an embodiment of the present application, referring to Figure 2portion of the sidewall 500 is located between the low-dimensional material layer 200 and the substrate 100, and another portion of the sidewall 500 is located on a side of the low-dimensional material layer 200 away from the substrate 100, the gate structure 800 includes a gate dielectric layer 810 and a gate metal layer 820, the gate dielectric layer 810 includes a first portion 811 located between the low-dimensional material layer 200 and the substrate 100, and a second portion 812 located on a side of the low-dimensional material layer 200 away from the substrate 100, a portion of the gate metal layer 820 is located between the first portion 811 and the substrate 100, and another portion of the gate metal layer 820 is located on a side of the second portion 812 away from the substrate 100, a portion of the source electrode 620 is located between the low-dimensional material layer 200 and the substrate 100, and another portion of the source electrode 620 is located on a side of the low-dimensional material layer 200 away from the substrate 100, a portion of the drain electrode 630 is located between the low-dimensional material layer 200 and the substrate 100, and another portion of the drain electrode 630 is located on a side of the low-dimensional material layer 200 away from the substrate 100. That is, the sidewall, the gate dielectric layer, the source electrode, and the drain electrode are all arranged to surround the low-dimensional material layer, and the gate metal layer is arranged to surround the gate dielectric layer. In this way, the gate structure is a gate-all-around structure, which can further improve the gate control and make the transistor have better electrostatics, and the source electrode and the drain electrode form an embedded / encircling contact with the low-dimensional material layer, so that the source-drain metal material and the low-dimensional material layer can be more effectively contacted, the contact resistance can be reduced, and thus the contact quality can be further improved. Compared with a top-coverage source-drain electrode structure (see Figure 1 ), the encircling source-drain electrode structure can avoid the influence of the substrate on the contact quality of the source-drain electrode and the low-dimensional material layer, and the decline of the contact quality of the source-drain electrode and the low-dimensional material layer due to thermal expansion and stress and the like during a heat treatment process, and the sidewall can fix the low-dimensional material layer, so that the low-dimensional material layer can be prevented from moving during the fabrication of the source electrode, the drain electrode, and the gate structure.
[0069] In other words, a protective layer 300’B can be further arranged between the low-dimensional material layer 200 and the substrate 100, and the protective layer 300’B is a remaining portion after a protective material layer formed between the low-dimensional material layer and the substrate is patterned during the fabrication of the transistor. In this way, the low-dimensional material layer can be suspended during the fabrication of the transistor, so that a gate-all-around structure (see the gate structure shown in Figure 2 ) is obtained, the gate control is further improved, the transistor has better electrostatics, and an encircling source-drain structure is obtained, and the contact quality is further improved, and the source-drain contact resistance is reduced.
[0070] According to an embodiment of the present application, reference can be made to Figure 1The transistor can further include a dielectric protection layer 700 disposed on the side of the source 620 and the drain 630 away from the substrate 100 and between the sidewalls 500, the dielectric protection layer 700 being part of a dielectric protection material layer formed on the side of the source and the drain away from the substrate during the process of fabricating the transistor and patterned after the dielectric protection material layer is formed. Thus, the dielectric protection layer can be disposed to avoid damage to the source, the drain and the low-dimensional material layer caused by the etching process during the process of fabricating the transistor.
[0071] According to embodiments of the present application, referring to Figure 1 The surface of the sidewall 500 on the side away from the substrate 100 can be flush with the surface of the insulating layer 400' on the side away from the substrate 100, and the surface of the dielectric protection layer 700 on the side away from the substrate 100 can be flush with the surface of the sidewall 500 on the side away from the substrate 100. Thus, the sidewall can serve as a self-aligned mask during the process of fabricating the transistor, and the position relationship between the source, the drain and the gate can be well controlled, and the size and topography of the source, the drain and the gate can be well controlled, which improves the uniformity of the transistor and makes the transistor have a flat surface.
[0072] According to embodiments of the present application, the sidewall 500 has fixed charges. Specifically, the sidewall can be made of a material having fixed charges. Alternatively, the part of the sidewall close to the low-dimensional material layer is made of a material having fixed charges, and the part of the sidewall away from the low-dimensional material layer is made of a material with low dielectric constant, so that the fixed charges can be introduced into the sidewall, and the part of the sidewall away from the low-dimensional material layer is made of a material with low dielectric constant, which can further reduce the parasitic capacitance. By using the fixed charges to electrostatically dope the low-dimensional material layer under the sidewall, the threshold and the on-off state of the transistor can be well controlled without affecting the gate control ability of the gate.
[0073] According to other embodiments of the present application, the sidewall 500 has a dipole. Specifically, the sidewall can be made of two materials, and the dipole is formed at the interface between the two materials. For example, for the transistor structure with the low-dimensional material layer suspended, the first sidewall material and the second sidewall material are deposited in sequence by atomic layer deposition, the sidewall layer wraps the low-dimensional material layer, and the dipole is formed at the interface between the first sidewall material and the second sidewall material. Alternatively, for the transistor structure with the low-dimensional material layer directly disposed on the substrate, the dipole can also be introduced into the sidewall, for example, the first sidewall material and the second sidewall material are deposited in sequence, and the deposition method can be atomic layer deposition, chemical vapor deposition or physical vapor deposition, or a combination thereof, and the dipole is formed at the interface between the first sidewall material and the second sidewall material. By using the dipole to electrostatically dope the low-dimensional material layer under the sidewall, the threshold and the on-off state of the transistor can be well controlled without affecting the gate control ability of the gate.
[0074] According to the embodiments of the present application, by adjusting the size of the sidewall, or adjusting the density and distribution of the fixed charge in the sidewall, or adjusting the direction and size of the dipole moment in the sidewall and the distance between the dipole moment and the low-dimensional material layer, the threshold and on-off state of the transistor can be well controlled.
[0075] According to the embodiments of the present application, referring to Figure 3 , the low-dimensional material layer 200 can further include a plurality of sub-layers (e.g., 200A and 200B as shown in the figure), and the adjacent two sub-layers are filled with partial sidewall 500, partial source electrode 620, partial drain electrode 630 and partial gate structure 800, wherein the filled gate structure includes a gate dielectric layer surrounding the low-dimensional material layer and a gate metal layer surrounding the gate dielectric layer. Thus, referring to Figure 3 , the structure of vertically stacked low-dimensional material layers can be realized, and as the number of low-dimensional material layers increases, the driving capability of the transistor is higher, the performance of the transistor is significantly improved without increasing the area of the transistor, and the ring gate structure and the surrounding source-drain electrode structure can be formed. In other words, referring to Figure 3 , the protective layer 300’C is formed between the adjacent two sub-layers after the protective material layer formed between the adjacent two sub-layers in the process of manufacturing the transistor is patterned.
[0076] According to the embodiments of the present application, referring to Figures 1-3 , the transistor further includes a gate interconnection metal layer 40, which is arranged on the side of the gate structure 800 away from the substrate 100 and between the sidewalls 500. Thus, the interconnection between the gate structures is facilitated, thereby facilitating the application of voltage to the gate structure.
[0077] According to the embodiments of the present application, referring to Figures 1-3 , the substrate 100 is provided with a source interconnection metal layer 50 and a drain interconnection metal layer 60, the source interconnection metal layer 50 is connected to the source electrode 620, and the drain interconnection metal layer 60 is connected to the drain electrode 630. Specifically, for the transistor provided with a protective layer between the low-dimensional material layer and the substrate, the source interconnection metal layer 50 is directly connected to the source electrode 620, and the drain interconnection metal layer 60 is directly connected to the drain electrode 630 (referring to Figure 2 and Figure 3For a transistor with a low-dimensional material layer directly disposed on a substrate, the low-dimensional material layer does not completely cover the underlying substrate, for example, the low-dimensional material layer is a certain density of carbon nanotubes, then the source interconnection metal layer 50 is directly connected with the source electrode 620, and the drain interconnection metal layer 60 is directly connected with the drain electrode 630, to realize a similar wrap-around / embedded source-drain electrode structure (i.e., the source electrode and the drain electrode not only cover the surface of the carbon nanotubes, but also fill the area between adjacent carbon nanotubes to form a wrap-around / embedded source-drain electrode structure). Alternatively, the low-dimensional material layer completely covers the underlying substrate, for example, the low-dimensional material layer is a two-dimensional semiconductor material molybdenum disulfide, (the orthographic projection area of the source interconnection metal layer 50 and the source electrode 620 on the substrate 100 is greater than the orthographic projection area of the low-dimensional material layer 200 on the substrate 100, so that the source interconnection metal layer 50 and the source electrode 620 can be connected through the part located outside the low-dimensional material layer 200, and a similar wrap-around / embedded source electrode structure is formed. Similarly, the orthographic projection area of the drain interconnection metal layer 60 and the drain electrode 630 on the substrate 100 is greater than the orthographic projection area of the low-dimensional material layer 200 on the substrate 100, so that the drain interconnection metal layer 60 and the drain electrode 630 can be connected through the part located outside the low-dimensional material layer 200, and a similar wrap-around / embedded drain electrode structure is formed. Thus, the interconnection between the source electrodes is facilitated, and the interconnection between the drain electrodes is facilitated, and the source interconnection metal layer and the drain interconnection metal layer disposed in the substrate can also reduce the parasitic capacitance between the source-drain electrode and the gate electrode, further improving the performance of the transistor.
[0078] In summary, the transistor has the advantages of controllable threshold voltage, inhibition of off-state tunneling, low parasitic, excellent gate control and electrostatic control, etc., the manufacturing method has a self-alignment process, strong process compatibility, is compatible with large-scale manufacturing process, easy to realize three-dimensional integration, simple process, low cost, and can realize the advantages of vertical channel stacking, ring gate and ring source-drain, etc.
[0079] In another aspect of the present application, a method for manufacturing a transistor is provided. According to embodiments of the present application, the transistor manufactured by the method can be the transistor described above, so that the transistor manufactured by the method has the same features and advantages as the transistor described above, which will not be repeated here.
[0080] According to embodiments of the present application, with reference to Figure 4 the method comprises:
[0081] S100: forming a low-dimensional material layer on a substrate, and forming a plurality of side walls on the side of the low-dimensional material layer away from the substrate
[0082] In this step, a low-dimensional material layer is formed on a substrate, and a plurality of side walls are formed on the side of the low-dimensional material layer away from the substrate.
[0083] The structure of the substrate has been described in detail above and will not be repeated here. For example, the substrate can include a substrate and an insulating and heat-conductive layer formed on the substrate. According to an embodiment of the present application, in this step, the source interconnection metal layer and the drain interconnection metal layer can also be formed in the substrate in advance, so that the source interconnection metal layer is connected to the subsequently formed source electrode and the drain interconnection metal layer is connected to the subsequently formed drain electrode. In this way, the parasitic capacitance between the source / drain electrode and the gate electrode can be reduced, and the manufacturing process can be simplified.
[0084] The material constituting the low-dimensional material layer has been described in detail above and will not be repeated here. For example, the material constituting the low-dimensional material layer can include at least one of carbon nanotubes, nanowires, and two-dimensional materials. In this way, the transistor can have excellent performance when the above-mentioned materials are used as the channel material of the transistor.
[0085] According to an embodiment of the present application, forming the side wall can include:
[0086] (1) sequentially forming a protective material layer 300 and an insulating material layer 400 on the side of the low-dimensional material layer away from the substrate (see FIG. 3B). Figure 5
[0087] According to an embodiment of the present application, the material constituting the protective material layer satisfies the condition that it can be patterned by a non-destructive chemical etching method to remove part of the protective material, so as to achieve patterning of the protective material layer, and the patterning process will not damage the lattice structure of the low-dimensional material and will not cause pollution and damage to the low-dimensional material layer. The specific material constituting the protective material layer is not particularly limited as long as it satisfies the above-mentioned condition. For example, the material constituting the protective material layer can include at least one of yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide, and aluminum oxide. In this way, in the subsequent step, when etching other film layers, the protective material layer can protect the low-dimensional material layer from damage and pollution, and when etching the protective material layer formed by the above-mentioned materials, not only will it not cause damage and pollution to the low-dimensional material layer, but also it can remove impurities and molecules adsorbed on the surface of the low-dimensional material layer, so that the performance of the low-dimensional material layer can be better. It should be noted that when the protective material layer is formed by silicon oxide, chemical etching can be performed using hydrofluoric acid, and when the protective material layer is formed by aluminum oxide, chemical etching can be performed using phosphoric acid to achieve patterning of the protective material layer. When the low-dimensional material layer is carbon nanotubes, since there are gaps between the carbon nanotubes, the thickness of the protective material layer needs to satisfy the condition that the protective material layer can completely wrap the carbon nanotubes to protect the carbon nanotubes.
[0088] According to an embodiment of the present invention, the thickness of the protective material layer can be 3-50 nm. Therefore, the protective material layer can provide excellent protection for the low-dimensional material layer, and at the same time, it can mitigate defects such as lateral etching caused by excessive thickness of the protective material layer during etching.
[0089] The constituent materials and thickness of the insulating layer have been described in detail above and will not be repeated here. For example, the insulating layer may include multiple stacked insulating sublayers (e.g., Figure 5 The first sublayer 410 and the second sublayer 420 shown in (a) can have an insulating material layer thickness of 100-3000 nm. Therefore, the insulating material layer can be used for the fabrication of sidewalls, source / drain electrodes, and gate electrodes in subsequent steps. According to embodiments of the present invention, the number of stacked insulating sublayers can be designed according to the number of deposition processes for source / drain electrodes and gate electrodes in subsequent steps. For example, multiple insulating sublayers can be deposited at once to achieve a predetermined thickness, and then the source / drain electrodes and gate electrodes can be formed by repeatedly patterning the insulating material layer. Alternatively, the insulating sublayers can be deposited in multiple stages, such as pre-depositing a portion of the insulating sublayers, and then re-depositing a portion of the insulating sublayers after forming the source / drain electrodes to form the gate electrode.
[0090] There are no particular restrictions on the formation methods of the insulating and thermally conductive layer, the protective material layer, and the insulating material layer. For example, the above-mentioned film layers can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating.
[0091] There are no particular restrictions on the formation method of low-dimensional material layers. For example, low-dimensional material layers can be formed by physical transfer or solution deposition.
[0092] According to embodiments of the present invention, the deposition temperature of both the insulating material layer and the protective material layer can be below 400°C. This allows for the deposition of the insulating material layer and the protective material layer at lower temperatures, further improving the compatibility of the manufacturing process.
[0093] According to other embodiments of the present invention, in this step, a protective material layer as described above may also be formed between the substrate and the low-dimensional material layer. Specifically, refer to... Figure 10 In step (a), a protective material layer 300B is first formed on the insulating and thermally conductive layer 120, followed by a low-dimensional material layer 200 formed on the protective material layer 300B, then a protective material layer 300A formed on the low-dimensional material layer, and finally an insulating material layer 400 formed on the protective material layer 300A. Therefore, in subsequent steps, after patterning the insulating and protective material layers (such as after forming the first, second, and third grooves), the low-dimensional material layer can be suspended (see reference). Figure 10(b) in FIG. 6, to finally obtain a transistor with a ring gate structure (refer to FIG. 7). Figure 2 According to embodiments of the present application, referring to FIG. 6, Figure 15 The protective material layer 300A covers the low-dimensional material layer 200 (the portion in the dashed line frame in the figure), and the low-dimensional material layer 200 is provided below the protective material layer 300B (not shown in the figure). In the front-rear direction, the width of the low-dimensional material layer 200 is smaller than the width of the protective material layers 300A and 300B. Therefore, when the protective material layer is chemically etched, the protective material layer below the low-dimensional material layer can be etched away, so that the low-dimensional material layer is suspended.
[0094] According to embodiments of the present application, the thickness of the protective material layer 300B can be 3-50 nm. By setting the thickness of the protective material layer in the above range, after the subsequent step of etching away the portion of the protective material layer located in the gate region, the space formed can be used to set the gate dielectric layer and the gate metal layer to form a ring gate structure, and at the same time, when etching the protective material layer, adverse effects such as lateral etching caused by the protective material layer being too thick can be alleviated.
[0095] According to some embodiments of the present application, the low-dimensional material layer can be a single-layer structure, and the final obtained transistor structure is as shown in FIG. 8. Figure 1 and Figure 2 According to other embodiments of the present application, the low-dimensional material layer can also include a plurality of sub-layers, and a protective material layer described above is formed between any two adjacent sub-layers. In this way, the low-dimensional material layer can be vertically stacked, and when the first groove, the second groove, and the third groove are subsequently formed, the vertically stacked low-dimensional material layer can be suspended, which is convenient for forming a ring gate structure and a wrap-around source-drain electrode structure. The final obtained transistor structure is as shown in FIG. 9, which can further improve the performance of the transistor. Figure 3
[0096] (2) sequentially performing a patterning process on the insulating material layer and the protective material layer to form a plurality of first grooves arranged at intervals and expose part of the low-dimensional material layer. Specifically, first, perform a patterning process on the insulating material layer to expose the underlying protective material layer. The patterning process can be performed by using a photoresist as a mask and removing part of the insulating material layer by selective etching. More specifically, the patterning process can be performed by using a reactive ion etching. As described above, the insulating material layer includes a plurality of insulating sub-layers, and different insulating sub-layers can be patterned by using different etching processes. When the insulating material layer is etched, the protective material layer covers the low-dimensional material layer, thereby protecting the low-dimensional material layer from damage and contamination caused by the etching process. Subsequently, perform a patterning process on the protective material layer. Specifically, the patterning process can be performed by using a reactive solution or a reactive gas to chemically etch the protective material layer and then cleaning the protective material layer with water, thereby patterning the protective material layer and finally forming a plurality of first grooves 10 arranged at intervals and exposing part of the low-dimensional material layer (see (b) in FIG. 10). In this way, the first grooves can be formed without damaging and contaminating the low-dimensional material layer. Figure 5
[0097] According to an embodiment of the present application, the reactive solution can include an acidic solution or a basic solution. In this way, the patterning process on the protective material layer can be performed by using the acidic solution or the basic solution to react with the protective material layer, and the process of the acidic solution or the basic solution reacting with the protective material layer does not damage the crystal structure of the low-dimensional material and does not contaminate the low-dimensional material layer.
[0098] The specific components of the acidic solution and the basic solution are not particularly limited. For example, the acidic solution can include at least one of hydrochloric acid, acetic acid, nitric acid, phosphoric acid, and sulfuric acid. The basic solution can include at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide. In this way, the acidic solution or the basic solution described above can be used to react with the protective material layer to remove part of the protective material layer without damaging the crystal structure of the low-dimensional material and without contaminating the low-dimensional material layer. Taking the acidic solution as hydrochloric acid and the protective material layer as a yttrium oxide layer as an example, the hydrochloric acid can react with the yttrium oxide to form liquid yttrium chloride, and the excess hydrochloric acid and yttrium chloride can be washed away with water to form the grooves. The hydrochloric acid can clean the surface of the low-dimensional material layer well without damaging the properties of the low-dimensional material layer, and can remove the impurities introduced in the process, so that the exposed low-dimensional material layer has a good surface, which lays a foundation for subsequent deposition of a sidewall to form a good electrostatic doping. When the protective material layer is formed of aluminum oxide, the protective material layer can be chemically etched by using phosphoric acid, and when the protective material layer is formed of silicon oxide, the protective material layer can be chemically etched by using potassium hydroxide, without damaging the crystal structure of the low-dimensional material layer.
[0099] The specific component of the reaction gas is not particularly limited, for example, the reaction gas can include at least one of hydrogen chloride and hydrogen fluoride. Thus, the reaction gas described above can react with the protective material layer, remove part of the protective material layer, and not destroy the crystal lattice structure of the low-dimensional material.
[0100] According to the embodiment of the present application, when the protective material layer is also arranged between the low-dimensional material layer and the substrate, the low-dimensional material layer is arranged between the two protective material layers, and thus the etching of the two protective material layers can be realized by using the reaction solution or the reaction gas, so that the exposed low-dimensional material layer is suspended (see Figure 10 Thus, the low-dimensional material layer can be anchored at the preset position by the remaining part of the two protective material layers, so that the low-dimensional material layer can be prevented from falling off or moving. When the low-dimensional material layer includes a plurality of sub-layers arranged in a stack, and the protective material layer is also arranged between the adjacent two sub-layers, the protective material layer wraps the plurality of sub-layers, and after the etching of the protective material layer, the adjacent two sub-layers can also be suspended.
[0101] According to the embodiment of the present application, in this step, after the first groove is formed and part of the low-dimensional material layer is exposed, the exposed part of the low-dimensional material layer can be cleaned by using the wet cleaning method to remove the impurities, molecules, polymers and the like adhered to the surface of the low-dimensional material layer, so that the exposed low-dimensional material layer has a good surface, and lays a foundation for the subsequent deposition of the side wall to form a good electrostatic doping.
[0102] (3) Growing a side wall material layer in the first groove and on the side of the insulating material layer away from the substrate. Specifically, first, growing a side wall material layer 510 in the first groove and on the insulating material layer (see Figure 6 (c) and Figure 11According to embodiments of the present application, the method of forming the sidewall material layer can include at least one of atomic layer deposition, chemical vapor deposition, and physical vapor deposition. In this way, the material can be made to fill the first recess well, leaving no voids in the first recess, so as to avoid defects in the sidewall material layer. It should be noted that when the low-dimensional material layer is suspended (including the case where a protective material layer is disposed between the low-dimensional material layer and the substrate, and the case where the low-dimensional material layer includes a plurality of sub-layers stacked, and a protective material layer is disposed between two adjacent sub-layers), the sidewall material layer is grown using atomic layer deposition, and the material can be deposited along the surface, so that the sidewall material layer fills the suspended area below the low-dimensional material layer well. When the low-dimensional material layer is disposed at the surface of the substrate, the sidewall material layer can be grown using at least one of atomic layer deposition, chemical vapor deposition, and physical vapor deposition, and preferably atomic layer deposition. Since the width of the first recess is narrow, the thickness of the sidewall material layer deposited on the upper surface of the insulating material layer using atomic layer deposition can not be too thick, which facilitates subsequent steps and saves material and reduces cost.
[0103] (4) The sidewall material layer is patterned to form a sidewall. The patterning of the sidewall material layer can include at least one of reactive ion etching and chemical mechanical polishing. In this way, the sidewall can be formed in the first recess, and the sidewall can serve as a mask for a self-aligned process in subsequent steps, well controlling the positional relationship between the source / drain and the gate, reducing process cost, and improving the uniformity of the transistor.
[0104] According to embodiments of the present application, for the case where the low-dimensional material layer is suspended in the first recess, impurities, molecules, polymers, etc. adhering to the surface of the low-dimensional material layer are removed by wet cleaning, so that the exposed low-dimensional material layer has a good surface, laying a foundation for subsequent deposition of a sidewall to form a good electrostatic doping. After the sidewall is disposed in the first recess, part of the sidewall is between the low-dimensional material layer and the substrate, and part of the sidewall is on the side of the low-dimensional material layer away from the substrate, i.e., the sidewall surrounds the low-dimensional material layer, and the sidewall can well fix the low-dimensional material layer to avoid movement of the low-dimensional material layer in subsequent steps, and improve the performance of the transistor.
[0105] According to embodiments of the present application, in a subsequent step of forming the source and the drain, a photoresist mask is needed to be formed by patterning. In order to improve the accuracy of lithography, a flat surface can be obtained in this step, and the specific method of forming the flat surface is not particularly limited. For example, according to some embodiments of the present application, the sidewall material layer can be etched first until the upper surface of the sidewall material layer is between the upper and lower surfaces of the second sub-layer 420A farthest from the protective material layer, forming a sidewall roughcast 520 (see FIG. 5B). The sidewall roughcast 520 can be etched to form a sidewall 530 (see FIG. 5C). The sidewall 530 can be used as a mask for the subsequent step of forming the photoresist mask. Figure 6 (d) andFigure 11 (e) and (f) of FIG. 4B, then, the second sub-layer 420A and the side wall rough 520 are subjected to chemical mechanical polishing (CMP) to remove the second sub-layer 420A and part of the side wall rough 520, forming the side wall 500 such that the upper surface of the side wall 500 is flush with the upper surface of the first sub-layer 410A farthest from the protective material layer 300, wherein the first sub-layer 410A acts as a stopping layer for chemical mechanical polishing (refer to (g) of FIG. 4B). Figure 6 (e) and (f) of FIG. 4B, then, the second sub-layer 420A and the side wall rough 520 are subjected to chemical mechanical polishing (CMP) to remove the second sub-layer 420A and part of the side wall rough 520, forming the side wall 500 such that the upper surface of the side wall 500 is flush with the upper surface of the first sub-layer 410A farthest from the protective material layer 300, wherein the first sub-layer 410A acts as a stopping layer for chemical mechanical polishing (refer to (g) of FIG. 4B). Figure 11 (e) and (f) of FIG. 4B, then, the second sub-layer 420A and the side wall rough 520 are subjected to chemical mechanical polishing (CMP) to remove the second sub-layer 420A and part of the side wall rough 520, forming the side wall 500 such that the upper surface of the side wall 500 is flush with the upper surface of the first sub-layer 410A farthest from the protective material layer 300, wherein the first sub-layer 410A acts as a stopping layer for chemical mechanical polishing (refer to (g) of FIG. 4B).
[0106] Alternatively, according to some other embodiments of the present application, after forming the side wall rough 520, the second sub-layer 420A is subjected to chemical mechanical polishing to remove part of the second sub-layer 420A such that the upper surface of the remaining part of the second sub-layer 420A is flush with the upper surface of the side wall rough 520, i.e., the side wall rough 520 is the final side wall 500 (this case is not shown in the figures), in this embodiment, the side wall rough acts as a stopping layer for chemical mechanical polishing.
[0107] Alternatively, according to some other embodiments of the present application, the side wall material layer 510 is directly subjected to chemical mechanical polishing to remove the side wall material layer on the upper surface of the second sub-layer 420A, forming the side wall 500 such that the upper surface of the side wall 500 is flush with the upper surface of the second sub-layer 420A (this case is not shown in the figures), in this embodiment, the second sub-layer acts as a stopping layer for chemical mechanical polishing.
[0108] According to embodiments of the present application, the side wall has fixed charges therein, and the low-dimensional material layer can be electrostatically doped by the fixed charges in the side wall. Specifically, the side wall can be composed of a material having fixed charges. Alternatively, the part of the side wall close to the low-dimensional material layer is composed of a material having fixed charges, and the part of the side wall far from the low-dimensional material layer is composed of a material with low dielectric constant, so that fixed charges can be introduced in the side wall, and the part of the side wall far from the low-dimensional material layer composed of a material with low dielectric constant can further reduce the parasitic capacitance. By electrostatically doping the low-dimensional material layer below the side wall by the fixed charges, the threshold and on-off state of the transistor can be well regulated without affecting the gate control ability of the gate.
[0109] According to some embodiments of the present application, a dipole is introduced in the side wall, and the low-dimensional material layer is electrostatically doped by the dipole in the side wall. Specifically, the side wall can be composed of two materials, and the dipole is formed at the interface between the two materials. For example, for a transistor structure in which the low-dimensional material layer is suspended, the first side wall material and the second side wall material are sequentially deposited by atomic layer deposition, and the low-dimensional material layer is wrapped by the side wall layer, and the dipole is formed at the interface between the first side wall material and the second side wall material. Alternatively, for a transistor structure in which the low-dimensional material layer is directly arranged on the substrate, the dipole can also be introduced in the side wall. For example, the first side wall material and the second side wall material are sequentially deposited, and the deposition method can be at least one of atomic layer deposition, chemical vapor deposition, and physical vapor deposition, and the dipole is formed at the interface between the first side wall material and the second side wall material. By utilizing the dipole to electrostatically dope the low-dimensional material layer below the side wall, the threshold and the switching state of the transistor can be well controlled, and the gate control ability of the gate is not affected.
[0110] S200: Forming source and drain
[0111] In this step, the source and the drain are formed.
[0112] According to some embodiments of the present application, referring to Figure 7 , Figure 8 and Figure 12 , Figure 13 , the forming of the source and the drain can include: first, the insulating material layer and the protective material layer located between the two adjacent side walls are sequentially subjected to a patterning process to form a second groove 20, and part of the low-dimensional material layer 200 is exposed (refer to (f) in Figure 7 and (f) in Figure 12 ). Subsequently, the source and the drain are respectively formed in the second groove 20, so that the source and the drain are separated by the side wall. Thus, the side wall can be used as a mask for a self-aligned process for forming the source and the drain, the position of the source and the drain can be well controlled, the size and the edge profile of the source and the drain can be well controlled, the process cost can be reduced, and the uniformity of the transistor can be improved. In this step, the patterning process of the insulating material layer and the protective material layer is similar to that in S100, and will not be described herein again. According to some embodiments of the present application, in the finally formed transistor, the gate structure is located between the source and the drain, and the gate structure, the source, and the drain are separated by the side wall and are in contact with the side wall. Thus, the second groove formed in this step is formed by patterning the protective material layer and the insulating material layer in the region for forming the source and the drain, that is, the protective material layer and the insulating material layer between part of the side walls are subjected to a patterning process.
[0113] According to some embodiments of the present application, the forming of the source and the drain in the second groove can include:
[0114] First, a metallic material layer 610 is formed in the second groove, on the sidewall and the side of the insulating material layer away from the substrate (see reference). Figure 7 (g) and Figure 12 (g) of the present invention. According to embodiments of the present invention, the formation of the metal material layer may include physical vapor deposition (PVD) or atomic layer deposition (ALD). Thus, PVD offers better collimation and higher metal purity, while ALD allows material to grow along the surface; both deposition methods can achieve good metal material deposition. When the low-dimensional material layer is suspended, ALD is used to grow the metal material layer so that the metal material layer effectively fills the suspended area below the low-dimensional material layer or the suspended area between two adjacent low-dimensional material layers, facilitating the formation of an embedded / surround source / drain electrode structure. When the low-dimensional material layer is suspended, if the low-dimensional material layer is a carbon nanotube material and there are gaps between the carbon nanotubes, PVD can be used to form an embedded / surround source / drain electrode structure.
[0115] Subsequently, a dielectric protective material layer 710 (reference) is formed on the side of the metallic material layer away from the substrate. Figure 7 (h) and Figure 12 (h)). According to embodiments of the present invention, the method of forming the dielectric protective material layer may include atomic layer deposition, chemical vapor deposition, or physical vapor deposition, preferably atomic layer deposition. This allows the material to fill the second groove with a high aspect ratio well, without leaving gaps in the second groove, thus avoiding defects in the dielectric protective material layer. Atomic layer deposition is preferred because it ensures that the remaining portion of the second groove is completely filled while maintaining a relatively thin dielectric protective material layer deposited on the surface of the insulating material layer, facilitating subsequent steps and saving material.
[0116] Subsequently, the dielectric protective material layer is patterned, and portions of the dielectric material layer are selectively removed to form the dielectric protective layer, exposing the metallic material layer located on the sidewalls and the side of the insulating material layer furthest from the substrate (see reference). Figure 8 (i) and Figure 13 (i) in the middle.
[0117] Finally, remove the metal material layer located on the sidewalls and insulation layer away from the substrate (see reference). Figure 8 (j) and Figure 13In (j) of FIG. 6, the metal material layer on the side wall and the insulating material layer far from the substrate is removed to obtain the source and the drain, which are in contact with the side wall. According to the embodiment of the present application, the removal of the metal material layer on the side wall and the insulating material layer far from the substrate can be achieved by reactive ion etching or wet etching, preferably, wet etching. During the etching of the metal material layer on the side wall and the insulating material layer, the source and the drain metal of the source and drain region and the low-dimensional material layer are well separated from the source and drain metal of the etching region by the rough dielectric protection layer 720, so as to avoid the influence and damage of the etching process on the source and drain electrode and the low-dimensional material layer.
[0118] According to the embodiment of the present application, in the subsequent step of forming the gate dielectric layer, a photoresist mask is needed to be formed by patterning. In order to improve the accuracy of the photolithography, a flat surface can be obtained in this step. The specific method for forming the flat surface is not particularly limited. For example, the dielectric protection material layer is patterned to selectively remove part of the dielectric material layer to form the rough dielectric protection layer 720, and expose the metal material layer on the side wall and the insulating material layer far from the substrate (see (k) of FIG. 6). Figure 8 (i) of FIG. 6 and Figure 13 (i) of FIG. 6). The patterning of the dielectric protection material layer can include etching or chemical mechanical polishing. The etching can be achieved by reactive ion etching. Subsequently, the rough dielectric protection layer is patterned to selectively remove part of the rough dielectric protection layer to form the dielectric protection layer 700, so that the surface of the dielectric protection layer 700 far from the substrate is flush with the surface of the side wall far from the substrate (see (k) of FIG. 6 and Figure 8 (k) of FIG. 6 and Figure 13 (k) of FIG. 6). According to the embodiment of the present application, the patterning of the rough dielectric protection layer can be chemical mechanical polishing, or a combination of etching and chemical mechanical polishing. Thus, a structure with a flat surface can be obtained.
[0119] The specific material of the metal material layer is not particularly limited, and those skilled in the art can design according to the commonly used materials of the source and drain electrode in the transistor, such as palladium, scandium, etc.
[0120] According to the embodiment of the present application, after the formation of the second recess and the exposure of part of the low-dimensional material layer in this step, the exposed part of the low-dimensional material layer can be cleaned by wet cleaning to remove impurities, molecules, polymers, etc. adhered to the surface of the low-dimensional material layer, so as to make the exposed low-dimensional material layer have a good surface, and make the performance of the low-dimensional material layer be better.
[0121] In the case that the low-dimensional material layer is suspended in the second groove, the low-dimensional material layer is fixed by the sidewall layers on both sides of the second groove, the surface of the low-dimensional material layer is completely exposed, cleaning can be more effectively performed, and impurities, molecules, polymers and the like adhered to the surface of the low-dimensional material layer can be removed, so that the exposed low-dimensional material layer has a good surface, and the performance of the low-dimensional material layer can be better exerted.
[0122] S300: forming a gate structure to obtain a transistor
[0123] In this step, a gate structure (i.e., a gate) is formed to obtain a transistor.
[0124] According to an embodiment of the present application, referring to Figure 9 and Figure 14 , the forming of the gate structure can include: first, sequentially performing a patterning process on the insulating material layer and the protective material layer between the two sidewalls between the source and the drain, forming a third groove 30, and exposing part of the low-dimensional material layer 200 (refer to (l) in Figure 9 and (l) in Figure 14 ), and forming a gate structure in the third groove 30. Thus, the sidewall can be used as a self-aligned mask for forming the gate, the position of the gate can be well controlled, the size and edge profile of the gate can be well controlled, the process cost can be reduced, and the uniformity of the transistor can be improved. In this step, the patterning process of the insulating material layer and the protective material layer is similar to that in S100, which will not be described here.
[0125] According to an embodiment of the present application, a gate dielectric layer 810 and a gate metal layer 820 are sequentially formed in the third groove to form a gate structure (refer to (m) in Figure 9 and (m) in Figure 14 ), and the gate structure is in contact with the sidewall. In the case that the low-dimensional material layer is suspended in the third groove, a gate dielectric layer can be formed to surround the low-dimensional material layer, and a gate metal layer can be formed to surround the gate dielectric layer (refer to (m) in Figure 14 and (m) in Figure 3 ), which can further improve the gate control and make the transistor obtain better electrostatics.
[0126] According to an embodiment of the present application, the gate dielectric layer and the gate metal layer can be formed by first depositing a gate dielectric material layer and a gate metal material layer in sequence, and then performing selective removal on the gate dielectric material layer and the gate metal material layer away from the substrate side of the insulating material layer, the selective removal including reactive ion etching or chemical mechanical polishing, preferably chemical mechanical polishing, to form the gate dielectric layer and the gate metal layer. The deposition of the gate dielectric material layer and the gate metal material layer can be performed by atomic layer deposition, physical vapor deposition or chemical vapor deposition, and for the case that the low-dimensional material layer is suspended, atomic layer deposition is preferably used to form the gate dielectric layer and the gate metal layer to form a gate-all-around structure.
[0127] According to an embodiment of the present application, the gate dielectric layer can be composed of a single layer of material or multiple layers of material, and the gate metal layer can be composed of a single layer of material or multiple layers of material. The materials of the gate dielectric layer and the gate metal layer are not particularly limited, and those skilled in the art can design the materials according to the commonly used materials of the gate dielectric layer and the gate metal layer in transistors.
[0128] According to an embodiment of the present application, the step further includes forming a gate interconnection metal layer 40 in the third recess, the gate interconnection metal layer 40 being located on the gate metal layer (see FIG. 4D). Figure 9 Figure 14 Thus, the connection between the gate and external circuits can be achieved.
[0129] According to an embodiment of the present application, in this step, after forming the third recess and exposing part of the low-dimensional material layer, the exposed part of the low-dimensional material layer can be cleaned by wet cleaning to remove impurities, molecules, polymers and the like adhered to the surface of the low-dimensional material layer, so that the exposed low-dimensional material layer has a good surface, and the performance of the low-dimensional material layer is better.
[0130] For the case that the low-dimensional material layer is suspended in the third recess, the low-dimensional material layer is fixed by the sidewall layers on both sides of the third recess, and the surface of the low-dimensional material layer is completely exposed, so that the cleaning can be performed more effectively to remove impurities, molecules, polymers and the like adhered to the surface of the low-dimensional material layer, so that the exposed low-dimensional material layer has a good surface, and the performance of the low-dimensional material layer is better.
[0131] It should be noted that, Figures 1-3 and Figures 5-14 are cross-sectional views taken at the positions of the low-dimensional material layers, and therefore, Figures 1-3 and Figures 5-14 only show the positional relationship between the film layers and the low-dimensional material layers in the above cross sections.
[0132] In summary, the method has at least one of the following advantages:
[0133] (1) The method can well control the positional relationship between the source and drain electrodes and the gate electrode, reduce the process cost, and improve the performance of the transistor.
[0134] (2) The method can well control the size and edge morphology of the source and drain electrodes and the gate electrode, and improve the uniformity of the transistor.
[0135] (3) In the process of forming the side wall, the low-dimensional material layer can be fixed by the protective material layer, avoiding the movement, falling off or deformation of the low-dimensional material layer, and further improving the uniformity and process stability of the transistor.
[0136] (4) In the process of forming the source and drain electrodes and the gate electrode, the low-dimensional material layer can be fixed by the side wall, avoiding the movement, falling off or deformation of the low-dimensional material layer, and further improving the uniformity and process stability of the transistor.
[0137] (5) The method can make the low-dimensional material layer suspended, realize the ring gate structure, improve the gate control, and make the transistor obtain better electrostatics, while avoiding the interface effect of the low-dimensional material layer and the gate dielectric layer and the substrate.
[0138] (6) The method can make the low-dimensional material layer suspended, remove the impurities, molecules, polymers and the like adhered to the surface of the low-dimensional material layer through wet cleaning, so that the performance of the low-dimensional material layer is better.
[0139] (7) The method can make the low-dimensional material layer suspended, realize the ring source and drain structure, and make the source and drain metal material and the low-dimensional material layer more effectively contact, thereby further improving the contact quality, reducing the source and drain contact resistance, and improving the thermal stability of the contact.
[0140] (8) The protective material layer is composed of yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide, aluminum oxide and the like. The protective material layer can be etched by using a reaction solution or a reaction gas. The reaction solution and the reaction gas will not damage the low-dimensional material layer, but also can remove the adsorbed substances and ionic impurities on the surface of the low-dimensional material layer, improve the interface properties between the low-dimensional material layer and other film layers, and improve the performance of the transistor.
[0141] (9) In the process of forming the source and drain electrodes, the dielectric protective material layer is formed on the metal material layer. When etching the excess metal material, the dielectric protective material layer can isolate the metal material of the source and drain region from the etching area, so as to avoid the damage of the etching process to the source and drain electrodes and the low-dimensional material layer.
[0142] (10) By introducing fixed charges or dipoles in the sidewall, and electrostatically doping the low-dimensional material layer under the sidewall with the fixed charges or dipoles, the difference caused by the properties of the low-dimensional material itself can be reduced, and the threshold voltage and on-off state of the transistor can be adjusted without affecting the gate control and electrostatic regulation of the low-dimensional material layer by the gate region, so that the transistor can simultaneously meet multiple key indicators (such as on state, off state, threshold voltage, gate control, reliability, etc.).
[0143] In the description of the present application, the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and does not require the present application to be constructed and operated in a specific orientation, therefore cannot be understood as a limitation on the present application.
[0144] In the description of the present application, the description of the terms "one embodiment", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction. In addition, it should be noted that in the present specification, the terms "first", "second" are for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
[0145] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as a limitation on the present application, and the person skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.
Claims
1. A transistor, comprising: The transistor comprises: a substrate and a low-dimensional material layer disposed above the substrate; a plurality of sidewalls disposed on a side of the low-dimensional material layer away from the substrate, the sidewalls being spaced apart, the sidewalls being composed of two materials, a portion of the sidewalls near the low-dimensional material layer being composed of a material with fixed charge, and a portion of the sidewalls away from the low-dimensional material layer being composed of a material with low dielectric constant, a portion of the sidewalls being located between the low-dimensional material layer and the substrate, and another portion of the sidewalls being located on a side of the low-dimensional material layer away from the substrate; the low-dimensional material layer comprises a plurality of sub-layers, and adjacent two of the sub-layers are filled with a portion of the sidewalls, a portion of the source, a portion of the drain, and a portion of the gate structure, wherein the filled gate structure comprises a gate dielectric layer surrounding the low-dimensional material layer and a gate metal layer surrounding the gate dielectric layer, and a vertically stacked structure of the low-dimensional material layer can be achieved; and a protective material layer is formed between the substrate and the low-dimensional material layer; a source and a drain disposed on a side of the low-dimensional material layer away from the substrate; a gate structure disposed on a side of the low-dimensional material layer away from the substrate, the gate structure being located between the source and the drain, the gate structure, the source, and the drain being spaced apart by the sidewalls, and the gate structure, the source, and the drain being in contact with the sidewalls.
2. The transistor according to claim 1, wherein: the gate structure comprises a gate dielectric layer and a gate metal layer, the gate dielectric layer comprises a first portion located between the low-dimensional material layer and the substrate, and a second portion located on a side of the low-dimensional material layer away from the substrate, and a portion of the gate metal layer is located between the first portion and the substrate, and another portion of the gate metal layer is located on a side of the second portion away from the substrate, a portion of the source is located between the low-dimensional material layer and the substrate, and another portion of the source is located on a side of the low-dimensional material layer away from the substrate, a portion of the drain is located between the low-dimensional material layer and the substrate, and another portion of the drain is located on a side of the low-dimensional material layer away from the substrate.
3. The transistor of claim 1, wherein the material constituting the low-dimensional material layer comprises at least one of carbon nanotubes, nanowires, and two-dimensional materials.
4. The transistor of claim 1, wherein The transistor further comprises a gate interconnection metal layer disposed on a side of the gate structure away from the substrate and located between the sidewalls.
5. The transistor of claim 1, wherein The substrate is provided with a source interconnection metal layer connected to the source and a drain interconnection metal layer connected to the drain.
Citation Information
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