Parallel multi-level circulating current suppression topology and circulating current suppression method thereof

Abstract

The application discloses a parallel multi-level circulating current suppression topology and a circulating current suppression method thereof, and belongs to the field of circulating current suppression in a motor simulator for motor controller testing. The parallel multi-level circulating current suppression topology comprises n groups of parallel power semiconductor modules (n>=1), a driving board, a measurement and control unit and n common-mode inductors. The topology can be modularly designed, has good scalability, is applicable to any number of parallel inverter structures, and can expand the number of parallel branches. For an inductive coupling structure, only common-mode inductors need to be added to the original structure, and the structure has small output impedance and large differential-mode impedance, which is beneficial to circulating current suppression. The application adopts common-mode inductive coupling combined with model inverse operation mode, and the steps are as follows: collecting branch currents, converting the branch currents into circulating currents, calculating branch compensation voltages in combination with system state equations, and converting the compensation voltages into compensation duty cycles to add the compensation duty cycles into output PWM waves.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circulating current suppression in motor simulator, and more particularly, to a parallel multi-level circulating current suppression topology and a circulating current suppression method thereof. BACKGROUND

[0002] With the continuous progress of technology, there are higher and higher requirements for the functions, safety and reliability of motor controllers. Traditional mechanical motor test benches have poor repeatability, it is difficult to achieve extreme conditions, and it is difficult for a bench to simultaneously satisfy the testing of multiple different types of motors, increasing the research and development cycle and cost. A motor simulator is a power topology structure for testing a motor controller, and through simulating the port characteristics of a load and a current tracking algorithm, the motor simulator can replace a real motor to test the entire motor controller. Compared with traditional test benches, the motor body and mechanical load of the motor simulator are mathematical models, which can be artificially set and modified to adapt to motors with different parameters and various working conditions, and the motor simulator has the advantages of convenient testing and flexible operation. Parallel multi-level has the advantages of small output harmonics, easy maintenance, high efficiency, high redundancy and high reliability, and is very suitable as a power topology structure for a motor simulator. Through a multi-phase parallel voltage inverter, the current capacity can be greatly improved to obtain higher power, but current imbalance problems will occur. When the output ends of the inverters are connected in parallel, circulating currents will occur due to the inconsistent hardware parameters of the parallel inverters, the non-synchronous switching actions of the parallel inverters, or the inconsistent output electrical parameters. If the circulating currents are not properly handled, the total harmonic distortion of the three-phase currents will increase, the current stress and conduction loss of the switching devices will increase, the system efficiency will decrease, and even the power devices will be damaged. The current balancing problem is a key problem for the application of parallel multi-level structures.

[0003] Currently, there are three types of output coupling networks for parallel multi-level inverters, namely isolation, common-mode inductance and coupled inductance. Isolation uses a separate DC power supply or an AC isolation transformer, which increases the size and bulk of the entire parallel system and makes the entire system expensive. The common-mode inductance uses the characteristic that the sum of the three-phase currents is zero to suppress zero-sequence circulating currents, and the control method of the multi-level inverter is complex. The traditional coupled inductance system has the limitation that it is difficult to modularize and has poor scalability because there is no standardized design for the coupled inductance of any number of interleaved inverters. In terms of software, PI control is generally used. Since the currents of all branches of each phase need to be coordinate-transformed, if a centralized control method is used, the control system has a large amount of calculation, and if a distributed control method is used, the communication rate, synchronization mechanism and other issues need to be considered, which is difficult to implement. SUMMARY

[0004] The purpose of the present application is to solve the above-mentioned motor simulator parallel multi-level inverter circulating current problem, provide a topology structure which can realize effective suppression of high-frequency circulating current of parallel multi-level inverter, and a circulating current suppression method with good dynamic characteristics.

[0005] The technical solution adopted by the present application to solve the above-mentioned deficiencies of the prior art is:

[0006] A parallel multi-level circulating current suppression topology structure, comprising n groups of parallel power semiconductor modules (n≥1), a drive board, a measurement and control unit, and n common-mode inductors; each power semiconductor module is composed of two series-connected power semiconductor devices, one of which is used as an upper bridge arm, and the other is used as a lower bridge arm, the drains of the upper bridge arms of all power semiconductor modules are connected in parallel to the positive electrode of the same power supply, the sources of the lower bridge arms are connected in parallel to the negative electrode of the power supply, and the output ends are coupled through common-mode inductors and then connected in parallel to the same output interface as the total output port of the entire power topology structure; the measurement and control unit obtains the circulating current size of each branch based on the measured current signal, calculates the size of the compensation voltage of each branch in combination with the circulating current suppression algorithm, and controls the output PWM wave through the adjustment of the target duty cycle; the drive board amplifies the PWM wave signal output by the measurement and control unit into a PWM wave signal with a certain driving power, and then controls the output duty cycle of the power semiconductor module.

[0007] Preferably, the number of common-mode inductors is consistent with the number of power semiconductor modules, the output end of the power semiconductor module of the first branch is connected to the first coil of the first common-mode inductor, the output end of the power semiconductor module of the second branch is connected to the first coil of the second common-mode inductor, and the other branches are the same; the output end of the first coil of the first common-mode inductor is connected to the non-identical end of the second coil of the second branch, and so on, and the output end of the last common-mode inductor is connected back to the first coil, which is coupled step by step; the output ends of the power semiconductor modules of each branch are coupled through common-mode inductors respectively with the output ends of the previous and next two branches.

[0008] Preferably, based on the above-mentioned topology structure, the inductance matrix and the resistance matrix expressions which can reflect the coupling relationship between the inductances of the system are derived, the state equation with all parallel branch currents as state variables is established, and the specific parameters in the state equation are obtained in combination with the actual measurement of the mutual inductance, mutual inductance and resistance parameters of the common-mode inductor, wherein

[0009] The inductance matrix expression is In the formula, M n , L n-1 and L n-2 are the mutual inductance of the common-mode inductor of the nth branch inverter, the self-inductance of the first coil of the common-mode inductor, and the self-inductance of the second coil of the common-mode inductor, respectively; and the resistance matrix expression is In the formula, R nLet n be the output resistance of the nth branch inverter; the state equation expression is: In the formula, L0 is the inductance, V* and I* are the target voltage and current, and V and I are the current actual voltage and current.

[0010] Preferably, the power semiconductor module is a SiC MOSFET module, an IGBT module, etc.

[0011] Preferably, the self-inductance of the common-mode inductor is in the range of 10-30mH, and the common-mode inductors are coupled step by step.

[0012] A method for suppressing parallel multilevel circulating current includes the following steps:

[0013] Step 1: Collect the current of each branch of a single phase.

[0014] Step 2: Calculate the circulating current magnitude Δi for each branch current. n .

[0015] Step 3: Calculate the compensation voltage for each branch.

[0016] Step 4: Convert the compensation voltage of each branch into a duty cycle and add it to the modulation wave of that branch, thereby adjusting the duty cycle of the PWM wave output to achieve circulating current suppression.

[0017] Further, in step 2, the circulating current is defined as the difference between the magnitude of the current in each branch and the average current of the phase distributed across all branches. The magnitude of the circulating current Δi is calculated based on this definition. n .

[0018] Furthermore, in step 3, based on the circulating current amplitude of the parallel branches and combined with the state equations, the compensation voltage relationship of the circulating current suppression method is obtained by using model inverse operation. Feedback compensation is then used to achieve the circulating current suppression effect. The compensation voltage relationship of the circulating current suppression method is discretized to obtain the voltage compensation values ​​for each branch.

[0019] In the formula, ΔV(k) is the compensation voltage at the current moment, ΔI(k) is the circulating current at the current moment, L is the inductance matrix, R is the resistance matrix, and T... s For discrete periods, k i and k v For two custom constants whose absolute values ​​are less than or equal to 1.

[0020] Furthermore, the compensation duty cycle in step 4 In the formula This is the branch current to circulating current conversion matrix (n is the number of branches). Udc is the ratio of the triangular carrier amplitude to the bus voltage, where Udc is the bus voltage and a is the triangular carrier amplitude.

[0021] Further, when the parallel multi-level power topology is built, the electrical parameters are also fixed, for the steady system, from the current amplitude to the circulating current amplitude, compensation voltage and duty cycle conversion, the above inductance matrix, resistance matrix and current transformation matrix can be combined into a matrix To simplify the algorithm.

[0022] Further, the step 3 is discretized to the circulating current suppression method compensation voltage relationship, and the discretization method includes but is not limited to one-step Euler method, trapezoidal formula, improved Euler method, fourth-order Runge-Kutta and the like.

[0023] The present application has the following beneficial effects:

[0024] The topology structure of the present application can be modularly designed, has good scalability, is suitable for any number of parallel inverter structures, expands the number of parallel branches, and only needs to increase the common-mode inductance on the original structure for the inductance coupling structure. And the structure has small output impedance; the differential mode impedance is relatively large, which is beneficial to circulating current suppression. The circulating current suppression method of the present application can effectively suppress the circulating current, does not need to perform coordinate transformation, has small calculation amount and is relatively simple, only needs a matrix operation to realize the algorithm, and only needs to expand the matrix dimension for the increase of the number of branches. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 It is a single-phase power topology structure system block diagram.

[0026] Figure 2 It is a circulating current suppression method system block diagram.

[0027] Figure 3 It is a basic flow chart of the circulating current suppression method.

[0028] Figure 4 It is a single-phase 6-branch parallel single-phase experimental result graph.

[0029] Figure 5 It is a circulating current amplitude comparison graph before and after circulating current suppression.

[0030] Figure 6 It is a phase current harmonic analysis graph before and after circulating current suppression.

[0031] Figure 7 It is a first branch current harmonic analysis graph before and after circulating current suppression. DETAILED DESCRIPTION

[0032] A parallel multi-level circulating current suppression topology, comprising n groups of parallel power semiconductor modules (n >= 1), a driving board, a measurement and control unit and n common mode inductors; each power semiconductor module is composed of two series-connected power semiconductor devices, one of which is used as an upper bridge arm and the other as a lower bridge arm, the drains of the upper bridge arms of all power semiconductor modules are connected in parallel to the positive pole of the same power supply, the sources of the lower bridge arms are connected in parallel to the negative pole of the power supply, the output ends are coupled through common mode inductors and then connected in parallel to the same output interface as the total output port of the entire power topology structure; the measurement and control unit calculates the circulating current of each branch based on the measured current signal, calculates the size of the compensation voltage of each branch in combination with the circulating current suppression algorithm, and controls the output PWM wave through the adjustment of the target duty cycle; the driving board amplifies the PWM wave signal output by the measurement and control unit into a PWM wave signal with a certain driving power, and then controls the output duty cycle of the power semiconductor module.

[0033] The power semiconductor module of the application is a SiC MOSFET module, an IGBT module, etc., and in the embodiment, the SiC MOSFET module is taken as an example for description, and if an IGBT module is used, the SiC MOSFET module can be directly replaced by the IGBT module, without the need to make corresponding changes to the topology structure and the circulating current suppression algorithm.

[0034] The theoretical basis of the method of the application is as follows:

[0035] 1. Mathematical model of parallel multi-level circulating current suppression topology

[0036] As shown in Figure 1 The single-phase power topology structure system block diagram is shown in the left dashed box, the common mode inductor cascade coupling structure is shown in the right dashed box, and the two coils and one excitation core represent one common mode inductor. The output end of the SiC MOSFET module of the first branch is connected to the first coil of the first common mode inductor, the output end of the SiC MOSFET module of the second branch is connected to the first coil of the second common mode inductor, and the output ends of the SiC MOSFET modules of the other branches are connected in the same way; the output end of the first coil of the first common mode inductor is connected to the non-identical end of the second coil of the second branch, and the output end of the last common mode inductor is connected back to the first coil, and the coupling is performed step by step; the output ends of the SiC MOSFET modules of each branch are respectively coupled to the output ends of the front and rear two branches through common mode inductors, and the structure has small common mode impedance and large differential mode impedance, which is used to suppress circulating current and has good scalability. The equivalent differential mode inductance and common mode inductance are derived as follows: in order to simplify the circuit analysis, the following assumptions are made: the electrical parameters of each branch in the same structure are consistent, the inductance and mutual inductance are equal, and the resistance value is small and does not affect the inductance matrix derivation, so the influence of resistance can be ignored. The following can be obtained

[0037]

[0038] wherein V a is the common-mode inductor input terminal voltage, V0 is the common-mode inductor output terminal voltage, L0 is the inductance, I a is the current.

[0039] The voltage and current in formula (1) are vectors, and the inductance is a matrix, as follows:

[0040] I a = [i a1 , i a2 , …, i an ] T

[0041] V a = [v a1 , v a2 , …, v an ] T

[0042]

[0043] wherein L is the self-inductance of the common-mode inductor, and M is the mutual inductance of the common-mode inductor.

[0044] The current of each branch is decomposed into an average current and a circulating current, and the average current of each branch is equal, as shown in formula (2).

[0045] i a1 = i a1_ave + Δi a1 (2)

[0046] In order to derive the equivalent common-mode inductance, only the common-mode signal is considered, that is, only the average current is considered, and the current and voltage relationship of the first branch can be obtained as follows:

[0047]

[0048] wherein i an_ave is the average current of the nth branch, Δi an is the circulating current of the nth branch, L is the self-inductance of the common-mode inductor, M is the mutual inductance of the common-mode inductor, and v a0 is the voltage of the nth branch. In formula (3), since the average currents of the branches are equal, the common factor average current can be extracted to simplify formula (4).

[0049]

[0050] Similarly, the relationship between the average voltage of all branches and the average current can be simplified to equation (4). Assuming that all common-mode inductance electrical parameters are consistent and ignoring their resistance, the inductance matrix L0 can be converted to:

[0051]

[0052] Therefore, the equivalent common-mode inductance of the output network is:

[0053]

[0054] wherein is the equivalent common-mode inductance of the output network; 2L b_σ is the leakage inductance.

[0055] Similarly, for the analysis of the differential-mode signal, the differential-mode inductance is:

[0056]

[0057] When n = m or m = 0:

[0058]

[0059] wherein is the equivalent differential-mode inductance of the output network, L is the self-inductance of the common-mode inductance, n is the number of parallel branches, and m is the number of branches opened by the upper bridge arm.

[0060] When n is an even number greater than 0, then

[0061]

[0062] When n is an odd number, then

[0063]

[0064] is the minimum value of the differential-mode inductance. According to the formula, the output impedance (common-mode impedance) of the structure is equal to the leakage inductance; the differential-mode impedance is large, which is conducive to the suppression of circulating current. Moreover, the structure has good scalability. Expanding the number of parallel branches requires only adding a common-mode inductance to the original structure for the inductance coupling structure.

[0065] 2. Implementation of the parallel multi-level circulating current suppression method

[0066] Based on Figure 1 the single-phase power topology structure system block diagram, combined with the mathematical model of the common-mode inductance coupling structure, the actual output phase voltage V can be obtained according to Kirchhoff's voltage law:

[0067]

[0068] Similarly, the target voltage formula V* can be obtained:

[0069]

[0070] wherein

[0071] V = [v1, v2, …, v n ] T

[0072] I = [i1, i2, …, i n ] T

[0073] V * = [v1 * , v2 * , …, v n * ] T

[0074] I * = [i1 * , i2 * , …, i n * ] T

[0075]

[0076]

[0077]

[0078] wherein, v n , v n * , i n , i n * , R n , M n , L n-1 and L n-2 are the actual output voltage, the target output voltage, the actual output current, the target output current, the output resistance, the mutual inductance of the common mode inductor, the self-inductance of the first coil of the common mode inductor and the self-inductance of the second coil of the common mode inductor of the nth branch inverter, respectively.

[0079] The difference between the target voltage value and the current actual voltage value is the compensation voltage value of each branch of the circulating current suppression method. Therefore, the compensation voltage of each branch can be obtained by subtracting equation (11) from equation (12).

[0080]

[0081] According to the definition, I * -I in equation (13) is the circulating current vector, and V *V is the compensation voltage of the circulating current suppression algorithm, let ΔI = I * I; ΔV = V * V can simplify formula (13) to the following formula

[0082]

[0083] After Tustin discrete of formula (14), the following formula can be obtained

[0084]

[0085] In the formula, T s is the discrete period. Simplify formula (15), let

[0086] ΔV(k+1) = k v ΔV(k) (16)

[0087] ΔI(k+1) = k i ΔI(k) (17)

[0088] In the formula, k i and k v are two absolute values less than or equal to 1.

[0089] The purpose of the present application is to suppress circulating current, and the absolute value of circulating current ΔI(k+1) at the next moment should be less than ΔI(k). Similarly, the absolute value of compensation voltage ΔV(k+1) at the next moment should be less than ΔV(k). Then

[0090]

[0091]

[0092] In order to prevent the compensation voltage from being too large to affect the phase current closed-loop control, the inductance L and the discrete period T s are combined, which is two orders of magnitude apart, and k v = 0, k i = 0.995,

[0093]

[0094] As Figure 2 shown in the system block diagram of the circulating current suppression method. The specific implementation of the circulating current suppression method is as follows:

[0095] Step 1, collect the current of each branch of the single-phase through the current sensor.

[0096] Step 2, convert the circulating current of each branch to obtain the circulating current size Δi n .

[0097] Step 3, calculate each branch compensation voltage.

[0098] According to formula (20), each branch compensation voltage is calculated, and the compensation voltage limit is set to prevent over-modulation.

[0099] Step 4, according to the bus voltage and the triangular carrier amplitude, the compensation voltage is converted into duty ratio and added to the modulation wave to adjust the PWM wave output duty ratio.

[0100] In practical application, the input of the controller unit is the current sensor collected current of each branch, and the output is the PWM wave output duty ratio. It contains three calculation parts: branch current to circulating current calculation, each branch circulating current to compensation voltage calculation, and compensation voltage to duty ratio conversion. As Figure 3 The basic flow chart of the circulating current suppression method is shown in the figure, and the branch current to circulating current conversion matrix and the compensation voltage to compensation duty ratio conversion coefficient are replaced by H and K respectively for convenience of derivation.

[0101] The circulating current in the phase is equal to the current of the branch minus the average current of all branches of the phase. For n-parallel branches, the branch current to circulating current conversion matrix H can be obtained:

[0102]

[0103] For the compensation voltage to compensation duty ratio conversion coefficient, it is related to the bus voltage and the triangular carrier amplitude. For the triangular carrier with a valley of 0, formula (22) can be obtained, and K can also be obtained:

[0104]

[0105]

[0106] In the formula, Duty is the compensation duty ratio, ΔV is the compensation voltage of each branch, Udc is the bus voltage, and a is the triangular carrier amplitude. According to formula (23), formula (19) for calculating the compensation voltage of each branch, and the branch current to circulating current conversion matrix H, we can get:

[0107]

[0108] According to formula (24), when the parallel multi-level power topology structure is completed, the electrical parameters are also fixed, and it is a steady system. Therefore, all conversion coefficients can be combined into a matrix.

[0109] 3. Circulating current suppression effect

[0110] To verify the method proposed in this invention, a control algorithm was built based on FPGA. The motor model used in the experiment was a permanent magnet synchronous motor with fixed parameters. The motor had two pole pairs, a dq-axis inductance of 0.26 mH, a stator resistance of 0.03 Ω, and a permanent magnet flux linkage of 0.02 Wb. The motor model was discretized using the forward Euler method, with a discretization step length of 1 μs. The experimental results for a single-phase six-branch parallel single-phase circuit are as follows: Figure 4 As shown, the signals from top to bottom represent branch current, circulating current, and phase current, respectively. The first half of the figure shows the current waveform without the circulating current suppression algorithm enabled, clearly demonstrating the imbalance of branch currents. The second half shows the current waveform after the circulating current suppression algorithm is enabled (at 0.37 seconds, the circulating current suppression algorithm is enabled), showing a significant circulating current suppression effect compared to the first half of the current waveform without the algorithm. The circulating current in the figure also shows a significant change in amplitude before and after the algorithm is enabled. Before the algorithm is enabled, the circulating current amplitude is greater than 2A, and the frequency is consistent with the target current; after the algorithm is enabled, the circulating current amplitude is reduced to around 0.2A, a decrease of approximately 10 times.

[0111] To investigate the circulating current suppression effect of the invented circulating current suppression algorithm under different target current amplitudes at the same speed, a comparison of the circulating current amplitude before and after the algorithm was activated was presented on the motor simulator at a given speed of 10Hz, with the target phase current amplitude of the motor controller ranging from 6A to 60A. The graph shows that before the algorithm was activated, the circulating current amplitude increased with the increase of the phase current; however, after the algorithm was activated, the circulating current amplitude was suppressed to approximately 0.2A, verifying the effectiveness of the algorithm.

[0112] To investigate the impact of the circulating current suppression algorithm on the actual output phase current, Figure 4 Harmonic analysis is performed on the phase current, such as Figure 6 As shown. Figure 6 The figures, from top to bottom, show the phase current waveform, the phase current harmonic analysis before and after the circulating current suppression algorithm is enabled. The total harmonic distortion decreased from 2.38% to 1.38% after enabling the algorithm, indicating that the circulating current suppression algorithm can improve the phase current waveform.

[0113] Severe branch current distortion can increase inverter power loss, reduce efficiency, shorten the lifespan of switching devices, or even directly damage the inverter in extreme cases. Therefore, harmonic analysis of the branch current is also necessary. Figure 7 As shown Figure 4 Harmonic analysis of the first branch. Similarly, Figure 7The first branch current waveform diagram from top to bottom, the first branch current harmonic analysis diagram before the circulating current suppression algorithm is started, and the first branch current harmonic analysis diagram after the circulating current suppression algorithm is started. The total harmonic distortion of the first branch before and after the circulating current suppression algorithm is started is reduced from 6.44% to 1.64%, and the total harmonic distortion is obviously reduced.

[0114] Similarly, Table 1 lists the harmonic analysis of the circulating current suppression algorithm of the six branch currents before and after the circulating current suppression algorithm is started. From the table, it can be seen that after the circulating current suppression algorithm is added, the total harmonic distortion of all branches is obviously reduced, and the fundamental amplitude of all branches is basically stable at the same value, verifying the circulating current suppression effect of the circulating current suppression algorithm and reducing the total harmonic distortion of the branch.

[0115] Table 1 Branch output current harmonic analysis statistical table

[0116]

Claims

1. A parallel multilevel circulating current suppression topology, characterized in that: The parallel multi-level circulating current suppression topology includes n sets of parallel power semiconductor modules (n≥1), a driver board, a measurement and control unit, and n common-mode inductors. Each power semiconductor module consists of two power semiconductor devices connected in series, one of which serves as the upper bridge arm and the other as the lower bridge arm. The drains of the upper bridge arms of all power semiconductor modules are connected in parallel to the positive terminal of the same power supply, and the sources of the lower bridge arms are connected in parallel to the negative terminal of the same power supply. The output terminals are coupled through common-mode inductors and then connected in parallel to the same output interface, serving as the total output port of the entire power topology. The measurement and control unit calculates the circulating current magnitude of each branch based on the measured current signal, and calculates the compensation voltage of each branch using a circulating current suppression algorithm. By adjusting the target duty cycle, it controls the output PWM wave. The driver board amplifies the PWM wave signal output by the measurement and control unit into a PWM wave signal with a certain driving power, thereby controlling the output duty cycle of the power semiconductor modules. Based on the above topology, expressions for the inductance and resistance matrices that reflect the coupling relationships between inductors in the system are derived. A state equation is established with all parallel branch currents as state variables. Combining the actual measured self-inductance, mutual inductance, and resistance parameters of the common-mode inductor, the specific parameters in the state equation are obtained. The expression for the inductor matrix is ​​as follows: M in the formula n L n-1 With L n-2 These represent the mutual inductance of the common-mode inductor in the nth branch inverter, the self-inductance of the first coil of the common-mode inductor, and the self-inductance of the second coil of the common-mode inductor; the resistance matrix expression is... In the formula R n Let n be the output resistance of the nth branch inverter; the state equation expression is: In the formula, L0 is the inductance, V* and I* are the target voltage and current, and V and I are the current actual voltage and current.

2. The parallel multilevel circulating current suppression topology according to claim 1, characterized in that: The number of common-mode inductors is the same as the number of power semiconductor modules. The output terminal of the power semiconductor module of the first branch is connected to the first coil of the first common-mode inductor, the output terminal of the power semiconductor module of the second branch is connected to the first coil of the second common-mode inductor, and so on for the other branches. Then, the output terminal of the first coil of the first common-mode inductor is connected to the opposite terminal of the second coil input terminal of the second branch, and so on, until the output terminal of the last common-mode inductor is connected back to the first coil, thus coupling step by step. The output terminal of the power semiconductor module of each branch is coupled to the output terminals of the preceding and following branches through common-mode inductors.

3. The parallel multilevel circulating current suppression topology according to claim 1, characterized in that: The power semiconductor modules are SiC MOSFET modules and IGBT modules.

4. The parallel multilevel circulating current suppression topology according to claim 1, characterized in that: The self-inductance of common-mode inductors ranges from 10 to 30 mH, and they are coupled step-by-step to each other.

5. A circulating current suppression method using the parallel multilevel circulating current suppression topology according to any one of claims 1-4, comprising the following steps: Step 1: Collect the current of each branch of a single phase; Step 2: Calculate the circulating current magnitude Δi for each branch current. n ; Step 3: Calculate the compensation voltage for each branch; Step 4: Convert the compensation voltage of each branch into a duty cycle and add it to the modulation wave of that branch, thereby adjusting the duty cycle of the PWM wave output to achieve circulating current suppression.

6. The circulation suppression method according to claim 5, characterized in that: In step 2, the circulating current is defined as the difference between the magnitude of the current in each branch and the average magnitude of the total current in that phase distributed across all branches. The magnitude of the circulating current Δi is calculated based on this definition. n .

7. The circulation suppression method according to claim 5, characterized in that: In step 3, based on the circulating current amplitude of the parallel branches and the state equation, the compensation voltage relationship of the circulating current suppression method is obtained by using the inverse model operation. Feedback compensation is then used to achieve the circulating current suppression effect. The compensation voltage relationship of the circulating current suppression method is discretized to obtain the voltage compensation value for each branch. In the formula, αV(k) is the compensation voltage at the current moment, αI(k) is the circulating current at the current moment, L is the inductance matrix, R is the resistance matrix, and T... s For discrete periods, k i and k v For two custom constants whose absolute values ​​are less than or equal to 1; Discretize the compensation voltage relationship of the circulating current suppression method, and the discretization method includes, but is not limited to, the one-step Euler method, the trapezoidal formula, the improved Euler method, and the fourth-order Runge-Kutta method.

8. The circulation suppression method according to claim 5, characterized in that: The compensation duty cycle in step 4 In the formula This is the branch current to circulating current conversion matrix (n is the number of branches). Udc is the ratio of the triangular carrier amplitude to the bus voltage, a is the triangular carrier amplitude, L0 is the inductance, R is the resistance matrix, and T is the ratio of the triangular carrier amplitude to the bus voltage. s For discrete periods, k i and k v For two custom constants whose absolute values ​​are less than or equal to 1.

9. The circulation suppression method according to claim 5, characterized in that: Once the parallel multilevel power topology is built, the electrical parameters are also fixed, making it a steady system. From the acquired current amplitude to the circulating current amplitude, compensation voltage, and duty cycle conversion, the constants such as the inductor matrix, resistance matrix, and current transformation matrix can be combined into a single matrix. To simplify the algorithm, where Udc is the ratio of the triangular carrier amplitude to the bus voltage, a is the triangular carrier amplitude, L0 is the inductance, R is the resistance matrix, and T is the ratio of the triangular carrier amplitude to the bus voltage. s For discrete periods, k i and k v For each of the two user-defined constants whose absolute values ​​are less than or equal to 1, H is the branch current to circulating current conversion matrix.

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