Synchronization of electronic devices

Abstract

This disclosure relates to synchronization of electronic devices. In one embodiment, a switching power supply includes: an output stage; a clock generator configured to generate a first clock signal; and control circuitry configured to control the output stage based on the first clock signal, wherein the switching power supply is configured to have a first operating mode and a second operating mode, the first operating mode being synchronized by the first clock signal and the second operating mode being asynchronous, wherein the clock generator is configured to maintain the first clock signal at a constant value during the second operating mode.

Description

[0001] Cross-citation of related applications

[0002] This application claims priority to French patent application number FR2100872, filed on January 29, 2021, entitled “Synchronisation d'undispositive électronique”, which is hereby incorporated herein by reference to the fullest extent permitted by law.

[0003] This application relates to co-pending U.S. Patent Application No. 17 / 571,759, entitled “Synchronization of an Electronic Device,” filed on the same day as this application and associated with Attorney’s Case No. ST-20-RO-0111US01, which claims priority to French Patent Application No. FR2100869, entitled “Synchronisation d'un dispositif électronique,” ​​filed January 29, 2021, which is incorporated herein by reference. Technical Field

[0004] This disclosure generally relates to electronic systems and methods, and in specific embodiments relates to the synchronization of electronic devices. Background Technology

[0005] In a switching converter, the converter's supply voltage is chopped by a switching switch to implement an energy accumulation phase in the components, including inductive and capacitive elements, and a recovery phase for the energy accumulated in these components to the load connected to the converter's output.

[0006] To implement the various operational phases of the converter, the switching converter includes, for example, circuitry for generating a clock signal. The clock signal is, for example, a signal that periodically changes between high and low levels, corresponding respectively to high and low states of a binary signal. Summary of the Invention

[0007] Some embodiments relate to the synchronization of electronic devices with clock signals. Some embodiments relate to a power supply circuit that includes at least one switching power supply.

[0008] One embodiment provides a device including a switching power supply configured to have a first operating mode and a second operating mode, the first operating mode being synchronized by a first clock signal generated by a first clock signal generation circuit, wherein the first generation circuit is configured to, upon transitioning from the second operating mode to the first operating mode, make the first signal equal to the signal having the most recent rising edge in the second clock signal and a third clock signal complementary to the second clock signal.

[0009] Another embodiment provides a method for controlling a device, the device including a switching power supply configured to have a first operating mode and a second operating mode, the first operating mode being synchronized by a first clock signal generated by a first clock signal generation circuit, wherein upon transition from the second operating mode to the first operating mode, the first signal becomes equal to the second clock signal and a third clock signal complementary to the second clock signal, the signal having the most recent rising edge.

[0010] According to one embodiment, the device includes a first transistor and a second transistor connected in series between a node for applying a supply voltage and a node for applying a reference voltage, the first transistor and the second transistor being connected to each other via internal nodes, and the first transistor and the second transistor being controlled by a second circuit for generating control signals for the first transistor and the second transistor.

[0011] According to one embodiment, the device includes a capacitor connected between an output node of a switching power supply and a reference voltage application node, and an inductor connected between an internal node and an output node.

[0012] According to one embodiment, in a first operating mode, the first transistor and the second transistor are configured to periodically alternate between an on state and an off state.

[0013] According to one embodiment, in the second operating mode, when the voltage on the output node is less than the set point voltage, the second transistor is configured to be off and the first transistor is configured to be on.

[0014] According to one embodiment, the device is configured to generate a fourth signal having a first value during a first operating mode and a second value during a second operating mode.

[0015] According to one embodiment, the first clock signal generating circuit includes a third selection circuit configured to receive a second clock signal and a third clock signal as inputs, and has a control input connected to the output of a D flip-flop configured to receive the second clock signal at a data input and a fourth signal at a clock input.

[0016] According to one embodiment, the first clock signal generating circuit includes a fourth circuit configured to provide a second clock signal at its output, the output being coupled to the input of a third selection circuit via an inverter circuit.

[0017] According to one embodiment, the device includes a comparator that compares the voltage of an internal node with a reference voltage, and a fourth signal having a second value when the comparator determines that the voltage on the internal node is lower than the reference voltage.

[0018] Another embodiment provides a device including a switching power supply configured to have a first operating mode and a second operating mode, the first operating mode being synchronized by a first clock signal generated by a first clock signal generation circuit, wherein the first generation circuit is configured to maintain the first signal at a constant value during the second operating mode.

[0019] Another embodiment provides a method for controlling a device, the device including a switching power supply configured to have a first operating mode and a second operating mode, the first operating mode being synchronized by a first clock signal generated by a first clock signal generation circuit, wherein the first generation circuit maintains the first signal at a constant value during the second operating mode.

[0020] According to one embodiment, the device includes a first transistor and a second transistor connected in series between a node for applying a first supply voltage and a node for applying a second reference voltage, the first transistor and the second transistor being connected to each other via internal nodes, and the first transistor and the second transistor being controlled by a second circuit for generating control signals for the first transistor and the second transistor.

[0021] According to one embodiment, the device includes a first capacitor connected between an output node of a switching power supply and a node for applying a second reference voltage, and includes an inductor connected between an internal node and an output node.

[0022] According to one embodiment, in a first operating mode, the first transistor and the second transistor are configured to periodically alternate between an on state and an off state.

[0023] According to one embodiment, in the second operating mode, when the third voltage on the output node is less than the fourth setpoint voltage, the second transistor is configured to be off and the first transistor is configured to be on.

[0024] According to one embodiment, the device is configured to generate a fourth signal having a first value during a first operating mode and a second value during a second operating mode.

[0025] According to one embodiment, the first circuit includes: a first current source connected in series with a second capacitor between a first supply voltage application node and a second reference voltage application node; a first switch connected in parallel with the first capacitor; a second current source connected in series with the second switch and a third capacitor between the first supply voltage application node and the second reference voltage application node; and a third switch connected in parallel with a component including the third capacitor and the second switch.

[0026] According to one embodiment, the second switch is controlled by a fourth signal.

[0027] According to one embodiment, the first switch and the third switch are configured to be in an ON state during the second operating mode and in the opposite state during the first operating mode.

[0028] According to one embodiment, the first switch and the third switch are configured to receive substantially equal control signals during a second operating mode and complementary control signals during a first operating mode.

[0029] According to one embodiment, the second switch and the third capacitor are connected via an intermediate node, which is connected via a fourth switch to a node for applying a fifth voltage.

[0030] According to one embodiment, the fifth voltage is greater than or equal to the fourth setpoint voltage.

[0031] According to one embodiment, the fourth switch is configured to be controlled by a signal complementary to the fourth signal. Attached Figure Description

[0032] The above-described features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments given by way of illustrative illustrations, and are not limited to the accompanying drawings, wherein:

[0033] Figure 1 An embodiment of an electronic device is shown;

[0034] Figure 2 This is a set of timing diagrams illustrating the operation of one embodiment of a circuit used to generate clock signals;

[0035] Figure 3 An example implementation of a circuit for generating a clock signal is schematically shown, the circuit operating in... Figure 2 Description in Chinese;

[0036] Figure 4 It's a diagram. Figure 1 A set of timing diagrams for the operation of the device, including Figure 3 Examples;

[0037] Figure 5This is a set of timing diagrams illustrating the operation of another embodiment of a circuit for generating clock signals;

[0038] Figure 6 An embodiment of a clock signal generation circuit is schematically illustrated, the operation of which is... Figure 5 The description in the text; and

[0039] Figure 7 It's a diagram. Figure 1 A set of timing diagrams for the operation of the device, including Figure 6 Examples of implementations. Detailed Implementation

[0040] Similar features are indicated by similar reference numerals in the figures. In particular, common structural and / or functional features in various embodiments may be presented with the same reference and may handle the same structure, dimensions, and material properties.

[0041] For clarity, only the operations and elements useful for understanding the embodiments described herein are illustrated and described in detail.

[0042] Unless otherwise indicated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or can be coupled via one or more other elements.

[0043] In the following disclosure, unless otherwise stated, when referring to absolute positional qualifiers, such as the terms “front,” “back,” “up,” “down,” “left,” “right,” etc., or relative positional qualifiers, such as the terms “above,” “below,” “upper,” “lower,” etc., or directional qualifiers, such as “horizontal,” “vertical,” etc., refer to the orientation shown in the figure.

[0044] Unless otherwise stated, the terms “about,” “roughly,” “basically,” and “approximately” indicate within 10%, preferably within 5%.

[0045] Figure 1 This illustrates one embodiment of an electronic device 10. Device 10 is a voltage converter. In this example, converter 10 is a switching power supply type DC / DC converter that converts a DC supply voltage into a DC output voltage.

[0046] Converter 10 is configured to provide a DC output voltage VOUT. The converter includes an output node 12 at which the voltage VOUT is available.

[0047] The converter 10 is supplied with a DC supply voltage VDD. The converter 10 is then connected between a first conductive rail or node 14 connected to the voltage VDD and a second conductive rail or node 16 connected to a reference potential GND (e.g., ground).

[0048] Converter 10 is configured to provide voltage VOUT at a value substantially equal to the setpoint value. For this purpose, converter 10 receives a DC setpoint voltage VREF at input node 18, for example, a reference GND potential, the value of which is represented as the setpoint value of voltage VOUT, preferably equal to the setpoint value of voltage VOUT. In this example, voltages VOUT, VDD, and VREF are positive values.

[0049] In this example, converter 10 is a step-down or "buck" converter, meaning the voltage VOUT setpoint is less than the voltage VDD setpoint. In other words, the value of voltage VOUT is lower than the value of voltage VDD. Some embodiments can be implemented in other types of converters, such as boost or buck-boost converters.

[0050] The converter 10 includes a first MOS ("metal-oxide-semiconductor") transistor 20, preferably a PMOS (P-channel MOS transistor). The MOS transistor 20 is connected between node 14 and an internal first node 22 to which a voltage VLX is applied. In other words, a first conductive terminal of the transistor 20, such as its source, is connected to node 14, and a second conductive terminal of the transistor 20, such as its drain, is connected to the first node 22.

[0051] The converter 10 also includes a second MOS transistor 24, preferably an NMOS transistor (N-channel MOS transistor). Transistor 24 is connected between the first node 22 and node 16. In other words, the first conductive terminal of transistor 24, such as its source, is connected to node 16, and the second conductive terminal of transistor 24, such as its drain, is connected to the first node 22.

[0052] Therefore, transistors 20 and 24 are connected in series between node 14 and track 16, and are interconnected at the internal first node 22.

[0053] The converter 10 includes an inductive element or inductor 26. The inductor 26 is connected between the first node 22 and the node 12.

[0054] Converter 10 includes a first output capacitor 30 connected between nodes 12 and 16. As an example, this capacitor is in the range of 2.2 µF to 20 µF or greater. This output capacitor acts as a filter. In other words, this output capacitor of the converter smooths the current present at node 12 and stores the energy supplied to node 12 by the converter.

[0055] In operation, a load (not shown) is connected between node 12 and rail 16 so that it is powered by voltage VOUT.

[0056] The converter 10 includes a control circuit 28. The circuit 28 is configured to control the operation of the converter 10 to adjust the voltage VOUT, for example, to make the voltage value equal to a set value VREF.

[0057] The converter 10 includes two operating modes: synchronous operating mode and asynchronous operating mode.

[0058] The first operating mode is called "Continuous Conductive Mode" (CCM), such as pulse width modulation (PWM) or pulse frequency modulation (PFM) type, in which each operating cycle of the converter includes an energy accumulation phase in inductor 26 and first capacitor 30, followed by an energy recovery phase of the load connected to the converter. During the energy accumulation phase, the current flowing through inductor 26 increases. During the energy recovery phase, the current flowing through inductor 26 decreases. This operating mode is a synchronous mode, synchronized by a binary clock signal CLK, for example at a frequency of 2.4 MHz. Such an operating mode is considered, for example, the normal operating mode of the converter.

[0059] In some embodiments, the signal CLK is a periodic signal such that it has a high value during a portion of the signal's period, such as half of the period, and a low value during a recovery period, such as the other half of the period. The signal CLK has a duty cycle that is, for example, substantially equal to (e.g., equal to) 50%.

[0060] The second operating mode is called "Pulse Skip" (PSK) mode. In this mode, when the output voltage VOUT is lower than a reference voltage, such as the setpoint voltage VREF, transistor 24 remains off, while transistor 20 is on. Therefore, an energy storage phase is implemented when the output voltage is lower than the setpoint voltage VREF. For example, this operating mode is implemented when the load draws a low current. This operating mode is an asynchronous operating mode.

[0061] Control circuit 28 includes circuit 32, such as a state machine, that generates control signals for transistors 20 and 24. Circuit 32 therefore includes an output coupled (preferably connected) to a control terminal of transistor 20, at which a control signal for transistor 20 is provided. Circuit 32 also includes an output coupled (preferably connected) to a control terminal of transistor 24, at which a control signal for transistor 24 is provided.

[0062] Circuit 32 also includes an input connected to control circuit 34 for a first operating mode, in which circuit 32 receives a determination signal PWM based on the difference between the output voltage VOUT and the setpoint voltage VREF, representing the amplitude or frequency of the energy accumulation or energy recovery phase in the first operating mode. Therefore, the PWM signal is used by circuit 32 in the first operating mode and is not used, for example, during a second operating mode.

[0063] Circuit 34 includes, for example, a comparator 36, configured to compare an output voltage VOUT with a setpoint voltage VREF. Comparator 36 includes an input, preferably a non-inverting input, coupled (preferably connected) to node 18 where the voltage VREF is applied. Comparator 36 also includes an input, preferably an inverting input, coupled (preferably connected) to node 12. Comparator 36 includes an output providing a signal representing the difference between the voltage VOUT and the setpoint voltage VREF.

[0064] Circuit 34 includes another comparator 38. The other comparator 38 includes an input, preferably a non-inverting input, coupled (preferably connected) to the output of comparator 36. Comparator 38 also includes another input, preferably an inverting input, coupled (preferably connected) to the voltage ramp VRAMP application node. Comparator 38 includes an output, at which a PWM signal is provided. The output of the comparator is coupled (preferably connected) to one of the inputs of circuit 32.

[0065] Circuit 32 also includes an input coupled to control circuitry 40 for a second operating mode, in which circuit 32 receives a signal PSK that determines the timing of energy accumulation in the second operating mode based on the difference between the output voltage VOUT and the setpoint voltage VREF. In other words, for a first value of the signal PSK obtained when the output voltage is below the setpoint voltage VREF, transistor 20 is turned on to allow the first capacitor 30 to be charged. For a second value of the signal PSK, transistor 20 is turned off, and transistor 24 preferably remains off during the second operating mode. Therefore, the signal PSK is used by circuit 32 in the second operating mode and, for example, is not used during the first operating mode.

[0066] Circuit 40 includes, for example, a comparator 42 configured to compare an output voltage VOUT with a setpoint voltage VREF. Comparator 42 includes an input coupled (preferably connected) to node 18 where the voltage VREF is applied, preferably an inverting input. Comparator 42 also includes an input coupled (preferably connected) to node 12, preferably a non-inverting input. Comparator 42 includes an output providing a signal representing the difference between the voltage VOUT and the setpoint voltage VREF.

[0067] Circuit 40 includes another comparator 44. The other comparator 44 includes an input, preferably a non-inverting input, coupled (preferably connected) to a voltage ramp application node (e.g., ramp VRAMP). Comparator 44 also includes another input, preferably an inverting input, coupled (preferably connected) to a setpoint voltage VREF application node 18. Comparator 44 includes a control input coupled (preferably connected) to the output of comparator 42. Comparator 44 includes an output, at which a signal PSK provides the value of the output signal of comparator 42. The output of the comparator is coupled (preferably connected) to one of the inputs of circuit 32.

[0068] Therefore, when converter 10 is in the first operating mode, circuit 32 considers the PWM signal to determine the control signals for transistors 20 and 24 and does not consider the PSK signal. Therefore, when converter 10 is in the second operating mode, circuit 32 considers the PSK signal to determine the control signals for transistors 20 and 24 and does not consider the PWM signal.

[0069] Circuit 28 also includes a comparator 46. Comparator 46 includes a first input, preferably a non-inverting input, coupled (preferably connected) to the voltage GND application node 16, and a second input, preferably an inverting input, coupled (preferably connected) to the first node 22. Comparator 46 includes an output coupled (preferably connected) to circuit 32, providing a signal representing the difference between the voltage VLX at the first node 22 and the voltage at node 16. In other words, comparator 46 provides circuit 32 with a signal representing the sign of voltage VLX. If the converter operates in a first operating mode and the comparator determines that voltage VLX is less than voltage GND, circuit 32 causes the converter to enter a second operating mode.

[0070] Circuit 28 also includes a clock generation circuit 48 for generating a clock signal CLK. Circuit 28 therefore includes an output coupled (preferably connected) to circuit 32, on which the CLK signal is provided.

[0071] Clock generation circuit 48 includes an input coupled (preferably connected) to circuit 32, on which a signal MODE representing the operating mode of the converter is provided. For example, signal MODE takes a first value when converter 10 operates in a first operating mode and a second value when converter 10 operates in a second operating mode. Therefore, signal MODE takes the second value when the converter changes from the first operating mode to the second operating mode (i.e., when comparator 46 determines that voltage VLX is lower than voltage GND). For example, signal MODE changes to the first value when the current drawn by the load increases significantly.

[0072] When the converter switches from the second operating mode to the first operating mode, it switches from asynchronous mode to synchronous mode. The clock generation circuit 48, and particularly circuit 32, must be resynchronized. Circuit 32 is synchronized with the rising or falling edge (preferably the rising edge) of the clock signal CLK. When switching to the first operating mode, there may be a period of time between the change in the value of the signal MODE and the next rising edge of the clock signal. During this period, the load draws a significant amount of energy, and the transistor 20 connecting the supply voltage application node and the first node 22 is off. Therefore, the first capacitor 30 discharges rapidly during this cycle, which can cause a significant drop in the voltage supplied to the load.

[0073] Figure 2 , Figure 3 and Figure 4 An embodiment of a circuit for generating a clock signal based on the signal MODE and therefore on the operating mode of the converter is illustrated.

[0074] Figure 2 This is a set of timing diagrams illustrating the operation of one embodiment of a clock generation circuit 48 for generating clock signals. In this embodiment, the clock generation circuit 48 is configured to provide one of a binary clock signal CLK1 and a clock signal complementary to the first clock signal CLK1, having the most recent rising edge, when switching from a second operating mode to a first operating mode.

[0075] Figure 2 The timing diagram includes a timing diagram of a clock signal CLK1, which varies with time, for example, generated by an oscillator included in clock generation circuit 48; a timing diagram of a complementary clock signal / CLK1, which varies with time; and a timing diagram of a signal MODE, which varies with time, and thus illustrates the operating mode of the converter.

[0076] Figure 2 This represents four different and independent scenarios for transitioning from the second operating mode to the first operating mode.

[0077] exist Figure 2In the example, the first value of the signal MODE corresponding to the first operating mode, i.e., the synchronous operating mode, is a high value, and the second value of the signal MODE corresponding to the second operating mode, i.e., the asynchronous operating mode, is a low value.

[0078] In the first case, the time when switching from the second operating mode to the first operating mode is time T1. At time T1, the signal MODE changes from a low value to a high value. Additionally, at time T1, the signal CLK1 has a low value and its complementary signal / CLK1 has a high value. The duration between time T1 and the most recent rising edge of the signal CLK1 is duration D1, and the duration between time T1 and the most recent rising edge of the complementary signal / CLK1 is duration D1'. Duration D1 is shorter than duration D1'. Therefore, the clock signal CLK supplied to the circuit 32 by the clock generation circuit 48 and synchronized with the converter is signal CLK1.

[0079] In the second case, the transition from the second operating mode to the first operating mode occurs at time T2. At time T2, the signal MODE changes from a low value to a high value. Additionally, at time T2, signal CLK1 has a high value and its complementary signal / CLK1 has a low value. The duration between time T2 and the most recent rising edge of signal CLK1 is duration D2', and the duration between time T2 and the most recent rising edge of the complementary signal / CLK1 is duration D2. Duration D2 is shorter than duration D2'. Therefore, the clock signal CLK supplied to circuit 32 by clock generation circuit 48 and synchronized with the converter is the complementary signal of signal CLK1.

[0080] In the third case, the transition from the second operating mode to the first operating mode is at time T3. At time T3, the signal MODE changes from a low value to a high value. Furthermore, time T3 essentially corresponds to the rising edge of signal CLK1 and the falling edge of its complementary signal / CLK1. The duration between time T3 and the next most recent rising edge of signal CLK1 is essentially equal to the duration D3' of one cycle of clock signal CLK1, and the duration between time T3 and the most recent rising edge of the complementary signal / CLK1 of signal CLK1 is the duration D3 corresponding to half a cycle of clock signal CLK1. Duration D3 is shorter than duration D3'. Therefore, the clock signal CLK supplied to circuit 32 by clock generation circuit 48 and synchronized with the converter is the complementary signal / CLK1 of signal CLK1.

[0081] Similarly, in the fourth case, the transition from the second operating mode to the first operating mode is time T4. At time T4, the signal MODE changes from a low value to a high value. Furthermore, time T4 essentially corresponds to the falling edge of signal CLK1 and the rising edge of its complementary signal / CLK1. The duration between time T4 and the next most recent rising edge of signal CLK1 is essentially equal to the duration D4 of half a cycle of clock signal CLK1, and the duration between time T4 and the most recent rising edge of the complementary signal / CLK1 of signal CLK1 is the duration D4' of one cycle of clock signal CLK1. Duration D4 is shorter than duration D4'. Therefore, the clock signal CLK supplied by clock generation circuit 48 to circuit 32 and synchronized with the converter is signal CLK1.

[0082] When switching from the second operating mode to the first operating mode, if the CLK1 signal has a low value, the most recent rising edge is the rising edge of the CLK1 signal, and if the CLK1 signal has a high value, the most recent rising edge is the rising edge of the signal / CLK1.

[0083] In the worst-case scenario, namely the third and fourth scenarios, the duration between the rising edge of the MODE signal (i.e., the transition between the second and first operating modes) and the next rising edge of the CLK clock signal, in other words, the duration of capacitor discharge, is equal to half a clock cycle.

[0084] We could choose to supply signal CLK1 directly to circuit 32. However, in the worst case, the duration between the rising edge of signal MODE and the next rising edge of clock signal CLK can be substantially equal to the entire cycle of signal CLK1. This would be the case, for example, for time T3.

[0085] Figure 3 An example embodiment of a clock generation circuit 48 for generating clock signals is schematically shown, the operation of which is... Figure 2 As described in the text.

[0086] The clock generation circuit 48 includes circuit 50 (OSC), such as an oscillator circuit, which generates a clock signal CLK1 at output 51. Signal CLK1 is periodic and has a constant period. Signal CLK1 preferably remains unchanged during the first and second operating modes of the converter 10, and particularly preferably remains unchanged when switching from the first operating mode to the second operating mode or vice versa.

[0087] Clock generation circuit 48 includes a selection circuit or multiplexer 52. Multiplexer 52 includes an input 53 for receiving signal CLK1. Input 53 is coupled (preferably connected) to output 51 of circuit 50, on which signal CLK1 is provided. Multiplexer 52 includes an input 55 for a complementary signal / CLK1 to receive signal CLK1. Input 55 is connected to output 51 by an inverter circuit 54 that generates a complementary signal to the input signal at the output. Circuit 54 includes an input coupled (preferably connected) to input 53 of multiplexer 52 and an output coupled (preferably connected) to input 55 of multiplexer 52.

[0088] The clock generation circuit 48 also includes a flip-flop 58, preferably a D flip-flop. Flip-flop 58 includes a data input D coupled (preferably connected) to output 51. The flip-flop also includes a clock signal input coupled (preferably connected) to the signal MODE application node. Flip-flop 58 includes an output Q coupled (preferably connected) to the control terminal of multiplexer 52.

[0089] Therefore, input D continuously receives the clock signal CLK1. When switching from the second operating mode to the first operating mode, i.e. when the signal MODE has a rising edge, output Q assumes the value of signal CLK1 at that moment.

[0090] If signal CLK1 has a low value, such as Figure 2 In the first case, the output Q value is low, such as the binary value "0". The multiplexer is configured to output the signal CLK1 received at input 53 when the control signal received at the control input has this low value.

[0091] Similarly, if signal CLK1 has a high value, such as Figure 2 In the second case, the output value Q is a high value, such as the binary value "1". The multiplexer is configured to supply the output a signal complementary to signal CLK1 received at input 55 when the control signal received at the control input has this high value.

[0092] Therefore, the multiplexer is configured to output signal CLK1 when signal CLK1 has a low value on the rising edge of signal MODE, and to output a complementary signal / CLK1 of signal CLK1 when signal CLK1 has a high value on the rising edge of signal MODE.

[0093] Figure 4 It's a diagram. Figure 1 A set of timing diagrams for the operation of the device, including Figure 3 Examples of implementations. In particular, Figure 4 Including the timing diagram of the current (I) shown in the figure:

[0094] - The current drawn by the load is represented by curve 60;

[0095] - The current flowing through inductor 26, in Figures 1 to 3 In the embodiment, it is represented by curve 62; and

[0096] - The current flowing through inductor 26, in a manner similar to... Figure 1 In the converter 10, regardless of the operating mode, the signal CLK is equal to the signal CLK1, as represented by curve 64.

[0097] Figure 4 This includes a timing diagram illustrating binary signals:

[0098] - Signal CLK, represented by curve 66;

[0099] - Signal CLK1, represented by curve 68; and

[0100] - Signal MODE, represented by curve 70.

[0101] Figure 4 Includes a timing diagram illustrating the voltage (VOUT):

[0102] - Figures 1 to 3 The voltage VOUT in the embodiment is represented by curve 72; and

[0103] - Similar to Figure 1 The voltage VOUT in the converter 10 is equal to the signal CLK1 regardless of the operating mode, as represented by curve 74.

[0104] At time T11, the load begins to draw a larger current than before time T11. In other words, at time T11, the current drawn by the load (curve 60) changes from a low value to a high value. The output voltage VOUT begins to drop more than before time T11. At time T11, the converter is still in the operating mode it was in before time T11, namely asynchronous operating mode (PSK). The signal MODE had a low value at time T11 and before time T11.

[0105] At time T13, following time T11, the signal MODE goes high, meaning the converter will switch to synchronous operation mode (PWM). This change is caused by the voltage VOUT falling below the value of voltage VREF at the end of the PSK mode cycle.

[0106] Before time T13, signal CLK is equal to signal CLK1. At time T13, signal CLK1 has a high value, such that the nearest edge is the falling edge of signal CLK1, which is the rising edge of its complementary signal / CLK1. As described above, signal CLK therefore becomes equal to its complementary signal / CLK1.

[0107] The first rising edge of the signal CLK after time T13 occurs at time T15. From time T15 onwards, the average current flowing through inductor 26 increases, charging the first capacitor 30 and supplying power to the load. The voltage VOUT, represented by curve 72, decreases only slightly, and then begins to increase as the current, represented by curve 62, reaches a sufficiently large value, charging the capacitor.

[0108] At time T17, the first rising edge of signal CLK1, which occurred after time T13, occurs. With signal CLK remaining equal to signal CLK1, time T17 is the time when the average current in the load begins to increase, thanks to the subsequent alternating off and on (mode PWM) switching of transistors 20 and 24.

[0109] Figure 2 and Figure 3 The converter in this embodiment behaves similarly from time T15 to time T17, where signal CLK is signal CLK1. However, time T17 occurs half a cycle after time T15 for signal CLK1. This delay results in a difference in voltage VOUT during the transition from asynchronous to synchronous operation. Figure 2 and Figure 3 In the case of the converter in the embodiment, the voltage drop is lower than that in the case of the converter where signal CLK is signal CLK1. In fact, at time T19, which is later than time T15 and time T17, the difference between curves 72 and 74, which represent the voltage VOUT in these two cases, is about 5 mV in this example, which roughly corresponds to 10% of the total voltage drop after time T11.

[0110] therefore, Figures 2 to 4 One advantage of this embodiment is that the maximum possible capacitor discharge time is half the cycle of signal CLK1, that is, half the time when signal CLK1 is directly supplied to circuit 32. Therefore, when switching from the second operating mode to the first operating mode, the drop in voltage VOUT is less than the drop when signal CLK1 is directly supplied to circuit 32.

[0111] Figure 5 , Figure 6 and Figure 7Another embodiment of a circuit for generating a clock signal that depends on the signal MODE, and therefore on the operating mode of the converter, is illustrated.

[0112] Figure 5 This is a set of timing diagrams illustrating the operation of another embodiment of the clock generation circuit 48 for generating clock signals.

[0113] Figure 5 This includes a timing diagram illustrating the signal MODE as it varies with time (t). Figure 5 It also includes a timing diagram illustrating the clock signal CLK supplied to circuit 32 by clock generation circuit 48 as it varies with time (t).

[0114] Figure 5 It shows Figure 1 The converter operation consists of three stages. Specifically, Figure 5 The diagram shows two synchronous phases (PWM) separated by an asynchronous phase (PSK).

[0115] During the first synchronization phase, the signal CLK alternates periodically between high and low values. During the transition between the first synchronization phase and the asynchronous phase, i.e., when the signal MODE changes from a high value to a low value, the signal CLK is assumed to be low, preferably substantially zero.

[0116] The transition between the asynchronous phase and the second synchronous phase, i.e. the moment when the signal MODE changes from a low value to a high value, corresponds to the rising edge of the signal CLK.

[0117] In other words, the signal CLK is maintained at a constant value, preferably a low value, during asynchronous operation mode, and its periodicity is preferably restored by a rising edge during the transition to synchronous mode.

[0118] Figure 6 An embodiment of a clock generation circuit 48 for generating clock signals is schematically illustrated, the operation of which is... Figure 5 As described in the text.

[0119] The clock generation circuit 48 includes a current source 80, which is coupled in series (preferably connected) to a second capacitor 82 between a supply voltage application node (e.g., voltage application node VDD 14) and a reference voltage application node (e.g., voltage application node GND 16). Preferably, the current source 80 includes one terminal coupled (preferably connected) to node 14 and another terminal coupled (preferably connected) to a fourth node 84. Preferably, the second capacitor 82 includes one terminal coupled (preferably connected) to the fourth node 84 and another terminal coupled (preferably connected) to node 16.

[0120] The clock generation circuit 48 also includes another current source 86, coupled in series (preferably connected) with a switch 88 (e.g., a transistor) and a third capacitor 90 between a supply voltage application node (e.g., voltage application node VDD 14) and a reference voltage application node (e.g., voltage application node GND 16). Preferably, the current source 86 includes one terminal coupled (preferably connected) to node 14 and another terminal coupled (preferably connected) to the second node 92. Preferably, the switch includes one terminal (e.g., a conductive terminal) coupled (preferably connected) to the second node 92 and another terminal (e.g., a conductive terminal) coupled (preferably connected) to node 94. Preferably, the third capacitor 90 includes one terminal coupled (preferably connected) to the third node 94 and another terminal coupled (preferably connected) to node 16.

[0121] The assembly including current source 80 and second capacitor 82 is therefore connected in parallel with the assembly including current source 86, switch 88 and third capacitor 90.

[0122] Additionally, the clock generating circuit 48 preferably includes a switch 96, such as a transistor, connected between the third node 94 and the voltage application node VCH. More specifically, one terminal of the switch 96, such as a conductive terminal, is coupled (preferably connected) to the third node 94, and the other terminal, preferably a conductive terminal, is coupled (preferably connected) to the voltage application node VCH. The voltage VCH is preferably greater than or equal to the setpoint voltage VREF, for example, greater than or equal to 0.8 V.

[0123] Transistors 88 and 96 are controlled by complementary signals. Therefore, when one transistor 88 or 96 is turned off, the other transistor is turned on. Preferably, one transistor 88 or 96 is controlled by a signal MODE, while the other transistor is controlled by a signal / MODE that is complementary to MODE. Therefore, the control terminal of switch 88 is coupled (preferably connected) to the application node of signal MODE, and the control terminal of switch 96 is coupled (preferably connected) to the application node of signal / MODE.

[0124] The clock generating circuit 48 also includes a switch 98, such as a transistor, connected between the fourth node 84 and node 14. More specifically, the switch 98 includes a terminal (e.g., a conductive terminal) coupled (preferably connected) to the fourth node 84 and another terminal (e.g., another conductive terminal) coupled (preferably connected) to node 16. The switch 98 is therefore connected in parallel with the second capacitor 82. The switch 98 and the current source 80 are therefore connected in series between nodes 14 and 16.

[0125] Similarly, the clock generating circuit 48 includes a switch 100, such as a transistor, connected between the second node 92 and node 14. More specifically, the switch 100 includes a terminal (e.g., a conductive terminal) coupled (preferably connected) to the second node 92 and another terminal (e.g., another conductive terminal) coupled (preferably connected) to node 16. The switch 100 is thus connected in parallel with a component including a third capacitor 90 and a switch 88. The switch 100 and the current source 86 are thus connected in series between nodes 14 and 16.

[0126] During asynchronous operation, the control signals for transistors 98 and 100 are complementary. In other words, when transistor 98 is on, transistor 100 is off, and vice versa.

[0127] The clock generation circuit 48 includes a comparator circuit 102 configured to compare the voltage at the fourth node 84 with a reference voltage, preferably a setpoint voltage VREF, and to compare the voltage at the second node 92 with the same voltage, preferably a reference voltage, preferably a voltage VREF, compared with the voltage at the fourth node 84.

[0128] Circuit 102 includes an input coupled (preferably connected) to a fourth node 84, preferably an inverting input of a comparator. Circuit 102 includes an input coupled (preferably connected) to a second node 92, preferably an inverting input of a comparator. Circuit 102 includes an input coupled (preferably connected) to a reference voltage application node, preferably an inverting input of a comparator. Circuit 102 includes an output coupled (preferably connected) to node 104, on which a signal S representing a comparison between the voltage at the fourth node 84 and a reference voltage is provided. Circuit 102 includes an output coupled (preferably connected) to node 106, on which a signal R representing a comparison between the voltage at the second node 92 and a reference voltage is provided.

[0129] At the output, circuit 102 is connected to, for example, an RS flip-flop 108 formed by NAND logic gates. More specifically, flip-flop 108 includes a first input coupled (preferably connected) to node 104, preferably a so-called "set" input, and a second input connected to node 106, preferably a "reset" input. The flip-flop contains a first output and a second output referred to as "Q". The first output provides the binary control signal P2 for switch 98. Therefore, the first output of flip-flop 108 is coupled (preferably connected) to the control terminal of transistor 98. The second output provides a signal P1 that is complementary to signal P2.

[0130] In some embodiments, signal P1 may be a clock signal CLK provided to circuit 32.

[0131] The clock generation circuit 48 also includes a selection circuit 110. Circuit 110 receives signals P1 and P2 as inputs and provides a signal P for controlling switch 100 as an output. More specifically, one input of circuit 110 is coupled (preferably connected) to the "Q" output of flip-flop 108, while the other input of circuit 110 is coupled (preferably connected) to the "Q" output of flip-flop 108. "Output. The output of circuit 110 is coupled (preferably connected) to the control terminal of switch 100.

[0132] Circuit 110 also includes a control input for receiving a signal MODE. Circuit 110 is configured to output signal P1 when the signal MODE has a first value (preferably a high value) and to output signal P2 when the MODE signal has a low value.

[0133] Figure 7 It's a diagram. Figure 1 A set of timing diagrams for the operation of the device, including Figure 6 Examples of implementations.

[0134] Figure 7 Includes a timing diagram illustrating the current (I):

[0135] - The current drawn by the load, as shown in curve 115;

[0136] - exist Figure 6 During operation of the embodiment, current flows through inductor 26, as shown in curve 117; and

[0137] - in a similar Figure 1 The current flows through inductor 26 in the converter, where a periodic, unmodified clock signal is supplied to circuit 32, as shown in curve 119.

[0138] Figure 7 This includes a timing diagram illustrating binary signals:

[0139] - The clock signal CLK' is supplied to circuit 32 in the converter corresponding to curve 119, as shown in curve 121;

[0140] - Signal MODE' comes from the converter corresponding to curve 119, as shown in curve 123;

[0141] - Clock signal CLK is supplied to Figure 6 Circuit 32 in the embodiment is shown as curve 125; and

[0142] - Figure 6 The signal MODE of the embodiment is shown as curve 127.

[0143] Figure 7 Includes a timing diagram illustrating the voltage (V):

[0144] - Voltage VREF, as shown in curve 129;

[0145] - The voltage at node 84, as shown in curve 131; and

[0146] - The voltage at the second node 92 is shown in curve 133.

[0147] Figure 7 This includes a timing diagram illustrating binary signals:

[0148] - Signal P1, as shown in curve 135;

[0149] - P signal, as shown in curve 137; and

[0150] - The P2 signal is shown in curve 139.

[0151] At time T21, the load begins to draw a larger current than it had before time T21. In other words, at time T21, the current drawn by the load (curve 115) changes from a low value to a high value. Time T21 occurs when the device is operating in asynchronous mode.

[0152] In asynchronous operation mode, corresponding to the low value of signal MODE, signal CLK is kept at a constant value, which is low in this case.

[0153] The signal P2 controlling transistor 98 has a high value, keeping transistor 98 on. Therefore, the fourth node 84 is connected to node 16 through the conducting transistor and the voltage on the fourth node 84 (curve 131) is essentially equal to the voltage on node 16, i.e., 0 V, while the second capacitor 82 discharges at node 16.

[0154] Furthermore, transistor 88 is off while transistor 96 is on; these transistors are controlled by signals MODE and / MODE, respectively. Transistors 88 and 96 are thus in opposite states. Therefore, the third node 94 is connected to the voltage VCH application node via the conducting transistors. In other words, the voltage across the third capacitor 90 is voltage VCH.

[0155] Since signal MODE has a low value, signal P takes the value of signal P2, which is a high value. Transistor 100 is therefore turned on and the capacitor discharges at node 16. The voltage at the second node 92 (curve 133) is essentially equal to the voltage at node 16, which is 0 V.

[0156] Therefore, in asynchronous mode, the control signals for transistors 98 and 100 turn on the transistors, and preferably the control signals for transistors 98 and 100 are substantially equal.

[0157] At time T22, the voltage VLX on the first node 22 ( Figure 7 (Not shown) becomes lower than the voltage on node 16, for example, below 0 V. Then, the value of signal MODE changes from low to high.

[0158] Therefore, at time T22, signal P takes the value of signal P1, which is complementary to signal P2, i.e., a low value. Then transistor 100 is in the off state. In addition, transistor 88 becomes conductive and transistor 96 becomes off. Then, the voltage at the second node 92 is essentially equal to the voltage VCH, close to the threshold of transistor 88. The voltage at the second node 92 increases until it reaches the value VREF at time T23.

[0159] At time T23, the control signal of transistor 98, i.e., signal P2, is low, while the control signal P, i.e., signal P1, is high. Therefore, when capacitor 84 is charged by current source 80, the voltage at the second node 92 (curve 133) is essentially the value of node 16, and the voltage at the fourth node 82 (curve 131) increases. The clock signal CLK therefore is high at time T23 and remains high until the voltage at the fourth node 84 reaches the value VREF at time T24.

[0160] Then, the clock generation circuit 48 alternates between the first phases corresponding to the low state of the signal CLK, during which:

[0161] Transistor 98 is turned on and the voltage at the fourth node 84 is essentially 0 V; and

[0162] Transistors 100 and 96 are in the off state, transistor 88 is turned on and the voltage on the second node 92 increases until it reaches the value VREF, which causes a transition to the second stage.

[0163] During the second phase, corresponding to the high value of signal CLK:

[0164] Transistor 98 is in the off state and the voltage on node 84 increases until it reaches the value VREF, causing a transition to the first stage; and

[0165] Transistor 100 and transistor 88 are turned on, transistor 96 is turned off, and the voltage at the second node 92 is essentially 0 V.

[0166] Therefore, the duration between the transition from asynchronous mode to synchronous mode, i.e., the transition of the MODE signal from a low value to a high value, and the first rising edge of the clock signal, is the time between time T22 and time T23. This duration is mainly caused by the time it takes for the voltage on the second node 92 to reach the voltage on the third node 94 when transistor 88 is turned on. This time is relatively short, for example, between 1 ns and 10 ns.

[0167] We can choose not to keep the signal CLK at a constant value during asynchronous operation mode. Curves 119, 125, and 127 correspond to this example of a clock signal generation circuit. In this example, the circuit will not include transistors 88 and 96, nor will it include circuit 110. In this example, the third node 94 will be connected to the second node 92, and transistor 100 will be controlled by signal P1. The time between the transition from asynchronous mode to synchronous mode, i.e., the transition of signal MODE' from a low value to a high value, and the first rising edge of the clock signal CLK' depends on the value of signal CLK' when transitioning from asynchronous mode to synchronous mode, and can reach the value of the signal CLK' period. Figure 7 In the example shown, this duration corresponds to the time between time T25 and time T26, which is much longer than the duration between time T22 and time T23.

[0168] Figures 5 to 7 One advantage of this embodiment is that the voltage on the third node 94 in asynchronous mode, namely voltage VCH, is close enough to voltage VREF that the time required for the voltage on the second node 92 to reach VREF is small, and the first rising edge of the clock signal is close to the moment of transition from asynchronous mode to synchronous mode.

[0169] Figure 5 and Figure 7 Another advantage of the embodiments described is that, compared to most clock signal generation circuits, the embodiments only require the addition of a few electronic components.

[0170] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variations will readily conceive of. In particular, in the described embodiments, the circuitry is synchronized with the rising edge of a clock signal. Obviously, the described embodiments are compatible with circuitry synchronized on the falling edge, and modifications can be made by those skilled in the art based on this specification.

[0171] Finally, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art based on the functional descriptions provided above.

Claims

1. A switching power supply, comprising: Output stage; A clock generation circuit, configured to generate a first clock signal, the clock generation circuit comprising: A first current source is coupled in series with a second capacitor, and the first current source and the second capacitor are coupled between a supply terminal and a reference terminal. A first switch, which is coupled in parallel with the second capacitor; A second current source, coupled in series with a second switch and a third capacitor, is coupled between the supply terminal and the reference terminal; and A third switch, the third switch being coupled in parallel with a component including the third capacitor and the second switch; and A control circuit configured to control the output stage based on a first clock signal, wherein the switching power supply is configured to have a first operating mode and a second operating mode, the first operating mode being synchronized by the first clock signal and the second operating mode being asynchronous, wherein the clock generation circuit is configured to maintain the first clock signal at a constant value during the second operating mode.

2. The switching power supply of claim 1, wherein the control circuit is configured to generate a mode signal having a first value during a first operating mode and a second value during a second operating mode.

3. The switching power supply according to claim 1, further comprising: The supply terminal is configured to receive a first supply voltage; as well as The reference terminal is configured to receive a reference voltage, wherein the output stage includes a first transistor and a second transistor, and wherein the control circuit is configured to control the first transistor and the second transistor.

4. The switching power supply according to claim 3, wherein the first transistor and the second transistor are coupled in series between the supply terminal and the reference terminal, the first transistor and the second transistor are coupled to each other through a first intermediate node, and the switching power supply further comprises: An output node, wherein the output terminal is configured to provide an output voltage; A first capacitor is coupled between the output node and the reference terminal; as well as An inductor is coupled between the first intermediate node and the output node.

5. The switching power supply according to claim 3, wherein in the first operating mode, the control circuit is configured to control the first transistor and the second transistor to periodically alternate between an on state and an off state.

6. The switching power supply according to claim 3, wherein in the second operating mode, the control circuit is configured to control the second transistor to be in a turned-off state and the first transistor to be turned on when the output voltage at the output node coupled to the output stage is lower than a set point voltage.

7. The switching power supply of claim 1, wherein the control circuit is configured to generate a mode signal having a first value during a first operating mode and a second value during a second operating mode, and wherein the second switch is configured to be controlled by the mode signal.

8. The switching power supply of claim 1, wherein the first switch and the third switch are configured to be in an ON state during the second operating mode and in the opposite state during the first operating mode.

9. The switching power supply of claim 1, wherein the first switch and the third switch are configured to receive substantially equal control signals during the second operating mode and complementary control signals during the first operating mode.

10. The switching power supply according to claim 7 further includes a fourth switch, the fourth switch being coupled between a third intermediate node and a second intermediate node, the third intermediate node being coupled between the second switch and the third capacitor.

11. The switching power supply of claim 10, wherein the switching power supply is configured to provide an output voltage using the output stage based on a setpoint voltage, and wherein the voltage at the second intermediate node is greater than or equal to the setpoint voltage.

12. The switching power supply of claim 10, wherein the fourth switch is configured to be controlled by a signal complementary to the mode signal.

13. A method for controlling a switching power supply having a first operating mode and a second operating mode, the method comprising: A first clock signal is generated by a clock generation circuit, the clock generation circuit comprising: A first current source is coupled in series with a second capacitor, and the first current source and the second capacitor are coupled between a supply terminal and a reference terminal. A first switch, which is coupled in parallel with the second capacitor; A second current source, coupled in series with a second switch and a third capacitor, is coupled between the supply terminal and the reference terminal; and A third switch, which is coupled in parallel with a component including the third capacitor and the second switch; The output stage of the switching power supply is controlled based on the first clock signal, wherein the first operating mode is synchronized by the first clock signal, and the second operating mode is asynchronous; and During the second operating mode, the first clock signal is kept at a constant value.

14. The method of claim 13, further comprising: The output voltage is supplied to the load based on the setpoint voltage; as well as In response to an increase in the current drawn by the load, the system switches from the second operating mode to the first operating mode.

15. The method of claim 14, further comprising: A mode signal is generated, which has a first value during the first operating mode and a second value during the second operating mode; The second switch is controlled by the mode signal; as well as A fourth switch is controlled by a signal complementary to the mode signal. The fourth switch is coupled between a third intermediate node and a second intermediate node, and the third intermediate node is coupled between the second switch and the third capacitor.

16. The method of claim 15, further comprising receiving a voltage at the second intermediate node that is greater than or equal to the setpoint voltage.

17. A circuit comprising: Supply terminals; Reference terminal; A clock generation circuit, the clock generation circuit being configured to generate a first clock signal; A first comparator, the first comparator having an input configured to be coupled to an output node of an output stage; as well as A control circuit having a first input, a second input, and a first output, wherein the first input is coupled to the output of the first comparator, the second input is coupled to the output of the clock generation circuit, and the first output is configured to be coupled to a control terminal of the output stage, wherein the control circuit is configured to: The output stage is controlled to adjust the output voltage based on a setpoint voltage using either a first operating mode or a second operating mode. The first operating mode is synchronized via a first clock signal, and the second operating mode is asynchronous. A mode signal is generated, the mode signal having a first value during a first operating mode and a second value during a second operating mode, wherein the clock generation circuit includes: A first current source is coupled in series with a second capacitor, and the first current source and the second capacitor are coupled between the supply terminal and the reference terminal. A first switch, which is coupled in parallel with the second capacitor. A second current source, coupled in series with a second switch and a third capacitor, is coupled between the supply terminal and the reference terminal. The second switch includes a control terminal configured to receive the mode signal. A third switch is coupled in parallel with a component including the third capacitor and the second switch.

18. The circuit of claim 17, further comprising a second comparator having a first input, a second input, and a third input, the first input being coupled to a fourth intermediate node, the second input being coupled to a second intermediate node, and the third input being configured to receive the setpoint voltage, wherein the fourth intermediate node is coupled between the first current source and the second capacitor, and wherein the second intermediate node is coupled between the second current source and the second switch.

19. The circuit of claim 18, further comprising: A trigger having an input, a first output, and a second output, the input being coupled to a second comparator, the first output being coupled to a control terminal of a first switch, and the second output being complementary to the first output of the trigger; as well as A multiplexer having a first input, a second input, an output, and a control terminal, the first input being coupled to a first output of a flip-flop, the second input being coupled to a second output of the flip-flop, the output being coupled to a control terminal of a third switch, and the control terminal being configured to receive the mode signal.

20. The circuit of claim 17, wherein the clock generation circuit further comprises a fourth switch coupled between a third intermediate node and a second intermediate node, the third intermediate node being coupled between the second switch and the third capacitor.

21. The circuit of claim 20, wherein the fourth switch is configured to be controlled by a signal complementary to the mode signal.

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