Method for manufacturing a semiconductor device having a gallium-based compound semiconductor layer

Abstract

A method for manufacturing a semiconductor device, comprising: forming an alignment mark (30) in a non-element region (10A) of a gallium-based compound semiconductor layer (10); and after forming the alignment mark (30), forming an element structure in an element region (10B) of the gallium-based compound semiconductor layer (10). The formation of the alignment mark (30) further comprises: implanting metal ions into a portion of a surface layer portion of the non-element region (10A) of the gallium-based compound semiconductor layer (10); and annealing the gallium-based compound semiconductor layer (10).

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device having a gallium-based compound semiconductor layer. Background Art

[0002] As an alignment technique when forming an element structure in a semiconductor device, it is known to form a groove for an alignment mark at a part of a surface layer portion in a non-element region of a semiconductor layer. For example, JP 2020-21773 A describes an example of such a groove type alignment mark. Summary of the invention

[0003] In a semiconductor device, a trench-type alignment mark needs to maintain its concave shape through various steps in the process of forming an element structure of the semiconductor device. For example, the process of forming an element structure of a semiconductor device includes a film forming step of forming an epitaxial layer on the surface of a semiconductor layer by using an epitaxial growth technique. Even when such a film forming step is performed, the trench-type alignment mark needs to maintain its concave shape as an alignment mark.

[0004] According to the research of the present inventors, it was found that when the material of the semiconductor layer is a gallium-based compound semiconductor, it is difficult for the groove-type alignment mark to maintain a recessed shape due to deformation caused by the temperature when the epitaxial layer is formed, or deformation caused by the difference in the film formation speed of the epitaxial layer, depending on the crystal plane on the side surface of the groove.

[0005] The present disclosure provides a technology for forming a new alignment mark other than a trench-type alignment mark in a method of manufacturing a semiconductor device having a gallium-based compound semiconductor layer.

[0006] According to one aspect of the present invention, a method for manufacturing a semiconductor device includes: forming an alignment mark in a non-element region of a gallium-based compound semiconductor layer; and after forming the alignment mark, forming an element structure in an element region of the gallium-based compound semiconductor layer. The formation of the alignment mark includes: implanting metal ions into a portion of a surface layer portion of the non-element region of the gallium-based compound semiconductor layer; and annealing the gallium-based compound semiconductor layer.

[0007] According to such a method, the metal ion-implanted into a part of the surface layer portion of the non-element region in the ion implantation is aggregated and colored by annealing. Therefore, such a colored metal aggregate can be used for an alignment mark. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Objects, features, and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings, in which like parts are designated by like reference numerals, and in which:

[0009] Figure 1 is a diagram schematically showing a manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 : is a cross-sectional view schematically showing a main part of a gallium-based compound semiconductor layer in an alignment mark forming step according to the present embodiment.

[0011] Figure 3 : is a cross-sectional view schematically showing a main part of a gallium-based compound semiconductor layer in an alignment mark forming step according to the present embodiment.

[0012] Figure 4 : is a cross-sectional view schematically showing a main part of a gallium-based compound semiconductor layer in an alignment mark forming step according to the present embodiment.

[0013] Figure 5 is a cross-sectional view schematically showing a main portion of a gallium-based compound semiconductor layer in an alignment mark forming step according to the present embodiment; and

[0014] Figure 6 : is a cross-sectional view schematically showing a main portion of a gallium-based compound semiconductor layer in an element structure forming step in the semiconductor device according to the present embodiment. DETAILED DESCRIPTION

[0015] like Figure 1 As shown, the manufacturing process for manufacturing a semiconductor device according to an embodiment of the present disclosure includes an alignment mark forming process for forming an alignment mark and an element structure forming process for forming an element structure. The alignment mark forming process is performed before the element structure forming process. The element structure forming process includes various steps for forming an element structure (e.g., MOSFET). The element structure referred to here includes various semiconductor regions, such as an n-type drift region, an n-type JFET region, a p-type body region, and an n-type source region.

[0016] Hereinafter, the alignment mark forming process will be described in detail. First, in the alignment mark forming process, a gallium nitride-based semiconductor layer 10 is prepared as a gallium-based compound semiconductor layer, such as Figure 2As shown. The gallium nitride-based semiconductor layer 10 is not particularly limited. In this example, the gallium nitride-based semiconductor layer 10 is made of, for example, a single crystal of gallium nitride (GaN). Instead of the gallium nitride-based semiconductor layer 10, a gallium oxide (Ga2O3)-based semiconductor layer can be prepared as a gallium-based compound semiconductor layer. The gallium nitride-based semiconductor layer 10 is divided into a non-element area 10A and an element area 10B. The non-element area 10A is an area where an element structure is not formed. The non-element area 10A is not particularly limited. In this example, the non-element area 10A is an area corresponding to a cutting line. The element area 10B is an area where an element structure is formed.

[0017] Next, if Figure 3 As shown, a resist mask 20 is formed on the surface of the gallium nitride based semiconductor layer 10 by using a photolithography technique. The resist mask 20 has a plurality of openings 22 formed in a range corresponding to the non-element region 10A of the gallium nitride based semiconductor layer 10. The plurality of openings 22 are formed corresponding to positions where alignment marks are to be formed.

[0018] Next, if Figure 4 As shown by the arrows in FIG. 1 , metal ions are implanted into the surface layer portion of the gallium nitride-based semiconductor layer 10 exposed through the opening 22 of the resist mask 20 by using an ion implantation technique ( Figure 1 The metal to be ion-implanted is not particularly limited. In this example, the metal to be ion-implanted is, for example, magnesium. In this ion-implantation step, the concentration of the ion-implanted magnesium has a peak position located inside the gallium nitride-based semiconductor layer 10. Specifically, the curve of the ion-implanted magnesium has a peak value of 1×10 19 cm -3 or higher peak concentration, and the surface of the gallium nitride-based semiconductor layer 10 has a 1×10 17 cm -3 After the ion implantation step, the resist mask 20 is removed.

[0019] The angle of ion implantation is not particularly limited. In this example, the ion implantation angle is, for example, 0°. In the case where the ion implantation angle is 0°, the ion implantation angle is parallel to the crystal axis of the gallium nitride-based semiconductor layer 10. Therefore, it is possible to suppress the formation of defects in the surface layer portion of the gallium nitride-based semiconductor layer 10. In order to suppress the formation of defects and metal knocking, a through film of SiO2 or SiN may be formed on the surface of the gallium nitride-based semiconductor layer 10, and ion implantation may be performed through the through film.

[0020] Next, if Figure 5As shown, by using the annealing technique to heat the gallium nitride-based semiconductor layer 10 ( Figure 1 The annealing treatment step S2 is performed in the middle. The heating temperature of the annealing treatment step is not particularly limited. In this example, the gallium nitride-based semiconductor layer 10 is heated so that the temperature of the gallium nitride-based semiconductor layer 10 is 1000 degrees Celsius (°C) or higher. When such a high-temperature annealing treatment step is performed, the ion-implanted magnesium is aggregated and colored, thereby forming the alignment mark 30. In particular, at 1×10 19 cm -3 In the gallium nitride-based semiconductor layer 10 into which magnesium is ion-implanted at a concentration of 1×10 17 cm -3 The surface of the gallium nitride based semiconductor layer 10 into which magnesium is ion-implanted at a concentration of 0.1% or less can suppress the aggregation of magnesium. As a result, the formation of defects on the surface of the gallium nitride based semiconductor layer 10 can be suppressed.

[0021] The position of the alignment mark 30 is recognized by image analysis using a camera. Since the gallium nitride based semiconductor layer 10 is a material that transmits visible light, even if the alignment mark 30 is formed inside the gallium nitride based semiconductor layer 10, the alignment mark 30 can be recognized from the surface of the gallium nitride based semiconductor layer 10.

[0022] like Figure 1 As shown, after the alignment mark forming process, an element structure forming process for forming an element structure in the element region of the gallium nitride based semiconductor layer 10 is performed. In the element structure forming process, a metal aggregate in which magnesium is aggregated is used for the alignment mark 30. In the element structure forming process, various steps are performed. For example, the element structure forming process includes a film forming step S11 of forming an epitaxial layer on the surface of the gallium nitride based semiconductor layer 10, and an annealing treatment step S12 of activating an ion-implanted dopant.

[0023] Figure 6 A cross-sectional view of a main part of the gallium nitride-based semiconductor layer 10 after performing the film forming step S11 of the element structure forming process is schematically shown. An epitaxial layer 12 is formed on the surface of the gallium nitride-based semiconductor layer 10. The epitaxial layer 12 is made of gallium nitride and is transparent. Therefore, even after the epitaxial layer 12 is formed, the alignment mark 30 can be recognized through the surface of the epitaxial layer 12. It should be noted that such a film forming step is performed after forming a trench in the p-type body region, for example, so as to form an n-type JFET region in the trench.

[0024] In the case of a trench type alignment mark, when forming such an epitaxial layer 12, the concave shape of the trench type alignment mark is easily deformed and thus is unlikely to be accurately recognized by image analysis. On the other hand, the alignment mark 30 provided by the metal aggregate does not cause such recognition degradation.

[0025] Furthermore, as described above, since the concentration of magnesium ion implanted at the surface of the gallium nitride-based semiconductor layer 10 is adjusted to 1×10 17 cm -3 or less, and therefore, the defect density at the position above the alignment mark 30 in the gallium nitride based semiconductor layer 10 is low. Therefore, the crystallinity of the epitaxial layer 12 formed above the alignment mark 30 is also good, and the recognition degradation of the alignment mark 30 is suppressed.

[0026] As described above, during the element structure formation process, an annealing treatment step S12 for activating the dopant is also performed. The heating temperature of this annealing treatment step during the element structure formation process is higher than the heating temperature of the annealing treatment step during the alignment mark formation process. The heating temperature of the annealing treatment step during the element structure formation process is not particularly limited. In this example, the gallium nitride-based semiconductor layer 10 is heated so that the temperature of the gallium nitride-based semiconductor layer 10 is 1300°C or higher. Even if such a high-temperature annealing treatment is performed, the metal aggregates of magnesium are maintained and the alignment mark 30 does not disappear. In addition, when the annealing treatment is performed at a temperature of 1300°C or higher, a loop defect is formed in the metal aggregates of magnesium. Such a loop defect can help improve the recognition of the alignment mark 30.

[0027] The features of the technology disclosed in the present disclosure are summarized below. It should be noted that the technical elements described below are independent technical elements and have technical usefulness alone or in various combinations.

[0028] In one embodiment, a method for manufacturing a semiconductor device includes: forming an alignment mark 30 in a non-element region 10A of a gallium-based compound semiconductor layer 10; and after forming the alignment mark 30, forming an element structure in an element region 10B of the gallium-based compound semiconductor layer 10. The gallium-based compound semiconductor layer 10 is made of a compound semiconductor containing at least gallium. The gallium-based compound semiconductor layer 10 may be, for example, a gallium nitride-based semiconductor layer or a gallium oxide-based semiconductor layer. The gallium nitride-based semiconductor layer may be, for example, made of gallium nitride (GaN). As another example, the gallium oxide-based semiconductor layer may be made of α- or β-type gallium oxide (Ga2O3). The formation of the alignment mark 30 includes: implanting metal ions into a portion of a surface layer portion of the non-element region 10A of the gallium-based compound semiconductor layer 10; and annealing the gallium-based compound semiconductor layer 10.

[0029] In one embodiment, in the manufacturing method, the gallium-based compound semiconductor layer 10 may be a gallium nitride-based semiconductor layer, and the metal may be magnesium.

[0030] In the case where the metal to be ion-implanted is magnesium, magnesium may be ion-implanted into the gallium nitride-based semiconductor layer 10 during the ion implantation so that the peak concentration of magnesium is 1×10 19 cm -3 When magnesium is ion-implanted at such a high concentration, magnesium aggregation can be satisfactorily generated, and thus the alignment mark 30 can be formed by the non-ferrous metal aggregation.

[0031] In one embodiment, during the ion implantation, magnesium may be ion implanted into the gallium nitride-based semiconductor layer 10 so that the concentration of the ion implanted magnesium has a peak position located inside the gallium nitride-based semiconductor layer 10. By making the peak position of the concentration located inside the gallium nitride-based semiconductor layer 10, it is possible to suppress the generation of defects on the surface of the gallium nitride-based semiconductor layer 10 during the ion implantation. In addition, during the ion implantation, magnesium may be ion implanted into the gallium nitride-based semiconductor layer 10 so that the concentration of the magnesium implanted on the surface of the gallium nitride-based semiconductor layer 10 is 1×10 17 cm -3 Therefore, during ion implantation, it is possible to suppress the formation of defects on the surface of the gallium nitride-based semiconductor layer 10 .

[0032] In one embodiment, in the annealing, the gallium nitride based semiconductor layer 10 may be heated so that the temperature of the gallium nitride based semiconductor layer is 1000 degrees Celsius (° C.) or higher. In this case, magnesium aggregates can be satisfactorily generated and the alignment mark 30 of non-ferrous metal aggregates can be formed.

[0033] In one embodiment, in the manufacturing method, the element structure formation may include: forming an epitaxial layer 12 on the surface of the gallium-based compound semiconductor layer 10 by using an epitaxial growth technique. Even if such an epitaxial layer 12 is formed, the alignment mark 30 provided by the metal aggregate that has been formed in the formation of the alignment mark 30 can suppress the degradation of its recognition.

[0034] In one embodiment, in the manufacturing method, the formation of the element structure may include annealing the gallium-based compound semiconductor layer 10. In the annealing for forming the element structure, the gallium-based compound semiconductor layer 10 may be heated so that the temperature of the gallium-based compound semiconductor layer 10 is higher than the temperature of the annealing for forming the alignment mark 30. In this case, the annealing in forming the alignment mark 30 may be referred to as a first annealing, and the annealing in forming the element structure may be referred to as a second annealing. Even if such a high-temperature annealing is performed in the formation of the element structure, the degradation of the recognition of the alignment mark 30 can be suppressed.

[0035] Although only selected exemplary embodiments and examples have been chosen to illustrate the present disclosure, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made therein without departing from the scope of the present disclosure as defined by the appended claims. In addition, the foregoing description of exemplary embodiments and examples according to the present disclosure is provided for illustration only and not for limiting the disclosure as defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming an alignment mark (30) in a non-element region (10A) of a gallium-based compound semiconductor layer (10); and After the alignment mark (30) is formed, a device structure is formed in the device region (10B) of the gallium-based compound semiconductor layer (10). Wherein, the formation of the alignment mark (30) comprises: implanting metal ions into a portion of a surface layer portion of a non-element region (10A) of the gallium-based compound semiconductor layer (10); and The gallium-based compound semiconductor layer (10) is annealed, wherein The gallium-based compound semiconductor layer (10) is a gallium nitride-based semiconductor layer, and The metal is magnesium.

2. The method according to claim 1, wherein In the ion implantation, the magnesium is ion implanted into the gallium nitride-based semiconductor layer so that the peak concentration of the magnesium is 1×10 19 cm -3 or higher.

3. The method according to claim 1 or 2, wherein In the ion implantation, the magnesium is ion-implanted into the gallium nitride-based semiconductor layer so that a peak position at which the concentration of the magnesium has a peak is located inside the gallium nitride-based semiconductor layer.

4. The method according to claim 3, wherein In the ion implantation, the magnesium is ion implanted into the gallium nitride-based semiconductor layer so that the concentration of the magnesium at the surface of the gallium nitride-based semiconductor layer is 1×10 17 cm -3 or lower.

5. The method according to claim 1 or 2, wherein In the annealing, the gallium nitride-based semiconductor layer is heated so that the temperature of the gallium nitride-based semiconductor layer is 1000 degrees Celsius or higher.

6. The method according to any one of claims 1 to 2, wherein The formation of the element structure includes: An epitaxial layer (12) is formed on the surface of the gallium-based compound semiconductor layer (10) by epitaxial growth technology.

7. The method according to any one of claims 1 to 2, wherein The annealing in the formation of the alignment mark is a first annealing, The formation of the element structure includes: annealing the gallium-based compound semiconductor layer (10) as a second annealing, and In the second annealing, the gallium-based compound semiconductor layer (10) is heated so that the temperature of the gallium-based compound semiconductor layer (10) is higher than the temperature in the first annealing.

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