A method and system for determining overlay error

Abstract

Embodiments of the present application disclose a method and system for determining overlay error. The method includes: during the photolithography process for each layer of wafers, within each die on the reticle pattern, alignment marks are set along the middle of the side line of the cell array region; during the overlay alignment operation, the alignment marks of the current layer are measured against the alignment marks of the previous layer of the current layer by a measuring device to determine the overlay error between the current layer and the previous layer.

Description

[0001] This application is a divisional application of a Chinese patent application with an application date of January 2, 2020, an application number of 202010002054.7, and an invention title of "A Method and System for Determining Overlay Error". Technical Field

[0002] This application relates to, but is not limited to, the field of semiconductor manufacturing, and particularly relates to a method and system for determining overlay error. Background Art

[0003] Three-dimensional and non-volatile (3D NAND) memories are currently popular devices in the field of semiconductor memories. They adopt a device structure with vertically stacked multiple memory cells, which not only achieves extremely high data storage density but also reduces the unit cost of memory cells. Due to the multi-layer stacking of the device structure, multi-layer lithography and alignment are required in the process of manufacturing 3D NAND memories.

[0004] In the related art, in order to monitor the overlay alignment accuracy of each layer of the process, overlay marks are placed on the scribe lanes for measurement to monitor the product process, and the overlay process is compensated and controlled according to the measured overlay error value, so as to ensure the stability of the product. However, as the number of layers and thickness of the device increase, the stress distribution between the center and the edge of the wafer, each exposure area (Shot), and each die will become uneven. At this time, there will be obvious differences between the scribe lane and the conditions inside the die. Only relying on the overlay marks on the scribe lane can no longer accurately reflect the actual situation of the overlay error inside the die. If the overlay marks on the scribe lane are still used for measurement and compensation, there is a great risk of making the alignment accuracy of the overlay inside the die worse, which will have a great impact on the stability of the lithography process and the product process, and further lead to a serious reduction in the yield of the wafer.

[0005] In view of the above problems in the related art, no effective solution has been proposed yet. Summary of the Invention

[0006] In view of this, embodiments of the present application provide a method and system for determining overlay error.

[0007] The technical solution of the embodiments of the present application is implemented as follows:

[0008] On the one hand, embodiments of the present application provide a method for determining overlay error, and the method includes:

[0009] During the lithography process of each layer of the wafer, on each die in the reticle pattern, overlay marks are set along the side lines of the cell array region; each die includes a plurality of the cell array regions;

[0010] When performing overlay alignment operations, a measurement device measures the overlay marks of the current layer and the overlay marks of the previous layer of the current layer to determine the overlay deviation between the current layer and the previous layer.

[0011] On the other hand, an embodiment of the present application provides a system for determining overlay deviation, the system comprising:

[0012] A lithography process device for setting overlay marks along the side edges of the unit array region within each die on the reticle pattern during the lithography process for each layer of the wafer; each die includes a plurality of the unit array regions;

[0013] A measurement device for determining the overlay deviation between the current layer and the previous layer by measuring the overlay marks of the current layer and the overlay marks of the previous layer of the current layer when performing overlay alignment operations.

[0014] In an embodiment of the present application, overlay marks are set in the middle of the side edges of the unit array region within the die. In this way, the accurate overlay deviation within the die can be directly measured during the lithography process, thereby avoiding the risk of wafer scrapping caused by measuring the overlay deviation within the die only after chemical mechanical polishing and improving the product yield. And, since the overlay marks are set in the middle of the side edges of the unit array region, and the storage holes in the middle region of the unit array region are more densely distributed than those in the corner region, compared with setting the overlay marks at the corners of the unit array region, it can more accurately reflect the overlay alignment of the storage holes within the die, thereby further obtaining a more accurate overlay deviation value, and then more accurate deviation compensation can be performed according to this deviation value, making the product process more stable and precise. In addition, since there is no need to additionally set overlay marks on the scribe lane or dicing tape, the method for determining overlay deviation provided by the embodiment of the present application can also save process costs. Description of the Drawings

[0015] Figure 1A Schematic diagram of the effect of setting overlay marks on the scribe lane for overlay deviation measurement and compensation;

[0016] Figure 1B Schematic diagram of the implementation process of a method for determining overlay deviation provided by an embodiment of the present application;

[0017] Figure 1C Schematic diagram of setting overlay marks in the middle of the side edges of the unit array region according to an embodiment of the present application;

[0018] Figure 1D Schematic diagram of setting at least two overlay marks at different positions in the middle of each side edge of the unit array region according to an embodiment of the present application;

[0019] Figure 1ESchematic diagram of the effect of a method for determining overlay error provided by an embodiment of the present application;

[0020] Figure 2 Schematic flow chart of the implementation of a method for determining overlay error provided by an embodiment of the present application;

[0021] Figure 3 Schematic flow chart of the implementation of a method for determining overlay error provided by an embodiment of the present application;

[0022] Figure 4A Schematic flow chart of the implementation of a method for determining overlay error provided by an embodiment of the present application;

[0023] Figure 4B Schematic flow chart of the implementation of a batch-to-batch compensation control method provided by an embodiment of the present application;

[0024] Figure 5 Schematic diagram of the composition structure of a system for determining overlay error provided by an embodiment of the present application. Detailed implementation manners

[0025] In order to make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions of the present application will be further elaborated in detail below in conjunction with the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on the present application. All other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0026] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0027] If similar descriptions such as "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first\second\third" are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0029] To better understand the technical solutions described in the embodiments of the present application, first, the measurement criteria for the overlay alignment accuracy in the technical solutions of the present application will be described.

[0030] The lithography process generally includes steps such as spin coating, pre-baking, exposure, post-baking, development, and hard baking. Among them, exposure is the core step of the lithography process. Before exposure, it is necessary to align the pattern of the circuit device structure on the current layer photomask with the completed pattern of the previous layer in terms of size and position.

[0031] The accurate alignment of the pattern is one of the decisive factors for ensuring the normal operation of the circuit and devices. In actual application scenarios, the alignment accuracy of the pattern can be measured according to the alignment of the core devices in the circuit device structure pattern.

[0032] Taking a 3D NAND memory as an example, since in each layer of memory devices, the core structure is a memory hole, the alignment accuracy of each layer pattern with the previous layer pattern can be measured by the alignment of the memory holes. Figure 1A It is a schematic diagram of the effect of setting overlay marks on the scribe line for overlay deviation measurement and compensation. In the figure, 11 is the exposure area, 12 is the scribe line, 13 is the overlay mark set on the scribe line, 14 is the die in the exposure area, 15 is the overlay deviation vector in the die measured according to the overlay mark 13, 141 is the memory hole in the current layer die, and 142 is the memory hole in the previous layer die. Among them, the longer the length of the overlay deviation vector 15, the greater the deviation. The alignment of the current layer memory hole 141 with the previous layer memory hole 142 represents the actual overlay deviation of the product. When the current layer memory hole 141 is within the area of the previous layer memory hole 142, it means that the product meets the product process requirements. It can be seen that in Figure 1A , among the overlay deviation vectors measured according to the overlay marks 13 on the scribe line 12, the lengths of most vectors are very short, indicating that the overlay deviation measured according to the overlay marks on the scribe line meets the product process requirements; however, the actual situation of the overlay alignment of the memory holes in the die is that the deviation is very large, indicating that the actual overlay deviation in the die does not meet the product process requirements. That is, the overlay deviation measured according to the overlay marks on the scribe line cannot accurately reflect the actual situation of the overlay alignment of the memory holes in the die.

[0033] Based on the above measurement criteria for overlay alignment accuracy, the embodiments of the present application provide a method for determining overlay deviation. Figure 1B It is a flowchart for implementing the method for determining overlay deviation in the embodiments of the present application. As Figure 1B shown, the method includes:

[0034] Step S101, during the lithography process of each layer of the wafer, within each die on the reticle pattern, alignment marks are set along the middle of the side lines of the cell array region.

[0035] Here, by performing the lithography process on each layer of the wafer, the circuit device structure pattern on each layer of the reticle can be transferred to the photoresist covering the wafer. In the lithography process, before exposure, it is necessary to align the size and position of the circuit device structure pattern on the current layer of the reticle with the completed pattern of the previous layer. The previous layer is a layer of the wafer on which the lithography and etching of the circuit device structure pattern have been completed before the lithography process of the current layer of the wafer. When implemented, it can be adjacent to the current layer or not. For example, other dielectric thin film layers, conductive metal layers, etc. may be deposited between the previous layer and the current layer.

[0036] Here, the cell array region is located within the die and is the core area in the memory device, where a large number of memory holes are densely distributed, usually a rectangular area. When implemented, the middle of the side lines of the cell array region is the middle section of each side line and does not belong to the area of the four corners of the cell array region. Alignment marks are set along the middle of the side lines of the cell array region within each die on the reticle pattern. Here, when implemented, the alignment marks need to be as close as possible to the side lines of the cell array region, but cannot be set within the cell array region. In some embodiments, the set alignment marks can be closely attached to the middle of the side lines of the cell array region, as Figure 1C shown. In the figure, 16 is the alignment mark closely attached to the middle of the side lines of the cell array region, where the cell array region is located within die 14 and has a slightly smaller area than the die. The die is not shown in the figure.

[0037] In addition, since the area of the cell array region is only slightly smaller than the area of the die, the area available for setting marks within the die is limited. When implemented, the alignment marks can fall within the die or extend beyond the die range on the premise of being as close as possible to the middle of the side lines of the cell array region. This application embodiment does not limit this.

[0038] Step S102, during the alignment operation, the measurement device measures the alignment marks of the current layer and the alignment marks of the previous layer of the current layer to determine the alignment deviation between the current layer and the previous layer.

[0039] Here, the measurement device obtains the positions of the alignment marks of the current layer and the alignment marks of the previous layer of the current layer through measurement. By calculating the difference between the positions of the alignment marks corresponding to the current layer and the previous layer, the alignment deviation between the current layer and the previous layer can be determined. When implemented, step S102 can be performed in the yellow light process of the lithography process. In some embodiments, the position of the alignment mark can be represented by the coordinates of the alignment mark in the two-dimensional horizontal plane. Correspondingly, the alignment deviation between the current layer and the previous layer can be represented by a vector in the two-dimensional horizontal plane. For example, assuming that the position of an alignment mark of the current layer is (x1, y1) and the position of the corresponding alignment mark of the previous layer is (x2, y2), then the alignment deviation of the current layer at the position (x1, y1) relative to the corresponding position of the previous layer is (x1 - x2, y1 - y2).

[0040] It should be noted that the alignment marks provided in each die can be at least one alignment mark provided in the middle of each side line of the cell array region. In some embodiments, at least two alignment marks at different positions can also be provided in the middle of each side line of the cell array region, as Figure 1D shown. Correspondingly, when performing the alignment operation, the measurement device can measure each alignment mark of the current layer and the alignment mark at the corresponding position of the previous layer to determine the alignment deviation between the current layer and the previous layer.

[0041] In addition, the operation steps of the lithography process and the etching process not elucidated in the embodiments of the present application are clear to those skilled in the art and will not be elaborated herein. Those skilled in the art can adopt appropriate process steps for implementation according to the actual situation during implementation, and the embodiments of the present application do not limit this.

[0042] Based on the above measurement criteria for alignment accuracy, the method for determining the alignment deviation provided by the embodiments of the present application can achieve the effects as Figure 1E shown. As can be seen from Figure 1E , among the alignment deviation vectors measured according to the alignment mark 16, the lengths of most vectors are very short, indicating that the alignment deviation measured according to the alignment mark 16 meets the product process requirements. Moreover, the current layer storage holes 141 are all located within the area of the corresponding storage holes 142 of the previous layer, indicating that the actual situation of the alignment of the storage holes within the die also meets the product process requirements. It can be seen that the alignment deviation measured according to the alignment marks provided in the middle of the side lines closely adjacent to the cell array region can accurately reflect the actual situation of the alignment of the storage holes within the die.

[0043] The method for determining overlay error provided by the embodiment of the present application sets overlay marks along the middle of the side lines of the cell array region within the die. In this way, the accurate overlay error within the die can be directly measured during the lithography process, thereby avoiding the risk of wafer scrapping caused by measuring the overlay error within the die only after chemical mechanical polishing, and improving the product yield.

[0044] Moreover, since the overlay marks are set in the middle of the side lines of the cell array region, and the distribution of storage holes in the middle region of the cell array region is denser than that in the corner region, compared with setting overlay marks at the corners of the cell array region, it can more accurately reflect the overlay alignment of the storage holes within the die, thereby further obtaining a more accurate overlay error value. Furthermore, more accurate error compensation can be performed according to this error value, making the product process more stable and precise. In addition, since there is no need to additionally set overlay marks on the scribe lane or dicing tape, the method for determining overlay error provided by the embodiment of the present application can also save process costs.

[0045] The embodiment of the present application provides a method for determining overlay error. Figure 2 It is a flowchart for implementing the method for determining overlay error of the embodiment of the present application. As Figure 2 shown, the method includes:

[0046] Step S201, during the execution of the first lithography process by the marking device, in each die of the pattern on the first photomask, set a first overlay mark along the middle of the side lines of the cell array region; wherein, the first lithography process is the lithography process performed on the previous layer of wafer in the overlay alignment operation.

[0047] Here, when preparing and obtaining stacked two-layer circuit devices through the lithography process of overlaying and aligning two layers of wafers, first, the lithography process needs to be performed on the previous layer of wafer, that is, the first lithography process. Correspondingly, the first photomask is the photomask used for the exposure operation on the previous layer of wafer. The cell array region is located within the die and is the core region in the storage device, usually a rectangular region. In implementation, the middle of the side lines of the cell array region is the middle section of each side line and does not belong to the four corner regions of the cell array region. The first overlay mark needs to be set as close as possible to the side lines of the cell array region, but cannot be set within the cell array region. In some embodiments, the set overlay mark can be closely attached to the middle of the side lines of the cell array region. As Figure 1C shown, in the figure, 16 is the overlay mark closely attached to the middle of the side lines of the cell array region, where the cell array region is located within die 14 and has a slightly smaller area than the die, which is not shown in the figure.

[0048] Since the area of the unit array region is only slightly smaller than the area of the die, the size of the region within the die for setting the marks is limited. In implementation, the alignment marks can fall within the die or extend beyond the die range on the premise that they are as close as possible to the middle of the side line of the unit array region. This application's embodiments do not limit this.

[0049] Step S202, after the first lithography process is completed, the etching process equipment transfers the first alignment mark to the previous layer of the wafer by performing an etching process on the previous layer of the wafer.

[0050] Here, after the first lithography process is completed, the circuit device structure pattern on the first photomask is transferred to the photoresist covering the previous layer of the wafer. At the same time, the first alignment mark is also transferred to the photoresist covering the previous layer of the wafer. Subsequently, the etching process equipment performs an etching process, using the photoresist presenting the circuit device structure pattern as a mask to etch the area outside the photoresist-covered area on the previous layer of the wafer. After the etching process is completed, the circuit device structure pattern presented on the photoresist covering the previous layer of the wafer is transferred to the previous layer of the wafer, and at the same time, the first alignment mark is also transferred to the previous layer of the wafer.

[0051] Step S203, during the execution of the second lithography process, in each die of the pattern on the second photomask, a second alignment mark is set along the middle of the side line of the unit array region; wherein, the second lithography process is the lithography process performed on the current layer of the wafer in the alignment operation.

[0052] Here, the second lithography process is the lithography process performed on the current layer of the wafer. Correspondingly, the second photomask is the photomask used for the exposure operation on the current layer of the wafer. In implementation, the setting method of the second alignment mark can be the same as that of the first alignment mark, which will not be elaborated here.

[0053] Step S204, using the second photomask, by exposing the second wafer, the second alignment mark on the photomask is transferred to the photoresist covering the current layer of the wafer.

[0054] Here, during the exposure process, ultraviolet light can first be used to irradiate the surface of the wafer with a layer of photoresist through the second photomask, causing a chemical reaction in the photoresist in the exposure area; then, through a developing technique, the photoresist in the exposure area or the unexposed area is dissolved and removed, so that the pattern on the photomask is transferred to the photoresist. Thus, the second alignment mark is also transferred to the photoresist covering the current layer of the wafer.

[0055] In step S205, when performing the overlay alignment detection operation, the first overlay mark and the second overlay mark are measured by a measuring device to determine the overlay deviation between the current layer and the previous layer.

[0056] Here, the first overlay mark is the first overlay mark on the previous layer of the wafer, and the second overlay mark is the second overlay mark on the photoresist covering the current layer of the wafer. The measuring device measures the first overlay mark and the second overlay mark respectively to obtain the positions of the first overlay mark and the second overlay mark. By calculating the difference between the positions of the first overlay mark and the corresponding second overlay mark, the overlay deviation between the current layer and the previous layer can be determined.

[0057] In some embodiments, the position of the overlay mark can be represented by the coordinates of the overlay mark in the two-dimensional horizontal plane. Correspondingly, the overlay deviation between the current layer and the previous layer can be represented by a vector in the two-dimensional horizontal plane. For example, assuming that the position of a first overlay mark in the current layer is (x1, y1), and the position of the corresponding second overlay mark is (x2, y2), then the overlay deviation of the current layer at the position (x1, y1) relative to the corresponding position of the previous layer is (x1 - x2, y1 - y2).

[0058] Here, the number of overlay marks set in the pattern on each photomask layer can be at least one overlay mark set in the middle of each side line of the cell array region. In some embodiments, at least two overlay marks at different positions can also be set along the middle of each side line of the cell array region.

[0059] In some embodiments, steps S201 to S205 may be:

[0060] During the execution of the first lithography process, at least two first overlay marks are set in the middle of each side line of the cell array region within each die of the pattern on the first photomask; wherein, the first lithography process is the lithography process performed on the previous layer of the wafer in the overlay alignment operation;

[0061] After the first lithography process is completed, by performing an etching process, the at least one first overlay mark is transferred to the previous layer of the wafer;

[0062] During the execution of the second lithography process, at least two second overlay marks are set in the middle of each side line of the cell array region within each die of the pattern on the second photomask; wherein, the second lithography process is the lithography process performed on the current layer of the wafer in the overlay alignment operation; the at least two second overlay marks correspond to the positions of the at least two first overlay marks one by one;

[0063] Using the second photomask, by exposing the second wafer, at least two second alignment marks on the photomask are transferred to the photoresist covering the current layer wafer;

[0064] Correspondingly, when performing the alignment detection operation, the measurement device measures each first alignment mark and the second alignment mark at the corresponding position to determine the overlay deviation between the current layer and the previous layer.

[0065] It should be noted that the operation steps of the lithography process and the etching process not elaborated in the embodiments of the present application are clear to those skilled in the art and will not be elaborated herein. Those skilled in the art can adopt appropriate process steps according to the actual situation during implementation, and the embodiments of the present application do not limit this.

[0066] The embodiments of the present application provide a method for determining overlay deviation. Figure 3 This is the implementation flowchart of the method for determining overlay deviation in the embodiments of the present application, as Figure 3 shown, the method includes:

[0067] Step S301, during the lithography process of each layer of wafer by the lithography process equipment, alignment marks are set in the middle of the side line of the unit array area within each die on the photomask pattern;

[0068] Step S302, during the alignment operation, the measurement device measures the alignment marks of the current layer and the alignment marks of the previous layer of the current layer to determine the overlay deviation between the current layer and the previous layer;

[0069] Step S303, the compensation device of the lithography process equipment compensates for the deviation of the photomask pattern of the current layer according to the overlay deviation between the current layer and the previous layer;

[0070] Here, the compensation device of the lithography process equipment can determine the deviation compensation value of the current layer according to the overlay deviation between the current layer and the previous layer and in combination with the requirements of the product process for overlay accuracy. According to the determined deviation compensation value, the compensation device can perform deviation compensation adjustment on the photomask pattern of the current layer through a specific adjustment algorithm. During implementation, those skilled in the art can select an appropriate adjustment algorithm according to actual needs and select an appropriate way to represent the overlay deviation and the deviation compensation value according to the adjustment algorithm. The embodiments of the present application do not limit this.

[0071] In some embodiments, the overlay error between the current layer and the previous layer can be represented by a vector on a two-dimensional horizontal plane. Correspondingly, the deviation compensation value of the current layer can also be represented by a vector on a two-dimensional horizontal plane. For example, assuming the position of a registration mark on the current layer is (x1, y1), and the position of the corresponding registration mark on the previous layer is (x2, y2), then the overlay error of the current layer at the position (x1, y1) relative to the corresponding position on the previous layer is (x1 - x2, y1 - y2). If the requirement of the product process for overlay accuracy is that the deviation along the X-axis and the deviation along the Y-axis are both 0, then the deviation compensation value of the current layer at the position (x1, y1) should be (x2 - x1, y2 - y1). The compensation device can offset the registration mark at the position (x1, y1) and the corresponding circuit device according to the deviation compensation value (x2 - x1, y2 - y1), so as to realize the deviation compensation adjustment at the position of the registration mark on the reticle pattern.

[0072] In some embodiments, the registration marks of each layer can be at least one registration mark arranged in the middle of each side line of the cell array region. Correspondingly, the overlay error between the current layer and the previous layer is at least one vector on a two-dimensional horizontal plane. The compensation device can respectively obtain the corresponding deviation compensation value according to each overlay error vector, and offset each registration mark and the corresponding circuit device according to the corresponding deviation compensation value, so as to realize the deviation compensation adjustment of the reticle pattern of the current layer.

[0073] Step S304: The exposure device exposes the wafer of the current layer according to the compensated reticle pattern of the current layer.

[0074] Here, since the circuit device structure pattern presented on the photoresist covering the wafer of the current layer has not been transferred to the wafer through the etching process, therefore, it is also possible to rework the photolithography process, and re-expose the wafer of the current layer according to the compensated reticle pattern of the current layer, so as to obtain a circuit device structure pattern with higher overlay alignment accuracy on the photoresist covering the wafer of the current layer.

[0075] During implementation, it can be determined whether rework is required according to whether the deviation situation of the intra-die overlay alignment presented on the photoresist of the current layer meets the product process requirements. When it does not meet the product process requirements, first remove the existing photoresist on the wafer, and then perform the photolithography process again, and use the compensated reticle pattern of the current layer to expose the wafer of the current layer.

[0076] It should be noted that the implementation of the above steps S301 and S302 can respectively refer to the specific implementation manners of steps S101 and S102 in the foregoing embodiments. In addition, the operation steps of the lithography process and the etching process not elaborated in the embodiments of the present application are clear to those skilled in the art and will not be elaborated herein. Those skilled in the art can implement appropriate process steps according to the actual situation during implementation, and the embodiments of the present application do not limit this.

[0077] The method for determining overlay error provided by the embodiments of the present application sets overlay marks in the middle along the side line of the cell array area within the die. In this way, the accurate overlay error within the die can be directly measured during the lithography process, and real-time compensation can be performed when the overlay error does not meet the product process requirements, thereby reducing the risk of wafer scrapping and improving the product yield.

[0078] The embodiments of the present application provide a method for determining overlay error. Figure 4A It is a flowchart for implementing the method for determining overlay error in the embodiments of the present application. As Figure 4A shown, the method includes:

[0079] Step S401, during the lithography process of each layer of wafer by the lithography process equipment, within each die on the reticle pattern, overlay marks are set in the middle along the side line of the cell array area;

[0080] Step S402, during the overlay alignment operation, the measurement equipment determines the overlay error between the current layer and the previous layer by measuring the overlay marks of the current layer and the overlay marks of the previous layer of the current layer;

[0081] Step S403, the compensation device of the lithography process equipment performs deviation compensation on the reticle pattern of the current layer according to the overlay error between the current layer and the previous layer;

[0082] Step S404, the exposure device exposes the wafer of the current layer according to the compensated reticle pattern of the current layer;

[0083] Here, the implementation of the above steps S401 to S404 can respectively refer to the specific implementation manners of steps S301 to S304 in the foregoing embodiments.

[0084] Step S405, during the production process of each batch of products, the monitoring equipment monitors the process status of each batch of products in real time by obtaining the overlay error between each layer of wafer and the previous layer of wafer in real time.

[0085] Here, in the lithography process, the in-die overlay marks can be measured in the yellow light process, and the accurate overlay deviation between each layer of the wafer and the previous layer of the wafer can be obtained directly in real time, so as to realize the real-time monitoring of the process status of each batch of products. During implementation, it can also be displayed in real time in the form of reports, curve charts, etc.

[0086] In some embodiments, the monitoring device can also adopt the batch-to-batch (Run-to-Run, R2R) compensation control method according to the obtained overlay deviations between each layer of the wafer and the previous layer of the wafer in each historical batch of products, and perform overlay compensation control on the next batch of products. During implementation, the overlay deviation data between each layer of the wafer and the previous layer of the wafer in each historical batch of products can be modeled, and according to the generated model, the overlay deviation between each layer of the wafer and the previous layer of the wafer in the next batch of products can be predicted, so as to perform corresponding overlay compensation. Here, those skilled in the art can select a suitable modeling algorithm according to the actual business scenario, and the embodiments of the present application do not make any limitations in this regard.

[0087] In some embodiments, the method as Figure 4B shown can be adopted to perform batch-to-batch compensation control, and this method includes:

[0088] Step S411, obtaining the overlay deviations between each layer of the wafer and the previous layer of the wafer in a specific number of the most recent historical batches of products;

[0089] Here, the specific number can be a value preset according to the production situation.

[0090] Step S412, respectively determining the weights corresponding to the overlay deviations of each batch of products;

[0091] Here, the weights corresponding to the overlay deviations of each batch of products can be determined according to the yield of each batch of products, or can be determined according to the production order of each batch of products. Those skilled in the art can select a suitable weight determination method according to the actual business scenario, and the embodiments of the present application do not make any limitations in this regard.

[0092] Step S413, for the overlay deviation of each batch of products, respectively performing weighted calculation according to the corresponding weight to obtain the estimated overlay deviation of the next batch of products;

[0093] Step S414, performing pre-compensation for the overlay deviation of the next batch of products according to the estimated overlay deviation.

[0094] Here, the obtained estimated overlay error includes the data obtained by estimating the overlay error of each layer of the next batch of products. During the multi-layer stacking process of the next batch of products, when performing overlay alignment operations on each layer, the corresponding estimated overlay compensation value can be calculated according to the estimated overlay error of this layer, and the photomask pattern of this layer can be pre-compensated for overlay error according to this estimated overlay compensation value.

[0095] It should be noted that the operation steps of the lithography process and the etching process not elaborated in the embodiments of the present application are clear to those skilled in the art and will not be elaborated here. Those skilled in the art can adopt appropriate process steps for implementation according to the actual situation during implementation, and the embodiments of the present application do not limit this.

[0096] For the method for determining overlay error provided by the embodiments of the present application, overlay marks are set in the middle of the side line of the unit array area within the die. In this way, the accurate overlay error within the die can be directly measured in the lithography process, and the accurate overlay error between each layer of the wafer and the previous layer of the wafer can be obtained in real time, so as to realize real-time monitoring of the process status of each batch of products. In addition, according to the overlay errors between each layer of the wafer and the previous layer of the wafer in each historical batch of products obtained, a batch-to-batch compensation control method can be adopted for long-term overlay compensation control.

[0097] The embodiments of the present application provide a system for determining overlay error. Figure 5 As shown in the schematic diagram of the composition structure of the system, Figure 5 as shown, the system 500 includes:

[0098] A lithography process device 501, configured to set overlay marks in the middle of the side line of the unit array area within each die on the photomask pattern during the lithography process of each layer of the wafer;

[0099] A measuring device 502, configured to determine the overlay error between the current layer and the previous layer by measuring the overlay marks of the current layer and the overlay marks of the previous layer of the current layer during the overlay alignment operation.

[0100] In some embodiments, the lithography process device is further configured to set at least two overlay marks at different positions in the middle of each side line of the unit array area; correspondingly, the measuring device is further configured to determine the overlay error between the current layer and the previous layer by measuring each overlay mark of the current layer and the overlay mark at the corresponding position of the previous layer by the measuring device during the overlay alignment operation.

[0101] In some embodiments, the system further includes an etching process device. The lithography process device includes a marking device and an exposure device, wherein: the marking device is configured to, during the execution of a first lithography process, set a first set of alignment marks in the middle of the side of the cell array region within each die of the pattern on the first photomask, where the first lithography process is a lithography process performed on the wafer of the previous layer in the alignment operation; the etching process device is configured to, after the completion of the first lithography process, transfer the first set of alignment marks to the previous layer wafer by performing an etching process; the marking device is further configured to, during the execution of a second lithography process, set a second set of alignment marks in the middle of the side of the cell array region within each die of the pattern on the second photomask, where the second lithography process is a lithography process performed on the wafer of the current layer in the alignment operation; the exposure device is configured to use the second photomask to transfer the second set of alignment marks on the photomask to the photoresist covered on the current layer wafer by exposing the second wafer; correspondingly, the measuring device is further configured to, when performing the alignment detection operation, determine the alignment deviation between the current layer and the previous layer by measuring the first set of alignment marks and the second set of alignment marks.

[0102] In some embodiments, the lithography process device further includes: a compensation device configured to perform deviation compensation on the photomask pattern of the current layer according to the alignment deviation between the current layer and the previous layer; correspondingly, the exposure device is further configured to expose the wafer of the current layer according to the compensated photomask pattern of the current layer.

[0103] In some embodiments, the system further includes: a monitoring device configured to, during the production process of each batch of products, monitor the process status of each batch of products in real time by obtaining in real time from the measuring device the alignment deviation between each layer of wafers and the wafers of the previous layer.

[0104] In some embodiments, the compensation device is further configured to perform alignment compensation control on the next batch of products by using a batch-to-batch compensation control method according to the alignment deviations between each layer of wafers and the wafers of the previous layer in each historical batch of products.

[0105] In some embodiments, the compensation device is further configured to: obtain the alignment deviations between each layer of wafers and the wafers of the previous layer in a specific number of batches of products with the most recent history; respectively determine the weights corresponding to the alignment deviations of each batch of products; perform weighted calculations on the alignment deviations of each batch of products respectively according to the corresponding weights to obtain the estimated alignment deviation of the next batch of products; perform pre-compensation for the alignment deviation of the next batch of products according to the estimated alignment deviation.

[0106] The description of the above device embodiments is similar to that of the above method embodiments and has similar beneficial effects to the method embodiments. For the technical details not disclosed in the device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0107] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of this application. Therefore, the "in one embodiment" or "in an embodiment" that appears throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of this application, the sequence numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this application. The sequence numbers of the embodiments of this application above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0108] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0109] In several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed with each other can be through some interfaces. The indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0110] The units described as separate components above may or may not be physically separated. The components shown as units may or may not be physical units; they can be located in one place or distributed to multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0111] In addition, in each embodiment of the present application, each functional unit can be entirely integrated into one processing unit, or each unit can be separately regarded as one unit, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware, or in the form of a combination of hardware and software functional units.

[0112] Those of ordinary skill in the art can understand that all or part of the steps to implement the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps including the above method embodiments. The foregoing storage medium includes various media that can store program codes, such as removable storage devices, read-only memory (ROM), magnetic disks, or optical discs.

[0113] Alternatively, if the above integrated unit of the present application is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present application, in essence, or the part that contributes to the related art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the various embodiments of the present application. The foregoing storage medium includes various media that can store program codes, such as removable storage devices, ROM, magnetic disks, or optical discs.

[0114] The above is only the implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, it includes a plurality of cell array regions, with a side line surrounding the cell array regions, and alignment marks are arranged along the side lines of each of the cell array regions; wherein, the semiconductor device includes die, and the die includes a plurality of the cell array regions; the plurality of alignment marks are arranged in the middle of the side lines of each cell array region; There are two adjacent side lines between two adjacent cell array regions; one of the two adjacent side lines is provided with the alignment mark.

2. The semiconductor device according to claim 1, characterized in that, one or more alignment marks are arranged on each side line of each cell array region.

3. A method for determining alignment deviation, characterized in that, the method includes: During the photolithography process for each layer of wafer, alignment marks are arranged along the side lines of each cell array region within each die on the reticle pattern; each die includes a plurality of the cell array regions; During the alignment operation, the alignment marks of the current layer are measured against the alignment marks of the previous layer by a measuring device to determine the alignment deviation between the current layer and the previous layer; wherein, arranging the alignment marks along the side lines of each cell array region includes: arranging the alignment marks in the middle of the side lines of each of the cell array regions; there are two adjacent side lines between two adjacent cell array regions; one of the two adjacent side lines is provided with the alignment mark.

4. The method according to claim 3, characterized in that, arranging the alignment marks along the side lines of each cell array region includes: arranging at least two of the alignment marks at different positions along each side line of the cell array region; Correspondingly, during the alignment operation, the alignment marks of each of the current layer are measured against the alignment marks at the corresponding positions of the previous layer by the measuring device to determine the alignment deviation between the current layer and the previous layer.

5. The method according to claim 4, characterized in that, during the photolithography process for each layer of wafer, arranging the alignment marks along the side lines of each cell array region within each die on the reticle pattern includes: During the execution of the first photolithography process, first alignment marks are arranged along the side lines of the cell array regions within each die on the pattern of the first reticle; wherein, the first photolithography process is the photolithography process for the previous layer of wafer in the alignment operation; After the first photolithography process is completed, the first alignment marks are transferred to the previous layer of wafer by performing an etching process; During the execution of the second photolithography process, second alignment marks are arranged along the side lines of the cell array regions within each die on the pattern of the second reticle; wherein, the second photolithography process is the photolithography process for the current layer of wafer in the alignment operation; Using the second reticle, the second alignment marks on the reticle are transferred to the photoresist covered on the current layer of wafer by exposing the current layer of wafer. Correspondingly, when performing the overlay alignment detection operation, the measurement device measures the first overlay mark and the second overlay mark to determine the overlay deviation between the current layer and the previous layer.

6. The method according to any one of claims 3 to 5, wherein, the method further includes: performing deviation compensation on the photomask pattern of the current layer according to the overlay deviation between the current layer and the previous layer; performing exposure on the wafer of the current layer according to the compensated photomask pattern of the current layer.

7. The method according to claim 6, wherein, the method further includes: during the production process of each batch of products, monitoring the process status of each batch of products by obtaining the overlay deviation between each layer of wafers and the previous layer of wafers.

8. The method according to claim 7, wherein, the method further includes: performing overlay compensation control on the next batch of products by using a batch-to-batch compensation control method according to the overlay deviations between each layer of wafers and the previous layer of wafers in each historical batch of products.

9. The method according to claim 8, wherein, performing overlay compensation control on the current batch of products by using a batch-to-batch compensation control method according to the overlay deviations between each layer of wafers and the previous layer of wafers in each historical batch of products includes: obtaining the overlay deviations between each layer of wafers and the previous layer of wafers in a specific number of the most recent historical batches of products; respectively determining the weights corresponding to the overlay deviations of each batch of products; for the overlay deviation of each batch of products, respectively performing weighted calculation according to the corresponding weights to obtain the estimated overlay deviation of the next batch of products; performing pre-compensation of the overlay deviation on the next batch of products according to the estimated overlay deviation.

10. An overlay deviation determination system, wherein, the system includes: a lithography process device for setting overlay marks along the edges of each unit array region within each die on the photomask pattern during the lithography process for each layer of wafers; each die includes a plurality of the unit array regions; a measurement device for determining the overlay deviation between the current layer and the previous layer by measuring the overlay mark of the current layer and the overlay mark of the previous layer of the current layer during the overlay alignment operation; wherein, the lithography process device is further used for setting overlay marks in the middle of the edges of each of the unit array regions; there are two adjacent edges between two adjacent unit array regions; one of the two adjacent edges is provided with the overlay mark.

11. The system according to claim 10, wherein, the lithography process device is further used for setting at least two of the overlay marks at different positions along each edge of the unit array region; correspondingly, the measurement device is further used for determining the overlay deviation between the current layer and the previous layer by measuring each of the overlay marks of the current layer and the overlay marks at the corresponding positions of the previous layer during the overlay alignment operation.

12. The system according to claim 11, wherein, The system further includes an etching process device. The lithography process device includes a marking device and an exposure device, wherein: The marking device is configured to, during the execution of a first lithography process, set a first set of alignment marks along the side edges of the cell array region within each die of the pattern on the first photomask; wherein, the first lithography process is a lithography process performed on the wafer of the previous layer in the alignment operation; The etching process device is configured to, after the first lithography process is completed, transfer the first set of alignment marks to the wafer of the previous layer by performing an etching process; The marking device is further configured to, during the execution of a second lithography process, set a second set of alignment marks along the side edges of the cell array region within each die of the pattern on the second photomask; wherein, the second lithography process is a lithography process performed on the wafer of the current layer in the alignment operation; The exposure device is configured to use the second photomask to transfer the second set of alignment marks on the photomask to the photoresist covered on the wafer of the current layer by exposing the wafer of the current layer; Correspondingly, the measuring device is further configured to, when performing the alignment detection operation, determine the alignment deviation between the current layer and the previous layer by measuring the first set of alignment marks and the second set of alignment marks; 13. The system according to claim 12, wherein, The lithography process device further includes: a compensation device configured to perform deviation compensation on the photomask pattern of the current layer according to the alignment deviation between the current layer and the previous layer; Correspondingly, the exposure device is further configured to expose the wafer of the current layer according to the compensated photomask pattern of the current layer; 14. The system according to claim 13, wherein, The system further includes: a monitoring device configured to monitor the process status of each batch of products by obtaining the alignment deviation between each layer of wafer and the previous layer of wafer from the measuring device during the production process of each batch of products; 15. The system according to claim 14, wherein, The compensation device is further configured to perform alignment compensation control on the next batch of products by using a batch-to-batch compensation control method according to the alignment deviations between each layer of wafer and the previous layer of wafer of each batch of products in history; The compensation device is further configured to: obtain the alignment deviations between each layer of wafer and the previous layer of wafer of a specific number of batches of products closest to the current in history; respectively determine the weights corresponding to the alignment deviations of each batch of products; for the alignment deviations of each batch of products, perform weighted calculation respectively according to the corresponding weights to obtain the estimated alignment deviation of the next batch of products; perform pre-compensation of the alignment deviation on the next batch of products according to the estimated alignment deviation.

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