Enhancing solid state power semiconductor device characteristics with new cell geometry

Abstract

A semiconductor device and a method of manufacturing the same are disclosed. The device includes a heavily doped first conductivity type substrate and a lightly doped first conductivity type epitaxial layer formed on the substrate. A buffer layer between the substrate and the epitaxial layer is doped the first conductivity type at a doping level between the substrate and the epitaxial layer. A cell includes a body region doped a second conductivity formed in the epitaxial layer. The second conductivity type is opposite the first conductivity type. The cell includes a source region doped the first conductivity type and formed in at least the body region. The device further includes a short region doped the second conductivity type formed in the epitaxial layer separated from the source region of the cell by the body region of the cell, wherein the short region is electrically coupled to the source region.

Description

Technical Field

[0001] This invention relates primarily to metal-oxide field-effect transistors (MOSFETs), and more specifically, to MOSFET cell geometry. Background Technology

[0002] In conventional MOSFET devices, each cell layout includes a source junction and a short circuit from the source junction to the body region near the source. This source-to-body short circuit prevents activation of the parasitic bipolar junction transistor (BJT), thus allowing reverse current flow between the drain and source and reducing the MOSFET's blocking voltage from the open-emitter breakdown voltage (BVCBO) to the open-base breakdown voltage (BVCEO). Conventional MOSFET devices therefore have relatively large cells because the area directly adjacent to the source region is occupied by a shorted region containing a short junction conductively coupled to the source. This shorted region facilitates contact between the source and body regions. Because the shorted region occupies space, the body region must be larger to accommodate the contact. Therefore, the reduction in cell spacing in conventional technology is limited.

[0003] Figure 9 This indicates the nature of the pitch limitation caused by the short-circuit region. For example... Figure 9 As shown, the prior art cell geometry has a body region 901, which includes a source region 904 and a P+-doped shorting region 902 within the source region 904. This increases the size of the source region 904 and the body region 901, because the source region 904 must be large enough to surround the shorting region 902, and the body region 901 must be large enough to surround the enlarged source region 904. The larger size of the body region 901 means a larger cell pitch 905, because each cell occupies more space on the device surface. A combination of channel region charge and carriers is formed at the contact boundary between the body region 901 and the epitaxial junction field-effect transistor (JFET) region 903 in the channel region to allow current to flow through the device. The increased channel area means a lower device "on" resistance. As the channel and JFET density increases, the cell pitch decreases, and the on resistance decreases. Prior to this invention, reducing the cell pitch 905 was limited because previous layouts placed the shorting region 902 next to the source region 904.

[0004] Furthermore, many existing technologies use a common contact metal for both the source and shorting terminals. However, the source and body regions have opposite conductivity types. For example, in an N-type device, the source region is N-doped and the body region is P-doped. The optimal contact metal for P-doped silicon carbide (SiC) differs from the optimal contact metal for N-doped silicon carbide (SiC). This means that a suboptimal contact metal is used for either the electrode or source terminals.

[0005] It is with respect to these and other general considerations that the various embodiments of the present application have been made. SUMMARY

[0006] A semiconductor device is disclosed comprising a heavily doped first conductivity type substrate, a lightly doped first conductivity type epitaxial layer formed on the substrate, a body region of a second conductivity type formed in the epitaxial layer, wherein the second conductivity type is opposite the first conductivity type, a source region of the first conductivity type formed in the body region, the device further comprising a short region of the second conductivity type formed in the epitaxial layer, the short region separated from the source region of the cell by the body region of the cell, wherein the short region is conductively coupled to the source region.

[0007] wherein the body region of the cell forms an ohmic contact with the short region.

[0008] wherein a junction field effect transistor (JFET) region of the epitaxial layer separates a portion of the short region from the body region of the cell, and a strip of the short region interrupts the JFET region, wherein the strip of the short region forms an ohmic contact with the body region of the cell.

[0009] wherein the strip of the short region is of sufficient width to allow current flow from the short region to the body region.

[0010] wherein there are more than one cell, wherein the short region is shared between two and more cells.

[0011] wherein each of the plurality of cells is separated by a JFET region, wherein the JFET region is of a width selected to have a sufficiently low on-resistance and a reduced electric field across the gate oxide.

[0012] wherein there is a buffer layer between the substrate and the epitaxial layer, wherein the buffer layer is doped the first conductivity type at a doping level between the doping level of the substrate and the doping level of the epitaxial layer.

[0013] wherein there is an insulating gate formed over the epitaxial layer and a portion of the body region.

[0014] wherein the source region is at the center of the polygonal body region.

[0015] wherein there is a source terminal coupled to the source region, a short terminal coupled to the short region, wherein the material of the source terminal is different from the material of the short terminal.

[0016] wherein the material of the source terminal is a metal, the material of the short terminal is a metal, and the metal of the source terminal is different from the metal of the short terminal.

[0017] wherein the semiconductor device is a silicon carbide (SiC) device.

[0018] A semiconductor device is also disclosed comprising a heavily doped first conductivity type substrate; a lightly doped first conductivity type epitaxial layer formed on the substrate; a body region of a second conductivity type formed in the epitaxial layer, wherein the second conductivity type is opposite the first conductivity type; a source region of the first conductivity type formed in the body region; a short region of the second conductivity type formed in the epitaxial layer, wherein the body region of the cell forms an ohmic contact with the short region, and wherein the short region is conductively coupled to the source region. The device further comprises a source contact coupled to the source region, and a short contact coupled to the short region, wherein the material of the source contact is different than the material of the short contact. BRIEF DESCRIPTION OF DRAWINGS

[0019] Other features and advantages of the present application will be apparent from the following detailed description, taken in conjunction with the accompanying drawings of which:

[0020] Figure 1 A plan view of an epitaxial layer of an improved semiconductor device cell geometry having a square body region and a shared short region, in accordance with various aspects of the present application.

[0021] Figure 2 A plan view of an epitaxial layer of an alternative improved semiconductor device cell geometry having a hexagonal body region and a short region, in accordance with various aspects of the present application.

[0022] Figure 3 A plan view of an epitaxial layer of another alternative improved semiconductor device cell geometry having an octagonal body region and a diamond shaped short region, in accordance with various aspects of the present application.

[0023] Figure 4 A plan view of an epitaxial layer of another embodiment of an alternative improved semiconductor device cell geometry having a body region at a corner of a hexagonal short region, in accordance with various aspects of the present application.

[0024] Figure 5 A plan view of an epitaxial layer of another alternative improved semiconductor device cell geometry having a hexagonal body region and a hexagonal short region with a strip interrupting the JFET region, in accordance with various aspects of the present application.

[0025] Figure 6 A plan view of an epitaxial layer of another alternative improved semiconductor device cell geometry having a square body region and a square short region with a short region strip interrupting the JFET region and ohmically contacting the body region, in accordance with various aspects of the present application.

[0026] Figure 7 A top view of an epitaxial layer of another embodiment of an improved semiconductor device cell geometry having octagonal regions and square or diamond shaped short regions ohmically contacted by strips of short regions interrupting the JFET region, in accordance with various aspects of the present application.

[0027] Figure 8A A cross-sectional side view of a partially formed semiconductor device having an improved cell geometry with an epitaxial layer on a substrate, in accordance with various aspects of the present application.

[0028] Figure 8B A cross-sectional side view of a partially formed semiconductor device having an improved cell geometry with a JFET region in an epitaxial layer lightly doped with ions of a first conductivity type and formed on a substrate heavily doped with ions of the first conductivity type, in accordance with various aspects of the present application.

[0029] Figure 8C A cross-sectional side view of a partially formed semiconductor device having an improved cell geometry with a short region, a termination region and a gate via region, in accordance with various aspects of the present application.

[0030] Figure 8D A cross-sectional side view of a partially formed semiconductor device 20 having an improved cell geometry with a body region in a JFET region of an epitaxial layer after formation of a short region and a gate via region, in accordance with various aspects of the present application.

[0031] Figure 8E A cross-sectional side view of a partially formed semiconductor device having an improved cell geometry with a shield region under a body region in a JFET region of an epitaxial layer, in accordance with various aspects of the present application.

[0032] Figure 8F A cross-sectional side view of a partially formed semiconductor device having an improved cell geometry with a heavily doped source region in a body region, in accordance with various aspects of the present application.

[0033] Figure 8G A cross-sectional side view of a partially formed semiconductor device having an improved cell geometry showing cap layer application and implant anneal, in accordance with various aspects of the present application.

[0034] Figure 8HA cross-sectional side view of a partially formed semiconductor device having improved cell geometry, an insulating layer on the surface of the semiconductor device over the termination region, shorting region, JFET region, body region, source region, and gate via region, in accordance with various aspects of the present application.

[0035] Figure 8I A cross-sectional side view of a partially formed semiconductor device having improved cell geometry, a gate layer on the surface of the insulating layer, in accordance with various aspects of the present application.

[0036] Figure 8J A cross-sectional side view of a partially formed semiconductor device having improved cell geometry, an additional insulating layer on top of the gate layer and insulating layer, in accordance with various aspects of the present application.

[0037] Figure 8K A cross-sectional side view of a partially formed semiconductor device having improved cell geometry, a shorting junction and source junction formed through the insulating layer of the substrate bottom and a drain junction, in accordance with various aspects of the present application.

[0038] Figure 8L A cross-sectional side view of a partially formed semiconductor device having improved cell geometry, a power metal coupled source junction and a shorting junction on an insulating layer, in accordance with various aspects of the present application.

[0039] Figure 8M A cross-sectional side view of a semiconductor device having improved cell geometry, a shorting region coupled to a body region, in accordance with various aspects of the present application.

[0040] Figure 9 A top view of an epitaxial layer of a conventional semiconductor device cell geometry. DETAILED DESCRIPTION

[0041] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown, by way of illustration, specific embodiments in which the application can be practiced. For the purposes of convenience and ease of reference, the use of + or - after designating a conductivity or net impurity carrier type (P or N) generally refers to the relative concentration of net impurity carriers of the designated type within a semiconductor material. Generally, N+ material has a higher concentration of N-type net dopants (e.g., electrons) than N material, and N material has a higher concentration of carriers than N- material. Similarly, P+ material has a higher concentration of P-type net dopants (e.g., holes) than P material, and P material has a higher concentration than P- material. Note that what is relevant is the net concentration of carriers, not necessarily the dopants. For example, a material can be heavily doped with N-type dopants, but if the material is also sufficiently counter-doped with P-type dopants, the material can still have a relatively low net carrier concentration. As used herein, dopant concentrations less than about 10 16 / cm 3 may be considered "lightly doped," while dopant concentrations greater than about 10 18 / cm 3 may be considered "heavily doped."

[0042] A semiconductor device having improved cell geometry can include a substrate of a first conductivity type that is heavily doped and an epitaxial layer of the first conductivity type that is lightly doped formed on the substrate. In some embodiments, a buffer layer having a doping concentration higher than the epitaxial layer can be utilized between the substrate and the epitaxial layer. A region of the epitaxial layer is divided into at least one cell. The cell includes a body region doped with a second conductivity type formed in the epitaxial layer and a source region doped with the first conductivity type formed at least in the body region. The second conductivity type is opposite the first conductivity type. An additional operational region of the device includes a short region doped with the second conductivity type formed in the epitaxial layer separated from the source region of the cell by the body region of the cell, where the short region is electrically coupled with the source region.

[0043] The improved semiconductor device can include the cell body region ohmic contact with the short region. A junction field effect transistor (JFET) region of the epitaxial layer can separate a portion of the short region from the body region of the cell, and a strip of the short region can interrupt the JFET region. In such an implementation, the strip of the short region is ohmic contact with the body region of the cell. The improved semiconductor device can include a plurality of cells, where the short region is shared between two or more cells. The width of the strip of the short region can be sufficient to allow current to flow from the short region to the body region.

[0044] Improved semiconductor devices can also include multiple cells, where the short region is shared between two or more cells. Each of the multiple cells can be separated by a JFET region, and the width of the JFET region can be selected so that the device will have sufficiently low on-resistance and reduced electric field across the gate oxide.

[0045] Improved semiconductor devices can include a gate formed on a portion of the epitaxial layer and the body regions. The gate can include an insulating layer formed on top of the epitaxial layer and a conductive layer formed on top of the insulating layer.

[0046] Improved semiconductor devices can also include a source contact coupled to the source region and a short contact coupled to the short region, where the material of the source contact is different than the material of the short contact. The material of the source contact can be a metal, and the material of the short contact can be a metal different than the metal of the source contact.

[0047] Figure 1 A top view of an epitaxial layer showing an embodiment of improved semiconductor device cell geometry with square body regions and shared source regions, in accordance with various aspects of the present application. In the embodiment shown, the body regions 102 have a square or rectangular shape. JFET regions 103 are formed in the epitaxial layer of the semiconductor device between the body regions 102. A source contact 104 is formed over a source region 107 within the body regions 102. The source contact 104, as shown, is square and centered over the source region 107 within the body regions 102. The source region 107 and the source contact 104 can be any shape and can be located anywhere within the body regions 102, as long as a portion of the body regions 102 separates the source region 107 from the short regions 101 or the short region contact 105. The short regions 101 are separate from the body regions 102 and allow for a reduction in size of the body regions 102 and a reduction in pitch of the body regions 102. The short regions 101 are located between the body regions 102.

[0048] The short regions 101 can be ohmically contacted to at least one body region, and in some embodiments can be contacted to up to two, three, four, five, six, or more body regions. As shown, the short regions 101 are shared between four body regions 102, and each body region 102 is in contact with multiple short regions 101. The short regions 101 ensure that the body regions 102 are at the source voltage, thereby preventing current from flowing in reverse through the parasitic BJT. The width of the JFET regions 103 between the body regions is selected to have sufficiently low on-resistance and reduced electric field across the gate oxide. In Figure 1 In the embodiment shown, the short regions 101 are arranged at the intersection between four body regions.

[0049] The JFET region 103 and the epitaxial layer can be of a first conductivity type, where the first conductivity type is opposite to the second conductivity type. The body region 102 and the short region 101 can be formed in selected portions of the epitaxial layer by doping with a suitable second conductivity type dopant. The source region 107 can be formed in selected portions of the body region 102 by doping with a suitable first conductivity type dopant. For example, the epitaxial layer, the source region 107, and the JFET region 103 can be doped with N-type dopants, for example by ion implantation, and the short region 101 and the body region 102 can be similarly doped with P-type dopants. Examples of N-type dopants include, but are not limited to, phosphorus, nitrogen, arsenic, antimony, bismuth, lithium, or any other material that provides free negative charge carriers (e.g., electrons) when incorporated into a semiconductor material (e.g., silicon). Examples of P-type dopants include, but are not limited to, boron, aluminum, gallium, indium, or any other material that provides positive charge carriers (e.g., holes) when incorporated into a semiconductor material (e.g., silicon).

[0050] Figure 2 FIG. 2A shows a top view of an epitaxial layer representing an alternative implementation of an improved semiconductor device cell geometry having a hexagonal body region 202 and a short region 201, according to various aspects of the present application. The body region 202 shares a side with the short region 201. A small short contact 205 is located in the middle of the short region 201. A short contact 204 is located within a source region 207. The source region 207 is located within the body region 202, and the body region 202 separates the short region 201 from the source region 207. Here, the body region 202 is arranged around the long sides of the short region 201. Wide JFET regions 203 at the body region corners are largely avoided, ensuring a short intersection geometry. The hexagonal body region 202 is designed to have the same JFET gap everywhere, including the corners, resulting in a stable breakdown voltage. However, the BV of hexagonal and square cells can be lower than linear and octagonal cells due to the higher degree of electrical crowding at the corners.

[0051] Figure 3 FIG. 3A shows a top view of an epitaxial layer representing another alternative embodiment of an improved semiconductor device cell geometry having an octagonal body region 302 and a diamond or octagonal short region 301, according to various aspects of the present application. The sides of the diamond or octagonal body region 302 are in ohmic contact with the sides of the short region 301. A short contact 305 is conductively coupled to the source, and thus to a source contact 304 and a source region 307. In the embodiment shown, the short region is arranged at the intersection between four body regions.

[0052] Figure 4Figure 4A shows a top view of an epitaxial layer of another embodiment of improved semiconductor device cell geometry having hexagonal body regions 402 and hexagonal short regions 401, according to aspects of the present application. In the example shown, the body regions 402 are shaped to create an overall hexagonal shape of the body regions 402 and the collection of short regions 401. For simplicity, Figure 4 In the example shown, the body regions 402 are shaped to create an overall hexagonal shape of the body regions 402 and the collection of short regions 401. For simplicity, Figure 1 Figure 4B shows a single functional cell having six body regions 402 in ohmic contact with short regions 401. However, the semiconductor device can have multiple functional cells of the type shown arranged adjacent to each other. As shown, a source contact 404 is located in each source region 407, and the source regions 407 and source contacts 404 are shaped to be irregular hexagons to accommodate the shape of the body regions 402 and the corners of the short regions 401. The short regions 401 have hexagonal short contacts 405. Figure 4

[0053] Figures 1-4 Figure 4C shows an embodiment in which the short regions are in direct ohmic contact with the body regions. This allows for reduced cell pitch by overcoming the cell size reduction limitations due to the geometry of the short contacts near the source contacts. Figures 5-7 Figure 4D shows another embodiment in which the strips of short regions interrupt the JFET region and form ohmic contact between the short regions and the body regions. In addition, the short regions that are contacted by the strips of short regions allow for greater JFET region and channel density, as the short regions require less space. This allows for better channel density and reduced "on" resistance.

[0054] Figures 5-7 Figure 5A shows a top view of an epitaxial layer of another embodiment of improved semiconductor device cell geometry having hexagonal body regions 502 and hexagonal short regions 501, according to aspects of the present application. In the example shown, the body regions 502 are shaped to create an overall hexagonal shape of the body regions 502 and the collection of short regions 501. For simplicity,

[0055] Figures 5-7 ​This is a top view of an epitaxial layer illustrating another implementation of an improved semiconductor device cell geometry according to various aspects of the invention. In this embodiment, the cell geometry is characterized by a square body region 602 and a square shorting region 601, which is ohmetically contacted to the body via a strip of shorting region 606 interrupting JFET region 603. Source region 607 is electrically coupled to shorting region 601 via shorting region 605 and source junction 604, which are connected to the source and serve to maintain the short contact at the source voltage to prevent activation of parasitic JFETs.

[0056] Figures 1-4 This is a top view of an epitaxial layer illustrating yet another embodiment of an improved semiconductor device cell geometry according to various aspects of the present invention. In this embodiment, the cell geometry is characterized by an octagonal region 702 and an octagonal or rhomboid shorting region 701, which makes ohmic contact with the body region via a strip of shorting region 706 that interrupts JFET region 703. Shorting region 701 makes ohmic contact with body region 702 via the strip of shorting region 706, and shorting region 706 bridges the shorting region through JFET region 703 and interrupts JFET region 703. Source region 707 is electrically coupled to shorting region 701 at shorting junction 705 via source junction 704.

[0057] and Figures 5-7 The example shown is similar. Figures 1-7 The width of the JFET region between the body regions is chosen to have sufficiently low on-resistance and a reduced electric field across the gate oxide. The width and other dimensions of the shorting region band forming an ohmic contact with the body region are selected to maximize the JFET region without compromising the ohmic contact between the shorting region and the body region or multiple regions. Figures 1-7 In the illustrated embodiment, the JFET region is doped with ions of a first conductivity type, and the body region is doped with ions of a second conductivity type. The source region is doped with the first conductivity type, and the shorting region (including the shorting junction) is doped with the second conductivity type. The source region and the shorting region may be electrically coupled through the source metal. Although Preparation method Various shapes of the body region and the shorting region are depicted, but other shapes of the body region and the shorting region to reduce intercellular spacing (not shown in the figure) are also envisioned, such as circular, oval, pentagonal, etc.

[0058] Figures 8A-8L

[0059] Figure 8A This describes a method for manufacturing a semiconductor device having an improved unit geometry according to various aspects of the present invention. Figure 8BA cross-sectional side view of a partially formed semiconductor device having a JFET region 803 lightly doped with ions of a first conductivity type in an epitaxial layer 802 formed on a substrate 801 heavily doped with ions of the first conductivity type, in accordance with various aspects of the present application is shown. The JFET region can be doped by implanting ions of the first conductivity type at a concentration greater than the epitaxial layer 802. Alternatively, the JFET region 803 can be the same concentration as the epitaxial layer 802. The JFET region 803 can be doped by any known method, such as ion implantation, gas phase doping, etc.

[0060] Figure 8C A cross-sectional side view of a partially formed semiconductor device having a JFET region 803 lightly doped with ions of a first conductivity type in an epitaxial layer 802 formed on a substrate 801 heavily doped with ions of the first conductivity type, in accordance with various aspects of the present application is shown. The JFET region can be doped by implanting ions of the first conductivity type at a concentration greater than the epitaxial layer 802. Alternatively, the JFET region 803 can be the same concentration as the epitaxial layer 802. The JFET region 803 can be doped by any known method, such as ion implantation, gas phase doping, etc.

[0061] Figure 8D A cross-sectional side view of a partially formed semiconductor device after forming a short region 805, a termination region 804, and a gate via region 806, in accordance with various aspects of the present application is shown. The short region 805 is formed in the JFET region 803. The gate via region 806 is formed in the epitaxial layer 802. If the epitaxial layer is N-type, both the short region 805 and the gate via region 806 are heavily doped with ions of a second conductivity type, such as p-type dopants. A termination region 804 of the second conductivity type having a concentration greater than the epitaxial layer 802 can also be formed in the epitaxial layer 802. The length of the doping, the concentration of the doping, and the depth of the doping are selected according to the breakdown voltage required for the device. The short region 805, the termination region 804, and the gate via region 806 can be created by ion implantation or any other known method, such as gas phase doping, etc. The short region 805 and the gate via region 806 can be doped to a concentration of about 10 19 cm -3 .

[0062] Figure 8EA cross-sectional side view of a partially formed semiconductor device according to various aspects of the present application is shown after forming body regions 807 in JFET region 803 of epitaxial layer 802 after forming short regions 805 and gate via regions 806. Body regions 807 can be doped a second conductivity type at a lower concentration than short regions 805 or gate via regions 806. Although one body region 807 is shown, as described above, a cell or functional unit can include multiple body regions ohmic contact with at least one short region. Body regions can be doped via ion implantation or any other known method (e.g., gas phase doping, etc.). Body regions 807 can be doped at a concentration of about 10 17 cm -3 Next, a shield region is created as shown. Figure 8E

[0063] Figure 8F A cross-sectional side view of a partially formed semiconductor device according to various aspects of the present application is shown after forming shield regions 808 below body regions 807 in JFET region 803 of epitaxial layer 802. Shield regions 808 can be formed by ion implantation of ions of a second conductivity type at a concentration greater than that of body regions 807. Shield regions 808 can be doped at a concentration of about 10 18 cm -3 + / - 5 X 10 17 cm -3 .

[0064] Figure 8G A cross-sectional side view of a partially formed semiconductor device according to various aspects of the present application is shown after forming heavily doped source regions 809 in body regions 807. Source regions 809 can be heavily doped with ions of a first conductivity type by ion implantation. After implanting source regions, the semiconductor device can undergo a thermal anneal step.

[0065] Figure 8H ​A cross-sectional side view of a partially formed semiconductor device after formation of a capping layer 810 and implant anneal is shown, in accordance with various aspects of the present application. The capping layer 809 prevents surface atom migration, Si desorption, and dopant diffusion out of the semiconductor, such as SiC. The capping layer can be grown on the surface of the semiconductor device, which can be composed of, for example, but not limited to, silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum nitride (AIN), or graphite [carbon (C)]. The capping layer can be formed by, for example, coating the wafer or sample with the capping material after applying a suitable photoresist and baking at temperatures and times optimized for the selected photoresist. After formation of the capping layer 810, the partially formed semiconductor device can be heated in an oven to a temperature sufficient to anneal the implanted ions. The activation anneal temperature varies by semiconductor type. For example, to activate the dopants (>95%), a high temperature post-implant anneal is required (>1600 °C for SiC), even though the implant was performed at a high temperature.

[0066] After the anneal process, the capping layer 810 is removed.

[0067] After the activation anneal, the sacrificial oxidation process can be completed.

[0068] A smooth surface roughness can improve device performance, such as ohmic contact. Therefore, the sacrificial oxidation process can be performed after ion implantation and dry etching, prior to formation of the insulating layer. The sacrificial oxidation can be accomplished by thermal (wet or dry) oxidation. The oxide layer is then removed by wet etching. The sacrificial oxidation and removal can be performed one or more times to ensure a lower surface roughness.

[0069] Figure 8I A cross-sectional side view of a partially formed semiconductor device after formation of an insulating layer 811 on the surface of the semiconductor device over the termination region 804, short region 805, JFET region 803, body region 807, source region 809, and gate via region 806, in accordance with various aspects of the present application, is shown. The insulating layer 810 can be an oxide, such as silicon oxide, grown on the surface of the semiconductor device by thermal oxidation or any other known oxide formation method. Next, as shown in Figure 8J the gate layer 812 is formed on the surface of the insulating layer 811. The gate layer can be composed of polysilicon or another conductive material and can be formed by deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like. The formation of the gate layer 812 can include additional steps such as gate layer doping, gate layer patterning, and gate layer etching. Additional contact material such as tungsten disilicide (WSi2) can also be formed on the gate layer to increase conductivity and signal speed. These additional steps can be necessary to form a gate with the appropriate dimensions and conductivity of the semiconductor device. After creating the gate layer 812, the gate is complete. Figure 8KA cross-sectional side view of the fabrication of a semiconductor device with improved cell geometry is shown after deposition of an additional insulating layer 813 over the gate layer 812 and insulating layer 811, in accordance with various aspects of the present application. The additional insulating layer 813 can be composed of silicon oxide, and can alternatively be grown on the surface by thermal oxidation. After formation of the additional dielectric layer, the insulating layer 811 and additional insulating layer 813 are densified. Figure 8L A cross-sectional side view of the fabrication of a semiconductor device is shown after formation of the shorting junction 815 and source junction 814 through the insulating layers 811, 813 and drain junction 821 at the bottom of the substrate 801, in accordance with various aspects of the present application. In some embodiments, a wafer backgrinding process can be performed to reduce the wafer thickness and produce a reduced on-resistance. In such embodiments, the drain junction 821 is the last step formed after backgrinding and laser annealing. After densification, holes are formed in the insulating layer 812 over the source region 809 and shorting region 805 using any suitable technique, such as plasma dry etching through openings in a contact mask. The contact mask can be removed by plasma ashing and cleaning with a removal solution or by any other known mask removal technique, such as but not limited to planarization or polishing. The shorting junction and source junction can then be formed in the holes in the insulating layers 811, 813. For example, but not limited to, a barrier layer of Ti / TiN can be formed to line the contact connection holes, and the remaining portion of the holes can then be filled with a contact metal to form conductive plugs on top of the barrier layer. The source junction 814 and shorting junction 815 can be composed of the same metal, such as nickel or the like. The contact metal of the shorting junction 815 can be different from the contact metal of the source junction 814. For example, the N-type junction in a SiC device can be nickel, while the P-type junction can be nickel, titanium, aluminum, cobalt, or combinations thereof. At the bottom of the substrate 801, the drain junction 821 can be formed by deposition. The semiconductor device can also be heated in an oven or rapid thermal anneal (RTA) chamber under different environments (e.g., N or Ar) to anneal the ohmic resistance junctions.

[0070] Figure 8M A cross-sectional side view of the formation of a semiconductor device with improved cell geometry is shown, in accordance with various aspects of the present application, with a power metal 816 coupling the source junction 814 and shorting junction 815 on the insulating layer 813. The metal can be disposed on the surface of the insulating layer 813 by deposition techniques such as physical vapor deposition (PVD), sputtering, or the like. The metal can then be patterned and selectively etched to form the final powder metal 816 on the upper surface of the insulating layer 813. Figures 5-7 A cross-sectional side view of a semiconductor device is shown, in accordance with various aspects of the present application, with the shorting region 820 coupled to the body region 807. The portion of the shorting region 820 in contact with the body region 807 can be as Figures 1-4A portion of the shorting region zone shown, or can be a portion of the main body region in the contact body region shown. Finally, a polyimide layer (not shown in the figures) can be formed on the surface of the insulating layer 813 to protect the insulating layer and complete the semiconductor device. The indefinite article "a" or "an" A portion of the shorting region zone shown, or can be a portion of the main body region in the contact body region shown. Finally, a polyimide layer (not shown in the figures) can be formed on the surface of the insulating layer 813 to protect the insulating layer and complete the semiconductor device.

[0071] According to various aspects of the present application, semiconductor devices with improved cell geometry allow for the use of different metals for the source and shorting contacts. This facilitates optimization of the contacts. Furthermore,

[0072] While the application has been described in detail with respect to certain preferred versions thereof, alternative, modified and equivalent versions thereof should become apparent to those skilled in the art. Accordingly, the scope of the present application should not be limited to the description of the above versions but should be given the full scope of the appended claims and any and all equivalents thereof. Any optional feature of the application, whether preferred or not, can be employed with any other optional feature or combination of features. In the claims, means-plus-function clauses, if any, are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Thus, although a form of ​ ​ indicates a quantity of one or more of the items in the following lists. The phrase "consisting essentially of shall not be construed to, unless otherwise indicated herein, extend to the corresponding "consisting of form of the claim. Any use of the term "including" or "containing" is not limiting and is understood immediately following the term to mean "comprising." Any use of the term "or" in the claims is considered 6, the phrase "means for" as used in the claims is not to be construed as limiting it to the means-plus-function aspects as set forth in 35 U.S.C. § 112,

Claims

1. A semiconductor device, comprising: A heavily doped substrate of the first conductivity type; A lightly doped epitaxial layer of the first conductivity type is formed on the substrate; A buffer layer located between a substrate and an epitaxial layer, the doping level of the buffer layer being between that of the substrate and the epitaxial layer, and being of a first conductivity type; A unit, the unit comprising, A bulk region doped with a second conductivity type is formed in the epitaxial layer, wherein the second conductivity type is opposite to the first conductivity type; A source region doped with a first conductivity type is formed at least in the bulk region; The device also includes: A short-circuit region of a second conductivity type is formed in the epitaxial layer, the short-circuit region being separated from the source region of the cell by the body region of the cell; An insulating layer is formed over the short-circuit region, the body region, and the source region; The shorting region is electrically coupled to the source region through a shorting connector electrically connected to the shorting region through the insulating layer, a source connector electrically connected to the source region through the insulating layer, and a power metal layer electrically connected between the shorting connector and the source connector, wherein the power metal layer is formed above the insulating layer.

2. The semiconductor device of claim 1, wherein the body region of the cell and the shorting region form an ohmic contact.

3. The semiconductor device of claim 2, wherein a junction field-effect transistor (JFET) region of the epitaxial layer separates a portion of the shorting region from the body region of the cell, and a strip of the shorting region interrupts the JFET region, wherein the strip of the shorting region forms an ohmic contact with the body region of the cell.

4. The semiconductor device of claim 3, wherein the strip width of the shorting region is sufficient to allow current to flow from the shorting region to the body region.

5. The semiconductor device of claim 1 or 3 further comprises one or more units, wherein the shorting region is shared between two or more units.

6. The semiconductor device of claim 5, wherein each of the plurality of cells is separated by a JFET region, wherein the width of the JFET region is selected to have sufficiently low on-resistance and reduced electric field across the gate oxide.

7. The semiconductor device of claim 1, comprising a gate formed over an epitaxial layer and a portion of a body region, the gate comprising an insulating layer formed on the epitaxial layer and a conductive layer formed on the insulating layer.

8. The semiconductor device of claim 1, wherein the source region is located at the center of the polygonal body region.

9. The semiconductor device of claim 1, wherein the material of the source terminal is different from the material of the shorting terminal.

10. The semiconductor device of claim 9, wherein the source terminal is made of metal, the shorting terminal is made of metal, and the metal of the source terminal is different from the metal of the shorting terminal.

11. The semiconductor device according to any one of claims 1-10, wherein the semiconductor device is a silicon carbide (SiC) device.

12. A semiconductor device, comprising: A heavily doped substrate of the first conductivity type; A lightly doped epitaxial layer of the first conductivity type is formed on the substrate; A buffer layer located between a substrate and an epitaxial layer, the doping level of the buffer layer being between that of the substrate and the epitaxial layer, and being of a first conductivity type; A unit, the unit comprising, A bulk region doped with a second conductivity type is formed in the epitaxial layer, wherein the second conductivity type is opposite to the first conductivity type; A source region doped with a first conductivity type is formed at least in the bulk region; The device also includes: A short-circuit region of a second conductivity type is formed in the epitaxial layer, wherein the body region of the cell forms an ohmic contact with the short-circuit region; The device also includes: A source connector coupled to the source region and a short connector coupled to the short region, wherein the material of the source connector is different from the material of the short connector; An insulating layer is formed over the short-circuit region, the body region, and the source region; The shorting region is electrically coupled to the source region through a shorting connector electrically connected to the shorting region through the insulating layer, a source connector electrically connected to the source region through the insulating layer, and a power metal layer electrically connected between the shorting connector and the source connector, wherein the power metal layer is formed above the insulating layer.

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