Bandwidth Equalization Method and Apparatus

Abstract

The present application provides a bandwidth balancing method and apparatus. The method includes: monitoring the access frequencies of multiple cache memories; determining a cold cache memory and a hot cache memory among the multiple cache memories; determining hot spot information in the hot cache memory, and recording first index information of the hot spot information and identification information of the cold cache memory in a target entry, where the target entry is an entry in a redirection data table. The present application greatly alleviates the problem of uneven request distribution, thereby improving the problem of serious imbalance in obtaining bandwidth and enhancing the performance of information acquisition.

Description

Technical Field

[0001] This application relates to the field of data communication, and in particular, to a bandwidth balancing method and apparatus. Background Art

[0002] To improve the efficiency of obtaining instructions, a cache (high-speed buffer memory) is usually set between the processor core and the main memory, and the instructions frequently obtained from the main memory are cached in the cache. Then, when the processor core obtains the instruction to be obtained, it first determines whether the instruction to be obtained exists in the cache by a matching method. If so, the instruction to be obtained is obtained from the cache. If not, the instruction to be obtained is obtained from the main memory.

[0003] With the vigorous development of 5G technology, the requirements for the bandwidth and latency of obtaining instructions are getting higher and higher, and the processor core is also developing in the direction of multi-core parallel computing. The original single cache is increasingly difficult to meet the requirements of instruction acquisition. To solve the above problems, multiple caches are usually used to solve the bandwidth and latency problems of obtaining instructions.

[0004] However, in the solution using multiple caches, the mapping relationship between the storage blocks in the main memory and the multiple caches is determined by the physical address of the storage block in the main memory. In this way, when storing the instructions in the storage block in the main memory in multiple caches, it is necessary to determine the cache for storing the instruction according to the physical address of the storage block storing the instruction. Since the physical address of the instruction is the physical address of the storage block storing the instruction, it can be understood that the deployment method of the instructions stored in the main memory in multiple caches is only determined by the physical address of the instruction. Based on this, when executing the request for obtaining the instruction to be obtained, if the physical addresses of the instructions to be obtained mostly point to the same cache, there will be a problem of uneven request distribution, which will further lead to serious imbalance of the instruction acquisition bandwidth and degradation of the instruction acquisition performance. Summary of the Invention

[0005] This application provides a bandwidth balancing method and apparatus, which are used to solve the problems of uneven request distribution, serious imbalance of the instruction acquisition bandwidth, and degradation of the instruction acquisition performance caused by the fact that the deployment method of the instructions in the main memory in multiple caches is only determined by the physical address of the instructions in the main memory.

[0006] In a first aspect, a bandwidth balancing method is provided, including: monitoring the access frequencies of multiple high-speed buffer memories; determining a cold-point high-speed buffer memory and a hot-point high-speed buffer memory among the multiple high-speed buffer memories; determining hot-point information in the hot-point high-speed buffer memory; and recording the first index information of the hot-point information and the identification information of the cold-point high-speed buffer memory in a target entry, where the target entry is an entry in a redirection data table.

[0007] By monitoring the access frequencies of multiple caches, determining cold caches and hot caches among the multiple caches, and recording the first index information of the hot information in the hot cache and the IDs of the cold caches in the target entry of the redirection data table, that is, redirecting the hot information in the cache with a high access frequency to the cache with a low access frequency, the deployment method of information in multiple caches is changed, and the deployment method of information in multiple caches is related to the access frequency of each cache. In this way, when obtaining information according to a request, the problem of uneven request distribution can be greatly alleviated, thereby improving the problem of serious imbalance in the acquisition bandwidth and enhancing the performance of information acquisition. In addition, since the distribution of information in multiple caches is related to the access frequency of each cache, the estimation of information acquisition performance can be realized. Moreover, only based on the access frequency of each cache, the redirection of hot information can be achieved, and the steps are simple and easy to implement.

[0008] In a possible implementation manner, the monitoring of the access frequencies of multiple caches includes: in response to a frequency monitoring instruction, monitoring the access frequencies of the multiple caches in each monitoring period based on a monitoring period.

[0009] In a possible implementation manner, the determination of cold caches and hot caches among the multiple caches includes: according to the access frequency of each cache, determining the cache with the maximum access frequency as the hot cache and the cache with the minimum access frequency as the cold cache; or according to the access frequency of each cache, determining the caches with an access frequency greater than a first preset frequency as the hot caches and the caches with an access frequency less than a second preset frequency as the cold caches, where the first preset frequency is greater than the second preset frequency.

[0010] In a possible implementation manner, the determination of hot information in the hot cache includes: determining whether the access frequency of the hot cache reaches the frequency configured in the register and whether the difference between the access frequency of the hot cache and the access frequency of the cold cache is greater than a configured value; if so, determining hot information in the hot cache.

[0011] By determining whether the access frequency of the hot cache reaches the frequency configured in the register and whether the difference between the access frequency of the hot cache and the access frequency of the cold cache is greater than the configured value, and when this condition is met, determining hot instructions in the hot cache, so as to record the first index information of the hot instructions and the identification information of the cold cache in the target entry, thereby realizing the redirection of the hot instructions. In other words, a limiting condition is provided for starting the redirection process, and only when this limiting condition is met can the redirection process be started, improving the accuracy of starting the redirection process.

[0012] In a possible implementation manner, determining hot information in the hot cache includes: determining whether the access frequency of the hot cache is greater than n times the access frequency of the cold cache; if so, determining hot information in the hot cache.

[0013] By determining whether the access frequency of the hot cache is greater than n times the access frequency of the cold cache, and when this condition is met, determining hot instructions in the hot cache, so as to record the first index information of the hot instructions and the identification information of the cold cache in the target entry, thereby realizing the redirection of the hot instructions. In other words, a limiting condition is provided for starting the redirection process, and only when this limiting condition is met can the redirection process be started, improving the accuracy of starting the redirection process.

[0014] In a possible implementation manner, determining hot information in the hot cache includes: monitoring the access frequency of each cache line in the hot cache; determining a hot cache line in the hot cache according to the access frequency of each cache line; and determining the information stored in the hot cache line as hot information.

[0015] In a possible implementation manner, the redirection data table includes multiple entries, and each entry includes a first identifier and a second identifier. The first identifier is a valid flag or an invalid flag, and the second identifier is a hot flag or a non-hot flag.

[0016] In a possible implementation, recording the first index information of the hotspot information and the identification information of the cold cache memory in the target entry includes: determining candidate entries from the multiple entries according to the first identification and the second identification of each entry in the multiple entries, where the candidate entries include the entries in the multiple entries with the first identification being an invalid flag and the entries with the second identification being a non-hotspot flag; determining a target entry from the candidate entries; and recording the first index information of the hotspot information and the identification information of the cold cache memory in the target entry.

[0017] In a possible implementation, after recording the first index information of the hotspot information and the identification information of the cold cache memory in the target entry, it further includes: setting the second identification in the target entry to a hotspot flag, and setting the first identification in the target entry to a valid flag.

[0018] In a possible implementation, the method further includes: monitoring the access frequency of each entry in the redirection data table; determining whether the access frequency of a first entry is less than a third preset frequency, where the first entry is the entry with the second identification being the hotspot flag; modifying the second identification of the first entry with the access frequency less than the third preset frequency to a non-hotspot flag; determining whether the access frequency of a second entry is greater than a fourth preset frequency, where the second entry is the entry with the second identification being the non-hotspot flag; modifying the second identification of the second entry with the access frequency greater than the fourth preset frequency to a hotspot flag; where the fourth preset frequency is greater than the third preset frequency.

[0019] By monitoring the access frequency of each entry in the redirection data table and according to the comparison result between the access frequency of the entry and the third preset frequency or the fourth preset frequency, it is determined whether to change the state of the second identification in the entry, that is, to determine whether to change the cold / hot state of the instruction corresponding to the first index information in the entry, so as to realize the real-time monitoring and update of the cold / hot state of the instruction corresponding to the first index information of each entry in the redirection data table, and ensure the timeliness and accuracy of the information in the redirection data table.

[0020] In a possible implementation, the method further includes: filling the hotspot information into the cold buffer line in the cold cache memory.

[0021] In a possible implementation, the method further includes: determining any buffer line in the cold cache as the cold buffer line; or determining buffer lines in the cold cache with an access frequency less than a fifth preset frequency as cold buffer lines; or determining the buffer line with the lowest access frequency in the cold cache as the cold buffer line.

[0022] In a possible implementation, the method further includes: reading a first request, where the first request is a request for obtaining information to be obtained, and the first request carries second index information, where the second index information is index information for obtaining the information to be obtained; determining first index information of the information to be obtained according to the second index information; matching the first index information of the information to be obtained with the first index information in each entry in the redirection data table; if the first index information in an entry matches the first index information of the information to be obtained, determining the cache corresponding to the cache identifier information in the entry that matches the first index information of the information to be obtained as the first target cache; and sending the second index information to the first target cache, so that the first target cache obtains the information to be obtained according to the second index information.

[0023] By determining the first index information of the information to be obtained according to the second index information, matching the first index information of the information to be obtained with the first index information in each entry in the redirection data table, and when there is a matching entry, determining the cache corresponding to the cache identifier information in the matching entry as the first target cache, and sending the second index information to the first target cache, so that the first target cache obtains the information to be obtained according to the second index information, the shunting of the first request is realized based on the redirection data table, greatly alleviating the problem of uneven request distribution, thereby improving the problem of serious imbalance in request acquisition bandwidth and enhancing the information acquisition performance.

[0024] In a possible implementation, the method further includes: if the first index information in each entry does not match the first index information of the information to be obtained, determining the first target cache according to the second index information and the mapping rule; and sending the second index information to the first target cache, so that the first target cache obtains the information to be obtained according to the second index information.

[0025] In a possible implementation, the method further includes: receiving third index information sent by a first target cache memory, where the third index information is calculated from the second index information and a storage interval, and the third index information is generated by the first target cache memory when it determines that the acquisition of the information to be acquired is not completed according to the end identifier in the information to be acquired; determining first index information of the information to be acquired according to the third index information; matching the first index information of the information to be acquired with the first index information in each entry in a redirection data table; if the first index information in an entry matches the first index information of the information to be acquired, determining the cache memory corresponding to the identifier information of the cache memory in the entry that matches the first index information of the information to be acquired as a second target cache memory; and sending the third index information to the second target cache memory, so that the second target cache memory acquires the information to be acquired according to the third index information.

[0026] In a possible implementation, the method further includes: if the first index information in each entry does not match the first index information of the information to be acquired, determining a second target cache memory according to the third index information and a mapping rule; and sending the third index information to the second target cache memory, so that the second target cache memory acquires the information to be acquired according to the third index information.

[0027] In a second aspect, a bandwidth balancing device is provided, including: a first monitoring module, configured to monitor the access frequencies of multiple cache memories; a first determining module, configured to determine a cold cache memory and a hot cache memory among the multiple cache memories; a second determining module, configured to determine hot information in the hot cache memory; and a recording module, configured to record the first index information of the hot information and the identifier information of the cold cache memory in a target entry, where the target entry is an entry in a redirection data table.

[0028] In a possible implementation, the first monitoring module is specifically configured to, in response to a frequency monitoring instruction, monitor the access frequencies of the multiple cache memories in each monitoring period based on a monitoring period.

[0029] In a possible implementation manner, the first determination module is specifically configured to determine, according to the access frequency of each of the cache memories, the cache memory with the maximum access frequency as the hot cache memory, and the cache memory with the minimum access frequency as the cold cache memory; or determine, according to the access frequency of each of the cache memories, the cache memories with access frequencies greater than a first preset frequency as the hot cache memories, and the cache memories with access frequencies less than a second preset frequency as the cold cache memories, where the first preset frequency is greater than the second preset frequency.

[0030] In a possible implementation manner, the second determination module is specifically configured to determine whether the access frequency of the hot cache memory reaches the frequency configured in the register and whether the difference between the access frequency of the hot cache memory and the access frequency of the cold cache memory is greater than a configured value; if so, determine hot spot information in the hot cache memory.

[0031] In a possible implementation manner, the second determination module is specifically configured to determine whether the access frequency of the hot cache memory is greater than n times the access frequency of the cold cache memory; if so, determine hot spot information in the hot cache memory.

[0032] In a possible implementation manner, the second determination module is specifically configured to monitor the access frequency of each buffer line in the hot cache memory; determine a hot buffer line in the hot cache memory according to the access frequency of each buffer line; and determine the information stored in the hot buffer line as the hot spot information.

[0033] In a possible implementation manner, the redirection data table includes a plurality of entries, and each entry includes a first identifier and a second identifier. The first identifier is a valid flag or an invalid flag, and the second identifier is a hot spot flag or a non-hot spot flag.

[0034] In a possible implementation manner, the recording module is specifically configured to determine a candidate entry from the plurality of entries according to the first identifier and the second identifier of each entry in the plurality of entries, where the candidate entry includes the entries in the plurality of entries with the first identifier being an invalid flag and the entries with the second identifier being a non-hot spot flag; determine a target entry from the candidate entries; and record the first index information of the hot spot information and the identifier information of the cold cache memory in the target entry.

[0035] In a possible implementation, it further includes: a setting module, configured to set the second identifier in the target entry as a hot spot mark, and set the first identifier in the target entry as a valid mark.

[0036] In a possible implementation, it further includes: a second monitoring module, configured to monitor the access frequency of each entry in the redirection data table; a first determination module, configured to determine whether the access frequency of a first entry is less than a third preset frequency, where the first entry is an entry with the second identifier being the hot spot mark; a first modification module, configured to modify the second identifier of the first entry with the access frequency less than the third preset frequency to a non-hot spot mark; a second determination module, configured to determine whether the access frequency of a second entry is greater than a fourth preset frequency, where the second entry is an entry with the second identifier being the non-hot spot mark; a second modification module, configured to modify the second identifier of the second entry with the access frequency greater than the fourth preset frequency to a hot spot mark; where the fourth preset frequency is greater than the third preset frequency.

[0037] In a possible implementation, it further includes: a filling module, configured to fill the hot spot information into a cold spot buffer line in the cold spot cache memory.

[0038] In a possible implementation, it further includes: a third determination module, configured to determine any buffer line in the cold spot cache memory as the cold spot buffer line; or determine a buffer line with an access frequency less than a fifth preset frequency in the cold spot cache memory as the cold spot buffer line; or determine the buffer line with the minimum access frequency in the cold spot cache memory as the cold spot buffer line.

[0039] In a possible implementation, it further includes: a reading module, configured to read a first request, where the first request is a request for obtaining information to be obtained, and the first request carries second index information, where the second index information is index information for obtaining the information to be obtained; a fourth determination module, configured to determine first index information of the information to be obtained according to the second index information; a first matching module, configured to match the first index information of the information to be obtained with the first index information in each entry in the redirection data table; a fifth determination module, configured to, if the first index information in an entry matches the first index information of the information to be obtained, determine the cache memory corresponding to the cache memory identifier information in the entry that matches the first index information of the information to be obtained as a first target cache memory; a first sending module, configured to send the second index information to the first target cache memory, so that the first target cache memory obtains the information to be obtained according to the second index information.

[0040] In a possible implementation, it further includes: a sixth determination module, configured to, if the first index information in each of the table entries does not match the first index information of the information to be acquired, determine a first target cache memory according to the second index information and the mapping rule; a second sending module, configured to send the second index information to the first target cache memory, so that the first target cache memory acquires the information to be acquired according to the second index information.

[0041] In a possible implementation, it further includes: a receiving module, configured to receive third index information sent by a first target cache memory, where the third index information is calculated from the second index information and a storage interval, and the third index information is generated by the first target cache memory when it determines that the acquisition of the information to be acquired is not completed according to an end flag in the information to be acquired; a seventh determination module, configured to determine the first index information of the information to be acquired according to the third index information; a second matching module, configured to match the first index information of the information to be acquired with the first index information in each table entry in a redirect data table; an eighth determination module, configured to, if the first index information in a table entry matches the first index information of the information to be acquired, determine the cache memory corresponding to the identification information of the cache memory in the table entry that matches the first index information of the information to be acquired as a second target cache memory; a third sending module, configured to send the third index information to the second target cache memory, so that the second target cache memory acquires the information to be acquired according to the third index information.

[0042] In a possible implementation, it further includes: a ninth determination module, configured to, if the first index information in each of the table entries does not match the first index information of the information to be acquired, determine a second target cache memory according to the third index information and the mapping rule; a fourth sending module, configured to send the third index information to the second target cache memory, so that the second target cache memory acquires the information to be acquired according to the third index information.

[0043] In a third aspect, a computer-readable storage medium is provided, including a computer program, where when the computer program is executed on a computer, the computer is enabled to execute the method according to any one of the first aspect.

[0044] In a fourth aspect, a computer program is provided, which is used to execute the method according to any one of the first aspect when the computer program is executed by a computer.

[0045] In a fifth aspect, a chip is provided, including a processor and a memory. The memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute the method described in any one of the first aspects. Description of the Drawings

[0046] Figure 1 Schematic diagram of the application scenario of the bandwidth balancing method provided by the embodiment of the present application;

[0047] Figure 2 Schematic diagram of the process of the bandwidth balancing method provided by the embodiment of the present application;

[0048] Figure 3 Schematic diagram of the process of recording the first index of the hot instruction and the ID of the cold cache in the target entry provided by the embodiment of the present application;

[0049] Figure 4 The first part of the schematic diagram of the process of an information acquisition method provided by the embodiment of the present application;

[0050] Figure 5 The second part of the schematic diagram of the process of an information acquisition method provided by the embodiment of the present application;

[0051] Figure 6 The third part of the schematic diagram of the process of an information acquisition method provided by the embodiment of the present application;

[0052] Figure 7 The fourth part of the schematic diagram of the process of an information acquisition method provided by the embodiment of the present application;

[0053] Figure 8 Schematic diagram of the application scenario including multiple caches provided by the embodiment of the present application;

[0054] Figure 9 Schematic diagram of the structure of the Slice cache provided by the embodiment of the present application;

[0055] Figure 10 The first part of the schematic diagram of the process of another information acquisition method provided by the embodiment of the present application;

[0056] Figure 11 The second part of the schematic diagram of the process of another information acquisition method provided by the embodiment of the present application;

[0057] Figure 12 The third part of the schematic diagram of the process of another information acquisition method provided by the embodiment of the present application;

[0058] Figure 13 Schematic diagram of the structure of a bandwidth balancing device provided by the embodiment of the present application. Detailed implementation manners

[0059] The technical solutions in the present application will be described below with reference to the accompanying drawings.

[0060] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings in the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0061] The terms "first", "second", etc. in the description, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that comprises a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0062] It should be understood that in the present application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B may be singular or plural. The character " / " generally means that the associated objects before and after are in an "or" relationship. "At least one (one) of the following" or similar expressions refer to any combination of these items, including any combination of single item (one) or plural items (ones). For example, at least one (one) of a, b or c may mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c may be single or multiple.

[0063] Figure 1 is a schematic diagram of the application scenario of the bandwidth balancing method provided for the embodiments of the present application. As Figure 1 shown, the application scenario may include: a plurality of caches (high-speed buffer memories), a plurality of processor cores, a main memory (not shown in the figure), a redirection module, a redirection data table, and a crossbar. Among them:

[0064] The main memory includes multiple memory blocks, each memory block is composed of a certain number of memory cells, and each memory module is used to store information. The main memory can be a data main memory, that is, the information stored in the main memory is data, or it can be an instruction main memory, that is, the information stored in the main memory is an instruction. This application does not make special limitations on this.

[0065] Next, taking the main memory as an instruction main memory as an example, the principle of each module in this application scenario will be described.

[0066] The way to store the instruction to be stored in the main memory can be: judge whether the size of the instruction to be stored is greater than the capacity of the memory block in the main memory. If the size of the instruction to be stored is equal to or less than the storage capacity of the memory block, then store the instruction to be stored as a whole in a memory block; if the size of the instruction to be stored is greater than the storage capacity of the memory block, then divide the instruction to be stored into multiple instruction segments according to the size of the instruction to be stored and the storage capacity of the memory block, and then store the divided multiple instruction segments in multiple memory blocks.

[0067] In addition, an End Indicator (EI) can also be set for the instruction stored in the memory block. When the EI flag is 0, it indicates that the instruction stored in the memory block is one instruction segment of the corresponding instruction to be stored and is not the last instruction segment of the instruction to be stored. If the EI flag is 1, it indicates that the instruction stored in the memory block is the last instruction segment of the corresponding instruction to be stored, or it indicates that the instruction stored in the memory block is the corresponding instruction to be stored. Based on this, if the size of the instruction to be stored is equal to or less than the storage capacity of the memory block, then store the instruction to be stored as a whole in a memory block, and set the EI flag of the instruction (i.e., the instruction to be stored) in this memory block to 1. If the size of the instruction to be stored is greater than the storage capacity of the memory block, then divide the instruction to be stored into multiple instruction segments according to the size of the instruction to be stored and the capacity of the memory block, and then store the multiple instruction segments in multiple memory blocks, where the number of multiple instruction segments is the same as the number of multiple memory blocks, and one instruction segment corresponds to one memory block. Finally, set the EI flag for the instruction stored in each memory block. If the instruction stored in the memory block is not the last instruction segment of the instruction to be stored, then set the EI flag of the instruction stored in the memory block to 0. If the instruction stored in the memory block is the last instruction segment of the instruction to be stored, then set the EI flag of the instruction stored in this memory block to 1. In this way, when storing the instruction to be stored, by setting the EI flag of the instruction stored in each memory block, it is possible to judge whether the instruction stored in the memory block is an instruction segment of the instruction to be stored or the instruction to be stored through the EI flag of the instruction stored in the memory block. The detailed process will be described in the part of obtaining information below and will not be elaborated here.

[0068] Each cache includes multiple cache lines, and each cache line is composed of multiple storage units. Each cache line is used to store instructions in a storage block in the main memory, and the storage capacity of each cache line is the same as that of each storage block in the main memory. It should be noted that the cache here can be, for example, a Slice cache (shard-based cache memory), etc., and the present application does not make special limitations on this.

[0069] The mapping rules between the storage blocks in the main memory and multiple caches include the mapping relationship between the storage blocks in the main memory and multiple caches and the mapping relationship between the storage blocks in the main memory and the buffer lines in the cache. Among them, the mapping relationship between the storage blocks in the main memory and multiple caches can be set according to specific application scenarios, and the present application does not make special limitations on this. The mapping relationship between the storage blocks in the main memory and the buffer lines in the cache can be, for example, any one of set associative, fully associative, direct mapping, etc., and the present application does not make special limitations on this.

[0070] Through the above mapping rules, the instructions stored in the storage blocks in the main memory can be cached in the cache. Specifically, the cache corresponding to the storage block and the corresponding buffer line in the corresponding cache can be determined according to the mapping rules, and then the instructions stored in the storage block are buffered in the corresponding buffer line in the corresponding cache.

[0071] The redirection module is used to monitor the access frequency of each cache in multiple caches, and adjust the storage location of hot instructions in multiple caches according to the access frequency of each cache, so as to balance the access frequency of each cache, achieve balanced distribution of requests, balance the acquisition bandwidth, and improve the performance of information acquisition.

[0072] The redirection data table is used to record the adjustment records of the redirection module for hot instructions. It should be noted that the redirection module and the redirection data table will be described in detail below, so they will not be elaborated here.

[0073] It should be noted that when the main memory is a data main memory, the working principle of each module in this application scenario is the same as that when the main memory is an instruction main memory, so it will not be elaborated here.

[0074] It should be noted that the above application scenarios are only exemplary and are not used to limit the present application.

[0075] Figure 2 It is a schematic flowchart of the bandwidth balancing method provided by the embodiment of the present application. The execution subject of this method can be, for example, the redirection module in the above application scenario, etc., which can execute Figure 2An apparatus or chip, etc., of the method shown herein. Herein, the main memory will be used as the instruction main memory, that is, the information stored in the main memory is used as an example to illustrate the present application. As Figure 2 shown, the method includes the following steps:

[0076] Step 201, monitor the access frequencies of multiple caches.

[0077] In the embodiments of the present application, the monitoring methods may include the following two types, where:

[0078] First, periodically monitor the access frequency of each cache among multiple caches within a monitoring period. Specifically, multiple monitoring times can be set. At the start of each monitoring time, monitor the access frequency of each cache within the monitoring period. The multiple monitoring times and the monitoring period can be set according to specific application scenarios, and no special limitation is made here. For example, the monitoring period can be 0.01 ms.

[0079] Second, in response to a frequency monitoring instruction, monitor the access frequencies of multiple caches within each monitoring period based on a monitoring period. Specifically, when it is necessary to monitor the access frequency of each cache among multiple caches, a frequency monitoring instruction can be sent to the execution entity (such as a redirection module) of this method, that is, enable the execution entity of this method, so that the execution entity of this method receives and responds to the frequency monitoring instruction, immediately starts timing and counting the number of accesses. When the timing reaches the monitoring period, record the counted number of accesses and calculate the access frequency.

[0080] In the above two methods, the way to obtain the access frequency of each cache within the monitoring period is as follows: First, the number of accesses of each cache within the monitoring period can be obtained through a counter. Then, the ratio of the number of accesses of each cache within the monitoring period to the duration of the monitoring period is determined as the access frequency of the corresponding cache. It should be noted that in the above method, the monitoring period of each cache is the same, and the number of accesses of each cache within the monitoring period is positively correlated with the access frequency. Therefore, the number of accesses of each cache within the monitoring period can also be directly determined as the access frequency of the corresponding cache within the monitoring period. This can reduce the calculation amount while ensuring data accuracy, improve the calculation efficiency, and save the calculation cost.

[0081] Through the way of periodic monitoring or timed monitoring, the dynamic monitoring of the access frequency of each cache is realized.

[0082] It should be noted that the above methods for monitoring the access frequencies of each cache among multiple caches are only exemplary and are not used to limit the present invention.

[0083] Step 202: Determine the cold cache and the hot cache among multiple caches.

[0084] In the embodiments of the present application, the cold cache and the hot cache can be determined in the following two ways, where:

[0085] Way 1: According to the access frequency of each cache, determine the cache with the maximum access frequency as the hot cache, and determine the cache with the minimum access frequency as the cold cache. Specifically, each cache can be sorted in descending order of access frequency, the cache ranked first is determined as the hot cache, and the cache ranked last is determined as the cold cache.

[0086] Way 2: According to the access frequency of each cache, determine the cache with an access frequency greater than the first preset frequency as the hot cache, and determine the cache with an access frequency less than the second preset frequency as the cold cache, where the first preset frequency is greater than the second preset frequency. It should be noted that the first preset frequency and the second preset frequency can be set according to the statistical results of historical data.

[0087] It should be noted that the above two ways are only exemplary and are not used to limit the present invention. For example, multiple caches can also be sorted in descending order of access frequency, and the caches ranked in the top X are determined as the hot caches, and the caches ranked in the last M are determined as the cold caches. Among them, the values of X and M can be the same or different. Other various methods can also be used to select the hot cache and the cold cache from multiple caches.

[0088] Step 203: Determine the hot instructions in the hot cache.

[0089] In the embodiments of the present application, if the main memory is an instruction main memory, the hot information is the hot instruction; if the main memory is a data main memory, the hot information is the hot data. Since this is an example with the main memory being an instruction main memory, the hot information here is the hot instruction.

[0090] For step 203, first, monitor the access frequency of each cache line in the hot cache, then, according to the access frequency of each cache line, determine the hot cache line in the hot cache, and finally, determine the instruction stored in the hot cache line as the hot instruction.

[0091] Specifically, the principle of monitoring the access frequency of each cache line in the hot cache is as follows:

[0092] Obtain the access count of each cache line in the hot cache through a counter within the same time interval. Then, determine the access frequency of the corresponding cache line as the ratio of the access count of each cache line within the same time interval to that same time interval. It should be noted that since each cache line corresponds to the same time interval, and there is a positive correlation between the access count of each cache line within the same time interval and the access frequency, therefore, the access count of each cache line within the same time interval can also be directly determined as the access frequency of the corresponding cache line within the same time interval. This reduces the computational amount while ensuring data accuracy, improves the computational efficiency, and saves the computational cost.

[0093] According to the access frequency of each cache line in the hot cache, the way to determine the hot cache line in the hot cache can be, for example: sort the cache lines in the hot cache in descending order of access frequency according to the access frequency of each cache line, and determine the cache line ranked first as the hot cache line; or compare the access frequency of each cache line with a set value, and determine the cache line with an access frequency greater than the set value as the hot cache line. It should be noted that the above methods are only exemplary and are not used to limit the present invention.

[0094] It should be noted that when there are multiple hot caches, the hot cache lines in each hot cache can be determined according to the above principle, and then the hot instructions corresponding to each cache line can be determined according to each hot cache line.

[0095] Step 204: Record the first index information of the hot instruction and the identification information (id) of the cold cache in the target entry, where the target entry is an entry in the redirection data table.

[0096] In the embodiments of the present application, the first index information of the hot instruction can be determined according to the mapping rules between the storage blocks in the main memory and multiple caches.

[0097] Next, the structure of the redirection data table will be described.

[0098] The redirected data table includes multiple entries. Each entry may include a first identifier and a second identifier. Among them, the first identifier is a valid flag or an invalid flag, that is, there are two choices for the value of the first identifier, and these two choices are a valid flag and an invalid flag. If the first identifier in the entry is a valid flag, there is valid information in the entry. If the first identifier in the entry is an invalid flag, there is no valid information in the entry; the second identifier is a hot flag or a non - hot flag, that is, there are two choices for the value of the second identifier, and these two choices are a hot flag and a non - hot flag. If the second identifier of the entry is a hot flag, the instruction corresponding to the first index information recorded in the entry is a hot instruction. If the second identifier of the entry is a non - hot flag, the instruction corresponding to the first index information recorded in the entry is a cold instruction. Based on this, each entry includes four areas. One area is used to record the first identifier, one area is used to record the second identifier, one area is used to record the first index information of the instruction, and one area is used to record the id of the cache.

[0099] It should be noted that the first index information of the instruction in each entry can be determined according to the mapping rules between the storage blocks in the main memory and multiple caches.

[0100] On this basis, as Figure 3 shown, the steps of recording the first index information of the hot instruction and the id of the cold cache in the target entry are as follows:

[0101] Step 301: Determine candidate entries among multiple entries according to the first identifier and the second identifier of each entry. Among them, the candidate entries include the entries with the first identifier being an invalid flag and the entries with the second identifier being a non - hot flag among multiple entries, that is, the candidate entries are the entries without valid information and the entries where the instruction corresponding to the first index information recorded in the entry is a cold instruction among multiple entries.

[0102] Step 302: Determine the target entry among the candidate entries. Specifically, any one of the candidate entries can be determined as the target entry; or if the candidate entries include entries with the first identifier being an invalid flag and entries with the second identifier being a non - hot flag, preferably any one of the entries with the first identifier being an invalid flag among the candidate entries is determined as the target entry; or if the candidate entries only include entries with the second identifier being a non - hot flag, any one of the entries with the hot identifier being a non - hot flag is determined as the target entry.

[0103] It should be noted that when the number of hot instructions is multiple, that is, when there are multiple hot caches and at least one hot cache line is included in at least one hot cache, or when there is one hot cache and multiple hot cache lines are included in this hot cache, the target entry of each hot instruction needs to be determined through the above principle.

[0104] Step 303: Record the first index information of the hot instruction and the id of the cold cache in the target entry.

[0105] In the embodiment of the present application, if there are multiple hot instructions, then first, the cold cache corresponding to each hot instruction needs to be determined respectively. Then, the first index information of each hot instruction and the id of its corresponding cold cache are recorded in the corresponding target entry.

[0106] If there is one hot instruction, first, the cold cache for this hot instruction needs to be determined. Then, the first index information of this hot instruction and the id of the determined cold cache are recorded in the corresponding target entry.

[0107] After executing step 303, the second identifier in the target entry can also be set to a hot mark to indicate that the instruction corresponding to the first index information recorded in the target entry is a hot instruction, and the first identifier in the target entry is set to a valid mark to indicate that there is valid information in the target entry.

[0108] The method for determining the cold cache corresponding to each hot instruction can be: determine the cold cache corresponding to each hot cache respectively, and then, determine the cold cache corresponding to each hot cache as the cold cache corresponding to the hot instruction in the corresponding hot cache. Among them:

[0109] The method for determining the cold cache corresponding to each hot cache can include:

[0110] If there is one cold cache, then determine this cold cache as the cold cache corresponding to each hot cache. That is, the cold cache corresponding to each hot cache is the same.

[0111] If there are multiple cold caches, the cold cache corresponding to each hot cache can be determined from the multiple cold caches. Among them, the cold caches corresponding to each hot cache can be completely the same, completely different, partially the same or partially different, etc., and no special limitation is made here.

[0112] When recording the first index information of the hot instruction and the ID of the cold cache in the target entry, simultaneously or afterwards, the hot instruction can also be filled into the cold cache line in the cold cache. That is, determine the cold cache line in the cold cache and fill the hot instruction into the cold cache line in the cold cache. Specifically, the method of determining the cold cache line in the cold cache can include: determining any one cache line in the cold cache as the cold cache line; or, monitoring the access frequency of each cache line in the cold cache and determining the cache line with an access frequency less than the fifth preset frequency in the cold cache as the cold cache line; or monitoring the access frequency of each cache line in the cold cache and determining the cache line with the minimum access frequency in the cold cache as the cold cache line. It should be noted that the above process is only exemplary and is not used to limit this application.

[0113] It should be noted that when there are multiple hot instructions, each hot instruction is filled into the cold cache line in its corresponding cold cache respectively.

[0114] Furthermore, in order to update the hot and cold status of the instructions corresponding to the first index information in each entry of the redirect data table, this application further includes: monitoring the access frequency of each entry in the redirect data table, determining whether the access frequency of the first entry is less than the third preset frequency, and modifying the second identifier of the first entry with an access frequency less than the third preset frequency to a non-hot mark, determining whether the access frequency of the second entry is greater than the fourth preset frequency, and modifying the second identifier of the second entry with an access frequency greater than the fourth preset frequency to a hot mark, where the first entry is the entry in the redirect data table with the second identifier being a hot mark, the second entry is the entry in the redirect data table with the second identifier being a non-hot mark, and the fourth preset frequency is greater than the third preset frequency.

[0115] The process of monitoring the access frequency of each entry in the redirect data table includes: determining the number of times the first index information stored in each entry in the redirect data table is successfully matched by the index information of the instruction to be obtained within a preset time interval, and determining the ratio of the number of times the first index information stored in each entry is successfully matched within the preset time interval to the preset time interval as the access frequency of the corresponding entry. It should be noted that since the preset time intervals corresponding to each entry are the same, and the number of times the first index information stored in each entry is successfully matched within the preset time interval is positively correlated with its access frequency, therefore, the number of times the first index information stored in each entry is successfully matched within the preset time interval can also be determined as the access frequency of the corresponding entry, which can improve the calculation efficiency, reduce the calculation amount and calculation cost on the premise of ensuring data accuracy.

[0116] By monitoring the access frequency of each entry in the redirect data table and determining whether to change the cold / hot state of the instruction corresponding to the first index information in the entry according to the comparison result of the access frequency of the entry with the third preset frequency or the fourth preset frequency, the real-time monitoring and update of the cold / hot state of the instruction corresponding to the first index information of each entry in the redirect data table are realized, ensuring the timeliness and accuracy of the information in the redirect data table.

[0117] To further confirm whether to redirect the hot instruction to further improve the accuracy of starting the redirection process, the hot instruction can be determined in the hot cache in the following two ways. Among them:

[0118] Method 1: Determine whether the access frequency of the hot cache reaches the frequency configured in the register and whether the difference between the access frequency of the hot cache and the access frequency of the cold cache is greater than the configured value. If so, determine the hot instruction in the hot cache. The frequency configured in the register can be, for example, 1000 MOPS.

[0119] In the above Method 1, if there are multiple hot caches, the cold cache corresponding to each hot cache can be determined in the cold cache, and it is determined whether the access frequency of each hot cache reaches the frequency configured in the register and whether the difference between the access frequency of each hot cache and the access frequency of its corresponding cold cache is greater than the configured value, and the hot instruction is determined in the hot cache that meets the above conditions. It should be noted that the method of determining the cold cache corresponding to each hot cache has been described above, so it will not be elaborated here.

[0120] Method 2: Determine whether the access frequency of the hot cache is greater than n times the access frequency of the cold cache. If so, determine the hot instructions in the hot cache.

[0121] In the above Method 2, if there are multiple hot caches, the cold cache corresponding to each hot cache can be determined in the cold cache, determine whether the access frequency of each hot cache is greater than n times the access frequency of its corresponding cold cache, and determine the hot instructions in the hot cache that meet the above conditions.

[0122] Obviously, through the limiting conditions for determining hot instructions provided in the above Method 1 and Method 2, when the limiting conditions are met, the hot instructions can be determined in the hot cache, so as to record the first index information of the hot instructions and the id of the cold cache in the target entry, so as to achieve the redirection of the hot instructions. It can be understood that: the above Method 1 and Method 2 provide limiting conditions for starting the redirection process, and only when the limiting conditions are met can the redirection process be started, improving the accuracy of starting the redirection process.

[0123] It should be noted that the execution principle of the bandwidth balancing method when the main memory is the data main memory is the same as that of the bandwidth balancing method when the main memory is the instruction main memory, so it will not be elaborated here.

[0124] In summary, by monitoring the access frequencies of multiple caches, determining the cold cache and the hot cache among multiple caches, and recording the first index information of the hot information in the hot cache and the id of the cold cache in the target entry of the redirection data table, that is, redirecting the hot information in the cache with a high access frequency to the cache with a low access frequency, the deployment method of information in multiple caches is changed, and the deployment method of information in multiple caches is related to the access frequency of each cache. In this way, when obtaining information according to a request, the problem of uneven request distribution can be greatly alleviated, thereby improving the problem of serious imbalance in the obtained bandwidth and improving the performance of information acquisition; in addition, since the distribution of information in multiple caches is related to the access frequency of each cache, the performance prediction of information acquisition can be realized; in addition, only according to the access frequency of each cache, the redirection of hot information can be realized, and the steps are simple and easy to implement.

[0125] Next, on the basis of the above bandwidth balancing method, the process of information acquisition will be described. Figure 4 This is the first part of the flowchart of an information acquisition method provided by an embodiment of the present application. Figure 5This is the second part of the flowchart of an information acquisition method provided by an embodiment of the present application. Figure 6 This is the third part of the flowchart of an information acquisition method provided by an embodiment of the present application. Figure 7 This is the fourth part of the flowchart of an information acquisition method provided by an embodiment of the present application. The execution entity of the information acquisition method may be the same as or different from the execution entity of the above bandwidth balancing method. The present application does not make special limitations on this. Below, taking the redirection module in Figure 1 as the execution entity, the main memory as the instruction main memory, and the information to be acquired as the instruction to be acquired as an example, the process of information acquisition will be described. As Figures 4 to 7 shown, the process of this information acquisition may include:

[0126] Step 401, the redirection module reads the first request. The first request is a request to acquire the instruction to be acquired. The first request carries second index information, and the second index information is the index information used to acquire the instruction to be acquired.

[0127] The number of second index information carried in the first request is at least one. If there are multiple second index information carried in the first request, then the first request is a request to acquire the instruction to be acquired corresponding to each second index information.

[0128] It should be noted that if the size of the instruction to be acquired is greater than the capacity of the storage block in the main memory, then the second index information is the index information of the storage block storing the first instruction segment of the instruction to be acquired; if the size of the instruction to be acquired is less than or equal to the capacity of the storage block in the main memory, then the second index information is the index information of the storage block storing the instruction to be acquired.

[0129] Step 402, the redirection module binds an execution thread to the first request. It should be noted that the execution thread is mapped one by one with the processor Core, and only the execution thread corresponding to the processor Core that has completed the previous instruction acquisition request can bind the first request again. When there are multiple bindable execution threads, the first request is bound to the execution thread with a shallower Inst Q (Instruction Queue) according to the depth of the instruction queue of the execution thread.

[0130] Step 403: The redirection module determines the first index information of the instruction to be fetched according to the second index information. The principle of determining the first index information of the instruction to be fetched in the second index information is as follows: The first index information of the instruction to be fetched is determined in the second index information through the mapping rule between the storage blocks in the main memory and multiple caches. The first index of the instruction to be fetched can be, for example, the second index information, or a part of the second index information, etc. For example, if the second index information is the physical address of the instruction to be fetched, the first index information of the instruction to be fetched can be the physical address of the instruction to be fetched or a part of the fields in the physical address of the instruction to be fetched.

[0131] It should be noted that if the first request carries multiple second index information, then in step 403, one of the second index information is selected, and step 403 and the following steps are executed according to the selected second index information.

[0132] Step 404: The redirection module matches the first index information of the instruction to be fetched with the first index information in each entry in the redirection data table.

[0133] Step 405: If the first index information in an entry matches the first index information of the instruction to be fetched, the redirection module determines the cache corresponding to the cache id in the entry that matches the first index information of the instruction to be fetched as the first target cache.

[0134] Step 406: The redirection module sends the second index information to the first target cache, so that the first target cache fetches the instruction to be fetched according to the second index information.

[0135] From steps 403 and 406, it can be seen that the first index information of the instruction to be fetched is determined according to the second index information, and the first index information of the instruction to be fetched is matched with the first index information in each entry in the redirection data table to determine whether the instruction to be fetched has been redirected according to the matching result. If so, the cache corresponding to the instruction to be fetched after redirection, that is, the first target cache, is determined to fetch the instruction to be fetched in the first target cache. If not, the cache corresponding to the instruction to be fetched, that is, the first target cache, is determined according to the mapping rule between the storage blocks in the main memory and multiple caches and in combination with the second index information, and the instruction to be fetched is fetched in the first target cache. For the specific process, see step 407.

[0136] Step 407: If the first index information in each entry does not match the first index information of the instruction to be fetched, the redirection module determines the first target cache according to the second index information and the mapping rule.

[0137] The mapping rule is the mapping relationship between the memory blocks in the main memory and multiple caches, as well as the mapping relationship between the memory blocks and the cache lines in multiple caches. The principle of determining the first target cache according to the instruction to be fetched and the mapping rule is as follows: based on the mapping relationship between the memory blocks and multiple caches, and combining with the second index information, determine the cache corresponding to the instruction to be fetched, that is, the first target cache.

[0138] Next, an example is given to illustrate the process of determining the cache corresponding to the instruction to be fetched based on the mapping relationship between the memory blocks and multiple caches and combining with the second index information.

[0139] If the mapping relationship between the memory blocks and multiple caches is set according to the physical address of the memory block and the id of the cache, and the mapping relationship is established between the preset field in the physical address of the memory block and the id of the cache, where both the physical address and the id of the cache are represented in binary, and the number of bits of the preset field in the physical address is the same as the number of bits of the id of the cache, that is, if the preset field of the physical address of the memory block is the same as the id of a cache, then determine this cache as the cache corresponding to this memory block. In this way, the second index information is the physical address of the instruction to be fetched, compare the preset field in the physical address of the instruction to be fetched with the id of each cache, and determine the cache whose id is the same as the preset field in the physical address of the instruction to be fetched as the cache corresponding to the instruction to be fetched.

[0140] Step 408: Send the second index information to the first target cache, so that the first target cache fetches the instruction to be fetched according to the second index information.

[0141] Step 409: The first target cache receives the second index information, and determines whether there is a cache line corresponding to the second index information in the first target cache according to the second index information and combining with the mapping relationship between the memory blocks in the main memory and the cache lines in the cache. If so, fetch the instruction to be fetched in the corresponding cache line.

[0142] Step 410: The first target cache sends the instruction to be fetched to the crossbar.

[0143] Step 411: The crossbar sends the instruction to be fetched to the ProcessorCore corresponding to the execution thread bound to the first request.

[0144] Step 412: The first target cache determines whether the to-be-fetched instruction (i.e., the to-be-fetched instruction fetched from the corresponding cache line in Step 409) has been fetched completely based on the EI flag in the to-be-fetched instruction.

[0145] Step 413: If the EI flag is 1, it is determined that the fetching of the to-be-fetched instruction has been completed, and the process jumps to Step 421.

[0146] Step 414: If the EI flag is 0, it is determined that the fetching of the to-be-fetched instruction has not been completed. The first target cache calculates the third index information based on the second index information and the storage interval. It should be noted that this storage interval is the address interval when storing different instruction segments of an instruction in the main memory.

[0147] Step 415: The first target cache sends the third index information to the redirection module.

[0148] Step 416: The redirection module receives the third index information sent by the first target cache and determines the first index information of the to-be-fetched instruction based on the third index information, and matches the first index information of the to-be-fetched instruction with the first index information in each entry in the redirection data table.

[0149] Step 417: If the first index information in an entry matches the first index information of the to-be-fetched instruction, the redirection module determines the cache corresponding to the id of the cache in the entry that matches the first index information of the to-be-fetched instruction as the second target cache.

[0150] Step 418: The redirection module sends the third index information to the second target cache so that the second target cache fetches the to-be-fetched instruction based on the third index information.

[0151] Step 419: If the first index information in each entry does not match the first index information of the to-be-fetched instruction, the redirection module determines the second target cache based on the third index information and the mapping rule.

[0152] Step 420: The redirection module sends the third index information to the second target cache so that the second target cache fetches the to-be-fetched instruction based on the third index information.

[0153] It should be noted that the principle of determining the second target cache according to the third index information is the same as that of determining the first target cache according to the second index information, so it will not be elaborated here. The principle of the second target cache obtaining the instruction to be obtained according to the third index information and the principle of the subsequent processing flow are the same as those of step 409 and its subsequent processing flow, so it will not be elaborated here.

[0154] Step 421: If the EI flag is 1, the redirection module determines whether there is any other available second index information in the first request, selects a second index information from the other available second index information in the first request, and repeats step 403 and the subsequent steps based on the second index information selected in this step.

[0155] Specifically, in this step, if the EI flag is 1, it indicates that the acquisition of the instruction to be obtained corresponding to the second index information selected in step 403 has been completed. Since the number of second index information in the first request is at least one, in the case where the number of second index information is multiple, other available second index information needs to be selected from the first request, and the above process is repeated based on the reselected second index information to obtain the instruction to be obtained corresponding to the reselected second index information.

[0156] It should be noted that if the EI flag is 1 and there is no other available first index information in the first request, it is determined that the processing of the first request is completed, and the redirection module can read a new request and process the new request.

[0157] Step 422: In step 409, if there is no cacheline corresponding to the second index information in the first target cache, the first target cache generates a Refill request according to the second index information.

[0158] Step 423: The first target cache sends the Refill request to the main memory.

[0159] Step 424: The main memory obtains the instruction to be obtained according to the second index information in the Refill request, generates a response message according to the instruction to be obtained and the second index information, and sends the instruction to be obtained to the Processor Core corresponding to the execution thread bound to the first request through the crossbar.

[0160] Step 425: The main memory sends the response message to the redirection module.

[0161] Step 426: The redirection module determines the first index information of the instruction to be obtained according to the second index information in the response message, and matches the first index information of the instruction to be obtained with the first index information stored in each entry in the redirection data table.

[0162] Step 427: If the first index information of the instruction to be obtained matches the first index information in an entry in the redirection data table, the redirection module determines the cache corresponding to the id of the cache in the entry that matches the first index information of the instruction to be obtained as the third target cache.

[0163] Step 428: The redirection module sends the response message to the third target cache.

[0164] Step 429: If the first index information of the instruction to be obtained does not match the first index information in any entry in the redirection data table, the redirection module determines the third target cache according to the second index information in the response message and in combination with the mapping rule.

[0165] Step 430: The redirection module sends the response message to the third target cache.

[0166] Step 431: The third target cache receives the response message and stores the instruction to be obtained in the response message in a cache line in the third target cache.

[0167] It should be noted that the information acquisition process where the main memory is the data main memory and the information to be obtained is the data to be obtained is the same as the above Steps 401 to 431. Therefore, it will not be elaborated here.

[0168] As can be seen from the above, the first index information of the information to be obtained is determined according to the second index information, the first index information of the information to be obtained is matched with the first index information in each entry in the redirection data table, and when there is a matching entry, the cache corresponding to the id of the cache in the matching entry is determined as the first target cache, and the second index information is sent to the first target cache so that the first target cache obtains the information to be obtained according to the second index information. Therefore, based on the redirection data table, the first request is shunted, greatly alleviating the problem of uneven request distribution, thereby improving the serious imbalance problem of the request acquisition bandwidth and improving the information acquisition performance.

[0169] Next, the above process will be illustrated with examples. Figure 8 A schematic diagram of an application scenario provided by an embodiment of the present application including multiple caches, such as Figure 8As shown, the application scenario includes a Slice cache (i.e., the cache in this application scenario is a Slice cache), a processor core, an IBUF (Input Buffer), REDIR1 (Redirect Module 1), a RedirectTable (Redirect Data Table), and a main memory ( Figure 8 not shown in the figure). Among them, the IBUF includes an input IFIFO (Input FIFO, First In First Out) and REDIR0 (Redirect Module 0). The number of Slice caches is 16, namely Slice cache0 to Slice cache15 in sequence. Each Slice cache includes 256 cache lines. The number of processor cores is 16, namely processor core0 to processor core15. The main memory is an instruction main memory, that is, the information stored in the main memory is instructions. The cache lines in each Slice cache are 8-way set-associative with the main memory, and the instructions stored in each storage block in the main memory are deployed in a zigzag pattern in multiple Slice caches.

[0170] It should be noted that when storing a to-be-stored instruction in the main memory, if the size of the to-be-stored instruction is greater than the capacity of the storage block in the main memory, the to-be-stored instruction is divided into multiple instruction segments according to the capacity of the storage block, and the multiple divided instruction segments are stored in multiple storage blocks. The number of the multiple divided instruction segments is equal to the number of the multiple storage blocks, and the physical addresses of the storage blocks storing adjacent instruction segments are separated by 8, that is, the interval between the physical addresses of adjacent instruction segments is 8. It should be noted that the interval 8 here is in decimal. If the size of the to-be-stored instruction is less than or equal to the capacity of the storage block, the to-be-stored instruction is stored as a whole in a storage block.

[0171] The mapping rule between the storage blocks in the main memory and the 16 Slice caches is: each storage block in the main memory is mapped to the 16 Slice caches in a zigzag pattern, and each Slice cache is 8-way set-associative with the storage blocks in the main memory. It should be noted that this mapping rule is set according to the physical address of the storage block and the id of each Slice cache.

[0172] The number of bits (binary) of the physical address of the storage block can be determined by the total number of storage blocks in the main memory and the storage bytes of each storage block. Here, the physical address of the storage block includes 18 bits, that is, the physical address of the storage block can be represented by PC[17:0]. It should be noted that the physical address of the storage block is the physical address of the instruction stored in the storage block, that is, the physical address of the instruction in the storage block is represented by PC[17:0].

[0173] The number of bits required to represent the id of the Slice cache in binary can be determined by the total number of Slice caches. Since the number of Slice caches is 16, the number of bits of the id of the Slice cache is 4 bits, that is, the id of the Slice cache can be represented by SLID[3:0].

[0174] Next, the above mapping rules will be described.

[0175] The way each memory block in the main memory is mapped to 16 Slice caches in a zigzag pattern is as follows: According to the physical address of the memory block in the main memory, the memory blocks in the main memory are divided into multiple memory block groups in units of 8, where each memory block group includes 8 memory blocks and the physical addresses of these 8 memory blocks are adjacent; then, the memory blocks in the memory block group a + 16b are mapped to the a-th Slice cache (i.e., Slice cache a), where the value range of a is [0, 15] and a is an integer, and b is greater than or equal to 0 and is an integer. In other words, the memory blocks in memory block group 0 (i.e., the memory blocks with physical addresses 0 to 7), memory block group 16 (i.e., the memory blocks with physical addresses 128 to 135), etc., which are memory block groups based on 0 and separated by 16, are mapped to Slice cache0; the memory blocks in memory block group 1 (i.e., the memory blocks with physical addresses 8 to 15), memory block group 17 (i.e., the memory blocks with physical addresses 136 to 143), etc., which are memory block groups based on 1 and separated by 16, are mapped to Slice cache1; and so on, the memory blocks in memory block group 15 (i.e., the memory blocks with physical addresses 120 to 127), memory block group 31 (i.e., the memory blocks with physical addresses 248 to 255), etc., which are memory block groups based on 15 and separated by 16, are mapped to Slice cache15. It should be noted that the physical addresses in this paragraph are all in decimal.

[0176] In this way, based on the above Z-shaped mapping method, PC[6:3] in the PC[17:0] of the storage block is used as a preset field to determine the Slice cache corresponding to the storage block according to the PC[6:3] of the storage block. That is, if the PC[6:3] of a storage block is the same as the SLID[3:0] of a Slice cache, then this Slice cache is the Slice cache corresponding to this storage block. Since the physical address of the storage block is the physical address of the instruction stored in the storage block, when caching the instruction stored in a storage block into one of the 16 Slice caches, the PC[6:3] of the instruction stored in this storage block is compared with the SLID[3:0] of each Slice cache, and the Slice cache with the SLID[3:0] the same as the PC[6:3] of the instruction is determined as the Slice cache corresponding to this instruction, and this instruction is cached into its corresponding Slice cache.

[0177] Next, in combination with Figure 9 the structure of each Slice cache will be described. Each Slice cache includes a Cache data and a TAG Table. Since the structure of each Slice cache is the same, therefore, next, only the Cache data and the TAG Table in one Slice cache will be described.

[0178] Specifically, the Cache data includes 256 cachelines (i.e., cacheline0 to cacheline255). Each cacheline is used to cache the instructions in the storage block in the main memory. Since an 8-way set associative method is adopted between the Slice cache and the main memory, the 256 cachelines can be divided into 32 groups of cachelines in units of 8. Among them, each group of cachelines includes 8 cachelines. The TAG Table consists of multiple rows and columns. Among them, one row corresponds to a group of cachelines. Each row includes 8 large columns. One large column is represented by one way. That is, each row includes a total of 8 ways, namely way0 to way7. The 8 ways in each row correspond one-to-one with the 8 cachelines in the corresponding group of cachelines. Each way stores the relevant information of the instruction stored in the cacheline corresponding to it.

[0179] Specifically, each way includes four parameters: VLD, TAG, lock, and dirty. Among them, VLD in the way is used to indicate whether there is an instruction stored in the cacheline corresponding to this way. If VLD is 0, it means there is no instruction stored in the cacheline corresponding to this way. If VLD is 1, it means there is an instruction stored in the cacheline corresponding to this way;

[0180] TAG in the way is the tag bit in the physical address of the instruction stored in the cacheline corresponding to this way;

[0181] lock in the way indicates whether the instruction stored in the cacheline corresponding to this way can be replaced. Among them, if lock is 1, it means the instruction stored in the cacheline corresponding to this way cannot be replaced. If lock is 0, it means the instruction stored in the cacheline corresponding to this way can be replaced;

[0182] dirty in the way indicates whether the instruction stored in the cacheline corresponding to this way is consistent with the information it should originally store. If dirty is 0, it means the instruction stored in the cacheline corresponding to this way is not consistent with the information it should originally store. If dirty is 1, it means the instruction stored in the cacheline corresponding to this way is consistent with the information it should originally store.

[0183] The line number corresponding to each way is the index bit in the physical address of the instruction stored in the cacheline corresponding to this way.

[0184] Based on the above mapping rules, PC[17:13] of the instruction in the storage block is used as the index bit, and PC[12:3] of the instruction in the storage block is used as the tag bit. In this way, when caching the instruction in the storage block into the Slice cache, the Slice cache corresponding to the instruction can be determined according to PC[6:3] of the instruction. Then, the line number corresponding to the instruction can be determined in its corresponding Slice cache according to PC[17:13] of the instruction. Next, a group of cachelines corresponding to the instruction can be determined according to the line number corresponding to the instruction. Then, the instruction is stored in one of the cachelines in the group of cachelines corresponding to it. Finally, the way corresponding to the cacheline storing the instruction is determined in the TAG Tab table of the Slice cache corresponding to the instruction, and the TAG in the corresponding way in the TAG Tab table of the corresponding Slice cache is updated according to PC[12:3] of the instruction.

[0185] On this basis, after determining the Slice cache corresponding to the instruction to be fetched, the process of fetching the instruction to be fetched from the corresponding Slice cache will be described.

[0186] First, determine the row corresponding to the instruction to be fetched in the TAG Tab table of the corresponding Slice cache according to the PC[17:13] of the instruction to be fetched. Then, match the PC[12:3] of the instruction to be fetched with the TAG in each way of the corresponding row. If a match is found, the matching way is determined as the way corresponding to the instruction to be fetched. Finally, look up the corresponding cacheline in the Cache data of the corresponding Slice cache according to the PC[17:13] of the instruction to be fetched and the id of the corresponding way, and fetch the instruction to be fetched from the corresponding cacheline.

[0187] Based on the above mapping rules, the first index information of the instruction is the PC[17:3] of the instruction, and the second index information is the physical address of the instruction to be fetched, that is, PC[17:0].

[0188] It should be noted that if the size of the instruction to be fetched is less than or equal to the capacity of the storage block, the PC[17:0] of the instruction to be fetched is the PC[17:0] of the storage block storing the instruction to be fetched in the main memory, and the PC[17:13] of the instruction to be fetched is the PC[17:13] of the storage block storing the instruction to be fetched in the main memory. If the size of the instruction to be fetched is greater than the capacity of the storage block, the PC[17:0] of the instruction to be fetched is the PC[17:0] of the storage block storing the first instruction segment of the instruction to be fetched in the main memory, and the PC[17:13] of the instruction to be fetched is the PC[17:13] of the storage block storing the first instruction segment of the instruction to be fetched in the main memory.

[0189] The RedirectTable includes multiple entries, such as Figure 8 As shown, one entry includes four parameters, namely the first identifier VLD, the second identifier HOT, the PC[17:3] of the hot spot information, and the id of the cold point Slice cache (i.e., SLID[3:0]). In Figure 8 If the first identifier VLD is 0, it is determined that the first identifier VLD is an invalid mark. If the first identifier VLD is 1, it is determined that the first identifier VLD is a valid mark. If the second identifier HOT is 0, it is determined that the second identifier is a non-hot spot mark. If the second identifier HOT is 1, it is determined that the second identifier is a hot spot mark.

[0190] In the initial state of the above application scenario, the instructions stored in the storage blocks in the main memory can be cached in 16 Slice caches according to the above mapping rules. Then, in the process of obtaining the instruction to be obtained based on the above application scenario, the above bandwidth equalization method is used to adjust the deployment positions of the hot instructions in the hot Slice cache among the 16 Slice caches, realizing the redirection of the hot instructions in the hot Slice cache, and thus achieving the role of balancing.

[0191] Specifically, the process of bandwidth equalization is as follows: REDIR1 detects the access frequency of each of the Slice caches from Slice cache0 to Slice cache15; then, determines the cold Slice cache and the hot Slice cache among Slice caches from Slice cache0 to Slice cache15 according to the access frequency of each Slice cache, and then determines the hot instructions in the hot Slice cache; finally, records the PC[17:3] of the hot instructions and the SLID[3:0] of the cold Slice cache in the target entry of the Redirect Table. It should be noted that since the execution principle of bandwidth equalization has been described above, it will not be elaborated here.

[0192] As Figures 10 to 12 shown, the process of obtaining the instruction to be obtained may include the following steps:

[0193] Step 1001, IBUF receives the first request and caches the first request in the IFIFO. The first request is a request for obtaining the instruction to be obtained, and the first request carries second index information, that is, the PC[17:0] of the instruction to be obtained. It should be noted that here, the case where the first request includes one piece of second index information is taken as an example for description.

[0194] Step 1002. If the IFIFO is not empty and at least one processor core has completed the previous instruction acquisition request, then REDIR0 reads the first request from the IFIFO and binds a corresponding execution thread to the first request. It should be noted that the execution threads correspond one-to-one with the processor cores. Since the number of processor cores is 16, the number of execution threads is also 16. It should be noted that the bound execution thread is the execution thread corresponding to the processor core that has completed the previous instruction acquisition request. In addition, if there are multiple bindable execution threads, that is, when multiple processor cores have all completed their previous instruction acquisition requests, the first request is allocated to the execution thread with a shallower Inst Q according to the depth of the Inst Q of the execution thread.

[0195] Step 1003, REDIR0 determines the first index information of the instruction to be fetched according to PC[17:0] of the instruction to be fetched. That is, PC[17:3] in PC[17:0] of the instruction to be fetched is used as the first index information of the instruction to be fetched.

[0196] Step 1004, REDIR0 matches PC[17:3] of the instruction to be fetched with PC[17:3] in each entry of the Redirect Table.

[0197] Step 1005, if PC[17:3] in an entry of the Redirect Table matches PC[17:3] of the instruction to be fetched, then REDIR0 determines the Slice cache corresponding to SLID[3:0] in the entry of the Redirect Table that matches PC[17:3] of the instruction to be fetched as the first target Slice cache.

[0198] Step 1006, REDIR0 sends PC[17:0] of the instruction to be fetched to the first target Slice cache.

[0199] Step 1007, if PC[17:3] in each entry of the Redirect Table does not match PC[17:3] of the instruction to be fetched, then REDIR0 determines the Slice cache corresponding to the instruction to be fetched according to PC[6:3] of the instruction to be fetched, and determines the corresponding Slice cache as the first target Slice cache.

[0200] Step 1008, REDIR0 sends PC[17:0] of the instruction to be fetched to the first target Slice cache.

[0201] Step 1009, the first target Slice cache receives PC[17:0] of the instruction to be fetched, and determines the target row in the TAG Table according to PC[17:13] (i.e., the index bit) of the instruction to be fetched, matches PC[12:3] (i.e., the tag bit) of the instruction to be fetched with the TAG in each way of the target row. If a match is found, the way corresponding to the TAG that matches PC[12:3] of the instruction to be fetched is determined as the target way. Then, according to PC[17:13] of the instruction to be fetched and the id of the target way, the cacheline corresponding to the instruction to be fetched is determined in the Cache data, and the instruction to be fetched is obtained from the cacheline corresponding to the instruction to be fetched.

[0202] Step 1010: The first target Slice cache sends the instruction to be fetched to the crossbar.

[0203] Step 1011: The crossbar sends the instruction to be fetched to the Processor Core corresponding to the execution thread bound to the first request.

[0204] Step 1012: The first target Slice cache determines whether the instruction to be fetched has been fetched based on the EI flag in the instruction to be fetched.

[0205] Step 1013: If the EI flag is 1, the first target Slice cache determines that the fetching of the instruction to be fetched has been completed, and jumps to step 1021.

[0206] Step 1014: If the EI flag is 0, the first target Slice cache determines that the fetching of the instruction to be fetched has not been completed, and obtains the third index information based on the PC[17:0] of the instruction to be fetched and the storage interval. Here, since the physical address interval of adjacent instruction segments is 8, the storage interval takes the value of 8, that is, the third index information is the binary sum of the PC[17:0] of the instruction to be fetched and 8.

[0207] Step 1015: The first target Slice cache sends the third index information to REDIR1.

[0208] Step 1016: REDIR1 receives the third index information sent by the first target Slice cache, and matches the PC[17:3] in the third index information with the PC[17:3] in each entry in the redirection data table.

[0209] Step 1017: If the PC[17:3] in an entry matches the PC[17:3] in the third index information, REDIR1 determines the Slice cache corresponding to the SLID[3:0] in the entry that matches the PC[17:3] in the third index information as the second target Slice cache.

[0210] Step 1018: REDIR1 sends the third index information to the second target Slice cache.

[0211] Step 1019: If the PC[17:3] in each entry does not match the PC[17:3] in the third index information, REDIR1 determines the Slice cache corresponding to the third index information based on the PC[6:3] in the third index information, and determines the Slice cache corresponding to the third index information as the second target Slice cache.

[0212] Step 1020, REDIR1 sends the third index information to the second target Slice cache.

[0213] It should be noted that the principle of the second target Slice cache receiving the third index information and obtaining the instruction to be obtained according to the third index information and the subsequent principle are the same as the principle and the subsequent principle of step 1009, so it will not be elaborated here.

[0214] Step 1021, if the EI flag is 1, REDIR1 can read the new request and process the new request. Since the first request here only includes one second index information, if the EI flag is 1, then read the new request and perform corresponding processing.

[0215] Step 1022, in step 1009, if there is no way corresponding to the PC[12:3] of the instruction to be obtained in the row corresponding to the PC[17:13] of the instruction to be obtained in the TAG Table, the first target Slice cache generates a Refill request according to the PC[17:0] of the instruction to be obtained.

[0216] Step 1023, the first target Slice cache sends the Refill request to the main memory.

[0217] Step 1024, the main memory obtains the instruction to be obtained according to the PC[17:0] of the instruction to be obtained in the Refill request, generates response information according to the instruction to be obtained and the PC[17:0] of the instruction to be obtained, and sends the instruction to be obtained to the ProcessorCore corresponding to the execution thread bound by the first request through the crossbar.

[0218] Step 1025, the main memory sends the response information to REDIR1.

[0219] Step 1026, REDIR1 matches the PC[17:3] of the instruction to be obtained in the response information with the PC[17:3] stored in each entry in the redirect data table.

[0220] Step 1027, if the PC[17:3] of the instruction to be obtained matches the PC[17:3] in an entry in the redirect data table, REDIR1 determines the Slicecache corresponding to the SLID[3:0] in the entry that matches the PC[17:3] of the instruction to be obtained as the third target Slice cache.

[0221] Step 1028, REDIR1 sends the response information to the third target Slice cache.

[0222] Step 1029, if the PC[17:3] of the instruction to be fetched does not match the PC[17:3] in any entry in the redirection data table, then REDIR1 determines the Slice cache corresponding to the PC[6:3] of the instruction to be fetched as the third target Slice cache.

[0223] Step 1030, REDIR1 sends the response information to the third target Slice cache.

[0224] Step 1031, the third target Slice cache receives the response information, stores the instruction to be fetched in the response information in a cacheline in the Cache data of the third target Slice cache, and updates the information in the corresponding way in the TAG Table for the cacheline storing the instruction to be fetched according to the PC[17:0] of the instruction to be fetched in the response information, that is, sets the VLD in the corresponding way to 1, the TAG to the PC[12:3] of the instruction to be fetched, the lock to 1, and the dirty to 1.

[0225] Figure 13 It is a schematic structural diagram of a bandwidth balancing device provided by an embodiment of the present application. As Figure 13 shown, the device 1300 may include: a first monitoring module 1301, a first determination module 1302, a second determination module 1303, and a recording module 1304. Among them, the first monitoring module 1301 is used to monitor the access frequencies of multiple caches; the first determination module 1302 is used to determine the cold caches and hot caches among the multiple caches; the second determination module 1303 is used to determine hot information in the hot caches; the recording module 1304 is used to record the first index information of the hot information and the identification information of the cold caches in a target entry, where the target entry is an entry in the redirection data table.

[0226] In a possible implementation manner, the first monitoring module 1301 is specifically configured to, in response to a frequency monitoring instruction, monitor the access frequencies of the multiple caches in each monitoring period based on a monitoring period.

[0227] In a possible implementation, the first determination module 1302 is specifically configured to determine, according to the access frequency of each of the caches, the cache with the maximum access frequency as the hot cache and the cache with the minimum access frequency as the cold cache; or determine, according to the access frequency of each of the caches, the caches with access frequencies greater than a first preset frequency as the hot caches and the caches with access frequencies less than a second preset frequency as the cold caches, where the first preset frequency is greater than the second preset frequency.

[0228] In a possible implementation, the second determination module 1303 is specifically configured to determine whether the access frequency of the hot cache reaches the frequency configured in the register and whether the difference between the access frequency of the hot cache and the access frequency of the cold cache is greater than a configured value; if so, determine hot information in the hot cache.

[0229] In a possible implementation, the second determination module 1303 is specifically configured to determine whether the access frequency of the hot cache is greater than n times the access frequency of the cold cache; if so, determine hot information in the hot cache.

[0230] In a possible implementation, the second determination module 1303 is specifically configured to monitor the access frequency of each buffer line in the hot cache; determine a hot buffer line in the hot cache according to the access frequency of each buffer line; and determine the information stored in the hot buffer line as hot information.

[0231] In a possible implementation, the redirection data table includes multiple entries, and each entry includes a first identifier and a second identifier, where the first identifier is a valid flag or an invalid flag, and the second identifier is a hot flag or a non-hot flag.

[0232] In a possible implementation, the recording module 1304 is specifically configured to determine a candidate entry in the multiple entries according to the first identifier and the second identifier of each entry in the multiple entries, where the candidate entry includes the entries in the multiple entries with the first identifier being an invalid flag and the entries with the second identifier being a non-hot flag; determine a target entry in the candidate entries; and record the first index information of the hot information and the identification information of the cold cache in the target entry.

[0233] In a possible implementation, it further includes: a setting module, configured to set the second identifier in the target entry as a hot spot marker, and set the first identifier in the target entry as a valid marker.

[0234] In a possible implementation, it further includes: a second monitoring module, configured to monitor the access frequency of each entry in the redirection data table; a first determination module, configured to determine whether the access frequency of a first entry is less than a third preset frequency, where the first entry is an entry with the second identifier being the hot spot marker; a first modification module, configured to modify the second identifier of the first entry with an access frequency less than the third preset frequency to a non-hot spot marker; a second determination module, configured to determine whether the access frequency of a second entry is greater than a fourth preset frequency, where the second entry is an entry with the second identifier being the non-hot spot marker; a second modification module, configured to modify the second identifier of the second entry with an access frequency greater than the fourth preset frequency to a hot spot marker; where the fourth preset frequency is greater than the third preset frequency.

[0235] In a possible implementation, it further includes: a filling module, configured to fill the hot spot information into a cold spot buffer line in the cold spot cache memory.

[0236] In a possible implementation, it further includes: a third determination module, configured to determine any buffer line in the cold spot cache memory as the cold spot buffer line; or determine a buffer line with an access frequency less than a fifth preset frequency in the cold spot cache memory as the cold spot buffer line; or determine the buffer line with the minimum access frequency in the cold spot cache memory as the cold spot buffer line.

[0237] In a possible implementation, it further includes: a reading module, configured to read a first request, where the first request is a request for obtaining information to be obtained, and the first request carries second index information, and the second index information is index information for obtaining the information to be obtained; a fourth determination module, configured to determine first index information of the information to be obtained according to the second index information; a first matching module, configured to match the first index information of the information to be obtained with the first index information in each entry in the redirection data table; a fifth determination module, configured to, if the first index information in an entry matches the first index information of the information to be obtained, determine the cache memory corresponding to the identifier information of the cache memory in the entry that matches the first index information of the information to be obtained as a first target cache memory; a first sending module, configured to send the second index information to the first target cache memory, so that the first target cache memory obtains the information to be obtained according to the second index information.

[0238] In a possible implementation, it further includes: a sixth determination module, configured to, if the first index information in each of the table entries does not match the first index information of the information to be obtained, determine a first target cache memory according to the second index information and the mapping rule; a second sending module, configured to send the second index information to the first target cache memory, so that the first target cache memory obtains the information to be obtained according to the second index information.

[0239] In a possible implementation, it further includes: a receiving module, configured to receive third index information sent by a first target cache memory, where the third index information is calculated from the second index information and a storage interval, and the third index information is generated by the first target cache memory when it determines that the acquisition of the information to be obtained is not completed according to an end identifier in the information to be obtained; a seventh determination module, configured to determine the first index information of the information to be obtained according to the third index information; a second matching module, configured to match the first index information of the information to be obtained with the first index information in each table entry in a redirect data table; an eighth determination module, configured to, if the first index information in a table entry matches the first index information of the information to be obtained, determine the cache memory corresponding to the identifier information of the cache memory in the table entry that matches the first index information of the information to be obtained as a second target cache memory; a third sending module, configured to send the third index information to the second target cache memory, so that the second target cache memory obtains the information to be obtained according to the third index information.

[0240] In a possible implementation, it further includes: a ninth determination module, configured to, if the first index information in each of the table entries does not match the first index information of the information to be obtained, determine a second target cache memory according to the third index information and the mapping rule; a fourth sending module, configured to send the third index information to the second target cache memory, so that the second target cache memory obtains the information to be obtained according to the third index information.

[0241] The above device of the present application can be used to execute Figures 2 to 7 the technical solutions of the method embodiments shown therein, and the implementation principles and technical effects are similar, which will not be elaborated here.

[0242] The present application further provides a computer-readable storage medium, including a computer program, which, when executed on a computer, causes the computer to execute Figures 2 to 7 any one of the methods.

[0243] The present application also provides a computer program, which is used to execute when the computer program is executed by a computer Figures 2 to 7 any of the methods in

[0244] The present application also provides a chip, including a processor and a memory. The memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute Figures 2 to 7 any of the methods in

[0245] Further, the chip may further include a memory and a communication interface. The communication interface may be an input / output interface, a pin, an input / output circuit, etc.

[0246] In the implementation process, each step of the above method embodiments can be completed by the integrated logic circuit in the hardware of the processor or the instructions in the form of software. The processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as being executed and completed by the hardware-coded processor, or executed and completed by a combination of the hardware and software modules in the coded processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0247] The memories mentioned in the above embodiments may be volatile memories or non-volatile memories, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memories of the systems and methods described herein are intended to include, but are not limited to, these and any other suitable types of memories.

[0248] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled artisans can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0249] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0250] In several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0251] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0252] In addition, in each embodiment of the present application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0253] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art or a part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0254] As described above, only the specific implementation manners of the present application are provided, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, and all should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A bandwidth equalization method, characterized in that Including: Monitoring the access frequencies of multiple caches; Determining a cold cache and a hot cache among the multiple caches; Determining hot information in the hot cache; Recording first index information of the hot information and identification information of the cold cache in a target entry, where the target entry is an entry in a redirection data table for determining a first target high-speed memory for storing a to-be-fetched instruction according to the first index information of the to-be-fetched instruction; Filling the hot information into a cold buffer line in the cold cache; 2. The method according to claim 1, wherein The monitoring the access frequencies of multiple caches includes: In response to a frequency monitoring instruction, monitoring the access frequencies of the multiple caches in each monitoring period based on a monitoring period; 3. The method according to claim 1, characterized in that, The determining a cold cache and a hot cache among the multiple caches includes: According to the access frequency of each cache, determining the cache with the maximum access frequency as the hot cache and the cache with the minimum access frequency as the cold cache; or According to the access frequency of each cache, determining caches with access frequencies greater than a first preset frequency as the hot caches and caches with access frequencies less than a second preset frequency as the cold caches, where the first preset frequency is greater than the second preset frequency; 4. The method according to claim 1, wherein The determining hot information in the hot cache includes: Determining whether the access frequency of the hot cache reaches a frequency configured in a register and whether the difference between the access frequency of the hot cache and the access frequency of the cold cache is greater than a configured value; If so, determining hot information in the hot cache; 5. The method according to claim 1, wherein The determining hot information in the hot cache includes: Determining whether the access frequency of the hot cache is greater than n times the access frequency of the cold cache; If so, determining hot information in the hot cache; 6. The method according to any one of claims 1 to 5, characterized in that, The determining hot information in the hot cache includes: Monitoring the access frequencies of each buffer line in the hot cache; Determining a hot buffer line in the hot cache according to the access frequency of each buffer line; Determining the information stored in the hot buffer line as the hot information; 7. The method according to any one of claims 1 to 5, characterized in that The redirection data table includes multiple entries, and each entry includes a first identifier and a second identifier. The first identifier is a valid flag or an invalid flag, and the second identifier is a hot flag or a non-hot flag; 8. The method according to claim 7, wherein The recording first index information of the hot information and identification information of the cold cache in a target entry includes: Determine candidate entries among the multiple entries according to the first identifier and the second identifier of each entry in the multiple entries, where the candidate entries include the entries in the multiple entries with the first identifier being an invalid mark and the entries with the second identifier being a non-hotspot mark; Determine a target entry among the candidate entries; Record the first index information of the hotspot information and the identifier information of the cold cache in the target entry.

9. The method according to claim 8, wherein After recording the first index information of the hotspot information and the identifier information of the cold cache in the target entry, it further includes: Set the second identifier in the target entry to a hotspot mark, and set the first identifier in the target entry to a valid mark.

10. The method according to claim 7, characterized in that The method further includes: Monitor the access frequency of each entry in the redirect data table; Judge whether the access frequency of a first entry is less than a third preset frequency, where the first entry is the entry with the second identifier being the hotspot mark; Modify the second identifier of the first entry with the access frequency less than the third preset frequency to a non-hotspot mark; Judge whether the access frequency of a second entry is greater than a fourth preset frequency, where the second entry is the entry with the second identifier being the non-hotspot mark; Modify the second identifier of the second entry with the access frequency greater than the fourth preset frequency to a hotspot mark; Wherein, the fourth preset frequency is greater than the third preset frequency.

11. The method according to any one of claims 1 to 5, 8 to 10, characterized in that The method further includes: Determine any buffer line in the cold cache as the cold buffer line; or Determine the buffer lines in the cold cache with the access frequency less than a fifth preset frequency as cold buffer lines; or Determine the buffer line with the minimum access frequency in the cold cache as the cold buffer line.

12. The method according to claim 1, wherein The method further includes: Read a first request, where the first request is a request for obtaining information to be obtained, and the first request carries second index information, and the second index information is index information for obtaining the information to be obtained; Determine the first index information of the information to be obtained according to the second index information; Match the first index information of the information to be obtained with the first index information in each entry in the redirect data table; If the first index information in an entry matches the first index information of the information to be obtained, determine the cache corresponding to the identifier information of the cache in the entry that matches the first index information of the information to be obtained as the first target cache; Send the second index information to the first target cache, so that the first target cache obtains the information to be obtained according to the second index information.

13. The method according to claim 12, wherein The method further includes: If the first index information in each entry does not match the first index information of the information to be obtained, determine the first target cache according to the second index information and the mapping rule; Send the second index information to the first target cache memory, so that the first target cache memory obtains the information to be obtained according to the second index information.

14. The method according to claim 12 or 13, characterized in that, The method further includes: Receiving third index information sent by the first target cache memory, where the third index information is calculated from the second index information and a storage interval, and the third index information is generated by the first target cache memory when it determines that the acquisition of the information to be obtained is not completed according to the end flag in the information to be obtained; Determine the first index information of the information to be obtained according to the third index information; Match the first index information of the information to be obtained with the first index information in each entry of the redirection data table; If the first index information in one entry matches the first index information of the information to be obtained, determine the cache memory corresponding to the identification information of the cache memory in the entry that matches the first index information of the information to be obtained as the second target cache memory; Send the third index information to the second target cache memory, so that the second target cache memory obtains the information to be obtained according to the third index information.

15. The method according to claim 14, characterized in that, The method further includes: If the first index information in each entry does not match the first index information of the information to be obtained, determine the second target cache memory according to the third index information and the mapping rule; Send the third index information to the second target cache memory, so that the second target cache memory obtains the information to be obtained according to the third index information.

16. A bandwidth equalization device, characterized in that, Includes: A first monitoring module, configured to monitor the access frequencies of multiple cache memories; A first determination module, configured to determine a cold cache memory and a hot cache memory among the multiple cache memories; A second determination module, configured to determine hot information in the hot cache memory; A recording module, configured to record the first index information of the hot information and the identification information of the cold cache memory in a target entry, where the target entry is an entry in the redirection data table, and the redirection data table is used to determine the first target high-speed memory for storing the instruction to be obtained according to the first index information of the instruction to be obtained; A filling module, configured to fill the hot information into the cold buffer lines in the cold cache memory.

17. The device according to claim 16, characterized in that, The first monitoring module is specifically configured to, in response to a frequency monitoring instruction, monitor the access frequencies of the multiple cache memories in each monitoring period based on a monitoring period.

18. The device according to claim 16, wherein, The first determination module is specifically configured to determine the cache memory with the highest access frequency as the hot cache memory and the cache memory with the lowest access frequency as the cold cache memory according to the access frequency of each cache memory; or determine the cache memories with access frequencies greater than a first preset frequency as the hot cache memories and the cache memories with access frequencies less than a second preset frequency as the cold cache memories according to the access frequency of each cache memory, where the first preset frequency is greater than the second preset frequency.

19. The device according to claim 16, characterized in that, The second determination module is specifically configured to determine whether the access frequency of the hot cache memory reaches the frequency configured in the register and whether the difference between the access frequency of the hot cache memory and the access frequency of the cold cache memory is greater than a configured value; if so, determine hot information in the hot cache memory.

20. The device according to claim 16, characterized in that The second determination module is specifically configured to determine whether the access frequency of the hot cache memory is greater than n times the access frequency of the cold cache memory; if so, determine hot information in the hot cache memory.

21. The device according to any one of claims 16 to 20, characterized in that The second determination module is specifically configured to monitor the access frequency of each buffer line in the hot cache memory; determine a hot buffer line in the hot cache memory according to the access frequency of each buffer line; and determine the information stored in the hot buffer line as hot information.

22. The device according to any one of claims 16 to 20, characterized in that, The redirect data table includes a plurality of entries, and each entry includes a first identifier and a second identifier. The first identifier is a valid flag or an invalid flag, and the second identifier is a hot flag or a non-hot flag.

23. The device according to claim 22, wherein, The recording module is specifically configured to determine a candidate entry in the plurality of entries according to the first identifier and the second identifier of each entry in the plurality of entries, where the candidate entry includes the entries in the plurality of entries with the first identifier being an invalid flag and the entries with the second identifier being a non-hot flag; determine a target entry in the candidate entries; and record the first index information of the hot information and the identification information of the cold cache memory in the target entry.

24. The device according to claim 23, characterized in that, Further included: A setting module for setting the second identifier in the target entry as a hot flag and setting the first identifier in the target entry as a valid flag.

25. The device according to claim 22, characterized in that, Further included: A second monitoring module for monitoring the access frequency of each entry in the redirect data table; A first judgment module for judging whether the access frequency of a first entry is less than a third preset frequency, where the first entry is the entry with the second identifier being the hot flag; A first modification module for modifying the second identifier of the first entry with an access frequency less than the third preset frequency to a non-hot flag; A second judgment module for judging whether the access frequency of a second entry is greater than a fourth preset frequency, where the second entry is the entry with the second identifier being the non-hot flag; A second modification module, configured to modify the second identifier of the second entry whose access frequency is greater than the fourth preset frequency to a hot spot mark; Wherein, the fourth preset frequency is greater than the third preset frequency.

26. The device according to any one of claims 16 to 20 and 23 to 25, characterized in that, Further comprising: A third determination module, configured to determine any buffer line in the cold spot cache memory as the cold spot buffer line; or determine a buffer line in the cold spot cache memory whose access frequency is less than a fifth preset frequency as the cold spot buffer line; or determine the buffer line with the lowest access frequency in the cold spot cache memory as the cold spot buffer line.

27. The device according to claim 16, characterized in that, Further comprising: A reading module, configured to read a first request, where the first request is a request for obtaining information to be obtained, and the first request carries second index information, where the second index information is index information for obtaining the information to be obtained; A fourth determination module, configured to determine first index information of the information to be obtained according to the second index information; A first matching module, configured to match the first index information of the information to be obtained with the first index information in each entry in the redirection data table; A fifth determination module, configured to, if the first index information in an entry matches the first index information of the information to be obtained, determine the cache memory corresponding to the identifier information of the cache memory in the entry that matches the first index information of the information to be obtained as the first target cache memory; A first sending module, configured to send the second index information to the first target cache memory, so that the first target cache memory obtains the information to be obtained according to the second index information.

28. The device according to claim 27, wherein, Further comprising: A sixth determination module, configured to, if the first index information in each entry does not match the first index information of the information to be obtained, determine a first target cache memory according to the second index information and a mapping rule; A second sending module, configured to send the second index information to the first target cache memory, so that the first target cache memory obtains the information to be obtained according to the second index information.

29. The device according to claim 27 or 28, characterized in that, Further comprising: A receiving module, configured to receive third index information sent by the first target cache memory, where the third index information is calculated from the second index information and a storage interval, and the third index information is generated by the first target cache memory when it determines that the acquisition of the information to be obtained is not completed according to an end identifier in the information to be obtained; A seventh determination module, configured to determine first index information of the information to be obtained according to the third index information; A second matching module, configured to match the first index information of the information to be obtained with the first index information in each entry in the redirection data table; An eighth determination module, configured to, if the first index information in an entry matches the first index information of the information to be obtained, determine the cache memory corresponding to the identifier information of the cache memory in the entry that matches the first index information of the information to be obtained as the second target cache memory; A third sending module, configured to send the third index information to the second target cache memory, so that the second target cache memory obtains the information to be obtained according to the third index information.

30. The device according to claim 29, characterized in that, Further comprising: A ninth determining module, configured to determine a second target cache memory according to the third index information and a mapping rule if the first index information in each of the table entries does not match the first index information of the information to be obtained; A fourth sending module, configured to send the third index information to the second target cache memory, so that the second target cache memory obtains the information to be obtained according to the third index information.

31. A computer-readable storage medium, including a computer program, which when executed on a computer, causes the computer to execute the method according to any one of claims 1 to 15.

32. A computer program, which when executed by a computer, is used to execute the method according to any one of claims 1 to 15.

33. A chip, including a processor and a memory, where the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute the method according to any one of claims 1 to 15.

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