Semiconductor devices and semiconductor chips

Abstract

This invention provides a semiconductor device and a semiconductor chip for suppressing the occurrence of bonding wire tilt. In a semiconductor unit (20), semiconductor chips (25-28) have gates (25a1-25a4, 26a1-26a4, 27a1-27a4, 28a1-28a4) respectively provided at the corners of their front surfaces. At this time, a bonding wire (29b) connects the gate (25a4) on the semiconductor chip (26) side with the gate (26a2) on the semiconductor chip (25) side. A bonding wire (29f) connects the gate (28a1) on the semiconductor chip (27) side with the gate (27a3) on the semiconductor chip (28) side.

Description

Technical Field

[0001] This invention relates to semiconductor devices and semiconductor chips. Background Technology

[0002] Semiconductor devices include power devices. Power devices are, for example, semiconductor chips incorporating IGBTs (Insulated Gate Bipolar Transistors) or power MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors). Such semiconductor devices include a ceramic circuit board on which the aforementioned semiconductor chip is disposed and a heat-dissipating substrate on which multiple such ceramic circuit boards are disposed. Furthermore, the control electrodes of the semiconductor chip, the main electrodes of the semiconductor chip, and the circuit patterns of the ceramic circuit boards are appropriately electrically connected via bonding wires. Thus, the semiconductor device can perform the desired function (for example, see Patent Document 1).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2004-363339 Summary of the Invention

[0006] Technical issues

[0007] During the manufacture of semiconductor devices, there is a possibility that the bonding wires contained in the semiconductor device may come into contact, causing the bonding wires to tilt. For example, the bonding wires connecting the control electrodes of semiconductor chips connected in parallel are highly likely to come into contact. This likelihood is even higher when the control electrodes of the semiconductor chips are located on the end side of the ceramic circuit substrate. Moreover, if the bonding wires connected to the control electrodes tilt and come into contact with the bonding wires connected to the main electrodes, the semiconductor device will experience poor conductivity and will not exhibit the desired function.

[0008] The object of the present invention is to provide a semiconductor device that suppresses the tilting of the bonding wires, and a semiconductor chip for such a semiconductor device.

[0009] Technical solution

[0010] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a first semiconductor chip having a first control electrode disposed at a corner of a first front side, a first output electrode disposed on the first front side, and a first input electrode disposed on a first back side; a second semiconductor chip disposed on a side portion of the first semiconductor chip and having a second control electrode disposed at a corner of a second front side, a second output electrode disposed on the second front side, and a second input electrode disposed on a second back side; and a first interconnecting wiring that connects the first control electrode on the side of the second semiconductor chip to the second control electrode on the side of the first semiconductor chip.

[0011] In addition, according to one aspect of the present invention, a semiconductor chip is provided, the semiconductor chip comprising: gates respectively disposed at the corners of a front surface that is rectangular in shape when viewed from above; gate channels respectively connected to the gates along the edges of the front surface; and an electrical-resistant structure disposed along the outer periphery of the front surface.

[0012] Invention Effects

[0013] According to the disclosed technology, it is possible to suppress the occurrence of bonding wire tilting and prevent a decrease in the reliability of semiconductor devices.

[0014] The above and other objects, features and advantages of the present invention will become clear from the following description in conjunction with the accompanying drawings, which illustrate preferred embodiments as examples of the present invention. Attached Figure Description

[0015] Figure 1 This is a top view of the semiconductor device according to the first embodiment.

[0016] Figure 2 This is a top view of the semiconductor cell in the first embodiment.

[0017] Figure 3 This is a cross-sectional view of the semiconductor cell in the first embodiment.

[0018] Figure 4 It is a top view of the semiconductor chip included in the semiconductor unit of the first embodiment.

[0019] Figure 5 This is a diagram showing the equivalent circuit implemented by the semiconductor device of the first embodiment.

[0020] Figure 6 This is a top view of a semiconductor cell for reference.

[0021] Figure 7 This is a top view of the semiconductor cell in the second embodiment.

[0022] Figure 8 This is a top view of the semiconductor device according to the third embodiment.

[0023] Symbol Explanation

[0024] 10, 10a: Semiconductor devices

[0025] 11: Heat dissipation substrate

[0026] 12a~12e, 29a~29h, 29i~29n, 29o1~29o8, 29p1~29p4, 29q1~29q4: junction lines

[0027] 20, 20a~20f: Semiconductor unit

[0028] 21, 21a, 21b: Ceramic circuit board

[0029] 22, 22a, 22b: Insulation boards

[0030] 23: Metal plate

[0031] 24a~24e, 24f~24j, 24k~24m, 24n~24p: Circuit patterns

[0032] 24a1, 24c1, 24e1, 24f1, 24g1, 24g2, 24j1, 24k1, 24l1, 24m1, 24n1, 24o1, 24p1: Contact areas

[0033] 24b1, 24c2, 24d1, 24e2, 24g3, 24h1, 24i1, 24j2: Connecting regions

[0034] 25-28, 31-38, 41-48: Semiconductor chips

[0035] 25a1~25a4, 26a1~26a4, 27a1~27a4, 28a1~28a4: Gate

[0036] 25b, 26b, 27b, 28b: Gate flow channels

[0037] 25c, 26c, 27c, 28c: Emitters

[0038] 25d, 26d, 27d, 28d: Electrically resistant structural parts;

[0039] A: First arm

[0040] B: Second arm Detailed Implementation

[0041] Hereinafter, the embodiments will be described with reference to the accompanying drawings. It should be noted that in the following description, [the following text is incomplete and requires further context]. Figure 1 In the semiconductor device 10, "front side" and "top surface" refer to the surface facing upwards. Similarly, in Figure 1 In the semiconductor device 10, "upper" indicates the upper direction. Figure 1 In the semiconductor device 10, "back side" and "lower surface" refer to the surfaces facing downwards. Similarly, in Figure 1 In the semiconductor device 10, "down" indicates the lower direction. The same directionality may be indicated in other figures as needed. "Front side," "upper surface," "upper," "back side," "lower surface," "lower," and "side side" are merely convenient expressions for determining relative positional relationships and do not limit the technical concept of the invention. For example, "upper" and "lower" do not necessarily mean a vertical direction relative to the ground. That is, the directions of "upper" and "lower" are not limited to the direction of gravity. Furthermore, in the following description, "main component" indicates a content of 80% by volume or more.

[0042] [First Implementation Method]

[0043] The following uses, with reference to the attached diagram. Figure 1 The semiconductor device of the first embodiment will be described. Figure 1 This is a top view of the semiconductor device according to the first embodiment. The semiconductor device 10 includes a heat dissipation substrate 11 and semiconductor units 20a to 20f electrically connected to contact areas (described later) on the heat dissipation substrate 11 via bonding lines 12a to 12e.

[0044] The heat dissipation substrate 11 is primarily composed of a metal with excellent thermal conductivity. Examples of such metals include aluminum, iron, silver, copper, or alloys containing at least one of these. Furthermore, to improve corrosion resistance, nickel may be formed on the surface of the heat dissipation substrate 11 through a plating process or similar method. Specifically, in addition to nickel, nickel-phosphorus alloys and nickel-boron alloys are also used. The heat dissipation substrate 11 is appropriately formed with mounting holes for mounting the semiconductor device 10 to an external device, and contact areas for inputting and outputting current to the semiconductor cells 20a to 20f.

[0045] The heat dissipation substrate 11 is primarily composed of a metal with excellent thermal conductivity. Examples of such metals include aluminum, iron, silver, copper, or alloys containing at least one of these. Furthermore, the heat dissipation substrate 11 has contact areas. These contact areas are electrically connected to the semiconductor cells 20a-20f via bonding wires. Additionally, the contact areas are electrically connected to the outside. Therefore, the outside is electrically connected to the semiconductor cells 20a-20f via the contact areas.

[0046] Additionally, the heat sink 11 has bolt holes formed on its front side for bolt engagement. By screwing bolts into these bolt holes, the semiconductor device 10 can be mounted to external devices and / or cooling units. It should be noted that the mounting of cooling units will be described later. To improve corrosion resistance, the surface of such a heat sink 11 can also be plated. The plating material in this case is composed primarily of, for example, nickel, nickel-phosphorus alloys, or nickel-boron alloys.

[0047] Semiconductor cells 20a-20f are arranged in a row in a predetermined direction relative to the front side of the heat sink substrate 11, for example, via solder or silver solder. Such semiconductor cells 20a-20f include a semiconductor chip and have the necessary functions, the semiconductor chip including predetermined power devices. It should be noted that... Figure 1 The semiconductor cells 20a to 20f shown are arranged in a row, and the number can be set as needed. Hereinafter, semiconductor cells 20a to 20f will be collectively referred to as semiconductor cell 20, and their details will be described later. It should be noted that the bonding lines 12a to 12e are mainly composed of a metal with excellent conductivity. Examples of such metals include gold, silver, copper, aluminum, or alloys containing at least one of these. The diameter of the bonding lines 12a to 12e is, for example, 100 μm or more and 1 mm or less.

[0048] Alternatively, a cooling unit can be mounted on the back side of the heat dissipation substrate 11 of such a semiconductor device 10 via thermal grease. The thermal grease is, for example, silicon mixed with filler containing metal oxides. Furthermore, the cooling unit is also constructed primarily of a material with excellent thermal conductivity, and its surface can be plated as needed. The cooling unit can be, for example, a heat sink composed of multiple heat sink fins or a water-cooled cooling device. Alternatively, the heat dissipation substrate 11 can be integrally formed with such a cooling unit.

[0049] Alternatively, a component electrically connecting semiconductor cells 20a-20f and heat sink 11 can be housed in a housing (illustration omitted) using wiring components. The wiring components are, for example, lead frames. In this case, the housing exposes the control terminals and external terminals included in the lead frames. It should be noted that control signals are input via the control terminals. Predetermined currents are input / output externally via the external terminals. Such a housing is constructed primarily of thermoplastic resin. Examples of such resins include, for instance, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0050] Next, use Figures 2-5 The semiconductor unit 20 will be described. Figure 2 This is a top view of the semiconductor cell in the first embodiment. Figure 3This is a cross-sectional view of the semiconductor cell according to the first embodiment. It should be noted that... Figure 3 yes Figure 2 The cross-sectional view at the point marked by the single-dotted line XX. Among them, Figure 3 The description of the junction line has been omitted. Figure 4 This is a top view of the semiconductor chip included in the semiconductor unit of the first embodiment. It should be noted that... Figure 4 These represent semiconductor chips 25 to 28 respectively. Figure 5 This is a diagram showing an equivalent circuit implemented using the semiconductor device of the first embodiment.

[0051] The semiconductor unit 20 has a first arm (upper arm) A and a second arm (lower arm) B, forming upper and lower arms. For example... Figure 2 and Figure 3 As shown, the semiconductor unit 20 includes a ceramic circuit substrate 21 and semiconductor chips 25-28 disposed on the front side of the ceramic circuit substrate 21. Furthermore, the back side of this ceramic circuit substrate 21 of the semiconductor unit 20 is disposed on a heat dissipation substrate 11 via solder or silver solder (not shown). Figure 1 ).

[0052] Semiconductor chips 25-28 are primarily composed of silicon or silicon carbide. These semiconductor chips 25-28 contain an IGBT and a FWD (Free Wheeling Diode) forming an RC (Reverse Conducting)-IGBT switching element within a single chip. The RC-IGBT chip constitutes a circuit in which the IGBT and FWD are connected in reverse parallel. It should be noted that... Figure 2 The orientation of the semiconductor chips 25-28 shown corresponds to the configuration of the semiconductor chips 25-28. Figure 4 The orientation of the semiconductor chips 25-28 shown. For example, Figure 2 The lower right corner of the semiconductor chip 25 corresponds to Figure 4 The gate 25a4 of the semiconductor chip 25. Additionally... Figure 2 The upper left corner of the semiconductor chip 28 corresponds to Figure 4 The gate 28a1 of the semiconductor chip 28 is shown. Such semiconductor chips 25-28 have input electrodes (collectors) on their back sides as main electrodes. Furthermore, semiconductor chips 25 and 26 are arranged in a row. Semiconductor chips 27 and 28 are also arranged in a row. It should be noted that semiconductor chips 25 and 26 are not limited to a single row, but may also be arranged in... Figure 2They are staggered in the left-right direction. For example, the gate 26a1 (or gate 26a2) of semiconductor chip 26 can extend from the gate 25a3 (or gate 25a4) of semiconductor chip 25 to the midpoint between gate 25a3 and gate 25a4. Similarly, semiconductor chips 27 and 28 can also be... Figure 2 They are staggered in the left and right directions.

[0053] Furthermore, semiconductor chips 25-28 will be further explained. For example... Figure 4 As shown, semiconductor chips 25-28 include gates (control electrodes) 25a1-25a4, 26a1-26a4, 27a1-27a4, and 28a1-28a4, which are rectangular in shape when viewed from above and are respectively disposed at the corners of the front side; gate channels 25b, 26b, 27b, and 28b connecting the gates 25a1-25a4, 26a1-26a4, 27a1-27a4, and 28a1-28a4 along the edge of the front side; and electrically resistant structural portions 25d, 26d, 27d, and 28d disposed along the outer periphery of the front side. It should be noted that the gates 25a1-25a4, 26a1-26a4, 27a1-27a4, and 28a1-28a4 are areas that can be bonded by bonding lines 29a, 29b, 29e, and 29f. Furthermore, semiconductor chips 25-28 each include emitters (output electrodes serving as main electrodes) 25c, 26c, 27c, and 28c on the inner side of their respective corners on the front side. It should be noted that, although not shown in the diagram, sensing electrodes are respectively provided near each of the gates 25a1-25a4, 26a1-26a4, 27a1-27a4, and 28a1-28a4.

[0054] The ceramic circuit board 21 is rectangular in shape when viewed from above. The ceramic circuit board 21 has an insulating plate 22 and a metal plate 23 formed on the back side of the insulating plate 22. Furthermore, the ceramic circuit board 21 has circuit patterns 24a to 24e formed on the front side of the insulating plate 22. The insulating plate 22 and the metal plate 23 are rectangular in shape when viewed from above. Additionally, the corners of the insulating plate 22 and the metal plate 23 may be chamfered into an R-shape or a C-shape. The metal plate 23 is smaller than the insulating plate 22 when viewed from above and is formed inside the insulating plate 22.

[0055] The insulating plate 22 is primarily composed of ceramic with excellent thermal conductivity. Furthermore, the insulating plate 22 uses ceramic with a flexural strength of, for example, 450 MPa or higher. Such ceramic is made of, for example, a composite material primarily composed of alumina and zirconium oxide added to the alumina, or a material primarily composed of silicon nitride. Additionally, the thickness of the insulating plate 22 is 0.5 mm or more and 2.0 mm or less.

[0056] The metal plate 23 is primarily composed of a metal with excellent thermal conductivity. Such a metal is, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these. Furthermore, the thickness of the metal plate 23 is 0.1 mm or more and 2.0 mm or less. To improve corrosion resistance, the surface of the metal plate 23 may be plated. Examples of plating materials used include, for instance, nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0057] The circuit patterns 24a to 24e are primarily composed of a metal with excellent electrical conductivity. Examples of such metals include silver, copper, nickel, or alloys containing at least one of these. Furthermore, the thickness of the circuit patterns 24a to 24e is 0.5 mm or more and 1.5 mm or less. To improve corrosion resistance, the surface of the circuit patterns 24a to 24e may be plated. Examples of plating materials used include nickel, nickel-phosphorus alloys, and nickel-boron alloys. The circuit patterns 24a to 24e are obtained by forming a metal layer on the front side of the insulating plate 22 and etching the metal layer. Alternatively, the circuit patterns 24a to 24e, pre-cut from the metal layer, may be pressed onto the front side of the insulating plate 22. It should be noted that... Figure 2 and Figure 3 The circuit patterns 24a to 24e shown are examples. The number, shape, and size of the circuit patterns 24a to 24e can be appropriately selected as needed. Furthermore, to improve corrosion resistance, the circuit patterns 24a to 24e can also be plated to form a plating material on their surface. Examples of such plating materials include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0058] As a ceramic circuit board 21 having such a structure, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate can be used. The ceramic circuit board 21 enables the heat generated in the semiconductor chips 25-28 to be conducted to the heat dissipation substrate 11 side via the circuit patterns 24a, 24c, the insulating plate 22, and the metal plate 23.

[0059] Circuit pattern 24a constitutes the collector pattern of the first arm A. Circuit pattern 24a is bonded to the collector formed on the back side of semiconductor chips 25 and 26 via solder. Circuit pattern 24a is generally rectangular in shape, including the portion containing contact area 24a1. Figure 2 The lower middle side protrudes. Such a circuit pattern 24a is configured with semiconductor chips 25 and 26 via solder (illustration omitted).

[0060] Circuit pattern 24b constitutes the control pattern of the first arm A. Circuit pattern 24b is connected to the gate 26a3 of the semiconductor chip 26 via bonding line 29a. Circuit pattern 24b has a connection region 24b1 connected to bonding line 29a. Figure 2 In the diagram, circuit pattern 24b extends from the portion containing connection area 24b1 along one side of insulating plate 22. Figure 2 (The lower middle side) extends perpendicularly to the arrangement direction of semiconductor chips 25 and 26.

[0061] Circuit pattern 24c constitutes the emitter pattern of the first arm A and the collector pattern of the second arm B. Circuit pattern 24c has a connection region 24c2 connecting bonding lines 29c and 29d, which are connected to the emitters (output electrodes) 25c and 26c of semiconductor chips 25 and 26. The connection region 24c2 extends in the same direction as the arrangement of semiconductor chips 25 and 26. Additionally, the circuit pattern 24c has collectors formed on the back side of semiconductor chips 27 and 28 bonded via solder. Circuit pattern 24c is generally rectangular in shape, with the portion including contact area 24c1 extending towards... Figure 2 The upper middle side protrudes. Circuit pattern 24c is arranged side by side with circuit pattern 24a.

[0062] Circuit pattern 24d constitutes the control pattern of the second arm B. Circuit pattern 24d is connected to the gate 27a1 of semiconductor chip 27 via bonding line 29e. Circuit pattern 24d has a connection region 24d1 located on the opposite side of connection region 24b1, separated from semiconductor chips 25-27. Circuit pattern 24d in... Figure 2 From the portion containing the connection region 24d1 along one side of the insulating plate 22 ( Figure 2 (The upper middle side) extends perpendicularly to the arrangement direction of semiconductor chips 27 and 28.

[0063] Circuit pattern 24e constitutes the emitter pattern of the second arm B. Circuit pattern 24e has a connection region 24e2 connecting bonding lines 29g and 29h, which are connected to the emitters 27c and 28c of semiconductor chips 27 and 28. Connection region 24e2 is arranged side-by-side with semiconductor chips 27 and 28. Therefore, circuit pattern 24e has a portion disposed on the opposite side of circuit pattern 24a, separated from circuit pattern 24c. Circuit pattern 24 is formed in an L-shape, orthogonal between the two orthogonal sides of circuit pattern 24c and the two sides of insulating plate 22. Furthermore, circuit pattern 24e on insulating plate 22... Figure 2 The lower middle part is provided with a contact area 24e1.

[0064] The bonding wires 29a to 29h are primarily composed of a metal with excellent electrical conductivity. Examples of such metals include gold, silver, copper, aluminum, or alloys containing at least one of these. Furthermore, the diameters of bonding wires 29a, 29b, 29e, and 29f are, for example, 120 μm or more and 130 μm or less, and the diameters of bonding wires 29c, 29d, 29g, and 29h are 390 μm or more and 410 μm or less.

[0065] Bonding line 29a bonds and electrically connects the gate 26a3 of semiconductor chip 26 to the connection region 24b1 of circuit pattern 24b. Bonding line 29b connects the gates 25a3 and 25a4 on the semiconductor chip 26 side to the gates 26a1 and 26a2 on the semiconductor chip 25 side. Specifically, at least one of the gates 25a3 and 26a1 is connected to each other and the gates 25a4 and 26a2 are connected. Alternatively, the gates 25a3 and 26a2 may be connected to each other or to each other. Figure 2 In the middle, bonding line 29b connects the gates 25a3 and 25a4 on the side of semiconductor chip 26 to the gates 26a1 and 26a2 on the side of semiconductor chip 25, the gates 25a4 and 26a2 that are closest to each other.

[0066] Bonding lines 29c and 29d electrically connect the emitters 25c and 26c of semiconductor chips 25 and 26 to the connection region 24c2 of circuit pattern 24c, perpendicular to the arrangement direction of semiconductor chips 25 and 26. In this case, bonding lines 29c and 29d are connected by continuously bonding multiple portions of the emitters 25c and 26c of semiconductor chips 25 and 26 to the connection region 24c2 of circuit pattern 24c.

[0067] Bonding line 29e electrically connects the gate 27a1 of semiconductor chip 27 to the connection region 24d1 of circuit pattern 24d. Bonding line 29f connects the gates 27a3 and 27a4 on the semiconductor chip 28 side with the gates 28a1 and 28a2 on the semiconductor chip 27 side. Specifically, at least one of gates 27a3 and 28a1 is connected to each other and gates 27a4 and 28a2 is connected. Alternatively, gates 27a3 and 28a2 or gates 27a4 and 28a1 may be connected. Figure 2 In the middle, bonding line 29f connects the gates 27a3 and 27a4 on the side of semiconductor chip 28 and the gates 28a1 and 28a2 on the side of semiconductor chip 27, the gates 27a3 and 28a1 that are closest to each other.

[0068] Bonding lines 29g and 29h electrically connect the emitters 27c and 28c of semiconductor chips 27 and 28 to the connection region 24e2 of circuit pattern 24e, perpendicular to the arrangement direction of semiconductor chips 27 and 28. In this case, bonding lines 29g and 29h are connected by continuously bonding multiple portions of the emitters 27c and 28c of semiconductor chips 27 and 28 to the connection region 24e2 of circuit pattern 24e.

[0069] Thus, semiconductor chips 25-28 are connected to circuit patterns 24a-24e via bonding lines 29a-29h, forming a... Figure 5 The converter circuit shown. Semiconductor unit 20 forms the first arm (upper arm) A via semiconductor chips 25 and 26, circuit patterns 24a and 24b, and bonding lines 29a and 29b. Furthermore, semiconductor unit 20 forms the second arm (lower arm) B via semiconductor chips 27 and 28, circuit patterns 24c and 24d, and bonding lines 29e and 29f. Moreover, semiconductor unit 20 includes a C1 terminal (corresponding to contact area 24a1), an E2 terminal (corresponding to contact area 24c1), and an E1C2 terminal (corresponding to contact area 24e1).

[0070] Then, a high-potential terminal of an external power supply is connected to the C1 terminal, which serves as the input P terminal, and a low-potential terminal of the external power supply is connected to the E2 terminal, which serves as the input N terminal. Then, a load (not shown) is connected to the E1C2 terminal, which serves as the output U terminal of the semiconductor unit 20. Thus, the semiconductor unit 20 functions as a converter.

[0071] Multiple semiconductor cells 20 with this structure can be arranged on the heat dissipation substrate 11. Lead frames (not shown) can be bonded to each contact area 24a1, 24c1, 24e1, and a sealing component can be used to seal the semiconductor chips 25-28 and bonding wires 29a-29h on the ceramic circuit substrate 21. The sealing component comprises a thermosetting resin and a filler material contained within the thermosetting resin. The thermosetting resin is, for example, epoxy resin, phenolic resin, or maleimide resin. The filler material is a filler. The filler is composed of, for example, silicon oxide, aluminum oxide, boron nitride, or aluminum nitride.

[0072] Next, use Figure 6 The semiconductor cell of the reference example for semiconductor cell 20 will be described. Figure 6 This is a top view of the semiconductor cell in the reference example. It should be noted that for... Figure 6For the semiconductor unit 120 shown, the same symbols are used for structures identical to those in semiconductor unit 20, and their descriptions are omitted. In semiconductor unit 120, semiconductor chips 125-128 are provided instead of semiconductor chips 25-28 in semiconductor unit 20. Semiconductor chips 125-128 are also RC-IGBTs, just like semiconductor chips 25-28. Each semiconductor chip 125-128 has a gate 125a-128a located at the center of its front end and an emitter 125b-128b located at the center of its front end.

[0073] Semiconductor chips 125 and 126 are arranged in a row with their gates 125a and 126a facing the opposite side to semiconductor chips 127 and 128. Bonding line 129a connects the connection region 24b1 of circuit pattern 24b to the gates 126a and 125a of semiconductor chips 126 and 125. Semiconductor chips 127 and 128 are arranged in a row with their gates 127a and 128a facing the semiconductor chips 125 and 126. Bonding line 129e connects the connection region 24d1 of circuit pattern 24d to the gates 127a and 128a of semiconductor chips 127 and 128. It should be noted that the diameter of bonding lines 129a and 129e is also between 120 μm and 130 μm.

[0074] In such a semiconductor cell 120, bonding lines 129a and 129e are wired from the connection regions 24b1 and 24d1 of circuit patterns 24b and 24d to the gates 125a and 128a via gates 126a and 127a, respectively. Furthermore, the bonding lines 129a and 129e are arched with a predetermined curvature relative to the front surfaces of the circuit patterns 24a and 24c. During processing of the semiconductor cell 120 and the heat sink substrate 11 on which multiple semiconductor cells 120 are disposed, the bonding lines 129a and 129e may come into contact, potentially causing them to tilt. In particular, when the semiconductor cell 120 is disposed at the very end of the heat sink substrate 11, the bonding line 129a is located at the very end and is therefore easily touched and tilted. If a semiconductor device is manufactured with the bonding line 129a tilted towards the bonding lines 29c and 29d, such a semiconductor device will have poor conductivity. The joint line 129e may also tilt toward the joint lines 29g, 29h or 29c, 29d.

[0075] On the other hand, in the semiconductor unit 20 included in the semiconductor device 10, semiconductor chips 25 to 28 are respectively provided with gates 25a1 to 25a4, 26a1 to 26a4, 27a1 to 27a4, and 28a1 to 28a4 at the corners of their front surfaces. Furthermore, the semiconductor unit 20 includes: a circuit pattern 24b disposed on any side of the semiconductor chip 26 other than the side where the semiconductor chip 25 is disposed; and a circuit pattern 24d disposed on any side of the semiconductor chip 27 other than the side where the semiconductor chip 28 is disposed. In this case, bonding line 29b connects the gate 25a4 on the semiconductor chip 26 side to the gate 26a2 on the semiconductor chip 25 side. Bonding line 29f connects the gate 28a1 on the semiconductor chip 27 side to the gate 27a3 on the semiconductor chip 28 side. Bonding line 29a connects the gate 26a3 on the side of circuit pattern 24b to circuit pattern 24b, and bonding line 29e connects the gate 27a1 on the side of circuit pattern 24d to circuit pattern 24d.

[0076] The semiconductor cell 20 of such a semiconductor device 10 applies a gate voltage via bonding lines 29a, 29b and bonding lines 29e, 29f. That is, by making the length between the connection portions of bonding lines 29a, 29b and 29e, 29f shorter than the length between the connection portions of bonding lines 129a, 129e in the reference example, the height of the arch can be reduced. Therefore, even if bonding lines 29a, 29b and 29e, 29f are touched from the outside, they are less likely to tip over. Furthermore, bonding line 29b connects to the gates 25a4, 26a2 on the semiconductor chip 27, 28 side, and bonding line 29f connects to the gates 27a3, 28a1 on the semiconductor chip 25, 26 side. That is, bonding lines 29b, 29f are wired inside the semiconductor cell 20. Therefore, bonding lines 29b, 29f are less likely to be touched from the outside, thereby preventing the bonding lines 29b, 29f from tipping over. Therefore, it is possible to prevent malfunctions caused by poor conductivity of the semiconductor device 10 and to prevent a decrease in the reliability of the semiconductor device 10.

[0077] It should be noted that in the semiconductor device 10, bonding wire 29a connects circuit pattern 24b to gate 26a3 on the side adjacent to circuit pattern 24b. Not limited to this, bonding wire 29a can also connect circuit pattern 24b to gate 26a4 on the side adjacent to circuit pattern 24b, depending on the shape and design specifications of circuit patterns 24a and 24b, or two bonding wires 29a can be used to connect circuit pattern 24b to gates 26a3 and 26a4 respectively. Furthermore, the connection between circuit pattern 24d and gates 27a1 and 27a2 on the side adjacent to circuit pattern 24d, based on bonding wire 29e, can also be made in the same way.

[0078] [Second Implementation]

[0079] In the second embodiment, using Figure 7 The semiconductor unit 20 having a circuit pattern different from that of the first embodiment will be described. Figure 7 This is a top view of the semiconductor cell according to the second embodiment. It should be noted that, regarding the semiconductor device of the second embodiment, in... Figure 1 The heat sink 11 shown is configured with multiple Figure 7 The semiconductor unit 20 shown is used instead of the semiconductor unit 20 in the first embodiment. Furthermore, the semiconductor chips 25-28 included in the semiconductor unit 20 of the second embodiment are the same as those in the first embodiment. Therefore, in Figure 7 The symbols for gate structures and other features included in semiconductor chips 25-28 are omitted. For semiconductor chips 25-28, it is possible to utilize... Figure 2 and Figure 4 The symbols shown.

[0080] The semiconductor unit 20 has a first arm A and a second arm B, forming upper and lower arms. The semiconductor unit 20 has a ceramic circuit substrate 21 and semiconductor chips 25-28 disposed on the front side of the ceramic circuit substrate 21. It should be noted that the semiconductor chips 25-28 are the same as in the first embodiment. Furthermore, the ceramic circuit substrate 21 of the semiconductor unit 20 is disposed on a heat dissipation substrate 11 via solder or silver solder (not shown). Figure 1 ).

[0081] The ceramic circuit board 21 is rectangular in shape when viewed from above. The ceramic circuit board 21 has an insulating plate 22 and a metal plate 23 formed on the back side of the insulating plate 22. Figure 7 (Illustrations omitted). Furthermore, the ceramic circuit board 21 has circuit patterns 24f to 24j formed on the front side of the insulating plate 22. The insulating plate 22 and the metal plate 23 are the same as those in the first embodiment. The circuit patterns 24f to 24j are constructed using the same material and thickness as the circuit patterns 24a to 24e in the first embodiment. Additionally, the circuit patterns 24f to 24j are formed on the insulating plate 22 in the same manner as the circuit patterns 24a to 24e in the first embodiment.

[0082] As a ceramic circuit board 21 having such a structure, a DCB substrate or an AMB substrate can be used, for example. The ceramic circuit board 21 enables the heat generated in the semiconductor chips 25-28 to be conducted to the heat dissipation substrate 11 side via the circuit patterns 24f, 24g, the insulating plate 22, and the metal plate 23.

[0083] Circuit pattern 24f constitutes the collector pattern of the first arm A. Circuit pattern 24f is bonded to the collector formed on the back side of semiconductor chips 25 and 26 via solder. Circuit pattern 24f is generally rectangular in shape, with the portion including contact area 24f1 facing... Figure 7 The circuit pattern 24f protrudes from the lower right side. Semiconductor chips 25 and 26 are arranged in this circuit pattern via solder (illustration omitted).

[0084] The circuit pattern 24h constitutes the control pattern of the first arm A. The circuit pattern 24h is electrically connected to the gate 26a3 of the semiconductor chip 26 via bonding line 29i. The circuit pattern 24h has a connection region 24h1 connected to the bonding line 29i. Figure 7 In the circuit pattern 24h, the circuit pattern extends from the portion containing the connection area 24h1 along one side of the insulating plate 22. Figure 7 (Lower middle side) extends perpendicularly to the arrangement direction of semiconductor chips 25 and 26.

[0085] Circuit pattern 24g constitutes the emitter pattern of the first arm A and the collector pattern of the second arm B. For circuit pattern 24g, the region including the connection region 24g3 (wiring region) extends towards circuit pattern 24f. Figure 7 Extending upwards, the connection region 24g3 is connected to the emitters (output electrodes) 25c and 26c of semiconductor chips 25 and 26 via bonding lines 29k. Additionally, the circuit pattern 24g has collectors formed on the back side of semiconductor chips 27 and 28 bonded via solder. The circuit pattern 24g is generally L-shaped and includes contact areas 24g1 and 24g2 in the described wiring area. The circuit pattern 24g is arranged along both sides of the circuit pattern 24f.

[0086] Circuit pattern 24i constitutes the control pattern of the second arm B. Circuit pattern 24i is connected to the gate 27a2 of semiconductor chip 27 via bonding line 29l. Circuit pattern 24i has a connection region 24i1 located symmetrically to the connection region 24h1. Figure 7 In the circuit pattern 24i, the circuit pattern 24h is point-symmetrical, along one side of the insulating plate 22 ( Figure 7 (Upper middle side), extending perpendicularly to the arrangement direction of semiconductor chips 27 and 28.

[0087] Circuit pattern 24j constitutes the emitter pattern of the second arm B. Circuit pattern 24j has a connection region 24j2 that connects the emitters 27c and 28c of semiconductor chips 27 and 28 to the bonding line 29n. Circuit pattern 24j is disposed on the opposite side of circuit pattern 24i, separated from circuit pattern 24g. Such circuit pattern 24j is provided with a contact region 24j1.

[0088] The bonding lines 29i to 29n are made of the same material as the bonding lines 29a to 29h in the first embodiment. Furthermore, the diameters of bonding lines 29i, 29j, 29l, and 29m are the same as those of bonding lines 29a, 29b, 29e, and 29f. The diameters of bonding lines 29k and 29n are the same as those of bonding lines 29c, 29d, 29g, and 29h.

[0089] Bonding line 29i electrically connects the gate 26a3 of the semiconductor chip 26 to the connection region 24h1 of the circuit pattern 24h. Bonding line 29j connects the gates 25a3 and 25a4 on the semiconductor chip 26 side to the gates 26a1 and 26a2 on the semiconductor chip 25 side. Specifically, at least one of the gates 25a3 and 26a1 and the gates 25a4 and 26a2 is connected. Figure 7 In the middle, bonding line 29j connects the gates 25a3 and 25a4 on the side of semiconductor chip 26 to the gates 26a1 and 26a2 on the side of semiconductor chip 25, the gates 25a4 and 26a2 that are closest to each other.

[0090] The bonding line 29k electrically connects the emitters 25c and 26c of the semiconductor chips 25 and 26 to the connection region 24g3 of the circuit pattern 24g, parallel to the arrangement direction of the semiconductor chips 25 and 26. In this case, the bonding line 29k connects multiple portions of the emitters 25c and 26c of the semiconductor chips 25 and 26 to the connection region 24g3 of the circuit pattern 24g.

[0091] Bonding line 29l electrically connects the gate 27a2 of semiconductor chip 27 to the connection region 24i1 of circuit pattern 24i. Bonding line 29m connects the gates 27a3, 27a4 on the semiconductor chip 28 side to the gates 28a1, 28a2 on the semiconductor chip 27 side. Specifically, at least one of gates 27a3, 28a1 and gates 27a4, 28a2 is connected. Figure 7 In the middle, the bonding line 29m connects the gate 27a3 and gate 28a1, which are closest to each other among the gates 27a3 and 27a4 on the side of semiconductor chip 28 and the gates 28a1 and 28a2 on the side of semiconductor chip 27.

[0092] The bonding line 29n electrically connects the emitters 27c and 28c of the semiconductor chips 27 and 28 to the connection region 24j2 of the circuit pattern 24j, parallel to the arrangement direction of the semiconductor chips 27 and 28. In this case, the bonding line 29n connects multiple portions of the emitters 27c and 28c of the semiconductor chips 27 and 28 to the connection region 24j2 of the circuit pattern 24j.

[0093] Thus, semiconductor chips 25-28 are connected to circuit patterns 24f-24j via bonding lines 29i-29n, configured in the same manner as in the first embodiment. Figure 5 The converter circuit shown is illustrated. Semiconductor unit 20 forms the first arm A via semiconductor chips 25 and 26, circuit patterns 24f and 24h, and bonding lines 29i and 29j. Furthermore, semiconductor unit 20 forms the second arm B via semiconductor chips 27 and 28, circuit patterns 24i, 24g, and 24j, and bonding lines 29l and 29m. Moreover, semiconductor unit 20 includes a C1 terminal (corresponding to contact area 24f1), an E2 terminal (corresponding to contact areas 24g1 and 24g2), and an E1C2 terminal (corresponding to contact area 24j1).

[0094] Then, a high-potential terminal of an external power supply is connected to the C1 terminal, which serves as the input P terminal, and a low-potential terminal of the external power supply is connected to the E2 terminal, which serves as the input N terminal. Then, a load (not shown) is connected to the E1C2 terminal, which serves as the output U terminal of the semiconductor unit 20. Thus, the semiconductor unit 20 functions as a converter.

[0095] The semiconductor unit 20 with such a structure can be disposed on the heat dissipation substrate 11, and lead frames (not shown) are bonded in each contact area 24f1, 24g1, 24g2, 24j1, and the semiconductor chips 25 to 28 and bonding lines 29i to 29n on the ceramic circuit board 21 are sealed with sealing members in the same manner as in the first embodiment.

[0096] In the semiconductor unit 20 of this second embodiment of the semiconductor device, semiconductor chips 25 to 28 are also provided with gates 25a1 to 25a4, 26a1 to 26a4, 27a1 to 27a4, and 28a1 to 28a4 respectively disposed at the corners of the front side. Furthermore, the semiconductor unit 20 includes: a circuit pattern 24h disposed on any side of the semiconductor chip 26 other than the side where the semiconductor chip 25 is disposed; and a circuit pattern 24i disposed on any side of the semiconductor chip 27 other than the side where the semiconductor chip 28 is disposed. In this case, bonding line 29j connects the gate 25a4 on the semiconductor chip 26 side to the gate 26a2 on the semiconductor chip 25 side. Bonding line 29m connects the gate 28a1 on the semiconductor chip 27 side to the gate 27a3 on the semiconductor chip 28 side. Bonding line 29i connects the gate 26a3 on the side of circuit pattern 24h to circuit pattern 24h, and bonding line 29l connects the gate 27a2 on the side of circuit pattern 24i to circuit pattern 24i.

[0097] In this semiconductor device, the semiconductor cell 20 applies a gate voltage via multiple bonding lines 29i, 29j and 29l, 29m. This shortens the length between the connection points of bonding lines 29i, 29j, 29l, 29m and reduces the height of the arch. Therefore, even if bonding lines 29i, 29j, 29l, 29m are touched from the outside, they are less likely to tip over. Furthermore, bonding line 29j connects to the gates 25a4, 26a2 on the semiconductor chip 27, 28 side, and bonding line 29m connects to the gates 27a3, 28a1 on the semiconductor chip 25, 26 side. That is, bonding lines 29j, 29m are wired inside the semiconductor cell 20. Therefore, bonding lines 29j, 29m are less likely to be touched from the outside, thus preventing them from tipping over. Therefore, malfunctions caused by poor conductivity in the semiconductor device can be prevented, and the reliability of the semiconductor device can be prevented.

[0098] It should be noted that in the second embodiment, the bonding line 29i can also connect the circuit pattern 24h to the gate 26a4 on the side adjacent to the circuit pattern 24h, or the circuit pattern 24h can be connected to the gates 26a3 and 26a4 respectively via two bonding lines 29i. Furthermore, the connection between the circuit pattern 24i based on the bonding line 29i and the gates 27a1 and 27a2 on the side adjacent to the circuit pattern 24g can also be made in the same way.

[0099] Furthermore, unlike the semiconductor cell 20 of the first embodiment, in the semiconductor cell 20 of the second embodiment, the circuit pattern 24j, which serves as the emitter pattern, does not extend along the side of the circuit pattern 24g. Additionally, in the semiconductor cell 20 of the second embodiment, bonding lines 29k and 29j are wired parallel to the arrangement direction of the semiconductor chips 25 and 26. Bonding lines 29n and 29m are wired parallel to the arrangement direction of the semiconductor chips 27 and 28. Therefore, the semiconductor cell 20 can be narrowed, and the semiconductor device equipped with such a semiconductor cell 20 can be miniaturized.

[0100] [Third Implementation Method]

[0101] Unlike the first and second embodiments, in the third embodiment, the method used is... Figure 8 The case of connecting the gates of semiconductor chips on different circuit patterns using bonding wires is explained. Figure 8 This is a top view of a semiconductor device according to a third embodiment.

[0102] The semiconductor device 10a includes a heat dissipation substrate 11, ceramic circuit substrates 21a and 21b disposed on the heat dissipation substrate 11, and semiconductor chips 31-34, 41-44 and 35-38, 45-48 disposed on the ceramic circuit substrates 21a and 21b respectively.

[0103] The ceramic circuit boards 21a and 21b are rectangular in shape when viewed from above. Each ceramic circuit board 21a and 21b has insulating plates 22a and 22b and metal plates (not shown) formed on the back sides of the insulating plates 22a and 22b, respectively. Furthermore, the ceramic circuit boards 21a and 21b have circuit patterns 24k-24m and 24n-24p formed on the front sides of the insulating plates 22a and 22b, respectively. The insulating plates 22a and 22b and the metal plates are the same as those in the first embodiment. The circuit patterns 24k-24m and 24n-24p are constructed using the same material and thickness as the circuit patterns 24a-24e in the first embodiment. Additionally, the circuit patterns 24k-24m and 24n-24p are formed on the insulating plates 22a and 22b in the same manner as the circuit patterns 24a-24e in the first embodiment.

[0104] As ceramic circuit substrates 21a and 21b having such a structure, DCB substrates and AMB substrates can be used, for example. Ceramic circuit substrates 21a and 21b can conduct heat generated in semiconductor chips 31-34, 41-44 and semiconductor chips 35-38, 45-48 to the heat dissipation substrate 11 side via circuit patterns 24k, 24n, insulating plates 22a, 22b and metal plates.

[0105] Circuit patterns 24k and 24n constitute collector patterns. Collectors formed on the back surfaces of semiconductor chips 31-34 and 35-38 are bonded to circuit patterns 24k and 24n via solder. Additionally, cathodes formed on the back surfaces of semiconductor chips 41-44 and 45-48 are bonded to circuit patterns 24k and 24n via solder. Furthermore, circuit patterns 24k and 24n in… Figure 8 The upper part is provided with contact areas 24k1 and 24n1 for connecting the main electrode terminals.

[0106] Circuit patterns 24m and 24p constitute a control pattern. Circuit pattern 24m is connected to a bonding line that connects to the gate of semiconductor chip 31. Circuit pattern 24m is provided with a contact area 24m1 for connecting to a control terminal. Circuit pattern 24p is connected to a bonding line that connects to the sensing electrode of semiconductor chip 35. Circuit pattern 24p is provided with a contact area 24p1 for connecting to a sensing terminal.

[0107] Circuit patterns 24l and 24o constitute an emitter pattern. Circuit patterns 24l and 24o are connected to bonding lines 29q1, 29q2, and bonding lines 29q3 and 29q4 that connect to the input electrodes (anodes) of semiconductor chips 43, 44, and semiconductor chips 47, 48. Circuit patterns 24l and 24o are provided with contact areas 24l1 and 24o1 for connecting to the main electrode terminals.

[0108] Semiconductor chips 31-38 are switching elements primarily composed of silicon or silicon carbide. These switching elements are, for example, IGBTs and power MOSFETs. When semiconductor chips 31-38 are IGBTs, a collector is provided on the back side as the main electrode, and a gate and emitter are provided on the front side as the main electrodes. When semiconductor chips 31-38 are power MOSFETs, a drain is provided on the back side as the main electrode, and a gate and source are provided on the front side as the main electrodes. Furthermore, semiconductor chips 31-38, similar to the first embodiment, include: gates (notation omitted) respectively disposed at the corners of the front side, which is rectangular in shape when viewed from above; gate channels (not shown) connecting the gates along the edges of the front side; and a current-resistant structure (not shown) disposed along the outer periphery of the front side. Additionally, semiconductor chips 31-38 each include an emitter or drain (not shown) on the inner side of each corner of the front side. It should be noted that, although not shown, sensing electrodes are provided near each gate. These semiconductor chips 31-38 are bonded to circuit patterns 24k and 24n, for example, by solder.

[0109] Furthermore, semiconductor chips 41-48 are diode elements primarily composed of silicon or silicon carbide. These diode elements are, for example, SBD (Schottky Barrier Diode) or PiN (P-intrinsic-N) diodes, and other FWD (Front-Wave Diodes). Such semiconductor chips 41-48 have a cathode as the main electrode on the back side and an anode as the main electrode on the front side. These semiconductor chips 41-44 and 45-48 are bonded to circuit patterns 24k and 24n, for example, via solder.

[0110] The bonding lines 29o1-29o8, 29p1, 29p2, and 29q1-29q4 are made of the same material as the bonding lines 29a-29h in the first embodiment. It should be noted that... Figure 8 The dotted lines indicating the joints are merely intentional; they are actually made of the same material and have the same diameter as joints 29o2–29o4 and 29o6–29o8. Furthermore, the dotted lines only mark joints 29p1 and 29p2.

[0111] Bonding line 29o1 electrically connects the gate (upper left corner) of semiconductor chip 31 to circuit pattern 24m. Bonding line 29o2 connects the gate (upper right corner) of semiconductor chip 31 to the gate (upper left corner) of semiconductor chip 32. Bonding line 29o3 crosses the gap between circuit patterns 24k and 24n, connecting the gate (upper right corner) of semiconductor chip 32 to the gate (upper left corner) of semiconductor chip 36. Bonding line 29o4 connects the gate (upper right corner) of semiconductor chip 36 to the gate (upper left corner) of semiconductor chip 35.

[0112] Additionally, bonding line 29o5 connects the gate (lower right corner) of semiconductor chip 31 to the gate (upper right corner) of semiconductor chip 33. Bonding line 29o6 connects the gate (upper right corner) of semiconductor chip 33 to the gate (upper left corner) of semiconductor chip 34. Bonding line 29o7 spans the gap between circuit patterns 24k and 24n, connecting the gate (upper right corner) of semiconductor chip 34 to the gate (upper left corner) of semiconductor chip 38. Bonding line 29o8 connects the gate (upper right corner) of semiconductor chip 38 to the gate (upper left corner) of semiconductor chip 37.

[0113] Therefore, the gate voltage input from circuit pattern 24m is applied to semiconductor chip 31 via junction line 29o1. The applied gate voltage from semiconductor chip 31 turns on junction lines 29o2 to 29o4 and is applied to semiconductor chips 32, 36, and 35. In addition, the applied gate voltage from semiconductor chip 31 turns on junction lines 29o5 to 29o8 and is applied to semiconductor chips 33, 34, 38, and 37.

[0114] Additionally, the sensing electrodes (not shown) of semiconductor chips 31, 32, 36, and 35 are connected along bonding lines 29o2 to 29o4 using dashed lines for sensing emitter wiring. The sensing electrodes (not shown) of semiconductor chips 33, 34, 38, and 37 are connected along bonding lines 29o6 to 29o8 using dashed lines for sensing emitter wiring. Sensing electrodes 29p1 connects the sensing electrodes (not shown) of semiconductor chips 37 and 35. Sensing electrodes 29p2 connect the sensing electrode (not shown) of semiconductor chip 35 to circuit pattern 24p.

[0115] Additionally, bonding line 29q1 connects the emitters of semiconductor chips 31 and 33, the anodes of semiconductor chips 41 and 43, and circuit pattern 24l. Bonding line 29q2 connects the emitters of semiconductor chips 32 and 34, the anodes of semiconductor chips 42 and 44, and circuit pattern 24l. Furthermore, bonding line 29q4 connects the emitters of semiconductor chips 36 and 38, the anodes of semiconductor chips 46 and 48, and circuit pattern 24o. Bonding line 29q3 connects the emitters of semiconductor chips 35 and 37, the anodes of semiconductor chips 45 and 47, and circuit pattern 24o.

[0116] In this third embodiment of the semiconductor device 10a, semiconductor chips 31-34 and 35-38 also have gates respectively provided at the corners of their front surfaces. The semiconductor device 10a includes circuit patterns 24k and 24n on which semiconductor chips 31-34 and 35-38 are respectively disposed. Furthermore, the semiconductor device 10a includes a circuit pattern 24m disposed on any side of semiconductor chip 31 other than the side on which semiconductor chips 32 and 33 are disposed, and a circuit pattern 24p disposed on any side of semiconductor chip 35 other than the side on which semiconductor chips 36 and 37 are disposed.

[0117] At this time, similarly to the first embodiment, in circuit pattern 24k, the gates of semiconductor chips 32 and 33 on the semiconductor chip 31 side are connected to the gate of semiconductor chip 31 on the semiconductor chip 32 and 33 side via bonding lines. Additionally, the gates of semiconductor chips 32 and 33 on the semiconductor chip 34 side are connected to the gate of semiconductor chip 34 on the semiconductor chip 32 and 33 side via bonding lines. It should be noted that in... Figure 8 In this example, the gates are connected by bonding lines 29o2, 29o5, and 29o6.

[0118] Furthermore, similarly to the first embodiment, in circuit pattern 24n, the gates of semiconductor chips 35 and 38 on the semiconductor chip 36 side are connected to the gate of semiconductor chip 36 on the semiconductor chip 35 and 38 side via bonding lines. Additionally, the gates of semiconductor chips 35 and 38 on the semiconductor chip 37 side are connected to the gate of semiconductor chip 37 on the semiconductor chip 35 and 38 side via bonding lines. It should be noted that in... Figure 8 In this example, the gates are connected by bonding lines 29o4 and 29o8.

[0119] Furthermore, in the third embodiment, in different circuit patterns 24k and 24n, the gates of semiconductor chips 36 and 38 on the side adjacent to semiconductor chips 32 and 34 are connected. It should be noted that in... Figure 8 In this example, the gates are connected by bonding lines 29o3 and 29o7.

[0120] Therefore, in the third embodiment, the length between the connection portions of the bonding lines connecting the gates of the semiconductor chips in the same circuit patterns 24k, 24n and different circuit patterns 24k, 24n can be shortened, and the height of the arch can also be reduced. Therefore, even if these bonding lines are touched from the outside, they are not easily tilted.

[0121] In particular, through the first to third embodiments, since the semiconductor chip has gates at the corners of its front side, the gates can be connected via bonding lines as described above. Furthermore, various wiring methods can be implemented using such a semiconductor chip.

[0122] The above only illustrates the principles of the invention. Furthermore, those skilled in the art can make various modifications and alterations. The invention is not limited to the correct structures and applications shown and described above; all corresponding modifications and equivalents are considered to be within the scope of the invention based on the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized by comprising: Having: a first semiconductor chip including a first control electrode provided at a corner of a first front surface, a first output electrode provided at the first front surface, and a first input electrode provided at a first back surface; a second semiconductor chip disposed at a side of the first semiconductor chip and including a second control electrode provided at a corner of a second front surface, a second output electrode provided at the second front surface, and a second input electrode provided at a second back surface; and a first connection wiring connecting between the first control electrode on the second semiconductor chip side and the second control electrode on the first semiconductor chip side, the first control electrode and the second control electrode, which are located closest to each other, among the first control electrode on the second semiconductor chip side and the second control electrode on the first semiconductor chip side, are connected only to the first connection wiring.

2. The semiconductor device according to claim 1, further comprising: a first control circuit pattern disposed at any side of the second semiconductor chip other than the side on which the first semiconductor chip is disposed; and a first input-output wiring connecting at least one of the second control electrodes on the first control circuit pattern side and the first control circuit pattern.

3. The semiconductor device according to claim 2, wherein the first input-output wiring connects the first control circuit pattern and at least one of the second control electrodes on the first control circuit pattern side.

4. The semiconductor device according to claim 2, comprising a first arm portion including: the first semiconductor chip and the second semiconductor chip connected by the first connection wiring; and the first control circuit pattern connected to the second semiconductor chip by the first input-output wiring and disposed at a side of the second semiconductor chip opposite to the first semiconductor chip, the first arm portion further including a first circuit pattern disposed at a side of the first control circuit pattern and provided with the first semiconductor chip and the second semiconductor chip.

5. The semiconductor device according to claim 4, further comprising a second arm portion including: a second circuit pattern disposed at a side of the first circuit pattern along an arrangement direction of the first semiconductor chip and the second semiconductor chip; a third semiconductor chip disposed at the second circuit pattern and including a third control electrode provided at a corner of a third front surface, a third output electrode provided at the third front surface, and a third input electrode provided at a third back surface; a fourth semiconductor chip disposed at a side of the third semiconductor chip along the arrangement direction and at the second circuit pattern and including a fourth control electrode provided at a corner of a fourth front surface, a fourth output electrode provided at the fourth front surface, and a fourth input electrode provided at a fourth back surface; and a fourth connection wiring connecting between the third control electrode on the second circuit pattern side and the fourth control electrode on the second circuit pattern side, the third control electrode and the fourth control electrode, which are located closest to each other, among the third control electrode on the second circuit pattern side and the fourth control electrode on the second circuit pattern side, are connected only to the fourth connection wiring. ​ ​ ​ a second connection wiring connecting the third control electrode on the fourth semiconductor chip side and the fourth control electrode on the third semiconductor chip side.

6. The semiconductor device according to claim 5, wherein the second connection wiring connects the third control electrode on the fourth semiconductor chip side and the fourth control electrode on the third semiconductor chip side, which are located closest to each other.

7. The semiconductor device according to claim 6, wherein the second arm portion further includes: a second control circuit pattern provided on any side of the third semiconductor chip other than the side on which the fourth semiconductor chip is provided; and a second input-output wiring connecting at least one third control electrode on the second control circuit pattern side and the second control circuit pattern.

8. The semiconductor device according to claim 7, wherein the first connection wiring connects the first control electrode on the third semiconductor chip and the fourth semiconductor chip side and the second control electrode, the second connection wiring connects the third control electrode on the first semiconductor chip and the second semiconductor chip side and the fourth control electrode.

9. The semiconductor device according to any one of claims 5 to 8, wherein the first arm portion further includes a first output wiring extending from the first output electrode and the second output electrode to a side direction with respect to a connection direction of the first connection wiring, and connected to the second circuit pattern.

10. The semiconductor device according to claim 5, wherein the second arm portion further includes: a third circuit pattern adjacent to the second circuit pattern on a side opposite the first circuit pattern, and provided along the second circuit pattern; and a second output wiring extending from the third output electrode and the fourth output electrode to a side direction with respect to a connection direction of the second connection wiring, and connected to the third circuit pattern.

11. The semiconductor device according to any one of claims 5 to 8, wherein the second circuit pattern includes a wiring region on a side of the first circuit pattern and adjacent to a side of the first semiconductor chip opposite the second semiconductor chip, the first arm portion further includes a first output wiring extending from the first output electrode and the second output electrode to a connection direction of the first connection wiring, and connected to the wiring region.

12. The semiconductor device according to claim 11, wherein the second arm portion includes: a third circuit pattern provided on a side of the second circuit pattern and on a side of the fourth semiconductor chip opposite the third semiconductor chip, and provided on a side of the second circuit pattern opposite the wiring region; and ​ a second output wiring extending from the third output electrode and the fourth output electrode in a direction of connection of the second connection wiring, and connected to the third circuit pattern.

13. The semiconductor device according to claim 5, wherein the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are RC-IGBTs, that is, reverse conducting insulated gate bipolar transistors.

14. The semiconductor device according to claim 1, wherein the semiconductor device includes: a first circuit pattern in which the first semiconductor chip is disposed; and a second circuit pattern disposed apart from the first circuit pattern by a gap, in which the second semiconductor chip is disposed, the first connection wiring connects between the first control electrode on the second semiconductor chip side and the second control electrode on the first semiconductor chip side across the gap.

15. The semiconductor device according to claim 14, wherein the first connection wiring connects the first control electrode on the second semiconductor chip side and the second control electrode on the first semiconductor chip side, which are located closest to each other.

16. The semiconductor device according to claim 14, wherein the first semiconductor chip and the second semiconductor chip are IGBTs, that is, insulated gate bipolar transistors.

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