Array substrate, display device

Abstract

The invention relates to the field of display technology and provides an array substrate and a display device. The array substrate comprises a pixel driving circuit and a data line. The pixel driving circuit comprises a driving transistor (DT), a first transistor (T1), and a second transistor (T2). The driving transistor (DT) and the first transistor (T1) are P-type transistors, and the second transistor (T2) is an N-type transistor. The array substrate further comprises: a base substrate (0) and a first conductive layer. The first conductive layer is arranged on one side of the base substrate (0). The first conductive layer comprises: a first conductive portion (13), a first gate line (11), and a second gate line (12). The first conductive portion (13) is used to form a gate of the driving transistor (DT); the first gate line (11) is located on one side of the first conductive portion (13), and a portion of the first gate line (11) is used to form the gate of the first transistor (T1); the second gate line (12) is located on a side of the first gate line (11) away from the first conductive portion (13), and a portion of the second gate line (12) is used to form the first gate of the second transistor (T2). The array substrate can reduce the pull-down effect on the gate of a driving transistor (DT) when the second transistor (T2) is turned off.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] In related technologies, pixel driver circuits can be formed using low-temperature polycrystalline oxide (LTPO) technology. LTPO technology combines N-type metal oxide transistors with P-type low-temperature polysilicon transistors to form pixel driver circuits. However, in pixel driver circuits formed using LTPO technology, when the N-type metal oxide transistor is turned off, it pulls down the gate of the driver transistor, thereby affecting the charging of the driver transistor gate.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Public content

[0005] According to one aspect of the present disclosure, an array substrate is provided, which includes a pixel driving circuit and a data line. The pixel driving circuit includes a driving transistor, a first transistor connected between a first electrode of the driving transistor and the data line, and a second transistor connected between a gate electrode and a second electrode of the driving transistor. The driving transistor and the first transistor are P-type transistors, and the second transistor is an N-type transistor. The array substrate also includes: a base substrate, a first conductive layer, the first conductive layer is arranged on one side of the base substrate, the first conductive layer includes: a first conductive portion, a first gate line, and a second gate line, the first conductive portion is used to form the gate of the driving transistor; the first gate line is located on one side of the first conductive portion, and a portion of the first gate line is used to form the gate of the first transistor; the second gate line is located on a side of the first gate line away from the first conductive portion, and a portion of the second gate line is used to form the first gate of the second transistor.

[0006] In an exemplary embodiment of the present disclosure, the first gate line is located on one side of the first conductive portion in the first direction and extends along the second direction, and the first direction and the second direction intersect. The first gate line includes: a first extension portion and a second extension portion, and the orthographic projection of the first extension portion on the base substrate is opposite to the orthographic projection of at least part of the first conductive portion on the base substrate in the first direction; the orthographic projection of the second extension portion on the base substrate is staggered with the orthographic projection of the first conductive portion on the base substrate in the first direction.

[0007] In an exemplary embodiment of the present disclosure, the distance between the orthographic projection of the first extension portion on the base substrate and the orthographic projection of the first conductive portion on the base substrate in the first direction is smaller than the distance between the orthographic projection of the second extension portion on the base substrate and the orthographic projection of the first conductive portion on the base substrate in the first direction.

[0008] In an exemplary embodiment of the present disclosure, the first extension portion includes a third edge facing the first conductive portion, the first conductive portion includes a fourth edge facing the first extension portion, and the size of the orthographic projection of the third edge on the substrate in the second direction is equal to the size of the orthographic projection of the fourth edge on the substrate in the second direction.

[0009] In an exemplary embodiment of the present disclosure, at least a portion of the second extension portion is used to form a gate of the first transistor.

[0010] In an exemplary embodiment of the present disclosure, the array substrate includes a plurality of the pixel driving circuits, the first conductive layer includes a plurality of the first conductive portions spaced apart along the second direction, the plurality of the first conductive portions being used to respectively form the gates of the driving transistors in different pixel driving circuits; the first gate line includes: a plurality of the first extension portions and a plurality of the second extension portions, the first extension portions being arranged in a one-to-one correspondence with the first conductive portions, the orthographic projection of the first extension portion on the base substrate and at least a portion of the corresponding first conductive portion being opposite to each other in the first direction; and a plurality of the second extension portions being connected between adjacent first extension portions.

[0011] In an exemplary embodiment of the present disclosure, the array substrate also includes a second conductive layer, which is arranged on a side of the first conductive layer away from the base substrate, and the second conductive layer includes: a second conductive portion, a third conductive portion, and a first conductive line, the orthographic projection of the second conductive portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate, and is electrically connected to the first conductive portion through a via; the third conductive portion is used to form a first electrode of the second transistor, and the orthographic projection of the first gate line on the base substrate is located between the orthographic projection of the second conductive portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate; the first conductive line is connected between the second conductive portion and the third conductive portion, and extends along the first direction, and the orthographic projection of the first conductive line on the base substrate intersects with the orthographic projection of the first gate line on the base substrate.

[0012] In an exemplary embodiment of the present disclosure, the second conductive layer further includes: a fourth conductive portion, the fourth conductive portion is connected to the first conductive line, and the orthographic projection of the fourth conductive portion on the substrate at least partially overlaps with the orthographic projection of the first gate line on the substrate; wherein, the fourth conductive portion includes a first edge, the first conductive line includes a second edge connected to the first edge of the fourth conductive portion, and the angle between the orthographic projection of the first edge on the substrate and the orthographic projection of the second edge on the substrate is less than 180 degrees.

[0013] In an exemplary embodiment of the present disclosure, an orthographic projection of the fourth conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first extending portion on the base substrate.

[0014] In an exemplary embodiment of the present disclosure, the orthographic projection of the second gate line on the substrate is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the third conductive portion on the substrate; the second gate line includes a third extension portion and a fourth extension portion alternately connected in sequence along the second direction, wherein the size of the orthographic projection of the third extension portion on the substrate in the first direction is smaller than the size of the orthographic projection of the fourth extension portion on the substrate in the first direction; the orthographic projection of the first conductive line on the substrate intersects with the orthographic projection of the third extension portion on the substrate.

[0015] In an exemplary embodiment of the present disclosure, part of the fourth extension portion is used to form a first gate of the second transistor.

[0016] In an exemplary embodiment of the present disclosure, the second conductive layer further includes a power line extending along the first direction; the array substrate further includes a third conductive layer, which is arranged on a side of the second conductive layer away from the base substrate.

[0017] In an exemplary embodiment of the present disclosure, the power line includes a fifth extension portion, the orthographic projection of the fifth extension portion on the base substrate is opposite to the orthographic projection of at least part of the first conductive portion on the base substrate in the second direction, the third conductive layer includes the data line, the data line extends along the first direction, and the orthographic projection of part of the data line on the base substrate is located on the orthographic projection of the fifth extension portion on the base substrate.

[0018] In an exemplary embodiment of the present disclosure, the third conductive layer includes: a fifth conductive part, the fifth conductive part is connected to the power line through a via, the orthographic projection of the fifth conductive part on the base substrate covers the orthographic projection of the first conductive part on the base substrate, and the orthographic projection of the fifth conductive part on the base substrate covers the orthographic projection of the second conductive part on the base substrate.

[0019] In an exemplary embodiment of the present disclosure, the array substrate also includes a third transistor, the first electrode of the third transistor is connected to the gate of the driving transistor, the second transistor and the third transistor are both N-type metal oxide transistors, the first conductive layer also includes: a third gate line, the third gate line is located on the side of the second gate line away from the first conductive portion, and extends along the second direction, part of the third gate line is used to form the gate of the third transistor; the third conductive layer includes a fifth conductive portion, the fifth conductive portion is connected to the power line through a via, and the orthographic projection of the fifth conductive portion on the base substrate covers the orthographic projection of the second transistor and the third transistor on the base substrate.

[0020] In an exemplary embodiment of the present disclosure, the array substrate includes: an R pixel driving circuit, a G pixel driving circuit, and a B pixel driving circuit; wherein the width-to-length ratio of the channel region of the driving transistor in the R pixel driving circuit, the width-to-length ratio of the channel region of the driving transistor in the G pixel driving circuit, and the width-to-length ratio of the channel region of the driving transistor in the G pixel driving circuit are not all the same.

[0021] In an exemplary embodiment of the present disclosure, the width-to-length ratio of the channel region of the driving transistor in the R pixel driving circuit is equal to the width-to-length ratio of the channel region of the driving transistor in the G pixel driving circuit, and the width-to-length ratio of the channel region of the driving transistor in the R pixel driving circuit is less than the width-to-length ratio of the channel region of the driving transistor in the R pixel driving circuit.

[0022] In an exemplary embodiment of the present disclosure, the width-to-length ratio of the channel region of the driving transistor in the R pixel driving circuit is 3.5 / 40, and the width-to-length ratio of the channel region of the driving transistor in the B pixel driving circuit is 3.5 / 25.

[0023] In an exemplary embodiment of the present disclosure, the array substrate further includes: a fourth conductive layer, the fourth conductive layer is stacked between the first conductive layer and the second conductive layer, the fourth conductive layer includes: a fourth gate line, the fourth gate line extends along the second direction, the orthographic projection of the first gate line on the base substrate is located between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the fourth gate line on the base substrate, and a portion of the fourth gate line is used to form the second gate of the second transistor.

[0024] In an exemplary embodiment of the present disclosure, the fourth gate line includes a sixth extending portion and a seventh extending portion alternately connected in sequence along the second direction;

[0025] In which, the size of the orthographic projection of the sixth extension portion on the base substrate in the first direction is smaller than the size of the orthographic projection of the seventh extension portion on the base substrate in the first direction; the orthographic projection of the first conductive line on the base substrate intersects with the orthographic projection of the sixth extension portion on the base substrate.

[0026] In an exemplary embodiment of the present disclosure, part of the seventh extension portion is used to form a second gate of the second transistor.

[0027] In an exemplary embodiment of the present disclosure, the array substrate further includes: a first active layer and a second active layer, the first active layer is stacked between the base substrate and the first conductive layer, and a portion of the first active layer is used to form the channel region of the driving transistor; the second active layer is stacked between the fourth conductive layer and the first conductive layer, and a portion of the second active layer is used to form the channel region of the second transistor and the third transistor.

[0028] In an exemplary embodiment of the present disclosure, the array substrate further includes: an enable signal line, an initial signal line, an anode layer, a first reset signal line, a second reset signal line, and a power line; and the pixel driving circuit further includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a capacitor. The first electrode of the third transistor is connected to the gate of the driving transistor, the second electrode is connected to the initial signal line, and the gate is connected to the second reset signal line; the first electrode of the fourth transistor is connected to the power line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the enable signal line; the first electrode of the fifth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the anode layer, and the gate is connected to the enable signal line; the first electrode of the sixth transistor is connected to the second electrode of the fifth transistor, the second electrode is connected to the initial signal line, and the gate is connected to the first reset signal line; and the capacitor is connected between the gate of the driving transistor and the power line.

[0029] In an exemplary embodiment of the present disclosure, the driving transistor, the fourth transistor, the fifth transistor, and the sixth transistor are P-type low-temperature polysilicon transistors.

[0030] According to one aspect of the present disclosure, a display device is provided, wherein the display device includes the above-mentioned array substrate.

[0031] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0033] Figure 1 This is a schematic diagram of the circuit structure of a pixel driving circuit disclosed herein;

[0034] Figure 2 for Figure 1 A timing diagram of each node in a driving method of a pixel driving circuit;

[0035] Figure 3 This is a structural diagram of an exemplary embodiment of the array substrate disclosed herein;

[0036] Figure 4 This is a structural diagram of another exemplary embodiment of the array substrate disclosed herein;

[0037] Figure 5 for Figure 4 The structural layout of the second conductive layer;

[0038] Figure 6 This is a structural diagram of another exemplary embodiment of the array substrate disclosed herein;

[0039] Figure 7 for Figure 6 Schematic diagram of the structure of the third conductive layer;

[0040] Figure 8 is the structural layout of the first active layer;

[0041] Figure 9 is the structural layout of the first conductive layer;

[0042] Figure 10 is the structural layout of the second active layer;

[0043] Figure 11 A combined layout of the first active layer, the first conductive layer, and the second active layer;

[0044] Figure 12 is the structural layout of the fourth conductive layer;

[0045] Figure 13 A combined layout of the first active layer, the first conductive layer, the second active layer, and the fourth conductive layer;

[0046] Figure 14 is the structural layout of the second conductive layer;

[0047] Figure 15A combined layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, and the second conductive layer;

[0048] Figure 16 is the structural layout of the third conductive layer;

[0049] Figure 17 A combined layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, the second conductive layer, and the third conductive layer;

[0050] Figure 18 is the structural layout of the anode layer;

[0051] Figure 19 A combination pattern of a first active layer, a first conductive layer, a second active layer, a fourth conductive layer, a second conductive layer, a third conductive layer, and an anode layer;

[0052] Figure 20 For the Figure 17 A partial cross-sectional view taken along the dotted line A;

[0053] Figure 21 This is a structural layout of the second conductive layer in another exemplary embodiment of the array substrate disclosed herein;

[0054] Figure 22 A combined layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, the second conductive layer, and the third conductive layer in another exemplary embodiment of the array substrate disclosed herein;

[0055] Figure 23 for Figure 22 Cross-sectional view along dotted line A. DETAILED DESCRIPTION

[0056] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0057] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one component of the illustrations to another component, these terms are used in this specification for convenience only, such as based on the orientation of the examples shown in the drawings. It is understood that if the device in the illustrations is turned upside down, the component described as "upper" will become the component "lower". Other relative terms such as "higher", "lower", "top", "bottom", "left", and "right" have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0058] The terms "a", "an", and "said" are used to indicate the presence of one or more elements / component distinctions / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / component distinctions / etc. may be present in addition to the listed elements / component distinctions / etc.

[0059] like Figure 1FIG2 is a schematic diagram of a circuit structure of a pixel driving circuit disclosed in the present invention. The pixel driving circuit may include: a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a capacitor C. The first transistor T1 has a first electrode connected to the data signal terminal Da, a second electrode connected to the first electrode of the driving transistor DT, and a gate connected to the first gate driving signal terminal G1; the fourth transistor T4 has a first electrode connected to the first power supply terminal VDD, a second electrode connected to the first electrode of the driving transistor DT, and a gate connected to the enable signal terminal EM; the gate of the driving transistor DT is connected to the node N, and the second electrode is connected to the first electrode of the fifth transistor T5; the second transistor T2 has a first electrode connected to the node N, a second electrode connected to the second electrode of the driving transistor DT, and a gate connected to the second gate driving signal terminal G2; the second electrode of the fifth transistor T5 is connected to the first electrode of the sixth transistor T6, and the gate is connected to the enable signal terminal EM; the second electrode of the sixth transistor T6 is connected to the initial signal terminal Vinit, and the gate is connected to the first reset signal terminal Re1; the first electrode of the third transistor T3 is connected to the node N, the second electrode is connected to the initial signal terminal Vinit, and the gate is connected to the second reset signal terminal Re2; and the capacitor C is connected between the first power supply terminal VDD and the node N. This pixel driving circuit can be connected to a light-emitting unit OLED to drive the light-emitting unit OLED to emit light. The light-emitting unit OLED is connected between the second electrode of the fifth transistor T5 and the second power supply terminal VSS. The second transistor T2 and the third transistor T3 may be N-type metal oxide transistors (NMOTs), which have low leakage current, thereby preventing leakage of power from the node N through the second and third transistors T2 and T3 during the light-emitting phase. Furthermore, the drive transistor DT, the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be low-temperature polysilicon transistors (LTPS). LTPS transistors have high carrier mobility, thus facilitating the realization of display panels with high resolution, high response speed, high pixel density, and high aperture ratio.

[0060] like Figure 2 As shown, Figure 1A timing diagram of each node in a driving method for a pixel driving circuit. G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, N represents the timing of the node N, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of the pixel driving circuit may include a reset phase t1, a compensation phase t2, and a light-emitting phase t3. In the reset phase t1: the first reset signal terminal Re1 outputs a low-level signal, the second reset signal terminal Re2 outputs a high-level signal, the third transistor T3 and the sixth transistor T6 are turned on, and the initial signal terminal Vinit inputs an initialization signal to the node N and the second electrode of the fifth transistor T5. During the compensation phase t2: the first gate drive signal terminal G1 outputs a low-level signal, the second gate drive signal terminal G2 outputs a high-level signal, the first transistor T1 and the second transistor T2 are turned on, and at the same time, the data signal terminal Da outputs a drive signal to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the drive signal and Vth is the threshold voltage of the drive transistor DT. During the light-emitting phase t3: the enable signal terminal EM outputs a low-level signal, the fourth transistor T4 and the fifth transistor T5 are turned on, and the drive transistor DT emits light under the action of the voltage Vdata+Vth stored in the capacitor C. According to the output current formula of the drive transistor I = (μWCox / 2L)(Vgs-Vth) 2 , where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0061] However, due to the parasitic capacitance between the gate and the first electrode of the second transistor T2, as shown in FIG. Figure 2As shown, after the compensation phase t2 ends, the second gate drive signal terminal G2 is reduced from a high level to a low level, that is, the gate of the second transistor T2 is reduced from a high level to a low level, and the voltage of the first electrode of the second transistor T2 is reduced under the capacitive coupling effect, and the voltage of the node N connected to the first electrode of the second transistor T2 is also reduced accordingly. According to the above-mentioned driving transistor output current formula, it can be seen that the voltage drop of node N (that is, the gate of the driving transistor) will affect the output current of the driving transistor. In order to ensure that the driving transistor outputs the required driving current normally, the source driving circuit needs to provide a data signal with a higher voltage value to the data signal terminal through the data line. Through simulation, when the above-mentioned pixel driving circuit displays grayscale 0, the voltage provided by the source driving circuit to the data line needs to be greater than 6.3V, but the maximum voltage provided by the existing source driving circuit to the data line is 6V, which cannot meet the normal display requirements.

[0062] Based on this, this exemplary embodiment provides an array substrate, which may include a pixel driving circuit and data lines. The circuit structure of the pixel driving circuit may be as follows: Figure 1 As shown, the driving method can be as follows Figure 2 As shown. Figure 3 The figure shows a structural layout of an exemplary embodiment of an array substrate of the present disclosure. The array substrate may further include: a base substrate 0, a first conductive layer, the first conductive layer being arranged on one side of the base substrate 0, the first conductive layer may include: a first conductive portion 13, a first gate line 11, and a second gate line 12, the first conductive portion 13 may be used to form the gate of the driving transistor; the first gate line 11 may be located on one side of the first conductive portion 13, and a portion of the first gate line 11 may be used to form the gate of the first transistor; the second gate line 12 may be located on a side of the first gate line 11 away from the first conductive portion 13, and a portion of the second gate line 12 may be used to form the first gate of the second transistor.

[0063] In this exemplary embodiment, the array substrate arranges the second gate line 12 on the side of the first gate line 11 away from the first conductive portion 13. On the one hand, this arrangement increases the distance between the second gate line 12 and the first conductive portion 13, reducing the lateral capacitance between the second gate line 12 and the first conductive portion 13, thereby reducing the pull-down effect of the second transistor gate on the driving transistor gate after the compensation phase ends; on the other hand, the first gate line 11 and the first conductive portion 13 can form a lateral capacitance, such as Figure 2As shown, after the compensation phase t2 ends, the first transistor jumps from a low level to a high level, so that the gate of the first transistor can pull up the gate of the driving transistor. The array substrate provided in this exemplary embodiment reduces the distance between the first gate line 11 and the first conductive portion 13, increases the lateral capacitance between the first gate line 11 and the first conductive portion 13, and thus can enhance the pull-up effect of the gate of the first transistor on the gate of the driving transistor. On the other hand, the first gate line 11 is located between the first conductive portion 13 and the second gate line 12, and the first gate line 11 can provide a certain shielding effect for the second gate line 12, thereby further reducing the pull-down effect of the gate of the second transistor on the gate of the driving transistor. In this exemplary embodiment, the pull-up effect of the first gate line 11 on the first conductive portion 13 is stronger than the pull-down effect of the second gate line 12 on the first conductive portion 13, so that the array substrate can offset the pull-down effect of the second transistor on the gate of the driving transistor to a certain extent.

[0064] It should be understood that in other exemplary embodiments, the pixel driving circuit in the array substrate may also have other circuit structures. In the pixel driving circuit formed using LTPO technology, the N-type first transistor connected between the gate of the driving transistor and the second electrode will exert a pull-down effect on the gate of the driving transistor after the compensation phase. Accordingly, other exemplary embodiments may also utilize the above-mentioned array substrate structure design to reduce the pull-down effect of the gate of the N-type first transistor on the gate of the driving transistor and increase the pull-down effect of the gate of the P-type second transistor on the gate of the driving transistor, thereby weakening the pull-down effect of the second transistor on the gate of the driving transistor.

[0065] In this exemplary embodiment, Figure 3As shown, the first gate line 11 can be located on one side of the first conductive portion 13 in the first direction Y1 and extend along the second direction X, wherein the first direction Y1 and the second direction X intersect. For example, the first direction Y1 and the second direction X can be perpendicular. The first gate line 11 can include: a first extension portion 111 and a second extension portion 112, wherein the orthographic projection of the first extension portion 111 on the substrate is opposite to the orthographic projection of at least part of the first conductive portion 13 on the substrate in the first direction Y1; and the orthographic projection of the second extension portion 112 on the substrate is staggered with the orthographic projection of the first conductive portion 13 on the substrate in the first direction Y1. Both the first direction and the second direction can be directions parallel to the plane of the substrate. The phrase "the orthographic projection of the first extending portion 111 on the substrate is opposite to the orthographic projection of at least a portion of the first conductive portion 13 on the substrate in the first direction Y1" can be understood as meaning that the area covered by the orthographic projection of the first extending portion 111 on the substrate in the first direction Y1 and the third direction Y2 is completely overlapped with the area covered by the orthographic projection of at least a portion of the first conductive portion 13 on the substrate in the first direction Y1 and the third direction Y2, wherein the first direction Y1 and the third direction Y2 are opposite. The phrase "the orthographic projection of the second extending portion 112 on the substrate is intersected with the orthographic projection of the first conductive portion 13 on the substrate in the first direction Y1" can be understood as meaning that the area covered by the orthographic projection of the second extending portion 112 on the substrate in the first direction Y1 and the third direction Y2 is opposite to the area covered by the orthographic projection of the first conductive portion 13 on the substrate in the first direction Y1 and the third direction Y2, wherein the first direction Y1 and the third direction Y2 are opposite.

[0066] In this exemplary embodiment, the distance S1 between the orthographic projection of the first extension portion 111 on the substrate and the orthographic projection of the first conductive portion 13 on the substrate in the first direction Y1 may be smaller than the distance S2 between the orthographic projection of the second extension portion 112 on the substrate and the orthographic projection of the first conductive portion 13 on the substrate in the first direction Y1. Figure 3As shown, the distance S1 between the orthographic projection of the first extension portion 111 on the substrate and the orthographic projection of the first conductive portion 13 on the substrate in the first direction Y1 can refer to the distance in the first direction Y1 between the edge of the orthographic projection of the first extension portion 111 on the substrate facing the first conductive portion 13 and the edge of the orthographic projection of the first conductive portion 13 on the substrate facing the first extension portion 111. The distance S2 between the orthographic projection of the second extension portion 112 on the substrate and the first conductive portion 13 on the substrate in the first direction Y1 can refer to the distance in the first direction Y1 between the edge of the orthographic projection of the second extension portion 112 on the substrate facing the first conductive portion 13 and the edge of the orthographic projection of the first conductive portion 13 on the substrate facing the second extension portion 112. This configuration reduces the distance in the first direction between the first extension portion 111 and the first conductive portion 13, increasing the lateral capacitance between the first extension portion 111 and the first conductive portion 13, thereby further enhancing the pull-up effect of the first gate line on the gate of the driver transistor.

[0067] In this exemplary embodiment, Figure 3 As shown, the first extension portion 111 includes a third edge 1111 facing one side of the first conductive portion 13, and the first conductive portion 13 includes a fourth edge 131 facing one side of the first extension portion 111. The size of the orthographic projection of the third edge 1111 on the substrate in the second direction X can be equal to the size of the orthographic projection of the fourth edge 131 on the substrate in the second direction X. This arrangement can greatly increase the capacitance of the lateral capacitor formed by the first extension portion 111 and the first conductive portion 13, thereby further enhancing the pull-up effect of the first gate line on the gate of the driving transistor. Both the third edge 1111 and the fourth edge 131 can extend along the second direction. It should be understood that in other exemplary embodiments, the third edge 1111 and the fourth edge 131 may also extend in a direction intersecting the second direction. In this case, the "size of the orthogonal projection of the third edge 1111 on the substrate in the second direction X" can be understood as the size of the right-angled side of a right triangle with the orthogonal projection of the third edge 1111 on the substrate as the hypotenuse, and the "size of the orthogonal projection of the fourth edge 131 on the substrate in the second direction X" can be understood as the size of the right-angled side of a right triangle with the orthogonal projection of the fourth edge 131 on the substrate as the hypotenuse, extending in the second direction. Furthermore, the size of the orthogonal projection of the third edge 1111 on the substrate in the second direction X may be smaller than the size of the orthogonal projection of the fourth edge 131 on the substrate in the second direction X.

[0068] In this exemplary embodiment, at least a portion of the second extension 112 can be used to form the gate of the first transistor. Because the orthographic projection of the second extension 112 on the substrate in the first direction is relatively large from the orthographic projection of the first conductive portion 13 on the substrate, this design can reserve sufficient space for the first transistor.

[0069] In this exemplary embodiment, Figure 3 As shown, the array substrate may include a plurality of the pixel driving circuits, the first conductive layer may include a plurality of the first conductive portions 13 spaced apart along the second direction X, the plurality of the first conductive portions 13 being used to respectively form the gates of the driving transistors in different pixel driving circuits; the first gate line 11 may include: a plurality of the first extension portions 111 and a plurality of the second extension portions 112, the first extension portions 111 may be arranged in a one-to-one correspondence with the first conductive portions 13, and the orthographic projection of the first extension portion 111 on the base substrate and the orthographic projection of at least part of the corresponding first conductive portion 13 on the base substrate are opposite in the first direction Y1.

[0070] In this exemplary embodiment, Figure 4 、 5 As shown, Figure 4 This is a structural diagram of another exemplary embodiment of the array substrate disclosed herein. Figure 5 for Figure 4The structural layout of the second conductive layer in the array substrate. The array substrate may further include a second conductive layer, which may be provided on a side of the first conductive layer away from the base substrate 0. The second conductive layer may include: a second conductive portion 22, a third conductive portion 23, and a first conductive line 21. The orthographic projection of the second conductive portion 22 on the base substrate 0 at least partially overlaps with the orthographic projection of the first conductive portion 13 on the base substrate 0, and is electrically connected to the first conductive portion 13 through a via 25. The third conductive portion 23 may be used to form the first electrode of the second transistor. The orthographic projection of the first gate line 11 on the base substrate 0 is located between the orthographic projection of the second conductive portion 22 on the base substrate and the orthographic projection of the third conductive portion 23 on the base substrate. The first conductive line 21 is connected between the second conductive portion 22 and the third conductive portion 23 so that the first electrode of the second transistor is connected to the gate of the driving transistor. The first conductive line 21 may extend along the first direction Y1. The orthographic projection of the first conductive line 21 on the base substrate intersects with the orthographic projection of the first gate line 11 on the base substrate. Since the orthographic projection of the first conductive line 21 on the substrate intersects the orthographic projection of the first gate line 11 on the substrate, a portion of the first conductive line 21 can form a parallel plate capacitor structure with a portion of the first gate line 11. Utilizing the coupling effect of this parallel plate capacitor structure, the first gate line 11 can pull up the first conductive line 21 after the compensation phase of the pixel drive circuit ends. Since the first conductive line 21 is electrically connected to the first conductive portion 13, this arrangement can further enhance the pull-up effect of the first gate line 11 on the first conductive portion 13.

[0071] In this exemplary embodiment, Figure 4 、 5 As shown, the second conductive layer may further include: a fourth conductive portion 24, the fourth conductive portion 24 may be connected to the first conductive line 21, the orthographic projection of the fourth conductive portion 24 on the substrate may at least partially overlap with the orthographic projection of the first gate line 11 on the substrate, wherein the fourth conductive portion 24 may include a first edge 241, the first conductive line 21 may include a second edge 211 connected to the first edge 241 of the fourth conductive portion, and the angle α between the orthographic projection of the first edge 241 on the substrate and the orthographic projection of the second edge 211 on the substrate is less than 180 degrees. Part of the fourth conductive portion 24 may form a parallel plate capacitor structure with part of the first gate line 11. By utilizing the coupling effect of the parallel plate capacitor structure, the first gate line 11 may pull up the fourth conductive portion 24 after the compensation stage of the pixel driving circuit ends. Since the fourth conductive portion 24 is electrically connected to the first conductive portion 13 through the first conductive line 21, this arrangement can further enhance the pull-up effect of the first gate line 11 on the first conductive portion 13. As shown Figure 4 、 5As shown, the fourth conductive portion 24 can be connected to the side of the first conductive line 21 opposite to the second direction X. Specifically, the orthographic projection of the fourth conductive portion 24 on the base substrate can at least partially overlap with the orthographic projection of the first extension portion 111 on the base substrate.

[0072] As shown in Table 1 below, C in Table 1 represents the parasitic capacitance formed by the first gate line and the first conductive portion (i.e., node N), and Vn represents the capacitance in the light-emitting stage. Figure 1 Table 1 shows the voltage of the middle node N and Vn corresponding to different parasitic capacitances C when the data signal voltage is 6 V. As can be seen from Table 1, the larger the parasitic capacitance C, the stronger the pull-up effect of the first gate line on the first conductive portion.

[0073] Table 1

[0074]

[0075]

[0076] In this exemplary embodiment, Figure 3 、 4As shown in FIG. 5 , the orthographic projection of the second gate line 12 on the substrate can be located between the orthographic projection of the first gate line 11 on the substrate and the orthographic projection of the third conductive portion 23 on the substrate. The second gate line 12 can include a third extension portion 123 and a fourth extension portion 124 alternately connected along the second direction X, wherein the orthographic projection of the third extension portion 123 on the substrate in the first direction Y1 can be smaller than the orthographic projection of the fourth extension portion 124 on the substrate in the first direction Y1. The orthographic projection of the first conductive line 21 on the substrate can intersect with the orthographic projection of the third extension portion 123 on the substrate. A portion of the third extension portion 123 can form a parallel plate capacitor structure with a portion of the first conductive line 21. Based on the coupling effect of this parallel plate capacitor structure, the third extension portion 123 can exert a pull-down effect on the first conductive line 21 after the pixel drive circuit compensation phase ends. Since the first conductive line 21 is electrically connected to the first conductive portion 13, the third extension portion 123 will exert a pull-down effect on the first conductive portion 13. In this exemplary embodiment, the dimension of the orthographic projection of the third extension portion 123 in the first direction Y1 is smaller than the dimension of the orthographic projection of the fourth extension portion 124 in the first direction Y1. This means that this exemplary embodiment reduces the dimension of the third extension portion 123 in the first direction Y1, thereby reducing the electrode area of ​​the parallel plate capacitor structure formed by the third extension portion 123 and the first conductive line 21. According to the capacitance calculation formula for a parallel plate capacitor, the capacitance of a parallel plate capacitor structure is proportional to its electrode area. This arrangement reduces the capacitance of the parallel plate capacitor structure formed by the third extension portion 123 and the first conductive line 21, thereby reducing the pull-down effect of the third extension portion 123 on the first conductive portion 13. Part of the fourth extension portion 124 can be used to form the first gate of the second transistor. The channel region of the second transistor can extend along the first direction Y1, thereby allowing the channel region of the second transistor to have a greater length, thereby reducing leakage current of the second transistor.

[0077] In this exemplary embodiment, Figure 4 、 5 As shown, the second conductive layer may further include a power line 26, which may extend along the first direction Y1 and may be used to provide Figure 1 The orthographic projection of the power line 26 on the substrate can intersect with the orthographic projection of the third extension portion 123 on the substrate. This arrangement can reduce the overlapping area between the power line 26 and the second gate line, thereby reducing the capacitive coupling effect caused by the power line 26 on the second gate line 12 when the voltage fluctuates.

[0078] like Figure 6 、 7 As shown, Figure 6 This is a structural diagram of another exemplary embodiment of the array substrate disclosed herein. Figure 7 for Figure 6 The array substrate may further include a third conductive layer, which may be disposed on a side of the second conductive layer away from the base substrate. Figure 5 、 6 As shown, the power line 26 may include a fifth extension 265, whose orthographic projection on the substrate opposes the orthographic projection of at least a portion of the first conductive portion 13 on the substrate in the second direction X. "The orthographic projection of the fifth extension 265 on the substrate opposes the orthographic projection of at least a portion of the first conductive portion 13 on the substrate in the second direction X" can be understood as meaning that the area covered by the orthographic projection of the fifth extension 265 on the substrate in the second direction and in the opposite direction to the second direction completely overlaps with the area covered by the orthographic projection of at least a portion of the first conductive portion 13 on the substrate in the second direction and in the opposite direction to the second direction. The third conductive layer may include the data line 31, which extends along the first direction Y1, and the orthographic projection of a portion of the data line 31 on the substrate may be located on the orthographic projection of the fifth extension 265 on the substrate. Among them, the fifth extension portion 265 is arranged between the data line 31 and the first conductive portion 13, and the fifth extension portion 265 receives a stable voltage, so that the fifth extension portion 265 can serve as a shielding layer to reduce the coupling capacitance between the data line 31 and the first conductive portion 13, thereby reducing the coupling effect of the data line 31 on the first conductive portion 13.

[0079] In this exemplary embodiment, Figure 6 、 7 As shown, the third conductive layer may further include a fifth conductive portion 35. The fifth conductive portion 35 may be connected to the power line 26 through a via 34. The orthographic projection of the fifth conductive portion 35 on the base substrate 0 may cover the orthographic projection of the first conductive portion 13 on the base substrate 0, and the orthographic projection of the fifth conductive portion 35 on the base substrate 0 may cover the orthographic projection of the second conductive portion 22 on the base substrate 0. The fifth conductive portion 35 covers the first conductive portion 13 and the second conductive portion 22, and the fifth conductive portion 35 receives a stable voltage. Thus, the fifth conductive portion 35 may serve as a shielding layer to reduce the capacitive coupling effect of other signals on the first conductive portion 13 and the second conductive portion 22. For example, the fifth conductive portion 35 may reduce the capacitive coupling effect of the data line and the anode layer on the first conductive portion 13 and the second conductive portion 22.

[0080] In this exemplary embodiment, Figure 6As shown, the first conductive layer may further include: a third gate line 14, the third gate line 14 is located on a side of the second gate line 12 away from the first conductive portion 13, and extends along the second direction X, and part of the third gate line 14 can be used to form the gate of the third transistor T3. Figure 6 As shown, the array substrate may further include a second active layer, which may be disposed between the first conductive layer and the second conductive layer. The second active layer may include a fourth active portion 6, which may extend along the first direction Y1. The orthographic projection of the fourth active portion 6 on the base substrate 0 intersects with the orthographic projection of the fourth extension portion 124 on the base substrate 0 to form Figure 1 The orthographic projection of the fourth active portion 6 on the substrate substrate 0 intersects with the orthographic projection of the third gate line 14 on the substrate substrate 0 to form Figure 1 The orthographic projection of the fifth conductive portion 35 on the substrate 0 may also cover the orthographic projections of the second transistor T2 and the third transistor T3 on the substrate 0. The material of the fourth active portion 6 may be a metal oxide, such as indium gallium zinc oxide. Accordingly, the second transistor and the third transistor may be metal oxide transistors. Metal oxide transistors may have characteristics that change under light conditions. By covering the second transistor T2 and the third transistor T3 with the fifth conductive portion 35, the influence of light on the output characteristics of the second transistor T2 and the third transistor T3 can be avoided.

[0081] The following exemplary embodiment describes the overall structure of the array substrate in detail:

[0082] like Figure 8-19 As shown, Figure 8 is the structural layout of the first active layer; Figure 9 is the structural layout of the first conductive layer; Figure 10 is the structural layout of the second active layer; Figure 11 A combined layout of the first active layer, the first conductive layer, and the second active layer; Figure 12 is the structural layout of the fourth conductive layer; Figure 13 A combined layout of the first active layer, the first conductive layer, the second active layer, and the fourth conductive layer; Figure 14 is the structural layout of the second conductive layer; Figure 15 A combined layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, and the second conductive layer; Figure 16 is the structural layout of the third conductive layer; Figure 17 A combined layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, the second conductive layer, and the third conductive layer; Figure 18 is the structural layout of the anode layer; Figure 19It is a combination layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, the second conductive layer, the third conductive layer, and the anode layer.

[0083] like Figure 11 、 8 As shown, the first active layer may include a first active portion 51 and a second active portion 52 extending along a first direction Y1, with the first active portion 51 and the second active portion 52 spaced apart along a second direction X. A third active portion 53 is connected between the first active portion 51 and the second active portion 52. The first active portion 51 may include a first sub-active portion 511 and a second sub-active portion 514, and the second active portion 52 may include a third sub-active portion 525 and a fourth sub-active portion 526. The third active portion 53 may be used to form the channel region of the driving transistor; the first sub-active portion 511 may be used to form the channel region of the first transistor; the second sub-active portion 514 may be used to form the channel region of the fourth transistor; the third sub-active portion 525 may be used to form the channel region of the fifth transistor; and the fourth sub-active portion 526 may be used to form the channel region of the sixth transistor. In this exemplary embodiment, the first active layer may be made of polysilicon material. Accordingly, the driving transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be P-type low-temperature polysilicon transistors.

[0084] like Figure 11 、 9 As shown, the first conductive layer includes the above-mentioned first conductive portion 13, the first gate line 11, the second gate line 12, and the third gate line 14. In addition, the first conductive layer may further include a fifth gate line 15 and a sixth gate line 16. The fifth gate line 15 is located on the side of the first conductive portion 1 away from the first gate line, and the sixth gate line 16 is located on the side of the fifth gate line 15 away from the first conductive portion 13. The first gate line 11, the second gate line 12, the third gate line 14, the fifth gate line 15, and the sixth gate line 16 may all extend along the second direction X. The first gate line 11 may be used to provide Figure 1 The first gate line 11 may include a first gate portion 113; the second gate line 12 may be used to provide a first gate drive signal terminal. Figure 1 The second gate driving signal terminal in the second gate line 12 may include a second gate portion 125; the third gate line 14 may be used as a second reset signal line for providing Figure 1 The second reset signal terminal in the third gate line 14 may include a third gate portion 143; the fifth gate line 15 may be used as an enable signal line for providing Figure 1 The enable signal terminal in the fifth gate line 15 may include a fourth gate portion 154 and a fifth gate portion 155; the sixth gate line 16 may be used as a first reset signal line for providing Figure 1The first reset signal terminal of the sixth gate line 16 includes a sixth gate portion 166. The first gate portion 113 can be used to form the gate of the first transistor T1, the second gate portion 125 can be used to form the first gate of the second transistor; the third gate portion 143 can be used to form the first gate of the third transistor; the fourth gate portion 154 can be used to form the gate of the fourth transistor; the fifth gate portion 155 can be used to form the gate of the fifth transistor; and the sixth gate portion 166 can be used to form the gate of the sixth transistor. The first gate portion 113 can be located on the second extension portion 112, and the second gate portion 125 can be located on the fourth extension portion 124.

[0085] like Figure 11 、 10 As shown, the second active layer may include a plurality of the fourth active portions 6 extending along the first direction Y1, the plurality of fourth active portions 6 may be spaced apart along the second direction X, and the plurality of fourth active portions 6 may be arranged in a one-to-one correspondence with the plurality of pixel driving circuits. Figure 10 As shown, the fourth active portion 6 may include a fifth sub-active portion 62 and a sixth sub-active portion 63. The fifth sub-active portion 62 may form the channel region of the second transistor, and the sixth sub-active portion 63 may form the channel region of the third transistor. The second gate line 12 may shield the fifth sub-active portion 62 from light, thereby preventing the output characteristics of the second transistor from being affected by light. The third gate line 14 may shield the sixth sub-active portion 63 from light, thereby preventing the output characteristics of the third transistor from being affected by light.

[0086] like Figure 12 、 13As shown, the fourth conductive layer may include a fourth gate line 74, a fifth gate line 75, a sixth gate line 76, and a sixth conductive portion 72. The fourth gate line 74, the fifth gate line 75, and the sixth gate line 76 may all extend along the second direction X. The fourth gate line 74 may be connected to the second gate line 12 via a via in a routing area surrounding the display area; the fifth gate line 75 may be connected to the third gate line 14 via a via in a routing area surrounding the display area. The orthographic projection of the first gate line 11 on the substrate is located between the orthographic projection of the first conductive portion 13 on the substrate and the orthographic projection of the fourth gate line 74 on the substrate. The fourth gate line 74 includes a sixth extension portion 746 and a seventh extension portion 747 alternately connected along the second direction X. The orthographic projection of the sixth extension portion 746 on the substrate in the first direction Y1 is smaller than the orthographic projection of the seventh extension portion 747 on the substrate in the first direction Y1. A portion of the seventh extension portion 747 may form the second gate of the second transistor. The fifth gate line 75 may include a seventh gate portion 753, which may form the second gate of the third transistor. The fourth gate line 74 and the second gate line 12 connected in parallel may increase the transmission speed of the gate drive signal transmitted thereon, thereby increasing the response speed of the second transistor. The fifth gate line 75 and the third gate line 14 connected in parallel may increase the transmission speed of the gate drive signal transmitted thereon, thereby increasing the response speed of the third transistor. The sixth gate line 76 may be used as an initial signal line to provide Figure 1 The initial signal end in the sixth conductive part 72 may include a plurality of first sub-conductive parts 721 and a plurality of second sub-conductive parts 722, and the plurality of first sub-conductive parts 721 and the plurality of second sub-conductive parts 722 are alternately distributed in sequence along the second direction X, and the second sub-conductive parts 722 are connected between adjacent first sub-conductive parts 721. The orthographic projection of the first sub-conductive part 721 on the base substrate can cover the orthographic projection of the first conductive part 13 on the base substrate. Among them, the second sub-conductive part 722 can be connected to the power line in the second conductive layer through a via, so that the first sub-conductive part 721 can serve as a shielding layer to reduce the capacitive coupling effect of other signals (for example, data lines, anode signals) on the first conductive part 13.

[0087] like Figure 14 、 15As shown, the second conductive layer includes the above-mentioned power line 26, the first conductive line 21, the third conductive part 23, the fourth conductive part 24, and the second conductive part 22. In addition, the second conductive layer may further include a first connecting part 27, a second connecting part 28, a third connecting part 29, and a fourth connecting part 201. The first connecting part 27 can be connected to the second active part 52 through a via 202 to connect the second pole of the sixth transistor. The first connecting part 27 is also connected to the sixth gate line 76 through a via 203, so that an initial signal terminal can be provided to the second pole of the sixth transistor through the sixth gate line 76. In addition, the first connecting part 27 can also be connected to the fourth active part 6 in the next row of pixel driving circuits through a via 204 to provide an initial signal terminal to the third transistor in the next row of pixel driving circuits through the sixth gate line 76. The second connecting part 28 can be connected to the second active part 52 through a via 205 to connect the second pole of the fifth transistor. The third connecting portion 29 is connected to the fourth active portion 6 through the via 206 to connect to the second electrode of the second transistor. The third connecting portion 29 can be connected to the second active portion 52 through the via 207 to connect to the second electrode of the driving transistor, thereby connecting the second electrode of the second transistor to the second electrode of the driving transistor. The fourth connecting portion 201 can be connected to the first active portion 51 through the via 208 to connect to the first electrode of the first transistor. The orthographic projection of the first conductive line 21 on the substrate can intersect with the orthographic projection of the sixth extension portion 746 on the substrate, thereby reducing the capacitance of the parallel plate capacitor structure formed by the sixth extension portion 746 and the first conductive line 21, thereby reducing the pull-down effect of the sixth extension portion 746 on the first conductive portion 13 after the compensation stage t2 ends. Figure 4 The second conductive portion 22 is connected to the first conductive portion 13 through the via 25, wherein the via 25 can penetrate Figure 13 The first sub-conductive portion 721 is formed in the via hole 25, and the conductive material in the via hole 25 is insulated from the first sub-conductive portion 721. A specific method for forming this structure may be to form a fourth dielectric layer on the side of the fourth conductive layer facing away from the base substrate, form a first via hole on the fourth dielectric layer that penetrates the fourth conductive layer and extends to the first conductive portion 13, form a fifth dielectric layer on the fourth dielectric layer, form the via hole 25 on the fifth dielectric layer, and the orthographic projection of the via hole 25 on the base substrate is located within the orthographic projection of the first via hole on the base substrate, and then form the second conductive portion on the fifth dielectric layer and fill the via hole 25.

[0088] like Figure 16 、 17As shown, the third conductive layer may include the above-mentioned data line 31 and the fifth conductive part 35. In addition, the third conductive layer may further include a fifth connecting part 32. The data line 31 may be connected to the fourth connecting part 201 through a via 33 to connect to the first electrode of the first transistor. The fifth conductive part 35 may be connected to the power line 26 through a via 34. The fifth connecting part 32 may be connected to the second connecting part 28 through a via 36 to connect to the second electrode of the fifth transistor. The distance between the first conductive part 13 and the first sub-conductive part 721 may be greater than the distance between the second conductive part 22 and the fifth conductive part 35. Figure 1 The two electrodes of the intermediate capacitor C may be mainly formed by the second conductive portion 22 and the fifth conductive portion 35 .

[0089] like Figure 18 、 19 As shown, the anode layer may include a first anode portion 81, a second anode portion 82, and a third anode portion 83. The first anode portion 81 may be connected to the fifth connection portion 32 via a via 84 to connect to the second electrode of the fifth transistor; the second anode portion 82 may be connected to the fifth connection portion 32 in another pixel driving circuit via a via 85; and the third anode portion 83 may be connected to the fifth connection portion 32 in another pixel driving circuit via a via 86. A G light-emitting unit may be formed on the first anode portion 81; an R light-emitting unit may be formed on the second anode portion 82; and a B light-emitting unit may be formed on the third anode portion 83.

[0090] like Figure 20 As shown, along Figure 17Partial cross-sectional view along the dashed line A. The array substrate may include a base substrate 0, a barrier layer 02 located on one side of the base substrate 0, a second buffer layer 03 located on the side of the barrier layer facing away from the base substrate 0, a first active layer (including a third active portion 53) located on the side of the second buffer layer 03 facing away from the base substrate 0, a second gate insulating layer 05 located on the side of the first active layer facing away from the base substrate, a first conductive layer (including a first conductive portion 13 and a second gate portion 125) located on the side of the second gate insulating layer facing away from the base substrate, a first dielectric layer 07 located on the side of the first conductive layer facing away from the base substrate, a first buffer layer 08 located on the side of the first dielectric layer 07 facing away from the base substrate 0, a second active layer (including a fifth sub-active portion 62) located on the side of the first buffer layer 08 facing away from the base substrate 0, and a The first gate insulating layer (including the first insulating portion 0101 and the second insulating portion 0102), the fourth conductive layer located on the side of the first gate insulating layer facing away from the substrate (including the first sub-conductive portion 721, the seventh extension portion 747, and the second sub-conductive portion 722), the second dielectric layer 012 located on the side of the fourth conductive layer facing away from the substrate, the second conductive layer (including the second conductive portion 22 and the power line 26) located on the side of the second dielectric layer 012 facing away from the substrate, the passivation layer 014 located on the side of the second conductive layer facing away from the substrate, the first planarizing layer 015 located on the side of the passivation layer 014 facing away from the substrate, the third conductive layer (including the fifth conductive portion 35) located on the side of the first planarizing layer 015 facing away from the substrate, and the second planarizing layer 19 located on the side of the third conductive layer facing away from the substrate. The third active portion 53 is used to form the channel region of the drive transistor DT, and the fifth sub-active portion 62 is used to form the channel region of the second transistor T2.

[0091] In this exemplary embodiment, the substrate may include a first polyimide (PI) layer, a first silicon oxide (SiO) layer, an amorphous silicon layer, a second polyimide (PI) layer, and a second silicon oxide layer, arranged in sequence. The barrier layer 02 may be located on the side of the second silicon oxide layer facing away from the first polyimide (PI) layer. The thickness of the first polyimide (PI) layer and the second polyimide (PI) layer may each be 90,000-110,000 ± 5% angstroms, for example, 90,000 angstroms, 95,000 angstroms, and 110,000 angstroms. The thickness of the first silicon oxide layer may be 5,000-7,000 angstroms, for example, 5,000 angstroms, 5,500 angstroms, and 7,000 angstroms. The thickness of the amorphous silicon layer may be 40-60 angstroms, for example, 40 angstroms, 45 angstroms, and 60 angstroms. The thickness of the second silicon oxide layer may be 4,500-6,500 angstroms, for example, 4,500 angstroms, 5,000 angstroms, and 6,500 angstroms.

[0092] In this exemplary embodiment, the second buffer layer 03 may include a first silicon nitride (SiN) layer and a third silicon oxide layer disposed sequentially, and the first silicon nitride layer may be located between the third silicon oxide layer and the substrate. The thickness of the first silicon nitride layer may be 900-1100 angstroms, for example, 900 angstroms, 950 angstroms, or 1100 angstroms; the thickness of the third silicon oxide layer may be 2000-4000 angstroms, for example, 2000 angstroms, 2500 angstroms, or 4000 angstroms. The first active layer may be a polycrystalline silicon layer, and the thickness of the first active layer may be 400-600 angstroms, for example, 400 angstroms, 500 angstroms, or 600 angstroms. The second gate insulating layer 05 may be a silicon oxide layer, and the thickness of the second gate insulating layer 05 may be 500-2000 angstroms, for example, 500 angstroms, 1500 angstroms, or 2000 angstroms. The first conductive layer and the fourth conductive layer may both be molybdenum layers, and the thickness of the first conductive layer and the fourth conductive layer may both be 1500-2500 angstroms, for example, 1500 angstroms, 2000 angstroms, and 2500 angstroms. The first dielectric layer 07 may be a silicon nitride layer, and the thickness of the first dielectric layer 07 may be 1200-1400 angstroms, for example, 1200 angstroms, 1300 angstroms, and 1400 angstroms. The first buffer layer 08 may be a silicon oxide layer, and the thickness of the first buffer layer 08 may be 3000-5000 angstroms, for example, 3000 angstroms, 3500 angstroms, and 5000 angstroms. The second active layer may be an indium gallium zinc oxide (IGZO) layer, and the thickness of the second active layer may be 300-500 angstroms, for example, 300 angstroms, 350 angstroms, and 500 angstroms. The second gate insulating layer 05 may be a silicon oxide layer, and the thickness of the second gate insulating layer 05 may be 1000-2000 angstroms, for example, 1000 angstroms, 1500 angstroms, or 2000 angstroms. The second conductive layer may include a first titanium layer, an aluminum layer, and a second titanium layer stacked in sequence, and the thickness of the first titanium layer and the second titanium layer may each be 300-700 angstroms, for example, 300 angstroms, 450 angstroms, and 700 angstroms. The thickness of the aluminum layer may each be 4500-6500 angstroms, for example, 4500 angstroms, 5000 angstroms, or 6500 angstroms. The second planarizing layer 19 may be a polyimide (PI) layer, and the thickness of the second planarizing layer 19 may be 10,000-20,000 angstroms, for example, 10,000 angstroms, 16,000 angstroms, or 20,000 angstroms.

[0093] In this exemplary embodiment, an anode layer may be further provided on the side of the second planar layer 19 facing away from the substrate, a pixel defining layer may be further provided on the side of the anode layer facing away from the substrate, and a support column may be further provided on the side of the pixel defining layer facing away from the substrate. The pixel defining layer may be a polyimide (PI) layer, and the thickness of the pixel defining layer may be 10,000-20,000 angstroms, for example, 10,000 angstroms, 16,000 angstroms, or 20,000 angstroms. The support column may be a polyimide (PI) layer, and the thickness of the support column may be 10,000-20,000 angstroms, for example, 10,000 angstroms, 16,000 angstroms, or 20,000 angstroms. The anode layer may include a first indium tin oxide layer, a silver layer, and a second indium tin oxide layer, which are sequentially provided. The thickness of the first indium tin oxide layer and the second indium tin oxide layer may be 50-100 angstroms, for example, 50 angstroms, 80 angstroms, and 100 angstroms, and the thickness of the silver layer may be 500-1500 angstroms, for example, 500 angstroms, 800 angstroms, and 1500 angstroms.

[0094] It should be understood that the structural film layers described above may also be made of other materials and have other thicknesses. For example, the dielectric layer and passivation layer may be made of materials such as silicon nitride or transparent organic resin, and the planar layer may be made of materials such as transparent polyimide (CPI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). The conductive layer may also be made of metal materials such as copper and molybdenum.

[0095] In this exemplary embodiment, because the second conductive portion 22 needs to form a capacitor electrode, it needs to be designed to have a large area. As a result, within the limited planar space, it is difficult for the fifth conductive portion 35 to completely cover the second conductive portion 22, which in turn makes the second conductive portion 22 susceptible to external noise interference. Furthermore, the larger area of ​​the second conductive portion 22 also easily forms a large parasitic capacitance with other structures. Due to this parasitic capacitance coupling effect, the gate of the driver transistor is more susceptible to external noise interference.

[0096] like Figure 21 、 22 As shown, Figure 21 This is a structural diagram of the second conductive layer in another exemplary embodiment of the array substrate disclosed herein. Figure 22 This is a combination layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, the second conductive layer, and the third conductive layer in another exemplary embodiment of the array substrate disclosed herein. Figure 22 The combined layout shown is Figure 17 The only difference between the combined layout shown is the structure of the second conductive layer. Figure 23 As shown, Figure 22Partial cross-sectional view along dotted line A in FIG. The array substrate may include a base substrate 0, a barrier layer 02 located on one side of the base substrate 0, a second buffer layer 03 located on a side of the barrier layer facing away from the base substrate 0, a first active layer (including a third active portion 53) located on a side of the second buffer layer 03 facing away from the base substrate 0, a second gate insulating layer 05 located on a side of the first active layer facing away from the base substrate, a first conductive layer (including a first conductive portion 13 and a second gate portion 125) located on a side of the second gate insulating layer facing away from the base substrate, a first dielectric layer 07 located on a side of the first conductive layer facing away from the base substrate, a first buffer layer 08 located on a side of the first dielectric layer 07 facing away from the base substrate 0, a second active layer (including a fifth sub-active portion 62) located on a side of the first buffer layer 08 facing away from the base substrate 0, and a second active layer 05 located on a side of the second active layer facing away from the base substrate. The first gate insulating layer (including the insulating portion 0102) on the side of the base substrate, the fourth conductive layer (including the first sub-conductive portion 721, the seventh extension portion 747, and the second sub-conductive portion 722) located on the side of the first gate insulating layer facing away from the base substrate, the second dielectric layer 012 located on the side of the fourth conductive layer facing away from the base substrate, the second conductive layer (including the second conductive portion 22 and the power line 26) located on the side of the second dielectric layer 012 facing away from the base substrate, the passivation layer 014 located on the side of the second conductive layer facing away from the base substrate, the first planarizing layer 015 located on the side of the passivation layer 014 facing away from the base substrate, the third conductive layer (including the fifth conductive portion 35) located on the side of the first planarizing layer 015 facing away from the base substrate, and the second planarizing layer 19 located on the side of the third conductive layer facing away from the base substrate. The third active portion 53 is used to form the channel region of the drive transistor DT, and the fifth sub-active portion 62 is used to form the channel region of the second transistor T2. The second conductive portion 22 is connected to the first conductive portion 13 through a via 87.

[0097] The first buffer layer 08 may be provided with a groove 411, the orthographic projection of the groove 411 on the base substrate at least partially overlapping with the orthographic projection of the first conductive portion 13 on the base substrate. The first sub-conductive portion 721 is located at the bottom of the groove 411, and the orthographic projection of the first sub-conductive portion 721 on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion 13 on the base substrate. The second sub-conductive portion 722 may be located outside the groove 411, that is, the orthographic projection of the second sub-conductive portion 722 on the base substrate does not intersect with the orthographic projection of the groove 411 on the base substrate.

[0098] The array substrate provided in this exemplary embodiment has a groove 411 disposed in the first buffer layer 08, and a first sub-conductive portion 721 disposed at the bottom of the groove 411. The provision of the groove 411 reduces the distance between the first sub-conductive portion 721 and the first conductive portion 13, thereby allowing the first sub-conductive portion 721 and the first conductive portion 13 to form two electrodes of a capacitor C. This exemplary embodiment eliminates the need for the extremely large second conductive portion 22 used in related art as a capacitor electrode, thereby reducing the noise impact of external signals on the gate of the drive transistor.

[0099] The ratio of the orthographic projection area of ​​the second conductive portion 22 on the substrate 0 to the orthographic projection area of ​​the first conductive portion 13 on the substrate 0 may be 4%-25%. For example, the ratio of the orthographic projection area of ​​the second conductive portion 22 on the substrate 0 to the orthographic projection area of ​​the first conductive portion 13 on the substrate 0 may be any one of 4%, 8%, 10%, 12%, 15%, 20%, and 25%.

[0100] In this exemplary embodiment, the ratio of the orthographic projection area of ​​the second conductive portion 22 on the base substrate 0 to the orthographic projection area of ​​the via hole 87 on the base substrate can be 1-2.5. For example, the ratio of the orthographic projection area of ​​the second conductive portion 22 on the base substrate 0 to the orthographic projection area of ​​the via hole 87 on the base substrate can be 1, 1.2, 1.5, 2.0, 2.5, etc. It should be understood that in other exemplary embodiments, due to process errors and other reasons, the orthographic projection area of ​​the second conductive portion 22 on the base substrate 0 can be slightly smaller than the orthographic projection area of ​​the via hole 87 on the base substrate.

[0101] In this exemplary embodiment, as shown in Table 2 below, Table 2 shows the data signal voltages required for different sizes of drive transistors DT at different brightness levels in LTPO technology, and the data signal voltages required for different sizes of drive transistors DT at different brightness levels in LPTS technology (transistors in the pixel drive circuit are all low-temperature polysilicon transistors). Wherein, DT size represents the width-to-length ratio of the channel region of the drive transistor DT; I represents the output current of the drive transistor; Vdata represents the data signal voltage; R255 (super bright), R255 (outdoor), R255 (indoor), and R0 represent different brightness levels of red pixel units; G255 (super bright), G255 (outdoor), G255 (indoor), and G0 represent different brightness levels of green pixel units; B255 (super bright), B255 (outdoor), B255 (indoor), and B0 represent different brightness levels of blue pixel units; and DR represents the driving voltage range, i.e., the difference between the data signal voltage at maximum brightness and the data signal voltage at minimum brightness.

[0102] Table 2

[0103]

[0104] It can be seen from Table 2 that, under the same size and brightness conditions, the data signal voltage required for the driving transistor DT in the LTPO technology is greater than the data signal voltage required for the driving transistor in the LTPS technology. This table verifies that the second transistor in the LTPO technology will lower the gate voltage of the driving transistor after the compensation phase, so that the pixel unit requires a higher data signal voltage when displaying the same brightness. In the prior art, the limit value of the output voltage of the source driver circuit is 6V. It can be seen from Table 2 that in the LTPO technology, when the brightness is R0 (i.e., no light emission), the data signal voltage required for the driving transistor is already greater than 6V, so that the display panel formed by the LTPO technology cannot be normally at the R0 brightness.

[0105] From Table 1 and Table 2, it can be seen that when the parasitic capacitance C is 5fF, the first gate line can pull up the first conductive part by 0.5V, so that in TPO technology, when the brightness is R0 (i.e., no light), the data signal voltage required to drive the transistor is within 6V.

[0106] Furthermore, Table 2 shows that the R pixel unit, the G pixel unit, and the B pixel unit have different drive voltage ranges. The source driver circuit needs to provide data signals with different drive voltage ranges to the R pixel unit, the G pixel unit, and the B pixel unit. The source driver circuit needs to switch between different drive voltage ranges, and therefore consumes more power. In this exemplary embodiment, the array substrate may include: an R pixel driver circuit, a G pixel driver circuit, and a B pixel driver circuit; the width-to-length ratio of the drive transistor channel region in the R pixel driver circuit, the width-to-length ratio of the drive transistor channel region in the G pixel driver circuit, and the width-to-length ratio of the drive transistor channel region in the G pixel driver circuit are not all the same. That is, among the R pixel driver circuit, the G pixel driver circuit, and the B pixel driver circuit, the width-to-length ratio of the drive transistor channel region in at least one of the pixel driver circuits is not equal to the width-to-length ratio of the drive transistor channel region in the other pixel driver circuits. For example, the width-to-length ratio of the drive transistor channel region in the R pixel driver circuit may be 3.5 / 40, and the width-to-length ratio of the drive transistor channel region in the B pixel driver circuit may be 3.5 / 25. From Table 2, it can be seen that compared with the channel region of the driving transistor in the R pixel driving circuit, the channel region of the driving transistor in the G pixel driving circuit, and the channel region of the driving transistor in the R pixel driving circuit having the same width-to-length ratio, this setting can reduce the difference in driving voltages between the R pixel unit, the G pixel unit, and the B pixel unit, thereby reducing the power consumption of the source driving circuit.

[0107] like Figure 8 、 19As shown, the driving transistor channel region in the B pixel unit is "Z"-shaped, while the driving transistor channel region in the R pixel unit and the driving transistor channel region in the G pixel unit are "S"-shaped. The width-to-length ratio of the driving transistor channel region in the B pixel unit is smaller than the width-to-length ratio of the driving transistor channel region in the R pixel unit and the width-to-length ratio of the driving transistor channel region in the G pixel unit.

[0108] This exemplary embodiment further provides a display device, wherein the display device may include the above-mentioned array substrate. The display device may be a mobile phone, a tablet computer, a television, or other display device.

[0109] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that fall within the generality of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0110] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. An array substrate, wherein: The array substrate includes a pixel driving circuit and a data line, the pixel driving circuit includes a driving transistor, a first transistor connected between a first electrode of the driving transistor and the data line, and a second transistor connected between a gate electrode and a second electrode of the driving transistor, the driving transistor and the first transistor are P-type transistors, and the second transistor is an N-type transistor. The array substrate further includes: substrate; A first conductive layer is provided on one side of the base substrate, and the first conductive layer includes: a first conductive portion, configured to form a gate of the driving transistor; a first gate line located on one side of the first conductive portion, wherein a portion of the first gate line is used to form a gate of the first transistor; a second gate line located on a side of the first gate line away from the first conductive portion, wherein a portion of the second gate line is used to form a first gate of the second transistor; The array substrate further includes: A second conductive layer is provided on a side of the first conductive layer facing away from the base substrate, and the second conductive layer includes: a second conductive portion, the orthographic projection of the second conductive portion on the base substrate at least partially overlapping with the orthographic projection of the first conductive portion on the base substrate, and being electrically connected to the first conductive portion through a via; a third conductive portion, configured to form a first electrode of the second transistor, wherein an orthographic projection of the first gate line on the substrate is located between an orthographic projection of the second conductive portion on the substrate and an orthographic projection of the third conductive portion on the substrate; A first conductive line is connected between the second conductive portion and the third conductive portion, and an orthographic projection of the first conductive line on the base substrate intersects with an orthographic projection of the first gate line on the base substrate.

2. The array substrate according to claim 1, wherein: The first gate line is located on one side of the first conductive portion in the first direction and extends along a second direction, the first direction and the second direction intersect, and the first gate line includes: a first extending portion, wherein an orthographic projection of the first extending portion on the base substrate is opposite to an orthographic projection of at least a portion of the first conductive portion on the base substrate in the first direction; A second extending portion, wherein an orthographic projection of the second extending portion on the base substrate and an orthographic projection of the first conductive portion on the base substrate are offset in the first direction.

3. The array substrate according to claim 2, wherein: The distance between the orthographic projection of the first extension portion on the base substrate and the orthographic projection of the first conductive portion on the base substrate in the first direction is smaller than the distance between the orthographic projection of the second extension portion on the base substrate and the orthographic projection of the first conductive portion on the base substrate in the first direction.

4. The array substrate according to claim 3, wherein: The first extension portion includes a third edge facing the first conductive portion, the first conductive portion includes a fourth edge facing the first extension portion, and the size of the third edge's orthographic projection on the base substrate in the second direction is equal to the size of the fourth edge's orthographic projection on the base substrate in the second direction.

5. The array substrate according to claim 3, wherein: At least a portion of the second extension is used to form a gate of the first transistor.

6. The array substrate according to claim 3, wherein: The array substrate includes a plurality of the pixel driving circuits, the first conductive layer includes a plurality of the first conductive portions spaced apart along the second direction, and the plurality of the first conductive portions are used to respectively form gates of driving transistors in different pixel driving circuits; The first gate line includes: a plurality of first extension portions, each of the first extension portions corresponding to the first conductive portion, wherein an orthographic projection of each first extension portion on the base substrate and an orthographic projection of at least a portion of the corresponding first conductive portion on the base substrate are opposite to each other in the first direction; A plurality of second extension portions are connected between adjacent first extension portions.

7. The array substrate according to claim 1, wherein: The second conductive layer further includes: a fourth conductive portion connected to the first conductive line, wherein an orthographic projection of the fourth conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first gate line on the base substrate; The fourth conductive portion includes a first edge, the first conductive line includes a second edge connected to the first edge of the fourth conductive portion, and an angle between an orthographic projection of the first edge on the base substrate and an orthographic projection of the second edge on the base substrate is less than 180 degrees.

8. The array substrate according to claim 7, wherein: The first gate line is located on one side of the first conductive portion in the first direction and extends along a second direction, the first direction and the second direction intersect, and the first gate line includes: a first extending portion, wherein an orthographic projection of the first extending portion on the base substrate is opposite to an orthographic projection of at least a portion of the first conductive portion on the base substrate in the first direction; a second extending portion, wherein an orthographic projection of the second extending portion on the base substrate and an orthographic projection of the first conductive portion on the base substrate are offset in the first direction; An orthographic projection of the fourth conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first extending portion on the base substrate.

9. The array substrate according to claim 1, wherein: The orthographic projection of the second gate line on the base substrate is located between the orthographic projection of the first gate line on the base substrate and the orthographic projection of the third conductive portion on the base substrate; The second gate line includes a third extension portion and a fourth extension portion alternately connected in sequence along a second direction, wherein a size of an orthographic projection of the third extension portion on the base substrate in the first direction is smaller than a size of an orthographic projection of the fourth extension portion on the base substrate in the first direction, and the first direction and the second direction intersect; An orthographic projection of the first conductive line on the base substrate intersects an orthographic projection of the third extension portion on the base substrate.

10. The array substrate according to claim 9, wherein: A portion of the fourth extension portion is used to form a first gate of the second transistor.

11. The array substrate according to claim 1, wherein: The second conductive layer further includes: a power line extending along a first direction; The array substrate further includes: The third conductive layer is arranged on a side of the second conductive layer away from the base substrate.

12. The array substrate according to claim 11, wherein: The power line includes a fifth extension portion, the orthographic projection of the fifth extension portion on the base substrate is opposite to the orthographic projection of at least part of the first conductive portion on the base substrate in a second direction, the first direction and the second direction intersect, and the third conductive layer includes: The data line extends along the first direction, and a portion of the data line's orthographic projection on the base substrate is located on the orthographic projection of the fifth extension portion on the base substrate.

13. The array substrate according to claim 11, wherein: The third conductive layer includes: A fifth conductive portion is connected to the power line through a via, wherein the orthographic projection of the fifth conductive portion on the base substrate covers the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection of the fifth conductive portion on the base substrate covers the orthographic projection of the second conductive portion on the base substrate.

14. The array substrate according to claim 11, wherein: The array substrate further includes a third transistor, a first electrode of the third transistor is connected to the gate of the driving transistor, and the second transistor and the third transistor are both N-type metal oxide transistors. The first conductive layer further comprises: a third gate line, located on a side of the second gate line away from the first conductive portion and extending along a second direction, a portion of the third gate line being used to form a gate of the third transistor, and the first direction and the second direction intersecting; The third conductive layer further includes: A fifth conductive portion is connected to the power line through a via hole, and the orthographic projection of the fifth conductive portion on the base substrate covers the orthographic projections of the second transistor and the third transistor on the base substrate.

15. The array substrate according to claim 1, wherein: The array substrate includes: an R pixel driving circuit, a G pixel driving circuit, and a B pixel driving circuit; The width-to-length ratios of the driving transistor channel regions in the R pixel driving circuit, the G pixel driving circuit, and the B pixel driving circuit are not all the same.

16. The array substrate according to claim 15, wherein: The width-to-length ratio of the driving transistor channel region in the R pixel driving circuit is equal to the width-to-length ratio of the driving transistor channel region in the G pixel driving circuit, and the width-to-length ratio of the driving transistor channel region in the R pixel driving circuit is less than the width-to-length ratio of the driving transistor channel region in the B pixel driving circuit.

17. The array substrate according to claim 16, wherein: The width-to-length ratio of the channel region of the driving transistor in the R pixel driving circuit is 3.5 / 40, and the width-to-length ratio of the channel region of the driving transistor in the B pixel driving circuit is 3.5 / 25.

18. The array substrate according to claim 1, wherein: The array substrate further includes: a fourth conductive layer, stacked between the first conductive layer and the second conductive layer, the fourth conductive layer comprising: A fourth gate line extends along the second direction, the orthographic projection of the first gate line on the substrate is located between the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the fourth gate line on the substrate, and a portion of the fourth gate line is used to form the second gate of the second transistor.

19. The array substrate according to claim 18, wherein: The fourth gate line includes a sixth extension portion and a seventh extension portion alternately connected in sequence along the second direction; The size of the orthographic projection of the sixth extending portion on the base substrate in the first direction is smaller than the size of the orthographic projection of the seventh extending portion on the base substrate in the first direction, and the first direction and the second direction intersect; An orthographic projection of the first conductive line on the base substrate intersects an orthographic projection of the sixth extension portion on the base substrate.

20. The array substrate according to claim 19, wherein: A portion of the seventh extension portion is used to form a second gate of the second transistor.

21. The array substrate according to claim 18, wherein: The array substrate further includes: a first active layer, stacked between the base substrate and the first conductive layer, wherein a portion of the first active layer is used to form a channel region of the driving transistor; A second active layer is stacked between the fourth conductive layer and the first conductive layer, and a portion of the second active layer is used to form a channel region of the second transistor.

22. The array substrate according to claim 1, wherein: The array substrate further includes: an enable signal line, an initial signal line, an anode layer, a first reset signal line, a second reset signal line, and a power line. The pixel driving circuit further includes: a third transistor, having a first electrode connected to the gate of the driving transistor, a second electrode connected to the initial signal line, and a gate connected to the second reset signal line; a fourth transistor, a first electrode connected to the power line, a second electrode connected to the first electrode of the driving transistor, and a gate connected to the enable signal line; a fifth transistor, wherein a first electrode is connected to the second electrode of the driving transistor, a second electrode is connected to the anode layer, and a gate is connected to the enable signal line; a sixth transistor, having a first electrode connected to the second electrode of the fifth transistor, a second electrode connected to the initial signal line, and a gate connected to the first reset signal line; A capacitor is connected between the gate of the driving transistor and the power line.

23. The array substrate according to claim 22, wherein: The driving transistor, the fourth transistor, the fifth transistor, and the sixth transistor are P-type low-temperature polysilicon transistors.

24. A display device, wherein: The display device includes the array substrate described in any one of claims 1-23.

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