Method for conformal coating of multiple rows of surface mount components in a lidless bga package and products made therefrom

Abstract

A method for conformally coating passive surface mount components of a printed circuit substrate soldered to a lidless flip chip ball grid array package includes securing a reinforcement ring to the substrate prior to forming a conformal coating on the passive surface mount components. The reinforcement ring is secured to the substrate such that the plurality of passive surface mount components and integrated circuit die are contained within an opening formed by the reinforcement ring. After the reinforcement ring is secured to the substrate, a conformal coating is formed on the passive surface mount components. The conformal coating extends over, around a perimeter of, and under each of the passive surface mount components. Products manufactured according to the method are also disclosed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Provisional Patent Application No. 62 / 915,796, filed October 16, 2019, entitled “Method for Conformal Coating of Multi-Row Surface Mount Components in an Uncapped BGA Package and Products Manufactured Therefrom,” which is expressly incorporated herein by reference in its entirety. Background Technology

[0003] Electronic devices, including integrated circuits, are used in computing devices such as, but not limited to, laptops, desktop computers, tablets, smartphones, game consoles, televisions, set-top boxes, wearable devices, internet servers, printers, and other devices. Electronic devices may include integrated circuit dies and passive surface-mount components, such as chip capacitors, packaged together on the same printed circuit substrate. For example, chip capacitors can be used to decouple integrated circuits from voltage fluctuations in the power supply. Integrated circuit dies may have very dense circuitry and may operate at very high frequencies to provide continuously improving performance levels. Some integrated circuit dies may have multiple processor cores and / or very large memory arrays on a relatively small die. In operation, such devices may generate more than 100 watts of heat. If heat is allowed to accumulate on the die, the performance of the integrated circuit may be degraded and / or the lifespan of the integrated circuit may be significantly shortened.

[0004] In some electronic devices, integrated circuits are mounted on the printed circuit substrate of a package in an inverted or flip-chip configuration, allowing the bonding pads of the integrated circuit die to be directly soldered to the electrical connections of the printed circuit substrate. In such flip-chip ball grid array (BGA) packages, a package cap is attached to the printed circuit substrate to protect the die and provide structural support to the substrate. Before the cap is attached, a thermally conductive material, also known as a thermal interface material (TIM), is applied to the back side of the die to provide a thermal path between the die and the package cap. A high-surface-area heat sink can be coupled to the package cap, allowing air convection to remove heat from the package cap.

[0005] In some other electronic devices, a cover is not used so that the TIM (Temperature Injection Molding) can directly contact the heatsink. Removing the cover from the thermal path improves the efficiency of heat removal from the integrated circuit die. In this coverless BGA package, a reinforcing ring surrounding the integrated circuit die and passive surface mount components is fixed to the substrate rather than to the cover to provide structural support to the substrate. Attached Figure Description

[0006] The embodiments will be more readily understood from the following description when accompanied by the following figures, wherein the same reference numerals denote the same elements, and wherein:

[0007] Figure 1 This is a schematic top view of an electronic device according to an example set forth in this disclosure.

[0008] Figure 2 This is based on an example set forth in this disclosure. Figure 1 A schematic side cross-sectional view of an electronic device.

[0009] Figure 3 This is based on an example set forth in this disclosure. Figure 1 An enlarged schematic side cross-sectional view of a portion of an electronic device.

[0010] Figure 4 This is based on another example set forth in this disclosure. Figure 1 An enlarged schematic side cross-sectional view of a portion of an electronic device.

[0011] Figure 5 This is based on another example set forth in this disclosure. Figure 1 An enlarged schematic side cross-sectional view of a portion of an electronic device.

[0012] Figure 6 It is a flowchart illustrating a method for conformally coating multiple passive surface mount components according to an example set forth in this disclosure.

[0013] Figure 7 It is a flowchart illustrating another method for conformally coating multiple passive surface mount components according to an example set forth in this disclosure.

[0014] Figure 8 It is a flowchart illustrating another method for conformally coating multiple passive surface mount components according to an example set forth in this disclosure.

[0015] Figure 9 It is a flowchart illustrating another method for conformally coating multiple passive surface mount components according to an example set forth in this disclosure.

[0016] Figure 10 It is a flowchart illustrating another method for conformally coating multiple passive surface mount components according to an example set forth in this disclosure. Detailed Implementation

[0017] In short, electronic devices comprising an integrated circuit die and a printed circuit substrate soldered to a BGA package require a conformal coating on the passive surface mount components. Passive surface mount components may include chip capacitors and / or chip resistors. During subsequent high-temperature processing, such as when the electronic device is soldered to a circuit board, some of the thermally conductive interphase (TIM) used to form a thermally conductive layer between the integrated circuit die and the heatsink may melt and flow off the integrated circuit die, contacting the passive surface mount components. Since the TIM is conductive, such contact can short-circuit the passive surface mount component terminals, rendering the electronic device inoperable. The conformal coating electrically insulates the passive surface mount component terminals from the TIM and from any other conductive materials that may contaminate the passive surface mount component terminals.

[0018] In BGA packages, passive surface mount components are typically arranged in rows around the periphery of the integrated circuit die. A conformal coating is formed on the passive surface mount components, and then a reinforcing ring, in the case of a capped or uncapped BGA package, is attached to the package substrate. This approach works well when there is only one row of passive surface mount components on any side of the integrated circuit die. However, as integrated circuit dies become denser and more complex, it is necessary to provide multiple adjacent rows of passive surface mount components on at least one side of the integrated circuit die. It has been found that conformal coatings formed over the large area required for multiple adjacent rows of passive surface mount components are prone to coating defects, such as voids in the coating, coating splits, and delamination between coating layers and between the coating layers and the substrate and passive surface mount components. The method described herein provides a conformal coating for multiple rows of passive surface mount components (e.g., chip capacitors) in an uncapped BGA package with significantly fewer voids or coating splits or delaminations, if any.

[0019] In some embodiments, a method for conformally coating passive surface mount components soldered to a printed circuit substrate of a capless flip-chip ball grid array package includes securing a reinforcing ring to the substrate before forming a conformal coating on the passive surface mount component. The reinforcing ring is secured to the substrate such that a plurality of passive surface mount components and an integrated circuit die are received within an opening formed by the reinforcing ring. After securing the reinforcing ring to the substrate, a conformal coating is formed on the passive surface mount component. The conformal coating extends above each passive surface mount component, around the periphery of each passive surface mount component, and below each passive surface mount component. In some embodiments, at least some of the passive surface mount components are disposed in a plurality of adjacent rows. In some embodiments, the plurality of passive surface mount components include a plurality of chip capacitors. In some embodiments, securing the reinforcing ring to the substrate includes adhering the reinforcing ring to the substrate with an adhesive and then allowing the adhesive to cure. In some embodiments, forming a conformal coating includes forming a base coat on a plurality of passive surface mount components, and then forming a top coat on each of the passive surface mount components and the base coat. The base coat extends around the periphery of each of the passive surface mount components and extends below each of the passive surface mount components between each of the passive surface mount components and the substrate. In some embodiments, both the base coat and the top coat are cured. In some embodiments, the base coat is cured prior to the formation of the top coat.

[0020] In some embodiments, the substrate and passive surface mount components are treated with plasma before forming the conformal coating. In some embodiments, the undercoat is treated with plasma before forming the topcoat. The plasma used to treat the substrate and passive surface mount components before forming the conformal coating, and the plasma used to treat the undercoat before forming the topcoat, are formed from gases including helium, argon, oxygen, or any combination of helium, argon, and oxygen.

[0021] In some embodiments, a first adhesive layer is formed on the substrate and on the passive surface mount component before forming a conformal coating on the passive surface mount component. In some embodiments, a second adhesive layer is formed on the base coating and on the passive surface mount component before forming a top coating.

[0022] In some embodiments, an electronic device packaged in a capless flip-chip ball grid array package includes a printed circuit substrate, an integrated circuit die soldered to the substrate, a plurality of passive surface mount components soldered to the substrate, a reinforcing ring fixed to the substrate, and a conformal coating disposed on the plurality of passive surface mount components. The substrate includes a ball grid array. The plurality of passive surface mount components and the integrated circuit die are received in openings formed by the reinforcing ring. At least some of the plurality of passive surface mount components are disposed in a plurality of adjacent rows. The device is manufactured by fixing the reinforcing ring to the substrate and forming a conformal coating on the plurality of passive surface mount components after fixing the reinforcing ring to the substrate. The conformal coating extends above each of the passive surface mount components, around the periphery of each of the passive surface mount components, and below each of the passive surface mount components. In some embodiments, the plurality of passive surface mount components includes a plurality of chip capacitors. In some embodiments, the plurality of passive surface mount components consists of a plurality of chip capacitors.

[0023] In some embodiments, forming a conformal coating includes forming an undercoat and a topcoat on a plurality of passive surface mount components. The undercoat extends around the periphery of each passive surface mount component and extends below each passive surface mount component between each passive surface mount component and a substrate. The topcoat is disposed on each passive surface mount component and on the undercoat extending around the periphery of each passive surface mount component.

[0024] In some embodiments, the device is further manufactured by forming a first adhesive layer on the substrate and the plurality of passive surface mount components before forming a conformal coating on the plurality of passive surface mount components. In some embodiments, the device is further manufactured by forming a second adhesive layer on the base coating and the plurality of surface mount components before forming a top coating. In some embodiments, the device is further manufactured by treating the substrate and the plurality of passive surface mount components with a first plasma before forming the base coating, the first plasma being formed of a gas including helium, argon, oxygen, or any combination thereof. In some embodiments, the device is further manufactured by treating the base coating and the top of the passive surface mount components with a second plasma, the second plasma being formed of a gas including helium, argon, oxygen, or any combination thereof.

[0025] In some embodiments, a method for conformally coating a plurality of passive surface mount components soldered to a printed circuit substrate of a capless flip-chip ball grid array package includes forming a first adhesive layer on the substrate and on each of the passive surface mount components, the capless flip-chip ball grid array package housing an integrated circuit die soldered to the substrate and a reinforcing ring secured to the substrate. A base coat is then formed on the first adhesive layer, the base coat extending around the periphery of each of the passive surface mount components and extending below each of the passive surface mount components and between each of the passive surface mount components and the substrate. A second adhesive layer is then formed on the base coat and on each of the passive surface mount components. A top coat is then formed on the second adhesive layer. In some embodiments, at least some of the passive surface mount components are disposed in a plurality of adjacent rows. In some embodiments, the plurality of passive surface mount components include a plurality of chip capacitors. In some embodiments, the plurality of passive surface mount components consist of a plurality of chip capacitors. In some embodiments, the undercoat is cured before the topcoat is formed. In some embodiments, the method further includes treating the substrate and passive surface mount components with a first plasma before forming the first adhesive layer. In some embodiments, the first plasma is formed from a gas comprising helium, argon, oxygen, or any combination of helium, argon, and oxygen. In some embodiments, the method further includes treating the undercoat with a second plasma before forming the second adhesive layer. In some embodiments, the second plasma is formed from a gas comprising helium, argon, oxygen, or any combination of helium, argon, and oxygen.

[0026] In some embodiments, an electronic device includes a printed circuit substrate having a ball grid array, an integrated circuit die soldered to the substrate, a plurality of passive surface mount components soldered to the substrate, a reinforcing ring fixed to the substrate, and a conformal coating disposed on the passive surface mount components. The passive surface mount components are disposed in a plurality of adjacent rows. The passive surface mount components and the integrated circuit die are received in openings formed by the reinforcing ring. The conformal coating includes a first adhesive layer, a base layer, a second adhesive layer, and a top layer. The first adhesive layer is disposed on the substrate and on each of the passive surface mount components. The base layer is disposed on the first adhesive layer and extends around the periphery of each of the passive surface mount components, and extends below each of the passive surface mount components between each of the passive surface mount components and the substrate. The second adhesive layer is disposed on the base layer and on each of the passive surface mount components. The top layer is disposed on the second adhesive layer. In some embodiments, the plurality of passive surface mount components include a plurality of chip capacitors. In some embodiments, the multiple passive surface mount components consist of multiple chip capacitors. In some embodiments, the integrated circuit die includes multiple central processing unit cores.

[0027] In some embodiments, the first and second adhesive layers comprise self-assembled monolayers based on phosphonate esters. In some embodiments, the undercoat comprises at least one polymer formed from a resin selected from epoxy phenolic resins and epoxy amine resins. In some embodiments, the topcoat comprises at least one polymer selected from silicone elastomers, acrylated urethane, and polymers derived from modified epoxy phenolic resins or modified amine resins.

[0028] In some embodiments, a method for conformally coating passive surface mount components soldered to a printed circuit substrate of a capless flip-chip ball grid array package includes securing a reinforcing ring to the substrate prior to forming a conformal coating on the passive surface mount component. The reinforcing ring is secured to the substrate such that a plurality of passive surface mount components and an integrated circuit die are received within an opening formed by the reinforcing ring. After securing the reinforcing ring to the substrate, a conformal coating is formed on the passive surface mount components. The conformal coating extends above each passive surface mount component, around the periphery of each passive surface mount component, and below each passive surface mount component. Forming the conformal coating includes: forming a base coat on the plurality of passive surface mount components, curing the base coat, forming a first top coat on the base coat, curing the first top coat, forming a second top coat on each passive surface mount component and on the cured first base coat, and curing the second top coat. The base coating extends around the periphery of each passive surface mount component in the passive surface mount components, and extends below each passive surface mount component between each passive surface mount component and the substrate. In some embodiments, the plurality of passive surface mount components include a plurality of chip capacitors. In some embodiments, the plurality of passive surface mount components consist of a plurality of chip capacitors.

[0029] In some embodiments, curing the first topcoat includes baking the first topcoat at a temperature of 95°C to 105°C for 50 to 70 minutes, and then baking the first topcoat at a temperature of 145°C to 155°C for 110 to 130 minutes. In some embodiments, curing the second topcoat includes baking the second topcoat at a temperature of 95°C to 105°C for 50 to 70 minutes, and baking the second topcoat at a temperature of 145°C to 155°C for 110 to 130 minutes.

[0030] In some embodiments, the substrate and passive surface mount components are treated with plasma before forming the conformal coating. In some embodiments, the base coating is treated with plasma before forming the first top coating. The plasma used to treat the substrate and passive surface mount components before forming the conformal coating, and the plasma used to treat the base coating before forming the first top coating, are formed from gases including helium, argon, oxygen, or any combination of helium, argon, and oxygen.

[0031] In some embodiments, a first adhesive layer is formed on the substrate and on the passive surface mount component before forming a conformal coating on the passive surface mount component. In some embodiments, a second adhesive layer is formed on the base coating and on the passive surface mount component before forming a first top coating.

[0032] In some embodiments, an electronic device packaged in a capless flip-chip ball grid array package includes a printed circuit substrate, an integrated circuit die soldered to the substrate, a plurality of passive surface mount components soldered to the substrate, a reinforcing ring secured to the substrate, and a conformal coating disposed on the plurality of passive surface mount components. The substrate includes a ball grid array. The plurality of passive surface mount components and the integrated circuit die are received in openings formed by the reinforcing ring. At least some of the plurality of passive surface mount components are disposed in a plurality of adjacent rows. The device is manufactured by securing the reinforcing ring to the substrate and forming a conformal coating on the plurality of passive surface mount components after securing the reinforcing ring to the substrate. The conformal coating extends above each of the passive surface mount components, around the periphery of each of the passive surface mount components, and below each of the passive surface mount components. Forming a conformal coating includes: forming a base coat on a plurality of passive surface mount components; curing the base coat; forming a first top coat on the base coat; curing the first top coat; forming a second top coat on each of the passive surface mount components and on the cured first base coat; and curing the second top coat. The base coat extends around the periphery of each of the passive surface mount components and extends below each of the passive surface mount components between each of the passive surface mount components and a substrate. In some embodiments, the plurality of passive surface mount components include a plurality of chip capacitors. In some embodiments, the plurality of passive surface mount components consist of a plurality of chip capacitors.

[0033] In some embodiments, curing the first topcoat includes baking the first topcoat at a temperature of 95°C to 105°C for 50 to 70 minutes, and then baking the first topcoat at a temperature of 145°C to 155°C for 110 to 130 minutes. In some embodiments, curing the second topcoat includes baking the second topcoat at a temperature of 95°C to 105°C for 50 to 70 minutes, and baking the second topcoat at a temperature of 145°C to 155°C for 110 to 130 minutes.

[0034] In some embodiments, a first adhesive layer is formed on the substrate and on the passive surface mount component before forming a conformal coating on the passive surface mount component. In some embodiments, a second adhesive layer is formed on the base coating and on the passive surface mount component before forming a first top coating.

[0035] In some embodiments, the substrate and passive surface mount components are treated with plasma before forming the conformal coating. In some embodiments, the base coating is treated with plasma before forming the first top coating. The plasma used to treat the substrate and passive surface mount components before forming the conformal coating, and the plasma used to treat the base coating before forming the first top coating, are formed from gases including helium, argon, oxygen, or any combination of helium, argon, and oxygen.

[0036] Figure 1 This is a schematic top view of an example of an electronic device 10, which includes a printed circuit substrate 12, an integrated circuit die 14, a plurality of chip capacitors 16, a reinforcing ring 18, and a conformal coating 20. The integrated circuit die 14 may be, for example, a central processing unit, a graphics processing unit, or a combination of these, an accelerated processing unit. In some embodiments, the integrated circuit die 14 includes a plurality of processing cores. In some embodiments, the reinforcing ring 18 is a rigid square band forming an opening 22. In some other embodiments, the reinforcing ring 18 may be a band having a shape other than a square (e.g., circular or rectangular). See below. Figure 3 , Figure 4 and Figure 5 Detailed description of conformal coating 20. (e.g.) Figure 1 As shown, some of the chip capacitors 16 are arranged in multiple rows, such as those in the first row R1 and the second row R2. Some of the other chip capacitors 16 are arranged in the third row R3. The first row R1 and the second row R2 are adjacent rows. The third row R3 does not have any adjacent rows of chip capacitors 16. Figure 1 As shown, for the chip capacitors 16 arranged in multiple rows, such as those in the first row R1 and the second row R2, the adjacent area covered by the conformal coating 20 is larger than the adjacent area covered by the conformal coating 20 for the chip capacitors 16 arranged in the third row R3.

[0037] Also refer to Figure 2The electrical device 10 also includes a ball grid array 24 comprising a plurality of solder balls 26 disposed on a surface of the substrate 12 opposite to the integrated circuit die 14. The ball grid array 24 can be used to electrically and mechanically connect the electrical device 10 to a larger printed circuit board (not shown) that is a component of any of a plurality of computing devices, for example, but not limited to, laptop computers, desktop computers, tablet computers, smartphones, game consoles, televisions, set-top boxes, wearable devices, internet servers, and printers. The printed circuit substrate 12 is a laminated substrate comprising a plurality of interconnects 28. The integrated circuit die 14 is electrically coupled to the plurality of interconnects 28 and mechanically secured to the substrate 12 by a plurality of solder joints 30. A die underfill 32 is disposed around the integrated circuit die 14 and the solder joints 20, thereby filling the space between the integrated circuit die 14 and the substrate 12. The die underfill 32 is a non-conductive polymer. The die underfill 32 prevents any molten TIM (not shown) or other conductive contaminants from shorting any solder joints 30 together. The chip capacitor 16 is electrically coupled to a plurality of interconnects 28 and mechanically secured to the substrate 12 via a plurality of solder joints 34. Specifically, the solder joints 34 electrically connect the terminals (not shown) of the chip capacitor 16 to the plurality of interconnects 28. The interconnects 28 electrically interconnect the integrated circuit die 14, the chip capacitor 16, and the solder balls 26 of the ball grid array 24. Figure 1 and Figure 2 As shown, the integrated circuit die 14 and a plurality of chip capacitors 16 are housed within an opening 22 formed by a reinforcing ring 18.

[0038] Also refer to Figure 3 The conformal coating 20 includes a base coating 36 and a top coating 38. The base coating 36 extends around the periphery of each of the sheet capacitors 16 and extends below each of the sheet capacitors 16 between the sheet capacitor 16 and the substrate 12. Although Figure 3 Although not shown, the capillary action of forming the undercoat 36 between the chip capacitor 16 and the substrate 12 can also cause the undercoat 36 to extend further to the top of each chip capacitor in the chip capacitor 16. A topcoat 38 is disposed on each chip capacitor in the chip capacitor 16 and on the undercoat 36, thereby extending around the periphery of the chip capacitor 16. In this configuration, the conformal coating 20 physically and electrically isolates the chip capacitor 16 from conductive contaminants such as TIM.

[0039] In some embodiments, the base coat 36 is an epoxy polymer. The base coat 36 is formed from an underfill resin, such as an epoxy phenolic resin, like U8439-105, or an epoxy amine resin, like U8410-119A, available from Namics Corporation, Japan. Other suitable underfill resins include U8443-14, U8410-73C, U8410-314A, U8439-1, and U8410-207, available from Namics Corporation; UF-5016-MP03, available from KCC Corporation, Seoul, South Korea; and CRP-4152R5, available from Sumitomo Bakelite Co., Ltd., Manchester, CT.

[0040] In some embodiments, the top coating 38 is formed of a coating resin, such as Dowsil. TM EA 6900 or Dowsil TM SE 4450, available from Dow Chemical Corporation, Midland, MI, is used to form silicone elastomers; or 9482, available from Dymax Corporation, Torrington, CT, is used to form acrylated urethane. Other suitable coating resins include Loctite Resinol 90C, Loctite 3515, and Loctite FP4470, available from Henkel Corporation, Rocky Hill, CT; DAPCO TM 3003 is available from Solvay USA, Chicago, IL; EW-3011 is available from 3M, St. Paul, MN; or modified epoxy phenolic resin or modified amine resin is available from Namics Corporation.

[0041] Also refer to Figure 4 In some embodiments, the conformal coating 20 further includes a first adhesive layer 40 and a second adhesive layer 42. The first adhesive layer 40 is disposed on the substrate 12 and on each of the sheet capacitors in the sheet capacitors 16. Figure 4 In this example, a base coating 36 is disposed on the first adhesive layer 40 and extends around the periphery of each of the sheet capacitors 16, and extends below each of the sheet capacitors 16 between the sheet capacitor 16 and the substrate 12. A second adhesive layer 42 is disposed on the base coating 36 and on each of the sheet capacitors 16. A top coating 38 is disposed on the second adhesive layer 42. Figure 3 As in the example, the conformal coating 20 physically and electrically isolates the sheet capacitor 16 from conductive contaminants such as TIM.

[0042] In some embodiments, the first adhesive layer 40 and the second adhesive layer 42 are self-assembled monolayers based on phosphonates, such as adhesive primers available from Aculon Inc., San Diego, CA.

[0043] Also refer to Figure 5 In some embodiments, the top coating 38 includes a first top coating 44 and a second top coating 46. The first top coating 44 is disposed on the bottom coating 36. Figure 5 As shown in the example, a first top coating 44 extends around the periphery of each of the chip capacitors 16 and flattens the gaps between the chip capacitors 16. A second top coating 46 is disposed on the first top coating 44 and on each of the chip capacitors 16. Figure 3 As in the example, the conformal coating 20 physically and electrically isolates the sheet capacitor 16 from conductive contaminants such as TIM.

[0044] In some embodiments, the first topcoat 44 and the second topcoat 46 are formed of the coating resin described above for the topcoat 38. In some embodiments, the first topcoat 44 and the second topcoat 46 are formed of the same coating resin. In some other embodiments, the first topcoat 44 and the second topcoat 46 are formed of different coating resins. In some embodiments, the first topcoat 44 is formed of the epoxy polymer described above for the basecoat 36, and the second topcoat 46 is formed of the coating resin described above for the topcoat 38.

[0045] In various embodiments, the thickness of the conformal coating 20, measured from the substrate 12 to the surface of the top coating 38 opposite to the substrate 12, can be as small as 600 micrometers, 625 micrometers, 650 micrometers, or 675 micrometers, or as large as 700 micrometers, 725 micrometers, or 750 micrometers, or any range defined between any two of the foregoing values, such as 600 micrometers to 750 micrometers, 625 micrometers to 725 micrometers, 650 micrometers to 700 micrometers, 675 micrometers to 700 micrometers, 675 micrometers to 725 micrometers, 700 micrometers to 750 micrometers, 700 micrometers to 725 micrometers, or 725 micrometers to 750 micrometers. Figures 1 to 5 The relative thickness of each layer, for example Figure 4 The base layer 36 and the first adhesive layer 40 shown are for illustrative purposes and are not drawn to scale.

[0046] Figure 6This is a flowchart illustrating a method for conformally coating a plurality of chip capacitors 16 according to an example set forth in this disclosure. As shown in block 100, the method begins, for example, by bonding an integrated circuit die 14 and the plurality of chip capacitors 16 to a substrate 12, as... Figure 1 As shown. At box 102, a reinforcing ring 18 is secured to the substrate 12, such that the integrated circuit die 14 and a plurality of chip capacitors 16 are accommodated within the opening 22. Following box 102, at box 104, a conformal coating is formed on the plurality of chip capacitors 16. Then, as shown in box 106, the method continues to produce an electrical device 10 having conformally coated chip capacitors 16. It has been found that by securing the reinforcing ring 102 to the substrate 12 before forming the conformal coating 20 on the chip capacitors 16, the conformal coating 20 has far fewer (if any) voids or splits or delamination of the bottom coating 36 and top coating 38 in the conformal coating 20 compared to forming the conformal coating 20 on the plurality of chip capacitors 16 in multiple rows after securing the reinforcing ring 18 to the substrate 12.

[0047] like Figure 6 As further shown, the method of attaching the reinforcing ring 18 to the substrate 12 begins, for example, by soldering the integrated circuit die 14 and a plurality of chip capacitors 16 to the substrate 12, as shown in box 108. At box 110, the reinforcing ring 18 is adhered to the substrate 12, for example, with an adhesive such as a silicone adhesive. In one embodiment, the adhesive is applied to the substrate 12, and then the reinforcing ring 18 is placed on the adhesive. Alternatively or additionally, the adhesive is applied to the reinforcing ring 18, and then the reinforcing ring 18 with the adhesive is placed on the substrate 12. Once the reinforcing ring 18 is adhered to the substrate 12, the adhesive cures at box 112. The method is then continued as shown in box 114 to manufacture the reinforcing ring 18 attached to the substrate 12.

[0048] Without being bound by any theory, it is believed that securing the reinforcing ring 18 to the substrate 12 prior to the formation of the conformal coating 20 helps stabilize the substrate 12, thereby reducing the mechanical stress applied to the conformal coating 20, which would otherwise lead to coating splitting and / or delamination. It is also believed that securing the reinforcing ring 18 to the substrate 12 prior to the formation of the conformal coating 20 avoids cross-contamination, which would occur if the conformal coating 20 were applied prior to attaching the reinforcing ring 18. It is believed that the larger the adjacent area covered by the conformal coating 20, the greater the mechanical stress in the conformal coating 20. Therefore, it is believed that this method is most advantageous when multiple chip capacitors 16 are arranged in multiple adjacent rows, such that the adjacent area covered by the conformal coating 20 for each chip capacitor 16 is larger than the adjacent area covered by the conformal coating 20 for those chip capacitors arranged in a single row. Figure 1 ).

[0049] Figure 7 This is a flowchart illustrating a method for conformally coating a plurality of chip capacitors 16 according to an example set forth in this disclosure. Consider together... Figure 1 , Figure 2 , Figure 3 and Figure 7 The method for forming the conformal coating 20 begins, for example, by soldering an integrated circuit die 14 and a plurality of chip capacitors 16 to a substrate 12 and securing a reinforcing ring 18 to the substrate 12, as shown in box 200. At box 202, a base coating 36 is formed by distributing underfill resin around the periphery of the plurality of chip capacitors 16 as described above. Capillary action draws some of the underfill resin into the space between the plurality of chip capacitors 16 and the substrate 12. The base coating 36 is then cured at box 204. At box 206, a top coating 38 is formed by distributing coating resin onto each of the chip capacitors 16 and onto the base coating 36 as described above. The top coating 38 is then cured at box 208. The method then continues, as shown in box 210, to produce an electrical device 10 having conformally coated chip capacitors 16.

[0050] In various embodiments, a two-step heating method can be used at frame 204 to cure the primer coating 36. In the first step of the two-step heating method, the primer coating 36 can be heated to a temperature as low as 85°C, 90°C, or 95°C, or as high as 100°C, 105°C, or 110°C, or to any temperature within any range defined between any two of the foregoing values, such as 85°C to 110°C, 90°C to 105°C, 95°C to 100°C, 95°C to 105°C, 90°C to 110°C, or 100°C to 105°C. In the first step of the two-step heating method, the base coating 36 can be heated for a time as short as 40 minutes, 45 minutes, 50 minutes, 55 minutes or 60 minutes, or for a time as long as 65 minutes, 70 minutes, 75 minutes or 80 minutes, or for any range between any two of the foregoing values, such as 40 to 80 minutes, 45 to 75 minutes, 50 to 70 minutes, 55 to 65 minutes, 55 to 60 minutes, 60 to 65 minutes or 60 to 70 minutes.

[0051] In the second step of the two-step heating method, the base coating 36 can be heated to a temperature as low as 130°C, 135°C, 140°C, 145°C or 150°C, or as high as 155°C, 160°C, 165°C or 170°C, or to a temperature within any range defined between any two of the foregoing values, such as 130°C to 170°C, 135°C to 165°C, 140°C to 160°C, 145°C to 155°C, 150°C to 160°C or 145°C to 150°C. In the second step of the two-step heating method, the base coating 36 may be heated for a period of time as short as 100 minutes, 105 minutes, 110 minutes, 115 minutes or 120 minutes, or as long as 125 minutes, 130 minutes, 135 minutes or 140 minutes, or any range between any two of the foregoing values, such as 100 to 140 minutes, 105 to 135 minutes, 110 to 130 minutes, 115 to 125 minutes, 120 to 130 minutes, 120 to 140 minutes or 110 to 120 minutes.

[0052] In various embodiments, at block 208, the top coating 38 can be cured using the two-step heating method described above for the undercoat 36 at block 204. In other various embodiments, a single-step heating method can be used to cure the top coating 38. In the single-step heating method, the top coating 38 can be heated to temperatures as low as 150°C, 155°C, or 160°C, or as high as 165°C, 170°C, or 175°C, or to any range defined between any two of the foregoing values, such as 150°C to 175°C, 155°C to 170°C, 160°C to 165°C, 160°C to 170°C, 150°C to 160°C, or 165°C to 170°C. In the single-step heating method, the top coating 38 can be heated for a time as short as 160 minutes, 165 minutes, 170 minutes, 175 minutes or 180 minutes, or for a time as long as 185 minutes, 190 minutes, 195 minutes or 200 minutes, or for any range between any two of the foregoing values, such as 160 minutes to 200 minutes, 165 minutes to 195 minutes, 170 minutes to 190 minutes, 175 minutes to 185 minutes, 175 minutes to 185 minutes, 170 minutes to 180 minutes, 180 minutes to 200 minutes or 180 minutes to 190 minutes.

[0053] In various other embodiments, at block 208, a three-step heating method can be used to cure the top coating 38. In the first step of the three-step heating method, the top coating 38 can be heated to a temperature as low as 85°C, 90°C, or 95°C, or as high as 100°C, 105°C, or 110°C, or to a temperature within any range defined between any two of the foregoing values, such as 85°C to 110°C, 90°C to 105°C, 95°C to 100°C, 95°C to 105°C, 90°C to 110°C, or 100°C to 105°C. In the first step of the three-step heating method, the top coating 38 can be heated for a time as short as 30 minutes, 35 minutes, 40 minutes or 45 minutes, or for a time as long as 50 minutes, 55 minutes or 60 minutes, or for any range between any two of the foregoing values, such as 30 to 60 minutes, 35 to 55 minutes, 40 to 50 minutes, 40 to 45 minutes, 45 to 50 minutes, 35 to 45 minutes or 45 to 50 minutes.

[0054] In the second step of the three-step heating method, the top coating 38 can be heated to a low of 110°C, 115°C, or 120°C, or up to 125°C, 130°C, or 135°C, or to any temperature within the range defined between any two of the aforementioned values, such as 110°C to 135°C, 115°C to 130°C, 120°C to 125°C, 120°C to 130°C, 115°C to 135°C, or 125°C to 130°C. In the second step of the three-step heating method, the top coating 38 can be heated for a short time of 30 minutes, 35 minutes, 40 minutes, or 45 minutes, or for a long time of 50 minutes, 55 minutes, or 60 minutes, or for any time within the range defined between any two of the aforementioned values, such as 30 minutes to 60 minutes, 35 minutes to 55 minutes, 40 minutes to 50 minutes, 40 minutes to 45 minutes, 45 minutes to 50 minutes, 35 minutes to 45 minutes, or 45 minutes to 50 minutes.

[0055] In the third step of the three-step heating method, the top coating 38 can be heated to a temperature as low as 130°C, 135°C, 140°C, 145°C or 150°C, or as high as 155°C, 160°C, 165°C or 170°C, or heated to any temperature within any range defined between any two of the foregoing values, such as 130°C to 170°C, 135°C to 165°C, 140°C to 160°C, 145°C to 155°C, 150°C to 160°C or 145°C to 150°C. In the third step of the three-step heating method, the top coating 38 can be heated for a time as short as 100 minutes, 105 minutes, 110 minutes, 115 minutes or 120 minutes, or for a time as long as 125 minutes, 130 minutes, 135 minutes or 140 minutes, or for any time within any range defined between any two of the foregoing values, such as 100 to 140 minutes, 105 to 135 minutes, 110 to 130 minutes, 115 to 125 minutes, 120 to 130 minutes, 120 to 135 minutes or 115 to 120 minutes.

[0056] In various other embodiments, at block 208, a four-step heating method can be used to cure the top coating 38. In the first step of the four-step heating method, the top coating 38 can be heated to a temperature as low as 85°C, 90°C, or 95°C, or as high as 100°C, 105°C, or 110°C, or to any temperature within any range defined between any two of the foregoing values, such as 85°C to 110°C, 90°C to 105°C, 95°C to 100°C, 95°C to 105°C, 90°C to 110°C, or 100°C to 105°C. In the first step of the four-step heating method, the top coating 38 can be heated for a time as short as 15 minutes, 20 minutes, 25 minutes or 30 minutes, or for a time as long as 35 minutes, 40 minutes or 45 minutes, or for any range between any two of the foregoing values, such as 15 minutes to 45 minutes, 20 minutes to 40 minutes, 25 minutes to 35 minutes, 25 minutes to 30 minutes, 30 minutes to 35 minutes, 35 minutes to 45 minutes or 20 minutes to 35 minutes.

[0057] In the second step of the four-step heating method, the top coating 38 can be heated to a temperature as low as 100°C, 105°C, or 110°C, or as high as 115°C, 120°C, 125°C, or 130°C, or to any temperature within any range defined between any two of the aforementioned values, such as 100°C to 130°C, 105°C to 125°C, 110°C to 120°C, 110°C to 115°C, or 115°C to 120°C. In the second step of the four-step heating method, the top coating 38 can be heated for a time as short as 15 minutes, 20 minutes, 25 minutes, or 30 minutes, or as long as 35 minutes, 40 minutes, or 45 minutes, or for any time within any range defined between any two of the aforementioned values, such as 15 minutes to 45 minutes, 20 minutes to 40 minutes, 25 minutes to 35 minutes, 25 minutes to 30 minutes, 30 minutes to 35 minutes, 35 minutes to 45 minutes, or 20 minutes to 35 minutes.

[0058] In the third step of the four-step heating method, the top coating 38 can be heated to a temperature as low as 115°C, 120°C, or 125°C, or as high as 130°C, 135°C, 140°C, or 145°C, or to any range defined between any two of the aforementioned values, such as 115°C to 145°C, 120°C to 140°C, 125°C to 135°C, 130°C to 135°C, or 125°C to 130°C. In the third step of the four-step heating method, the top coating 38 can be heated for a time as short as 15 minutes, 20 minutes, 25 minutes, or 30 minutes, or as long as 35 minutes, 40 minutes, or 45 minutes, or for any range defined between any two of the aforementioned values, such as 15 minutes to 45 minutes, 20 minutes to 40 minutes, 25 minutes to 35 minutes, 25 minutes to 30 minutes, 30 minutes to 35 minutes, 35 minutes to 45 minutes, or 20 minutes to 35 minutes.

[0059] In the fourth step of the four-step heating method, the top coating 38 can be heated to a temperature as low as 130°C, 135°C, 140°C, 145°C or 150°C, or as high as 155°C, 160°C, 165°C or 170°C, or to any temperature within any range defined between any two of the above values, such as 130°C to 170°C, 135°C to 165°C, 140°C to 160°C, 145°C to 155°C, 150°C to 160°C or 145°C to 150°C. In the fourth step of the four-step heating method, the top coating 38 can be heated for a time as short as 100 minutes, 105 minutes, 110 minutes, 115 minutes or 120 minutes, or for a time as long as 125 minutes, 130 minutes, 135 minutes or 140 minutes, or for any time within any range defined between any two of the foregoing values, such as 100 to 140 minutes, 105 to 135 minutes, 110 to 130 minutes, 115 to 125 minutes, 120 to 130 minutes, 120 to 135 minutes or 115 to 120 minutes.

[0060] Without being bound by any theory, it is believed that applying more progressive heating steps, such as two-step, three-step, and four-step heating, to the top coating 38 at frame 208 reduces shrinkage and stress in the top coating 38 during curing, particularly at the corners of the multiple sheet capacitors 16. Releasing stress in the top coating 38 at the corners of the multiple sheet capacitors 16 can reduce delamination of the conformal coating 20 from the multiple sheet capacitors 16.

[0061] In various embodiments, the thickness of the conformal coating 20, measured from the substrate 12 to the surface of the top coating 38 opposite to the substrate 12, can be as small as 600 micrometers, 625 micrometers, 650 micrometers, or 675 micrometers, or as large as 700 micrometers, 725 micrometers, or 750 micrometers, or any range defined between any two of the foregoing values, such as 600 micrometers to 750 micrometers, 625 micrometers to 725 micrometers, 650 micrometers to 700 micrometers, 675 micrometers to 700 micrometers, 675 micrometers to 725 micrometers, 700 micrometers to 750 micrometers, 700 micrometers to 725 micrometers, or 725 micrometers to 750 micrometers.

[0062] Figure 8 This is a flowchart illustrating a method for conformally coating a plurality of chip capacitors 16 according to another example set forth in this disclosure. Consider together Figure 1 , Figure 2 , Figure 3 and Figure 8 The method of forming the conformal coating 20 begins, for example, by soldering the integrated circuit die 14 and a plurality of chip capacitors 16 to the substrate 12 and fixing the reinforcing ring 18 to the substrate 12, as shown in box 300.

[0063] At frame 302, substrate 12 and a plurality of chip capacitors 16 are treated with a first plasma. The first plasma includes helium, argon, oxygen, or any combination of helium, argon, and oxygen. In various embodiments, the first plasma comprises oxygen in a weight percentage (wt%) as low as, for example, any one of 5 wt%, 10 wt%, 15 wt%, 20 wt%, 25 wt%, 30 wt%, 35 wt%, 45 wt%, or 50 wt%, or as high as 55 wt%, 60 wt%, 65 wt%, 70 wt%, 75 wt%, 80 wt%, 85 wt%, 90 wt%, or 95 wt%, or any range defined between any two of the foregoing values, for example, 5 wt% to 95 wt%, 10 wt% to 90 wt%, 15 wt% to 85 wt%, 20 wt% to 80 wt%, 25 wt% to 75 wt%, 30 wt% to 70 wt%, 35 wt% to 65 wt%, 40 wt% to 60 wt%, 45 wt%, 55 wt%, 50 wt% to 70 wt%, 20 wt% to 30 wt%, or 80 wt% to 95 wt%. In some implementations, the first plasma consists of oxygen and / or helium and / or argon.

[0064] At frame 304, an undercoat 36 is formed by distributing underfill resin around the periphery of the plurality of sheet capacitors 16 as described above. Capillary action draws some of the underfill resin into the space between the plurality of sheet capacitors 16 and the substrate 12. Then, at frame 306, an undercoat 36 is formed by, for example, referring to the above... Figure 7 The method described in frame 204 is used to cure the base coat 36.

[0065] At frame 308, the base coat 36 is treated with a second plasma. The second plasma comprises helium, argon, or oxygen, or any combination of helium, argon, and oxygen. In some embodiments, the second plasma comprises oxygen in a weight percentage (wt%) as low as, for example, any one of 5 wt%, 10 wt%, 15 wt%, 20 wt%, 25 wt%, 30 wt%, 35 wt%, 45 wt%, or 50 wt%, or as high as 55 wt%, 60 wt%, 65 wt%, 70 wt%, 75 wt%, 80 wt%, 85 wt%, 90 wt%, or 95 wt%, or any range defined between any two of the foregoing values, for example, 5 wt% to 95 wt%, 10 wt% to 90 wt%, 15 wt% to 85 wt%, 20 wt% to 80 wt%, 25 wt% to 75 wt%, 30 wt% to 70 wt%, 35 wt% to 65 wt%, 40 wt% to 60 wt%, 45 wt%, 55 wt%, 50 wt% to 70 wt%, 20 wt% to 30 wt%, or 80 wt% to 95 wt%. In some implementations, the second plasma consists of oxygen and / or helium and / or argon.

[0066] At frame 310, a top coating 38 is formed by dispensing the coating resin onto each of the sheet capacitors 16 and the base coating 36 as described above. Then at frame 312, a top coating is formed by, for example, referring to the above... Figure 7 The top coating 38 is cured using any of the methods described in box 208. Then, as shown in box 314, the method continues to produce an electrical device 10 having a conformally coated chip capacitor 16.

[0067] Without being bound by any theory, it is believed that the first plasma treatment at frame 302 modifies the treated surface by generating free radicals on the surface that bond more strongly with the base coating 36, and / or by removing contaminants from the treated surface, which would otherwise interfere with the bonding of the base coating 36. The stronger bonding and improved adhesion provided by the first plasma treatment can reduce or substantially eliminate the formation of voids between the base coating 36 and the plurality of sheet capacitors 16 and the substrate 12, and even in the space between each of the sheet capacitors 16 and the substrate 12 below the sheet capacitors 16. Similarly, it is believed that the second plasma treatment at frame 308 modifies the surface of the base coating 36 by generating free radicals on the surface of the base coating 36 that bond more strongly with the top coating 38, and / or by removing contaminants from the surface of the base coating 36 and the plurality of sheet capacitors 16, which would otherwise interfere with the bonding of the top coating 38. The stronger bonding and improved adhesion provided by the second plasma treatment can reduce or substantially eliminate the formation of voids between the top coating 38 and the base coating 36, and between the top coating 38 and the plurality of sheet capacitors 16.

[0068] Figure 9 This is a flowchart illustrating a method for conformally coating a plurality of chip capacitors 16 according to another example set forth in this disclosure. Consider together Figure 1 , Figure 2 , Figure 4 and Figure 9 The method for forming the conformal coating 20 begins, for example, by soldering the integrated circuit die 14 and a plurality of chip capacitors 16 to the substrate 12 and securing the reinforcing ring 18 to the substrate 12, as shown in block 400. As shown in block 402, a first adhesive layer 40 is formed on the substrate 12 and the plurality of chip capacitors 16. In one embodiment, the first adhesive layer 40 is formed by dispensing an adhesive primer to form, for example, a phosphonate-based self-assembled monolayer as described above. In various embodiments, the adhesive primer is dispensed by spraying, dipping, or wiping it onto the substrate 12 and the plurality of chip capacitors 16.

[0069] At frame 404, an undercoat 36 is formed by dispensing underfill resin onto the first adhesive layer 40 around the periphery of the plurality of sheet capacitors 16 as described above. Capillary action draws some of the underfill resin into the space between the plurality of sheet capacitors 16 and the substrate 12. Then, at frame 406, as shown above... Figure 7 The method described in frame 204 is used to cure the base coat 36.

[0070] As shown in box 408, a second adhesive layer 42 is formed on the base layer 36 and the plurality of chip capacitors 16. In one embodiment, the second adhesive layer 42 is formed by dispensing an adhesive primer to form, for example, a phosphonate-based self-assembled monolayer as described above. In various embodiments, the adhesive primer is dispensed by spraying, dipping, or wiping it onto the base layer 36.

[0071] At frame 410, a top coating 38 is formed by dispensing the coating resin onto each of the sheet capacitors 16 and the base coating 36 as described above. Then at frame 412, a top coating is formed by, for example, referring to the above... Figure 7 The top coating 38 is cured using any of the methods described in box 208. Then, as shown in box 414, the method continues to produce an electrical device 10 having a conformally coated chip capacitor 16.

[0072] Without being bound by any theory, it is believed that the first adhesive layer 40 formed at frame 402 is firmly bonded to the substrate 12 and the plurality of chip capacitors 16, and also firmly bonded to the undercoat 36 to bond the undercoat 36 to the substrate 12 and the chip capacitors 16. The stronger bonding provided by the first adhesive layer 40 can reduce or substantially eliminate the formation of voids and delamination between the undercoat 36 and the plurality of chip capacitors 16 and the substrate 12. Similarly, it is believed that the second adhesive layer 42 formed at frame 408 is firmly bonded to the undercoat 36 and the plurality of chip capacitors 16, and to the topcoat 38 to connect the topcoat 38 to the undercoat 36. The stronger bonding and improved adhesion provided by the second adhesive layer 42 reduces or substantially eliminates the formation of voids between the topcoat 38 and the undercoat 36, and between the topcoat 38 and the plurality of chip capacitors 16.

[0073] Figure 10 This is a flowchart illustrating a method for conformally coating a plurality of chip capacitors 16 according to another example set forth in this disclosure. Consider together Figure 1 , Figure 2 , Figure 5 and Figure 10The method for forming the conformal coating 20 begins, for example, by soldering the integrated circuit die 14 and a plurality of chip capacitors 16 to the substrate 12 and securing the reinforcing ring 18 to the substrate 12, as shown in block 500. At block 502, an undercoat 36 is formed by dispensing underfill resin onto the first adhesive layer 40 around the periphery of the plurality of chip capacitors 16 as described above. Capillary action draws some of the underfill resin into the space between the plurality of chip capacitors 16 and the substrate 12. Then, at block 504, the underfill resin is applied, for example, as shown above. Figure 7 The method described in frame 204 is used to cure the base coat 36.

[0074] At frame 506, a first top coating 44 of the top coating 38 is formed by dispensing a coating resin (or, alternatively, an epoxy polymer) around the periphery of the plurality of sheet capacitors 16 as described above. Then at frame 508, by, for example, referring to the above... Figure 7 The first top coating 38 is cured by any method described in box 208. At box 510, a second top coating 46 of the top coating 38 is formed by dispensing the coating resin onto each of the sheet capacitors 16 and onto the first top coating 44 as described above. Then at box 512, the coating is cured by, for example, as described above... Figure 7 The second top coating 46 is cured using any of the methods described in box 208. Then, as shown in box 514, the method continues to produce an electrical device 10 having a conformally coated chip capacitor 16.

[0075] Without being bound by any theory, it is believed that forming the top coating 38 in two parts reduces stress in the top coating 38, particularly at the edges of the plurality of chip capacitors 16. The first top coating 44 substantially flattens the area around the plurality of chip capacitors 16 and does not cover the edges of the plurality of chip capacitors 16 to any significant extent. Therefore, after curing, any stress formed in the first top coating 44 at the edges of the plurality of chip capacitors 16 is significantly less than the stress in an embodiment where the entire top coating 38 covers the edges of the plurality of chip capacitors 16 at once and cures in one step. The second top coating 46 is formed on the substantially flattened surface of the plurality of chip capacitors 16 and the cured first top coating 44. Therefore, the size of any exposed edges of the plurality of chip capacitors 16 is significantly reduced, thereby reducing any stress formed in the second top coating 46 at the edges of the plurality of chip capacitors 16.

[0076] Although for ease of explanation and understanding, Figure 7 , Figure 8 , Figure 9 and Figure 10 Examples are shown as individual methods, but it should be understood that this disclosure includes methods that combine elements of all four methods.

[0077] Although the examples above disclose chip capacitors as passive surface mount components, it should be understood that examples of chip resistors or other passive surface mount components, in addition to or in place of chip capacitors, are also covered by this disclosure.

[0078] As used herein, the phrase “any range between any two of the foregoing values” literally means that any range may be selected from any two values ​​listed preceding this phrase, regardless of whether the values ​​are in the lower or higher part of the list. For example, a pair of values ​​may be selected from two lower values, two higher values, or a lower and a higher value.

[0079] The detailed description and examples described above are presented for illustrative and descriptive purposes only and are not intended to be limiting. For example, the described operations can be performed in any suitable manner. The operations described herein can be performed in any suitable order, and the provided order is given for illustrative purposes only. Therefore, it is contemplated that embodiments of the invention cover any and all modifications, variations, or equivalents falling within the scope of the basic principles disclosed above and claimed herein. Furthermore, while hardware in the form of a processor executing code, a state machine capable of producing the same effect, or hardware in the form of special-purpose logic has been described above, other structures are also contemplated.

Claims

1. A method for conformally coating a plurality of passive surface mount components onto a printed circuit substrate of a capless flip-chip ball grid array package, the package further comprising an integrated circuit die soldered to the substrate, the method comprising: A reinforcing ring is fixed to the substrate having the welded passive surface mount components and the welded integrated circuit die, the plurality of passive surface mount components and the integrated circuit die being accommodated within an opening formed by the reinforcing ring, wherein at least some of the plurality of passive surface mount components are disposed in a plurality of adjacent rows; as well as After the reinforcing ring is secured to the substrate, a conformal coating is formed on the plurality of passive surface mount components. The conformal coating extends above each of the passive surface mount components, around the periphery of each of the passive surface mount components, and below each of the passive surface mount components. The formation of the conformal coating includes: A base coating is formed between the passive surface mount components in adjacent rows of the plurality of adjacent rows, and the base coating does not cover at least a portion of the top surface of the passive surface mount component; and A top coating is formed on each of the passive surface mount components in adjacent rows and on the bottom coating.

2. The method of claim 1, wherein the plurality of passive surface mount components comprises a plurality of chip capacitors.

3. The method of claim 2, wherein the undercoating extends around the periphery of each of the sheet capacitors and extends below each of the sheet capacitors between each of the sheet capacitors and the substrate.

4. The method of claim 3, further comprising: Curing the base coating; as well as The top coating is cured.

5. The method of claim 3, further comprising treating the substrate and the plurality of sheet capacitors with a first plasma prior to forming the conformal coating.

6. The method of claim 5, further comprising treating the undercoat with a second plasma.

7. The method of claim 3, further comprising forming a first adhesive layer on the substrate and on the plurality of sheet capacitors prior to forming the conformal coating on the plurality of sheet capacitors.

8. The method of claim 7, further comprising forming a second adhesive layer on the base coating and on the plurality of sheet capacitors prior to forming the top coating.

9. The method of claim 1, wherein forming the conformal coating comprises: The undercoat is formed, the undercoat extending around the periphery of each of the passive surface mount components and extending below each of the passive surface mount components between each of the passive surface mount components and the substrate; Curing the base coating; A first top coating is formed, which is disposed on the base coating; Curing the first top coating; The top coating is formed on the cured first top coating; as well as The top coating is cured.

10. The method of claim 9, wherein the plurality of passive surface mount components comprises a plurality of chip capacitors.

11. The method of claim 9, wherein curing the first top coating comprises: Bake the first top coating at a temperature of 95°C to 105°C for 50 to 70 minutes; as well as The first top coating is baked at a temperature of 145°C to 155°C for 110 to 130 minutes.

12. The method of claim 9, wherein curing the top coating comprises: The top coating is baked at a temperature of 95°C to 105°C for 50 to 70 minutes. as well as The top coating is baked at a temperature of 145°C to 155°C for 110 to 130 minutes.

13. The method of claim 9, further comprising treating the substrate and the plurality of passive surface mount components with plasma prior to forming the conformal coating.

14. The method of claim 13, further comprising treating the base coating with a second plasma prior to forming the first top coating.

15. The method of claim 9, further comprising forming a first adhesive layer on the substrate and on the plurality of passive surface mount components before forming the conformal coating on the plurality of passive surface mount components.

16. The method of claim 15, further comprising forming a second adhesive layer on the base coating and on the plurality of passive surface mount components prior to forming the first top coating.

17. An electronic device packaged in a capless flip-chip ball grid array package, the device comprising: A printed circuit substrate, the printed circuit substrate comprising a ball grid array; An integrated circuit die, wherein the integrated circuit die is soldered to the substrate; A plurality of passive surface mount components are soldered to the substrate, and at least some of the plurality of passive surface mount components are disposed in a plurality of adjacent rows; A reinforcing ring is fixed to the substrate, and the plurality of passive surface mount components and the integrated circuit die are accommodated within an opening formed by the reinforcing ring; as well as A conformal coating is disposed on the plurality of passive surface mount components, and the device is manufactured by the method described in any one of claims 1-8.

18. An electronic device comprising: A printed circuit substrate, the printed circuit substrate comprising a ball grid array; An integrated circuit die, wherein the integrated circuit die is soldered to the substrate; A plurality of passive surface mount components are soldered to the substrate, and at least some of the plurality of passive surface mount components are disposed in a plurality of adjacent rows; A reinforcing ring is fixed to the substrate, and the plurality of passive surface mount components and the integrated circuit die are accommodated within an opening formed by the reinforcing ring; as well as Conformal coating, wherein the conformal coating is disposed on the plurality of passive surface mount components, the conformal coating comprising: A first adhesive layer is disposed on the substrate and on each of the passive surface mount components; An undercoat layer is disposed on the first adhesive layer and extends around the periphery of each of the passive surface mount components and extends below each of the passive surface mount components between each of the passive surface mount components and the substrate; A second adhesive layer is disposed on the base coating and on each of the passive surface mount components; and A top coating layer is disposed on the second adhesive layer.

19. The apparatus of claim 18, wherein the integrated circuit die includes a plurality of central processing unit cores, and the plurality of passive surface mount components include a plurality of chip capacitors.

20. An electronic device packaged in a capless flip-chip ball grid array package, the device comprising: A printed circuit substrate, the printed circuit substrate comprising a ball grid array; An integrated circuit die, wherein the integrated circuit die is soldered to the substrate; A plurality of passive surface mount components are soldered to the substrate, and at least some of the plurality of passive surface mount components are disposed in a plurality of adjacent rows; A reinforcing ring is fixed to the substrate, and the plurality of passive surface mount components and the integrated circuit die are accommodated within an opening formed by the reinforcing ring; as well as A conformal coating is disposed on the plurality of passive surface mount components, and the device is manufactured by the method described in any one of claims 9-16.

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