Integrated Passive Device (IPD) components and packages and processes for implementing them

Abstract

An RF transistor package comprises a metal submount; a transistor die mounted on the metal submount; and a surface mount IPD component mounted on the metal submount. The surface mount IPD component comprises an insulating substrate having at least a first pad and a second pad disposed on a top surface and a bottom surface and on the top surface of the surface mount IPD component; at least one surface mount device having a first terminal and a second terminal—wherein the first terminal of the surface mount device is mounted on the first pad and the second terminal is mounted on the second pad, and at least one of the first terminal and the second terminal is configured to be isolated from the metal submount by the dielectric substrate—; and at least one wire bond coupled to at least one of the first pad and the second pad.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] This application is a partial continuation of U.S. application no. 16 / 797,290 filed on February 21, 2020, the entire contents of which are incorporated herein by reference.

[0003] The present invention relates to an integrated passive device (IPD) component. Furthermore, the present invention relates to a package implementing an integrated passive device (IPD) component. Furthermore, the present invention relates to a radio frequency (RF) package implementing a radio frequency (RF) device having an integrated passive device (IPD) component. Furthermore, the present invention relates to a radio frequency (RF) power amplifier transistor package implementing an RF device having an integrated passive device (IPD). Furthermore, the present invention relates to a process for manufacturing an integrated passive device (IPD) component. Furthermore, the present invention relates to a process for manufacturing a package implementing an integrated passive device (IPD) component. Furthermore, the present invention relates to a process for manufacturing an RF package implementing an RF device having an integrated passive device (IPD) component. Furthermore, the present invention relates to a process for manufacturing a radio frequency (RF) power amplifier transistor package implementing an integrated passive device (IPD) component. Background Technology

[0004] Transistor packages, such as radio frequency (RF) power amplifier transistor products, implement Integrated Passive Device (IPD) components. Typically, IPD components are mounted on printed circuit board (PCB)-based substrates, silicon (Si)-based substrates, and / or other substrates. Additionally, transistor packages generate significant heat that degrades the component, reduces efficiency, and decreases reliability. Furthermore, the demand for greater power from the transistor package generates even greater heat.

[0005] However, conventional printed circuit board (PCB)-based substrates, Si-based substrates, and / or others have poor thermal conductivity. More specifically, conventional printed circuit board (PCB)-based substrates, Si-based substrates, and / or others will not have sufficiently high thermal conductivity at sufficiently low temperatures required for the operation of transistor components, such as IPD components, for a lifespan of 10 to 20 years. Consequently, as the temperature of the transistor package rises, the component degrades, efficiency decreases, and reliability declines.

[0006] Additionally, radio frequency (RF) power amplifier transistor products typically implement wire-bond inductance to prevent unacceptable temperature rise of components within the package. For example, wire-bond inductance is used in pre-matching for high-power RF devices. However, this increases the number of wire bonds, which in turn increases manufacturing costs, manufacturing complexity, failure modes, and / or other factors.

[0007] Therefore, there is a need for integrated passive device (IPD) components that reduce cost, complexity, and failure modes without increasing operating temperature, RF products that implement integrated passive device (IPD) components, and / or said RF products.

[0008] One embodiment comprises an RF transistor package comprising: a metal submount; a transistor die mounted on the metal submount; a surface mount IPD component mounted on the metal submount, wherein the surface mount IPD component comprises a dielectric substrate having a top surface and a bottom surface and at least a first pad and a second pad disposed on the top surface of the surface mount IPD component; at least one surface mount device comprising a first terminal and a second terminal, wherein the first terminal of the surface mount device is mounted on the first pad and the second terminal is mounted on the second pad, and at least one of the first terminal and the second terminal is isolated from the metal submount by the dielectric substrate; and at least one wire bond coupled to at least one of the first pad and the second pad.

[0009] One embodiment comprises a surface mount IPD component configured to be mounted on a metal submount of a transistor package as a device, wherein the surface mount IPD component comprises a dielectric substrate comprising a top surface and a bottom surface and at least a first pad and a second pad disposed on the top surface of the surface mount IPD component; and at least one surface mount device comprising a first terminal and a second terminal, wherein the first terminal of the surface mount device is mounted on the first pad and the second terminal is mounted on the second pad, and at least one of the first terminal and the second terminal is isolated from the metal submount by the dielectric substrate, and at least one of the first pad and the second pad is configured as a wire bond pad.

[0010] A process for implementing an RF transistor package comprises the steps of: providing a metal submount; mounting a transistor die on the metal submount; mounting a surface mount IPD component on the metal submount, wherein the surface mount IPD component comprises a dielectric substrate having at least a first pad and a second pad disposed on the top surface of the surface mount IPD component and a top surface of the surface mount IPD component; providing a first terminal and a second terminal on a surface mount device; mounting the first terminal of the surface mount device on the first pad and mounting the second terminal of the surface mount device on the second pad; configuring at least one of the first terminal and the second terminal to be isolated from the metal submount by the dielectric substrate; and bonding at least one wire bond to at least one of the first pad and the second pad.

[0011] Additional features, advantages, and aspects of the present invention may be described or become apparent by considering the details, drawings, and claims for carrying out the invention subsequently. Furthermore, it should be understood that both the preceding summary and the details for carrying out the invention subsequently in this specification are illustrative and intended to provide further explanation without limiting the scope of the invention as claimed. Brief explanation of the drawing

[0012] The accompanying drawings, which are included in, incorporated into, and constitute part of this specification to better facilitate understanding of the invention, illustrate aspects of the invention and serve to explain the concept of the invention together with the detailed description. There is absolutely no attempt to show structural details of the invention in greater detail than may be necessary to fundamentally understand the invention and the various ways in which the invention may be practiced. In the drawings: FIG. 1 shows a perspective view of a package according to the present invention. FIG. 2 illustrates a cross-sectional view of a package according to the present invention. FIG. 3 illustrates a partial top view of a package according to a specific embodiment of the present invention. FIG. 4 illustrates a partial top view of a package according to another aspect of the present invention. FIG. 5 shows a perspective view of a package according to the present invention. Figure 6 illustrates a cross-sectional view of a package according to Figure 5. FIG. 7 illustrates a top view of an IPD component according to the present invention. FIG. 8 illustrates a side view of an IPD component according to FIG. 7. FIG. 9 illustrates a top view of another IPD component according to the present invention. FIG. 10 illustrates a top view of another IPD component according to the implemented disclosure. FIG. 11 illustrates an equivalent circuit for a package according to the present invention. FIG. 12 illustrates a side view of another IPD component according to the present invention. FIG. 13 includes FIG. 13a, which shows a top view of another IPD component according to the implemented disclosure; FIG. 13b, which shows a metal layer view of another IPD component; FIG. 13c, which shows a bottom metal layer view; and FIG. 13d, which shows a cross-sectional view. FIG. 14 illustrates a partial top view of a package according to another aspect of the present invention. FIG. 15 shows a process for manufacturing an IPD component according to the present invention. FIG. 16 shows a process for manufacturing a package according to the present invention. Specific details for implementing the invention

[0013] Aspects of the invention and their various features and beneficial details are illustrated in the accompanying drawings and are more fully described by reference to non-limiting aspects and examples that are described and / or illustrated in detail in the following description for the specific practice of the invention. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale, and that as will be recognized by those skilled in the art, features of one aspect may be employed together with other aspects even if not explicitly mentioned in this specification. Descriptions of known components and processing techniques are omitted to avoid unnecessarily obscuring the aspects of the invention. The examples used in this specification are intended only to facilitate understanding of the manner in which the invention may be practiced and further to enable those skilled in the art to practice the aspects of the invention. Therefore, the examples and aspects of this specification should not be construed as limiting the scope of the invention, which is defined only by the appended claims and applicable laws. Furthermore, it should be noted that across various views of the drawings and in different embodiments disclosed, similar reference numbers indicate similar parts.

[0014] Although terms such as first, second, etc. are used in this specification to describe various elements, it will be understood that these elements are not to be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the concept of the invention, the first element may be named the second element, and similarly, the second element may be named the first element. As used in this specification, the term "and / or" includes any combination of one or more of the associated and listed items and all combinations.

[0015] When an element such as a layer, zone, or substrate is referred to as being "on" or "onto" another element, it will be understood that this may exist directly on the other element, extend directly over the other element, or have intervening components. Conversely, if an element is referred to as being "directly on" or extending "directly over" another component, there are no intervening components. Likewise, when an element such as a layer, zone, or substrate is referred to as being "over" or extending "over" another element, it will be understood that this may exist directly on the other element, extend directly over the other element, or have intervening components. Conversely, if an element is referred to as being "directly over" or extending "directly over" another component, there are no intervening components. Furthermore, if a component is referred to as being "connected" or "coupled" to another component, it will be understood that this may be directly connected or coupled to the other component, or have intervening components. In contrast, if a component is referred to as being "directly connected" or "directly coupled" to another component, there is no intervening component.

[0016] Relative terms such as "below," "above," "upper," "lower," "horizontal," or "vertical" may be used herein to describe relationships between one element, layer, or zone and another element, layer, or zone as illustrated in the drawings. It will be understood that these terms and their foregoing description are intended to cover other orientations of the device in addition to the orientations illustrated in the drawings.

[0017] The terms used herein are intended to describe certain aspects only and are not intended to limit the invention. As used herein, the singular forms “one,” “one of,” and “it” are intended to include plural forms as well, unless the context makes it evident that they are not plural. Furthermore, when the terms “include,” “include,” “include,” and / or “include” are used herein, they specify the presence of the stated features, integers, steps, actions, components, and / or components, but do not impede the presence or addition of one or more other features, integers, steps, actions, components, and / or groups thereof.

[0018] Unless otherwise defined, all terms used herein (technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the present invention pertains. It will be further understood that terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification, and should not be interpreted in an ideal or overly formal sense unless explicitly defined otherwise in this specification.

[0019] The present invention relates directly to an integrated passive device (IPD) component. In particular, the IPD component may be fabricated on a dielectric substrate such as alumina, aluminum nitride (AlN), beryllium oxide (BeO), titanium oxide (TiO), metal-oxide substrate, high-dielectric metal-oxide substrate, high-dielectric substrate, thermally conductive high-dielectric material / substrate, thermally conductive high-dielectric material / substrate, and / or other similar thermally conductive dielectric substrate. In embodiments, the IPD component may be used for matching networks, pre-matching, bias-decoupling, thermal-grounding, and / or other purposes within RF power products and / or others. The IPD component may be placed within a package, such as an open cavity package or an over-molded package, together with a transistor die, such as a gallium nitride (GaN) transistor die, and other capacitors, IPDs, and / or others, and may be connected to each other and to package leads by wire bonds. Metal coverings on the top and bottom of the substrate, along with vias routed through the substrate, can enable the creation of bond pads, inductive strips, inductive coils, capacitive stubs, and / or others. Additionally, surface mount device (SMD) components, such as capacitors, resistors, inductors, and / or others, can be attached, for example, soldered, to the top of the IPD component.

[0020] According to the present invention, IPD components can be fabricated on alumina substrates, aluminum nitride (AlN) substrates, beryllium oxide (BeO) substrates (230-330 W / mK), and / or other dielectric substrates with similar thermal conductivity performance, instead of PCB-based or Si-based substrates. For example, the high thermal conductivity of alumina (>25 W / m C) allows the IPD component to be placed closer to the active die where high electric RF currents and / or others are present to pass through and generate heat, and to be used for higher power level operation. Conventional PCB-based substrates will not have a sufficiently high thermal conductivity to maintain the IPD component at the low temperatures required for operation with a lifespan of 10-20 years. Additionally, inductive traces on the disclosed substrate, such as strips, coils, and / or others, may be used to replace (or reduce) the wire-bond inductance required for various implementations, such as pre-match implementations for high-power RF devices, without the risk of exceeding an acceptable temperature rise for the components within the packaged product.

[0021] The disclosed IPD component can utilize the high bulk resistivity (1e14 uOhm-cm) of a substrate, such as an alumina substrate, which has high Q, low loss, and / or other characteristics, thereby enabling the configuration of an IPD component that increases the efficiency, gain, and / or other characteristics of RF products using such a component. Compared to low-resistivity PCB-based substrates and Si-based substrates for implementing IPDs that have rapidly increasing losses at higher frequencies, it has been found that high-resistivity alumina-based substrates for implementing IPD components, such as high-resistivity alumina substrates for implementing IPD components, have improved performance, reliability, and / or other characteristics at higher frequencies.

[0022] For example, alumina has a high dielectric constant (er=9.8) compared to Si and PCB, which can be advantageous in certain cases. For example, aspects of the present disclosure may realize low-value embedded and / or integrated capacitors by using and / or configuring an alumina dielectric substrate and top and / or bottom metal coverings on an IPD component. Such configurations may be used to create second harmonic termination stubs, third harmonic termination stubs, and / or others for input pre-matching, output pre-matching, and / or others within an RF power device, for example.

[0023] Additionally, the coefficient of thermal expansion for alumina is low for implementations such as the substrate of the disclosed IPD component (7.0). In this regard, alumina for implementation as a substrate of the disclosed IPD component is a good match for reducing and / or avoiding delamination of the component for certain flange applications. The disclosed IPD component is configured to provide an equally distributed impedance across the width and / or range of the active die to avoid power loss due to unequally distributed effects.

[0024] FIG. 1 shows a perspective view of a package according to the present invention.

[0025] FIG. 2 illustrates a cross-sectional view of a package according to the present invention.

[0026] FIG. 3 illustrates a partial top view of a package according to a specific embodiment of the present invention.

[0027] FIG. 4 illustrates a partial top view of a package according to another aspect of the present invention.

[0028] In particular, FIGS. 1, 2, 3, and 4 illustrate exemplary embodiments of a package (100) that may include any one or more other features, components, arrays, etc. as described herein. In particular, FIGS. 1, 2, 3, and 4 show a package (100) that may be implemented as an RF package, an RF amplifier package, an RF power amplifier package, a radio frequency (RF) power transistor package, a radio frequency (RF) power amplifier transistor package, and / or as described herein. The package (100) may include one or more semiconductor devices (400) and at least one IPD component (200). In embodiments, the package (100) may include a plurality of at least one IPD component (200); in embodiments, the package (100) may include a single embodiment of at least one IPD component (200). And in some embodiments, the package (100) may include multiple parallel implementations of at least one IPD component (200).

[0029] At least one IPD component (200) may be implemented as an RF device as described herein. At least one IPD component (200) may be implemented as a matching network, a harmonic termination circuit, an integrated passive device (IPD), a capacitor, a resistor, an inductor, and / or other such. As described in more detail herein, at least one IPD component (200) may be implemented with thermal conductivity, thermal management, and / or other such as increasing efficiency, performance, and / or reliability.

[0030] One or more semiconductor devices (400) may be wide band-gap semiconductor devices, ultra-wide band devices, GaN-based devices, metal semiconductor field-effect transistors (MESFETs), metal oxide field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), high electron-mobility transistors (HEMTs), wide band gap (WBG) semiconductors, power modules, gate drivers, general-purpose broadband components, telecom components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components, Doherty structures and / or other such components.

[0031] The package (100) may be implemented to include an open cavity structure suitable for use with at least one IPD component (200) of the present invention. In particular, the open cavity structure may utilize an open cavity package design. In some embodiments, the open cavity structure may include a lid or other enclosure for protecting interconnects, circuit components, at least one IPD component (200), one or more semiconductor devices (400), and / or others. The package (100) may include a ceramic body (402) and one or more metal contacts (404). In other embodiments, the package (100) may include a plurality of one or more metal contacts (404); and in embodiments, the package (100) may include a plurality of parallel implementations of one or more metal contacts (404) and a parallel implementation of one or more semiconductor devices (400).

[0032] Within the package (100), one or more semiconductor devices (400) may be attached to a support (102) via a die attachment material (422). One or more interconnects (104) may couple one or more semiconductor devices (400) to a first contact of one or more metal contacts (404) and a second contact of one or more metal contacts (404), at least one IPD component (200), and / or others. Additionally, within the package (100), at least one IPD component (200) may be placed on the support (102) via a die attachment material (422) having one or more interconnects (104) illustrated in an exemplary configuration capable of connecting between the package (100), at least one IPD component (200), and / or one or more semiconductor devices (400). The support (102) can dissipate heat generated by one or more semiconductor devices (400) and at least one IPD component (200) while simultaneously isolating and protecting one or more semiconductor devices (400) and at least one IPD component (200) from the external environment.

[0033] The support (102) may be implemented as a metal submount and may be implemented as a support, surface, package support, package surface, package support surface, flange, metal flange, heat sink, common source support, common source surface, common source package support, common source package surface, common source package support surface, common source flange, common source heat sink, lead frame, metal lead frame and / or other etc. The support (102) may include an insulating material, a dielectric material, and / or other etc.

[0034] Additionally, one or more semiconductor devices (400) may include one or more transistor dies that may include one or more lateral-diffusion metal-oxide semiconductor (LDMOS) transistors, GaN-based transistors, metal semiconductor field-effect transistors (MESFETs), metal oxide field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), high electron-mobility transistors (HEMTs), wide band gap (WBG) transistors, and / or others.

[0035] FIG. 5 shows a perspective view of a package according to the present invention.

[0036] Figure 6 illustrates a cross-sectional view of a package according to Figure 5.

[0037] In particular, FIGS. 5 and 6 illustrate other exemplary embodiments of a package (100) that may include any one or more other features, components, arrays, etc. as described herein. In particular, FIGS. 5 and 6 show a package (100) that may be implemented as an RF package, an RF amplifier package, an RF power amplifier package, a radio frequency (RF) power transistor package, a radio frequency (RF) power amplifier transistor package, and / or as described herein. The package (100) may include one or more semiconductor devices (400), at least one IPD component (200), and / or others. As described in more detail herein, at least one IPD component (200) may be implemented with thermal conductivity, thermal management, and / or others that increase efficiency, performance, and reliability.

[0038] Additionally, within the package (100), at least one IPD component (200) may be disposed on a support (102) as described herein, having one or more interconnects (104) illustrated in an exemplary configuration. The package (100) may include an over-mold (530), one or more input / output pins (532), and a support (102). The over-mold (530) substantially surrounds one or more semiconductor devices (400) attached to the support (102) using a die attachment material (538). The over-mold (530) may be formed of plastic or a plastic polymer compound, which may be injection molded around the support (102), one or more semiconductor devices (400), at least one IPD component (200), and / or others, thereby protecting them from the external environment. One or more semiconductor devices (400) and / or at least one IPD component (200) can be coupled to one or more input / output pins (532) through one or more interconnects (104).

[0039] In one embodiment, the over-mold configuration substantially surrounds one or more semiconductor devices (400), at least one IPD component (200), and / or others. The over-mold configuration may be formed from plastic, mold compound, plastic compound, polymer, polymer compound, plastic polymer compound, and / or others. The over-mold configuration may be injection molded, transfer molded, and / or compression molded around one or more semiconductor devices (400), at least one IPD component (200), and / or others, thereby protecting at least one IPD component (200), at least one semiconductor device (400), and other components of the package (100) from the external environment.

[0040] FIG. 7 illustrates a top view of an IPD component according to the present invention.

[0041] FIG. 8 illustrates a side view of an IPD component according to FIG. 7.

[0042] In particular, FIG. 7 illustrates at least one IPD component (200) that can be implemented with thermal conductivity, thermal management, and / or other factors that increase efficiency, performance, and reliability. At least one IPD component (200) of the package (100) can implement at least one device (202). In one embodiment, at least one IPD component (200) of the package (100) can implement one of at least one device (202). In one embodiment, at least one IPD component (200) of the package (100) can implement a plurality of at least one devices (202). At least one IPD component (200) can be implemented as an RF device, and at least one IPD component (200) can connect at least one device (202) to the package (100), to one or more semiconductor devices (400), and / or other factors. At least one IPD component (200) can be implemented as a submount for at least one device (202).

[0043] In embodiments, the RF device may be configured and implemented within at least one IPD component (200). In particular, the RF device may be configured and implemented within at least one IPD component (200) and may include a GaN-based HEMT die, a silicon-based LDMOS transistor die, and / or others as described herein. The RF device may include a matching network, a harmonic termination circuit, an integrated passive device (IPD), etc.

[0044] In particular, the RF device may be configured and implemented as a matching network, harmonic termination circuit, integrated passive device (IPD), and others within at least one IPD component (200), and less expensive ceramic-based surface mount devices (SMDs) may be utilized, typically mounted directly on traces on at least one IPD component (200), to replace more expensive silicon-based capacitors. In various embodiments, the present invention relates to mounting surface mount discrete device(s) (SMDs) on at least one IPD component (200) implemented as a submount, which may be mounted on a support (102) such as a metal flange, a metal lead frame, a base, or others. The submount may be wire-bonded or otherwise coupled to an RF device, such as a die, by means of input and / or output leads of an RF package that may be based on metal.

[0045] FIG. 7 further illustrates that at least one IPD component (200) may include a plurality of interconnect pads (206), and one or more may be configured as interconnect bond pads. One or more interconnects (104) may be connected to the plurality of interconnect pads (206). One or more interconnects (104) may be implemented as one or more wires, wire bonds, leads, vias, edge plating, circuit traces, tracks, clippings, and / or other such. In one embodiment, one or more interconnects (104) may utilize the same type of connection. In one embodiment, one or more interconnects (104) may utilize different types of connections.

[0046] One or more interconnects (104) may utilize ball joints, wedge joints, flexible joints, ribbon joints, metal clip attachments, and / or other types. In one embodiment, one or more interconnects (104) may utilize the same type of connection. In one embodiment, one or more interconnects (104) may utilize different types of connections.

[0047] One or more interconnects (104) may include various metal materials including one or more of aluminum, copper, silver, gold, and / or others. In one embodiment, one or more interconnects (104) may utilize the same type of metal. In one embodiment, one or more interconnects (104) may utilize different types of metal. One or more interconnects (104) may be connected to a plurality of interconnect pads (206) by adhesive, solder, sintering, eutectic bonding, thermal compression bonding, ultrasonic bonding / welding, clip components, and / or as described herein.

[0048] Referring to FIG. 8, at least one IPD component (200) may include a substrate (204). The substrate (204) may include alumina, aluminum nitride (AlN), beryllium oxide (BeO), titanium oxide (TiO), metal-oxide substrate, high dielectric metal-oxide substrate, high dielectric substrate, thermally conductive high dielectric material / substrate, and / or other similar dielectric material having thermal conductivity performance. The substrate (204) may be fabricated as an alumina substrate, an aluminum nitride (AlN) substrate, a beryllium oxide (BeO) substrate, and / or other similar dielectric material having thermal conductivity performance. The substrate (204) may include alumina, aluminum nitride (AlN), beryllium oxide (BeO), titanium oxide (TiO), metal-oxide substrate, high dielectric metal-oxide substrate, high dielectric substrate, thermally conductive high dielectric material / substrate, and / or other similar dielectric material having thermal conductivity performance. An embodiment of a substrate (204) containing alumina benefits from the high thermal conductivity properties (>25 W / m² C) of alumina, which allows it to be placed closer to an active die, such as one or more semiconductor devices (400), through which at least one IPD component (200) and associated IPD components, such as at least one device (202), pass and generate heat and / or other such things, and to be used for high power level operation. A substrate (204) implementing alumina, aluminum nitride (AlN), beryllium oxide (BeO), titanium oxide (TiO), metal-oxide substrate, high-dielectric metal-oxide substrate, high-dielectric substrate, thermally conductive high-dielectric material / substrate, and / or other dielectric materials with similar thermal conductivity performance consequently allows the IPD component of at least one IPD component (200), such as at least one device (202), to operate at a lower temperature, thereby increasing the reliability required for operation with a lifespan of 10-20 years.

[0049] As described herein, a substrate (204) implementing an alumina substrate (1e14 uOhm-cm), aluminum nitride (AlN), and / or other dielectric materials having similar thermal conductivity performance enables at least one IPD component (200) to implement a configuration of an IPD component, such as at least one device (202), having high Q, low loss, and / or other such characteristics, thereby increasing the efficiency, gain, and / or other such characteristics of an RF product using such components. Additionally, a substrate (204) implementing alumina, aluminum nitride (AlN), beryllium oxide (BeO), titanium oxide (TiO), metal-oxide substrate, high dielectric metal-oxide substrate, high dielectric substrate, thermally conductive high dielectric material / substrate, and / or other dielectric materials having similar thermal conductivity performance as described herein enables at least one IPD component (200) implementing a configuration of an IPD component, such as at least one device (202), to have better performance at higher frequencies. Additionally, a substrate (204) implementing an alumina substrate, an aluminum nitride (AlN) substrate, a beryllium oxide (BeO) substrate, and / or a dielectric material substrate with other similar thermal conductivity performance as described herein benefits from a low coefficient of thermal expansion (e.g., alumina is as low as 7.0). In this regard, a substrate (204) implementing an alumina substrate, an aluminum nitride (AlN) substrate, a beryllium oxide (BeO) substrate, and / or a dielectric material substrate with other similar thermal conductivity performance achieves a good coefficient of thermal expansion matching for a specific flange application, e.g., a support (102), thereby reducing and / or avoiding delamination.

[0050] At least one device (202) may be one or more of a surface mount device (SMD) component, a surface mount device (SMD) capacitor, a ceramic capacitor, a surface mount device (SMD) oscillator, a surface mount device (SMD) ceramic capacitor, an inductor, a surface mount device (SMD) inductor, a resistor, a surface mount device (SMD) resistor, a power divider, a surface mount device (SMD) power divider, a power splitter, a surface mount device (SMD) power splitter, an amplifier, a balanced amplifier, a surface mount device (SMD) amplifier, a surface mount device (SMD) balanced amplifier, a combiner, a surface mount device (SMD) combiner, and / or other such. At least one device (202) may be implemented as a radio frequency device, a radio frequency circuit device, a radio frequency component device, or other such.At least one device (202) may be implemented as a radio frequency device, a radio frequency circuit device, a radio frequency component device, or the like, and may be a surface mount device (SMD) radio frequency component, a surface mount device (SMD) radio frequency capacitor, a radio frequency ceramic capacitor, a surface mount device (SMD) oscillator, a surface mount device (SMD) radio frequency ceramic capacitor, a radio frequency inductor, a surface mount device (SMD) radio frequency inductor, a radio frequency resistor, a surface mount device (SMD) radio frequency resistor, a radio frequency power divider, a surface mount device (SMD) radio frequency power divider, a radio frequency power splitter, a surface mount device (SMD) radio frequency power splitter, a radio frequency amplifier, a balanced radio frequency amplifier, a surface mount device (SMD) radio frequency amplifier, a surface mount device (SMD) radio frequency balanced amplifier, a radio frequency combiner, a surface mount device (SMD) radio frequency combiner, a surface mount device (SMD) resistor, a surface mount device (SMD) providing tuning, stability, and baseband impedance. It may be one or more of the device (SMD), resistor, and / or other.

[0051] The package (100) may be implemented as an RF package, and at least one device (202) may be implemented as a radio frequency device that may include a connection, a support, or the like, a transmitter, a transmitter function, a receiver, a receiver function, a transceiver, a transceiver function, a matching network function, a harmonic termination circuit, an integrated passive device (IPD), etc. At least one device (202) implemented as a radio frequency device may be configured to transmit radio waves and modulate them to carry data with a transmitter power output, harmonics, and / or band edge requirements that allow the radio waves to be allowed, or may perform operations such as supporting such. At least one device (202) implemented as a radio frequency device may be configured to receive radio waves and demodulate radio waves, or may perform operations such as supporting such. At least one device (202) implemented as a radio frequency device may be configured to transmit radio waves and modulate said radio waves to carry data with permissible transmitter power output, harmonics, and / or band edge requirements, or may perform operations such as supporting such; and may be configured to receive radio waves and demodulate said radio waves, or may perform operations such as supporting such.

[0052] Referring to FIG. 8, the substrate (204) may include an upper surface (222). The upper surface (222) may be located in a plane roughly parallel to the x-axis or in a plane roughly parallel to the upper surface of the support (102). In this regard, it may generally be defined as falling within 0° - 15°, 0° - 2°, 2° - 4°, 4° - 6°, 6° - 8°, 8° - 10°, 10° - 12°, or 12° - 15°. The upper surface (222) may support a plurality of interconnection pads (206). The plurality of interconnection pads (206) may include a plurality of bond pad regions. A plurality of interconnection pads (206) may be formed by a metal surface on the upper surface (222) of the substrate (204) and may include metallic materials such as copper, gold, nickel, palladium, silver, etc. and combinations thereof.

[0053] In some embodiments, at least one device (202) may include a terminal disposed on the bottom surface. Accordingly, if a device such as at least one device (202) is mounted directly on the support (102) of the package (100), a short circuit will occur. For example, at least one device (202) implemented as a surface mount device (SMD) component, such as a surface mount device (SMD) ceramic capacitor, may include one or more terminals disposed on the bottom surface of the surface mount device (SMD) component. Accordingly, if at least one device (202) configured as a surface mount device (SMD) component is mounted on the support (102) of the package (100), a short circuit will occur.

[0054] Accordingly, the present invention utilizes a substrate (204) of at least one IPD component (200) to support at least one device (202). The substrate (204) may be mounted on the upper surface of a support (102). The substrate (204) may be mounted on the upper surface of the support (102) by means of adhesive, soldering, sintering, process bonding, ultrasonic welding, and / or as described herein. In one embodiment, the substrate (204) may be mounted directly on the upper surface of the support (102). In one embodiment, the substrate (204) may be mounted on the upper surface of the support (102) with an interposed structure, component, and / or other such. The upper surface of the support (102) may be parallel to the x-axis; and the substrate (204) may be positioned vertically on the support (102) along the y-axis as shown in FIGS. 2 and FIGS. 6. In one embodiment, the substrate (204) may be at least partially insulating. More specifically, the substrate (204) may insulate at least one device (202) from the support (102) at least partially.

[0055] Referring again to FIG. 7, one or more of the plurality of interconnect pads (206) may be surfaces for coupling to one or more interconnects (104). Thus, it may be beneficial to ensure that the surfaces of the plurality of interconnect pads (206) are kept clean. In particular, attaching at least one device (202) to the plurality of interconnect pads (206) may result in solder being transferred to other surfaces of the plurality of interconnect pads (206). Accordingly, as illustrated in FIG. 7, the plurality of interconnect pads (206) may include a solder barrier (216) disposed between various coupling areas of one or more interconnects (104) to one or more interconnect pads (206) and coupling areas of at least one device (202) to the plurality of interconnect pads (206).

[0056] The upper surface (222) may further implement a plurality of interconnect pads (206) as first terminal bond pads. The first terminal bond pads may be located in a plane schematically parallel to the x-axis or in a plane schematically parallel to the upper surface (222). The first terminal bond pads may be connected to a first terminal of at least one device (202). In this regard, a first connection (220) may be formed between the first terminal bond pad and the first terminal. The first connection (220) may include adhesive, soldering, sintering, process bonding, ultrasonic welding, and / or the likes described herein. The first terminal bond pads may be formed by a metal surface on the upper surface (222) of the substrate (204) and may include metallic materials such as copper, gold, nickel, palladium, silver, etc. and combinations thereof.

[0057] The upper surface (222) may further implement one of the plurality of interconnection pads (206) as a second terminal bond pad. The second terminal bond pad may be located in a plane schematically parallel to the x-axis or in a plane schematically parallel to the upper surface (222). The second terminal bond pad may be connected to a second terminal of at least one device (202). In this regard, a second connection (218) may be formed between the second terminal bond pad and the second terminal. The second terminal bond pad may be partially electrically connected to the plurality of interconnection pads (206). The second connection (218) may include adhesive, soldering, sintering, process bonding, ultrasonic welding, and / or the likes described herein. The second terminal bond pad may be formed by a metal surface on the upper surface (222) of the substrate (204) and may include a metallic material such as copper, gold, nickel, palladium, silver, etc. and combinations thereof. Additionally, the upper surface (222) of the substrate (204) may include additional terminals for at least one device (202) as needed.

[0058] At least one IPD component (200) may include a metallization layer (240) located on the lower surface of the substrate (204) opposite the upper surface (222). The metallization layer (240) may be located in a plane roughly parallel to the x-axis or in a plane roughly parallel to the upper surface (222). In one embodiment, the metallization layer (240) may be implemented as a full-face metallic layer on the lower surface of the substrate (204) opposite the upper surface (222). Additionally or alternatively, at least one IPD component (200) may be single-sided having a single metallic layer; at least one IPD component (200) may be double-sided having two metallic layers on both sides of one substrate layer of the substrate (204); and / or at least one IPD component (200) may be a multilayer having outer and inner layers of aluminum, copper, silver, gold, and / or other materials alternating with the layers of the substrate. At least one IPD component (200) may include features such as distinct conductive lines, tracks, circuit traces, pads for connections, vias for passing connections between layers of aluminum, copper, silver, gold, and / or other materials, and solid conductive regions for EM shielding or other purposes.

[0059] Additionally or alternatively, at least one IPD component (200) may include conductors on different layers that can be connected using vias which may be metal plating holes, such as copper plating holes, aluminum plating holes, silver plating holes, gold plating holes, and / or others that can function as electrical tunnels passing through a dielectric substrate. At least one IPD component (200) may include a "through-hole" component that can be mounted by their wire leads that pass through the substrate (204) and are soldered to a trace on the other side. At least one IPD component (200) may include a "surface-mount" component that can be attached by their leads and / or terminals.

[0060] At least one IPD component (200) and / or a metal coating layer (240) may be manufactured using one or more fabrication techniques including print screening or disposal of solder paste, print screening or disposal of epoxy, a silk screen printing process, a photoengraving process, a printing process on a transparent film, a photomask process, a photo-sensitized board process, a laser resist ablation process, a milling process, a laser etching process, and / or similar processes. In one or more embodiments, at least one IPD component (200) may be configured to mechanically support and electrically connect at least one device (202) to at least one IPD component (200) and other electronic components.

[0061] Additionally, at least one IPD component (200) may include a via (228). The via (228) may extend from a plurality of interconnect pads (206) to a metal cladding layer (240). Thus, a terminal of at least one device (202) may be connected to a first terminal bond pad through a first connection (220) and to at least the metal cladding layer (240) through a via (228) to form an electrical connection and / or electrical contact with the support (102). The via (228) may also be connected to the support (102) through the metal cladding layer (240) to form an electrical connection and / or electrical contact with the support (102). In other embodiments, the via (228) may be implemented only as a partial via. The via (228) may be a metal-plated hole or a metal-filled hole that can function as an electrical tunnel passing through the substrate (204). The via (228) may include a metallic material such as copper, gold, nickel, palladium, silver, etc. and combinations thereof. The via (228) may be located in a plane schematically perpendicular to the x-axis, a plane schematically parallel to the x-axis, and / or a plane schematically perpendicular to the top plane (222).

[0062] In a specific embodiment, a first embodiment of at least one IPD component (200) is illustrated in FIG. 7, wherein a plurality of at least one device (202) implemented as SMD capacitors are disposed on an alumina substrate implementation of a substrate (204). One end of the SMD capacitor may be electrically connected to a conductive trace implemented by a plurality of interconnection pads (206) that are connected to a bond pad. A bond wire, such as one or more interconnections (104), may be attached to the bond pad implemented by the plurality of interconnection pads (206) to connect at least one IPD component (200) to another component within the package (100). A thin strip of solder mask implemented by a solder barrier (216) may protect the bond pad from solder contamination during the reflow attachment of the SMD component. The other end of the SMD capacitor may be electrically connected to ground (the back of at least one IPD component (200)) through a conductive trace and / or via (228), a metal cladding layer (240), and / or other means.

[0063] FIG. 9 illustrates a top view of another IPD component according to the present invention.

[0064] In particular, FIG. 9 illustrates at least one IPD component (200) that may include any and all of the features, configurations, arrays, forms of implementation, modes and / or those described herein. Additionally, FIG. 9 illustrates that at least one IPD component (200) may include a circuit structure (260). In particular, the circuit structure (260) may be disposed adjacent to at least one device (202) and may be configured to provide an inductance, capacitance, resistance, and / or other such things. In one embodiment, the circuit structure (260) may be a metallic surface disposed on the upper surface (222) and may form a capacitor together with a metal coating layer (240). Additionally, the circuit structure (260) may be configured as an inductive strip, an inductive coil, a capacitive stub, and / or other such things. In one embodiment, the circuit structure (260) may be placed on at least one IPD component (200), printed on at least one IPD component (200), and / or may implement a resistor such as a thin film resistor, a thick film resistor, a printed thin film resistor, a printed thick film resistor, and / or other resistors.

[0065] In one embodiment, the circuit structure (260) may be implemented as an open-ended shunt stub. In this regard, the circuit structure (260) may be constructed using an upper metal covering on the upper surface (222) on the substrate (204), and a lower metal covering implemented by the dielectric and metal covering layer (240) of the substrate (204) creates capacitance. As illustrated in FIG. 9, a plurality of interconnect pads (206) implementing the open-ended shunt stub may be spaced apart from each other between at least one device (202) to form a low value capacitance suitable for second or third harmonic optimization for one or more semiconductor devices (400). A plurality of interconnect pads (206) implementing harmonic shunt stubs can be placed on at least one IPD component (200) so that one stub available for each of one or more semiconductor devices (400) may exist. An additional capacitance region can be created using a large continuous rectangular area implementation form of a circuit structure (260) connected to the shunt stub and located after a row of vias (228).

[0066] Referring again to FIG. 4, the package (100) of FIG. 4 illustrates an implementation of at least one IPD component (200) illustrated in FIG. 7 together with an implementation of at least one IPD component (200) illustrated in FIG. 9. In particular, FIG. 7 illustrates a package (100) that implements the embodiment of FIG. 4 of at least one IPD component (200) and the embodiment of FIG. 7 of at least one IPD component (200), which is used with one or more semiconductor devices (400), such as active dies, which may be, for example, GaN dies, within a packaged RF power product. The embodiment of FIG. 7 of at least one IPD component (200) may be used to form capacitance in a shunt LC network within output pre-matching, and the embodiment of FIG. 4 of at least one IPD component (200) may be used to form pre-match in a low-pass LC network at the input. An open-end type stub can be configured to enable higher efficiency by providing an optimal second harmonic impedance at the input to one or more semiconductor devices (400), together with one or more interconnects (104), such as wire bonds to each tub of one or more semiconductor devices (400).

[0067] FIG. 10 illustrates a top view of another IPD component according to the implemented disclosure.

[0068] In particular, FIG. 10 illustrates at least one IPD component (200) that may include any and all of the features, configurations, arrays, forms of implementation, modes and / or those described herein. Additionally, FIG. 10 shows that at least one IPD component (200) may include a structure of multiple interconnect pads (206) that may be routed along the outer edge of at least one IPD component (200) and may also continue behind at least one device (202). In this regard, the multiple interconnect pads (206) may be configured as thin, curved lines; or the multiple interconnect pads (206) may be implemented as wider, shorter lines to provide a desired circuit. Various forms of implementation of the multiple interconnect pads (206) of FIG. 10 may provide greater flexibility for manipulating the impedance provided at harmonic frequencies. Additionally, the embodiment of FIG. 10 can operate with one or more semiconductor devices (400) having different numbers of tubs, because the bond pads implemented by a plurality of interconnect pads (206) can be continuous across the width of the die. Referring again to FIG. 3, a package (100) is shown that implements the embodiment of FIG. 10 of at least one IPD component (200) on the input side or right side of the package (100).

[0069] FIG. 11 illustrates an equivalent circuit for a package according to the present invention.

[0070] In particular, FIG. 11 illustrates an equivalent circuit design representing the topology illustrated in FIG. 10 and FIG. 11. On the output side or left, one or more interconnects (104), such as wire bonds, and at least one IPD component (200) implementing at least one device (202), such as an SMD cap, form a shunt LC network. One or more interconnects (104), such as wire bonds, start from one or more semiconductor devices (400), pass through at least one IPD component (200), and are directly connected to one or more metal contacts (404) implemented as output RF leads for a series inductor. On the input side or right, at least one IPD component (200) may be configured such that a circuit structure (260) or substrate implementing an open-ended shunt stub has low capacitance formed by top and bottom metals. Additionally, one or more interconnects (104) implemented as wire bonds can be connected to one or more semiconductor devices (400) and can form a shunt-LC or shunt-open stub. This embodiment can be used to optimize the existing harmonic impedance to the input of one or more semiconductor devices (400) and to optimize the efficiency and linearity of the package (100). A low-pass LCL network can be created by one or more interconnects (104), e.g., wire bonds, and at least one device (202), e.g. SMD cap, can now connect one or more semiconductor devices (400) and RF input leads.

[0071] FIG. 12 illustrates a side view of another IPD component according to the present invention.

[0072] In particular, FIG. 12 illustrates at least one IPD component (200) that may include any and all of the features, configurations, arrays, forms of implementation, modes and / or those described herein. Additionally, FIG. 12 illustrates that at least one IPD component (200) may include an edge plating (230). The edge plating (230) may extend from the top surface (222) and / or a plurality of interconnection pads (206) to a metal coating layer (240). The edge plating (230) may be located in a plane schematically perpendicular to the x-axis or in a plane schematically perpendicular to the top surface (222). Thus, a terminal of at least one device (202) may be connected to at least the metal coating layer (240) through the edge plating (230) via a first connection (220) to form an electrical connection and / or electrical contact with the support (102). The edge plating (230) extends through the metal coating layer (240) to the support (102) to form an electrical connection and / or electrical contact with the support (102). The edge plating (230) may comprise metallic materials such as copper, gold, nickel, palladium, silver, etc. and combinations thereof. In one or more embodiments, the edge plating (230) comprises a routed and plated constellation configuration and / or a long-hole configuration also called castellation or edge plating. In one or more embodiments, the edge plating (230) may be more cost-effective compared to utilizing vias because vias can sometimes be plugged.

[0073] FIG. 13 includes FIG. 13a, which shows a top view of another IPD component according to the implemented disclosure; FIG. 13b, which shows a metal layer view of another IPD component; FIG. 13c, which shows a bottom metal layer view; and FIG. 13d, which shows a cross-sectional view.

[0074] In particular, FIG. 13 illustrates at least one IPD component (200) that may include any and all of the features, configurations, arrays, forms of implementation, modes and / or those described herein. Additionally, FIG. 13 illustrates that at least one IPD component (200) may be implemented as a multilayer substrate. In particular, at least one IPD component (200) of FIG. 13 may include three metal layers and two dielectric layers. However, similar features may be applied to any type of multilayer stack-up. A plurality of interconnect pads (206) may be configured as an output shunt-LC consisting of at least one device (202) implemented as an upper metal layer trace and an SMD capacitor, as shown in FIG. 13a. One end of at least one device (202) that can be implemented as an SMD capacitor can be routed to a metal cladding layer (240) or a ground layer by a via (228) that connects the upper metal layer of at least one device (202) to a metal cladding layer (240) or a lower metal layer.

[0075] At least one IPD component (200) of FIG. 13 may implement an output series inductance by implementing a second metal layer as illustrated in FIG. 13b. The metal layer (290) illustrated in FIG. 13b may be routed back to the top layer of at least one IPD component (200) to be connected to a plurality of interconnection pads (206) implemented as bond pads and wire bonds, and in one embodiment may be implemented with vias (228) implemented using partial / blind vias connecting only the top two layers of at least one IPD component (200). An exemplary cross-section of a multilayer stack-up of at least one IPD component (200) is illustrated in FIG. 13d.

[0076] FIG. 14 illustrates a partial top view of a package according to another aspect of the present invention.

[0077] In particular, FIG. 14 illustrates a package (100) that may include any and all of the features, configurations, arrangements, forms of implementation, modes and / or those described herein. Additionally, FIG. 14 illustrates that the package (100) implements at least one IPD component (200) of FIG. 13 as a multilayer ceramic IPD for input and output. Note that using this configuration requires only a small number of short wire bonds from one or more semiconductor devices (400) to at least one IPD component (200), and from the end of at least one IPD component (200) to one or more metal contacts (404) implemented as RF input leads and / or RF output leads. Additionally, there is no wire bond loop across the top of at least one device (202), such as an SMD cap, which can help reduce input / output coupling within the package (100), provide improved stability and gain, and save on the cost of gold wire bonds.

[0078] The adhesive of the present invention may be utilized in an adhesive bonding process that may include applying an intermediate layer to bond surfaces to be bonded. The adhesive may be an organic or inorganic adhesive; and the adhesive may be deposited on the surface of one or both of the surfaces to be bonded. The adhesive may be utilized in an adhesive bonding process that may include applying an adhesive material having a specific coating thickness at a specific bonding temperature for a specific processing time in an environment that may include applying a specific tool pressure. In one embodiment, the adhesive may be a conductive adhesive, an epoxy-based adhesive, a conductive epoxy-based adhesive, and / or others.

[0079] The solder of the present invention may comprise solder and / or may be utilized to form a solder interface that may be formed from the solder. The solder may be any fusible metal alloy that can be used to form a bond between surfaces to be connected. The solder may be lead-free solder, lead solder, process solder, or others. Lead-free solder may contain tin, copper, silver, bismuth, indium, zinc, antimony, a labeling material of other metals, and / or others. Lead solder may contain lead, other metals such as tin, silver, and / or others. The solder may further comprise flux as needed.

[0080] The sintering of the present invention may utilize a process of compacting and forming a conductive mass of a material by heat and / or pressure. The sintering process may be operated without melting the material to its liquefaction point. The sintering process may include sintering metallic nano or hybrid powders within a paste or epoxy. The sintering process may include sintering in a vacuum. The sintering process may include sintering using a shielding gas.

[0081] The eutectic bonding of the present invention may utilize a process soldering process capable of forming a process system. The process system may be used between surfaces to be connected. The eutectic bonding may utilize a metal, which may be an alloy, and / or an intermetallic material that transitions from a solid to a liquid state or from a liquid to a solid state at a specific composition and temperature. The eutectic alloy may be deposited by sputtering, vaporization, electroplating, and / or other methods.

[0082] The ultrasonic welding of the present invention may utilize a process in which high-frequency ultrasonic acoustic vibrations are locally applied to components attached to each other under pressure. The ultrasonic welding can create a solid weld between the surfaces to be connected. In one embodiment, the ultrasonic welding may include applying a sonicated force.

[0083] The package (100) can be implemented in various different applications. In this regard, the package (100) may be implemented in applications implementing components such as high video bandwidth power amplifier transistors, single-path radio frequency power transistors, single-stage radio frequency power transistors, multi-path radio frequency power transistors, Doherty structures, multi-stage radio frequency power transistors, GaN-based radio frequency power amplifier modules, lateral-diffusion metal-oxide semiconductor (LDMOS) devices, LDMOS radio frequency power amplifier modules, radio frequency power devices, ultra-wideband devices, GaN-based devices, metal semiconductor field-effect transistors (MESFETs), metal oxide field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), high electron-mobility transistors (HEMTs), wide band gap (WBG) semiconductors, power modules, gate drivers, general-purpose broadband components, telecom components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components, and / or others. Package (100) may be implemented as a power package. Package (100) may be implemented as a power package and may implement applications and components as described in this specification.

[0084] The package (100) may be implemented as a radio frequency package. The package (100) may be implemented as a radio frequency package and may implement applications and components as described in this specification. The package (100) implemented as a radio frequency package may include a connection, a support, etc., a transmitter, a transmitter function, a receiver, a receiver function, a transceiver, a transceiver function, etc. The package (100) implemented as a radio frequency package may be configured to transmit radio waves and modulate them to carry data with acceptable transmitter power output, harmonics, and / or band edge requirements, or may perform operations such as supporting such. The package (100) implemented as a radio frequency package may be configured to receive radio waves and demodulate radio waves, or may perform operations such as supporting such. A package (100) implemented as a radio frequency package may be configured to transmit radio waves and modulate said radio waves to carry data with permissible transmitter power output, harmonics, and / or band edge requirements, or may perform operations such as supporting such; and may be configured to receive radio waves and demodulate said radio waves, or may perform operations such as supporting such.

[0085] At least one IPD component (200) may be an active device, a passive device, an integrated passive device (IPD), a transistor device, or the like. At least one IPD component (200) may include any electrical component for any application. In this regard, at least one IPD component (200) may be a high video bandwidth power amplifier transistor, a single-path radio frequency power transistor, a single-stage radio frequency power transistor, a multipath radio frequency power transistor, a multi-stage radio frequency power transistor, a GaN-based radio frequency power amplifier module, a lateral-diffusion metal-oxide semiconductor (LDMOS) device, an LDMOS radio frequency power amplifier module, a radio frequency power device, an ultra-wideband device, a GaN-based device, a metal semiconductor field-effect transistor (MESFET), a metal oxide field-effect transistor (MOSFET), a junction field-effect transistor (JFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a high electron-mobility transistor (HEMT), a wide band gap (WBG) semiconductor, a power module, a gate driver, a general-purpose broadband component, a telecom component, an L-band component, an S-band component, an X-band component, a C-band component, a Ku-band component, a satellite communication component, and / or other such components. At least one IPD component (200) implemented as a radio frequency device may be configured to transmit radio waves and modulate them to carry data with acceptable transmitter power output, harmonics, and / or band edge requirements, or may perform operations such as supporting such. At least one IPD component (200) implemented as a radio frequency device may be configured to receive radio waves and demodulate radio waves, or may perform operations such as supporting such.At least one IPD component (200) implemented as a radio frequency device may be configured to transmit radio waves and modulate said radio waves to carry data with permissible transmitter power output, harmonics, and / or band edge requirements, or may perform operations such as supporting such; and may be configured to receive radio waves and demodulate said radio waves, or may perform operations such as supporting such.

[0086] In one embodiment, at least one IPD component (200) may be a high electron mobility transistor (HEMT). In this regard, the HEMT may be a group 3-nitride-based device, and such HEMT may be implemented for high-power radio frequency (RF) applications, for low-frequency high-power switching applications, and for other applications. For example, the material properties of group 3-nitrides, such as GaN and their alloys, enable high voltage and high current to be obtained along with high RF gain and linearity for RF applications. A typical group 3-nitride HEMT relies on the formation of a two-dimensional electron gas (2DEG) at the interface between a high-bandgap group nitride (e.g., AlGaN) barrier layer and a low-bandgap group nitride material (e.g., GaN) buffer layer, where the small bandgap material has a higher electron affinity. The 2DEG is an accumulation layer within the small bandgap material and may include high electron concentration and high electron mobility.

[0087] FIG. 15 shows a process for manufacturing an IPD component according to the present invention.

[0088] In particular, FIG. 15 illustrates a process for forming an IPD component (600) related to an IPD component (200) as described herein. It should be noted that aspects of the process for forming the IPD component (600) may be performed in a different order consistent with the aspects described herein. Additionally, it should be noted that parts of the process for forming the IPD component (600) may be performed in a different order consistent with the aspects described herein. Furthermore, the process for forming the IPD component (600) may be modified to have more or fewer processes consistent with the various aspects disclosed herein.

[0089] Initially, the process of forming the IPD component (600) may include the process of forming the substrate (602). More specifically, the substrate (204) may be configured, structured, and / or implemented as described herein. The process of forming the substrate (602) may include forming the substrate (204) to include alumina, aluminum nitride (AlN), beryllium oxide (BeO), titanium oxide (TiO), metal-oxide substrate, high dielectric metal-oxide substrate, high dielectric substrate, thermally conductive high dielectric material / substrate, and / or other similar dielectric material having thermal conductivity performance, and the substrate (204) may be fabricated as an alumina substrate, an aluminum nitride (AlN) substrate, a beryllium oxide (BeO) substrate, and / or other similar dielectric material having thermal conductivity performance, and the substrate (204) may include alumina, aluminum nitride (AlN), beryllium oxide (BeO), titanium oxide (TiO), metal-oxide substrate, high dielectric metal-oxide substrate, high dielectric substrate, thermally conductive high dielectric material / substrate, and / or other similar dielectric material having thermal conductivity performance. In one embodiment, the manufacturing of the substrate (204) may begin with an alumina strip. The strip size may be optimized to suit what subsequent assembly equipment, such as SMT, dicing, and die attachment equipment, can process.

[0090] Furthermore, the process of forming the IPD component (600) may include forming a metal coating layer (604). More specifically, the metal coating layer (240) may be configured, structured, and / or implemented as described herein on at least a portion of the substrate (204). The process of forming the metal coating layer (604) may include utilizing one or more fabrication techniques including print screening for solder paste, print screening for epoxy, a silk screen printing process, a photolithography process, a printing process on a transparent film, a photomask process combined with an etching process, a photosensitive board process, a laser resist ablation process, a milling process, a laser etching process, a direct metal printing process, and / or similar processes.

[0091] Additionally, the process of forming the metal coating layer (604) may include forming interconnection pads. More specifically, a plurality of interconnection pads (206) may be configured, structured, and / or implemented on the substrate (204) as described herein. The process of forming the interconnection pads may include utilizing one or more fabrication techniques including print screening for solder paste, print screening for epoxy, silk screen printing process, photolithography process, printing process on a transparent film, photomask process combined with an etching process, photosensitive board process, laser resist ablation process, milling process, laser etching process, direct metal printing process, and / or similar processes.

[0092] Additionally, the process of forming the IPD component (600) may include forming a solder barrier (606). In one or more embodiments, the solder barrier (216) may be formed within a selected area on the upper surface of at least one IPD component (200). In an additional embodiment, the solder barrier (216) may be disposed over the entire surface of at least one IPD component (200) and may be selectively etched and / or otherwise removed from a selected location on the upper surface of at least one IPD component (200).

[0093] Additionally, the process of forming the IPD component (600) may include placing at least one device on the substrate (608). More specifically, at least one device (202) may be configured, structured, and / or implemented on the substrate (204) as described herein. In one embodiment, at least one device (202) may be placed on the substrate (204) using an adhesive, soldering, sintering, process bonding, ultrasonic welding, and / or the likes described herein as described herein.

[0094] More specifically, the process of forming the IPD component (600) may include manufacturing to form at least one IPD component (200) within the panel. The process of forming the IPD component (600) may include implementing a pick and place assembly to place at least one device (202) on at least one IPD component (200) of the panel. The process of forming the IPD component (600) may include implementing a reflow process with the panel. The process of forming the IPD component (600) may include cutting the panel using cutting equipment, such as wafer, circuit board, or package sawing equipment, to separate at least one IPD component (200) from the panel, which may have the advantage that at least one IPD component (200) can be placed on a dicing tape on a ring frame that can be directly loaded into a die attach equipment for subsequent assembly into a package (100).

[0095] In one embodiment, the process of forming the IPD component (600) may involve processing using a surface mount technology (SMT) line. The surface mount technology (SMT) line may utilize a number of processes including solder printing, component placement, solder reflow, and / or others. Additional processes may include a flux cleaning step to remove all flux residue, wire bonding, dicing, mounting on a dicing tape, dicing, mechanical sawing or laser cutting, or a combination of all of these, and component testing. Additionally, at least one IPD component (200) may be placed on a dicing tape, which may now serve as an input to a die attachment device.

[0096] FIG. 16 shows a process for manufacturing a package according to the present invention.

[0097] In particular, FIG. 16 illustrates a process for forming a package (700) related to a package (100) as described herein. It should be noted that aspects of the process for forming the package (700) may be performed in a different order consistent with the aspects described herein. Additionally, it should be noted that parts of the process for forming the package (700) may be performed in a different order consistent with the aspects described herein. Furthermore, the process for forming the package (700) may be modified to have more or fewer processes consistent with the various aspects disclosed herein.

[0098] Initially, the process of forming the package (700) may include the process of forming a support (702). More specifically, the support (102) may be configured, structured, and / or implemented as described herein. In one embodiment, the process of forming the support (702) may include forming the support (102) as a support, surface, package support, package surface, package support surface, flange, heat sink, common source heat sink, and / or other such.

[0099] The process of forming the package (700) may include the process of forming the IPD component (600). More specifically, at least one IPD component (200) may be configured, structured, and / or implemented as described herein with respect to FIG. 15 and its associated description. Subsequently, the process of forming the IPD component (600) may include attaching at least one IPD component (200) to a support (102). In this regard, at least one IPD component (200) and / or a substrate (204) may be mounted on the upper surface of the support (102) by means of an adhesive, soldering, sintering, process bonding, ultrasonic welding, and / or as described herein.

[0100] The process of forming the package (700) may include the process of forming one or more interconnects (706). More specifically, the one or more interconnects (104) may be configured, structured, and / or implemented as described herein. In one embodiment, the process of forming one or more interconnects (706) may include forming one or more interconnects (104) by forming one or more wires, leads, vias, edge plating, circuit traces, tracks, and / or other such. In one embodiment, the process of forming one or more interconnects (706) may include connecting one or more interconnects (706) by means of an adhesive, soldering, sintering, process joining, ultrasonic welding, clip components, and / or as described herein.

[0101] The process of forming the package (700) may include a process of sealing the package (708). More specifically, the package (100) may be configured, structured, and / or implemented as described herein. In one embodiment, the process of sealing the package (708) may include forming an open cavity configuration, an over-mold configuration, or other such configurations.

[0102] Although this specification has been described in terms of exemplary embodiments, those skilled in the art will recognize that the invention may be modified and practiced within the spirit and scope of the appended claims. The examples described above are merely illustrative and do not constitute an exhaustive list of all possible designs, embodiments, applications, or variations of the invention.

Claims

Claim 1 As an RF transistor package, a metal submount; a transistor die mounted on the metal submount; a surface mount IPD component mounted on the metal submount - the surface mount IPD component comprises a dielectric substrate comprising a top surface and a bottom surface and at least a first pad and a second pad disposed on the top surface of the surface mount IPD component -; at least one surface mount device comprising a first terminal and a second terminal - the first terminal of the surface mount device is mounted on the first pad and the second terminal is mounted on the second pad, and at least one of the first terminal and the second terminal is isolated from the metal submount by the dielectric substrate -; An RF transistor package comprising at least one wire bond coupled to at least one of a first pad and a second pad, wherein the dielectric substrate of the surface mount IPD component comprises a material having thermal conductivity that operates at a lower temperature and improves device reliability, and wherein the material comprises at least one of alumina, aluminum nitride (AlN), and beryllium oxide (BeO). Claim 2 delete Claim 3 An RF transistor package comprising: a metal submount; a transistor die mounted on the metal submount; a surface mount IPD component mounted on the metal submount, wherein the surface mount IPD component comprises a dielectric substrate comprising a top surface and a bottom surface and at least a first pad and a second pad disposed on the top surface of the surface mount IPD component; at least one surface mount device comprising a first terminal and a second terminal, wherein the first terminal of the surface mount device is mounted on the first pad and the second terminal is mounted on the second pad, and at least one of the first terminal and the second terminal is configured to be isolated from the metal submount by the dielectric substrate; and at least one wire bond coupled to at least one of the first pad and the second pad, wherein the dielectric substrate of the surface mount IPD component comprises a dielectric material having thermal conductivity that operates at a lower temperature and improves device reliability, and comprises an alumina substrate. Claim 4 An RF transistor package according to claim 1, wherein the surface mount IPD component comprises a metallization layer located on the bottom surface of a dielectric substrate. Claim 5 In claim 1, the dielectric substrate of the surface mount IPD component comprises a multilayer dielectric substrate, forming an RF transistor package. Claim 6 An RF transistor package according to claim 1, wherein the surface mount IPD component comprises a metallic surface disposed on the top surface of a dielectric substrate, and the metallic surface is configured to implement a circuit structure comprising one or more of a capacitor, an inductor, and a resistor. Claim 7 In claim 1, the RF transistor package comprises one or more LDMOS transistor dies, wherein the transistor die comprises one or more LDMOS transistor dies. Claim 8 In claim 1, the transistor die comprises one or more GaN-based HEMTs, forming an RF transistor package. Claim 9 In claim 1, the RF transistor package comprises a plurality of transistors. Claim 10 In claim 9, the plurality of transistors are configured in a Doherty configuration, an RF transistor package. Claim 11 In claim 1, the surface mount IPD component comprises a plurality of surface mount devices mounted on the top surface of the surface mount IPD component, forming an RF transistor package. Claim 12 An RF transistor package according to claim 1, wherein the dielectric substrate comprises at least one of a via configured to form an electrical connection between the surface mount device and the metal submount, an edge plating configured to form an electrical connection between the surface mount device and the metal submount, a wire bonding configured to form an electrical connection between the surface mount device and the metal submount, and a clip configured to form an electrical connection between the surface mount device and the metal submount. Claim 13 An RF transistor package according to claim 1, wherein the dielectric substrate comprises at least one of a via configured to form an electrical connection between the surface mount device and the source of the transistor die, an edge plating configured to form an electrical connection between the surface mount device and the source of the transistor die, a wire bonding configured to form an electrical connection between the surface mount device and the source of the transistor die, and a clip configured to form an electrical connection between the surface mount device and the source of the transistor die. Claim 14 In claim 1, the RF transistor package, wherein the at least one wire bond is configured to electrically couple the surface mount device to the transistor die. Claim 15 In claim 1, the surface mount device is an RF transistor package comprising a ceramic capacitor. Claim 16 In claim 1, the surface mount device is an RF transistor package including a resistor. Claim 17 An RF transistor package according to claim 1, wherein the at least one wire bond is configured to electrically couple the surface mount device to one or more metal contacts. Claim 18 A device comprising: a surface mount IPD component configured to be mounted on a metal submount of a transistor package, wherein the surface mount IPD component comprises a dielectric substrate comprising a top surface and a bottom surface and at least a first pad and a second pad disposed on the top surface of the surface mount IPD component; and at least one surface mount device comprising a first terminal and a second terminal, wherein the first terminal of the surface mount device is mounted on the first pad and the second terminal is mounted on the second pad, wherein at least one of the first terminal and the second terminal is isolated from the metal submount by the dielectric substrate, wherein at least one of the first pad and the second pad is composed of a wire bond pad, and wherein the dielectric substrate of the surface mount IPD component comprises a material having thermal conductivity that operates at a lower temperature and improves device reliability, wherein the material comprises at least one of alumina, aluminum nitride (AlN), and beryllium oxide (BeO). Claim 19 delete Claim 20 As an RF transistor package, the device comprises: a metal submount; a transistor die mounted on the metal submount; a surface mount IPD component mounted on the metal submount, wherein the surface mount IPD component comprises a dielectric substrate comprising a top surface and a bottom surface and at least a first pad and a second pad disposed on the top surface of the surface mount IPD component; at least one surface mount device comprising a first terminal and a second terminal, wherein the first terminal of the surface mount device is mounted on the first pad and the second terminal is mounted on the second pad, and at least one of the first terminal and the second terminal is configured to be insulated from the metal submount by the dielectric substrate; and at least one wire bond coupled to at least one of the first pad and the second pad, wherein the dielectric substrate of the surface mount IPD component comprises a dielectric material having thermal conductivity that operates at a lower temperature and improves device reliability, and comprises an alumina substrate. Claim 21 In claim 18, the surface-mount IPD component comprises a metallized layer located on the bottom surface of a dielectric substrate. Claim 22 In claim 18, the dielectric substrate of the surface mount IPD component comprises a multilayer substrate, the device. Claim 23 In claim 18, the surface mount IPD component comprises a metallic surface configured to implement a circuit structure including one of a capacitor, an inductor, and a resistor. Claim 24 In claim 18, the surface mount IPD component is configured to be implemented within an RF transistor package comprising an LDMOS transistor die, a device. Claim 25 In claim 18, the surface mount IPD component is configured to be implemented within an RF transistor package comprising a GaN-based HEMT, a device. Claim 26 In claim 18, the surface mount IPD component is configured to be implemented within an RF transistor package comprising a plurality of transistors, a device. Claim 27 In claim 26, the device wherein the plurality of transistors are configured in a Doherty structure. Claim 28 In claim 18, the surface mount IPD component comprises a plurality of surface mount devices mounted on the upper surface of the surface mount IPD component. Claim 29 A device according to claim 18, wherein the dielectric substrate comprises at least one of a via configured to form an electrical connection between the surface mount device and the metal submount, an edge plating configured to form an electrical connection between the surface mount device and the metal submount, a wire bonding configured to form an electrical connection between the surface mount device and the metal submount, and a clip configured to form an electrical connection between the surface mount device and the metal submount. Claim 30 A device according to claim 18, wherein the dielectric substrate comprises at least one of a via configured to form an electrical connection between the surface mount device and the source of the transistor die, an edge plating configured to form an electrical connection between the surface mount device and the source of the transistor die, a wire bonding configured to form an electrical connection between the surface mount device and the source of the transistor die, and a clip configured to form an electrical connection between the surface mount device and the source of the transistor die. Claim 31 In claim 18, the surface mount device comprises a ceramic capacitor. Claim 32 In claim 18, the surface mount device is a device comprising a resistor. Claim 33 In claim 18, the device, wherein the at least one wire bond is configured to electrically couple the surface mount device to a die implemented within an RF transistor package. Claim 34 In claim 18, the device, wherein the at least one wire bond is configured to electrically couple the surface mount device to one or more metal contacts. Claim 35 A process for implementing an RF transistor package, comprising: providing a metal submount; mounting a transistor die on the metal submount; mounting a surface mount IPD component on the metal submount, wherein the surface mount IPD component comprises a dielectric substrate including a first pad and a second pad disposed on the top surface of the surface mount IPD component and a top surface of the surface mount IPD component; providing a first terminal and a second terminal on a surface mount device; mounting the first terminal of the surface mount device on the first pad and mounting the second terminal of the surface mount device on the second pad; and configuring at least one of the first terminal and the second terminal to be isolated from the metal submount by the dielectric substrate. and the method comprises the step of bonding at least one wire bond to at least one of the first pad and the second pad, wherein the dielectric substrate of the surface mount IPD component comprises a material having thermal conductivity that operates at a lower temperature and improves device reliability, and the material comprises at least one of alumina, aluminum nitride (AlN), and beryllium oxide (BeO). , RF transistor package implementation process. Claim 36 delete Claim 37 An RF transistor package comprising: a metal submount; a transistor die mounted on the metal submount; a surface mount IPD component mounted on the metal submount, wherein the surface mount IPD component comprises a dielectric substrate comprising a top surface and a bottom surface and at least a first pad and a second pad disposed on the top surface of the surface mount IPD component; at least one surface mount device comprising a first terminal and a second terminal, wherein the first terminal of the surface mount device is mounted on the first pad and the second terminal is mounted on the second pad, and at least one of the first terminal and the second terminal is configured to be isolated from the metal submount by the dielectric substrate; and at least one wire bond coupled to at least one of the first pad and the second pad, wherein the dielectric substrate of the surface mount IPD component comprises a dielectric material having thermal conductivity that operates at a lower temperature and improves device reliability, and comprises an alumina substrate, an RF transistor package implementation process. Claim 38 In claim 35, the surface mount IPD component comprises a metallization layer located on the bottom surface of a dielectric substrate, in an RF transistor package implementation process. Claim 39 In claim 35, the dielectric substrate of the surface mount IPD component comprises a multilayer substrate, in an RF transistor package implementation process. Claim 40 In claim 35, the surface mount IPD component comprises a metallic surface configured to implement a circuit structure including one of a capacitor, an inductor, and a resistor, in an RF transistor package implementation process. Claim 41 In claim 35, the RF transistor package implementation process, wherein the transistor die includes an LDMOS transistor die. Claim 42 In claim 35, the transistor die comprises an RF transistor package implementation process including a GaN-based HEMT. Claim 43 In claim 35, the process further comprises the step of implementing a plurality of transistors, an RF transistor package implementation process. Claim 44 In claim 43, the process further comprises the step of implementing the plurality of transistors in a Doherty structure, an RF transistor package implementation process. Claim 45 An RF transistor package implementation process according to claim 35, wherein the process further comprises the step of implementing a surface-mount IPD component having a plurality of surface-mount devices; and the step of mounting the plurality of surface-mount devices on the top surface of the surface-mount IPD component. Claim 46 An RF transistor package implementation process according to claim 35, wherein the process further comprises the step of configuring the dielectric substrate to include at least one of a via for forming an electrical connection between the surface mount device and the metal submount, edge plating configured to form an electrical connection between the surface mount device and the metal submount, wire bonding configured to form an electrical connection between the surface mount device and the metal submount, and a clip configured to form an electrical connection between the surface mount device and the metal submount. Claim 47 An RF transistor package implementation process according to claim 35, wherein the process further comprises the step of configuring the dielectric substrate to include at least one of a via configured to form an electrical connection between the surface mount device and the source of the transistor die, an edge plating configured to form an electrical connection between the surface mount device and the source of the transistor die, a wire bonding configured to form an electrical connection between the surface mount device and the source of the transistor die, and a clip configured to form an electrical connection between the surface mount device and the source of the transistor die. Claim 48 In claim 35, the process further comprises the step of configuring the at least one wire bond to electrically couple the surface mount device to the transistor die, an RF transistor package implementation process. Claim 49 An RF transistor package implementation process according to claim 35, wherein the process further comprises the step of configuring the at least one wire bond to electrically couple the surface mount device to one or more metal contacts. Claim 50 In claim 35, the surface mount device comprises an RF transistor package implementation process including a ceramic capacitor. Claim 51 In claim 35, the surface mount device comprises an RF transistor package implementation process including a resistor.

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