Clock phase fixing method and system for a ground-based interferometric radar system

Abstract

The application provides a clock phase fixing method and system of a ground-based interferometric radar system, and the method comprises the following steps: fixing the phase of a data output clock DCO generated by a chip internal frequency division of a digital-to-analog converter clock DACCLK of the ground-based interferometric radar system relative to a data output clock of an analog-to-digital converter clock ADCCLK chip; the DACCLK and the ADCCLK are homologous and phase-aligned, the phase of a data output clock of the ADCCLK chip is fixed relative to the ADCCLK; fixing the phase of a DAC data generation clock DDS_CLK generated by a region clock buffer BUFR frequency division of the DCO relative to the DCO; fixing the phase of a DAC chip internal clock DACINT relative to an input clock DCI and the DCO clock respectively; fixing the rising edge of a repetition frequency pulse PRF generation clock PRF_CLK of the ground-based interferometric radar system relative to the rising edges of the DAC, the ADC, the DCO and the DDS_CLK; and providing a phase-locked time reference for the ground-based interferometric radar system based on the phase-fixed DAC, ADC, DCO and DDS_CLK. The scheme can improve the deformation detection precision of the radar system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radar technology, in particular to a clock phase fixing method and system of a ground-based interferometric radar system. BACKGROUND

[0002] The ground-based interferometric radar system applies frequency-modulated continuous wave (FMCW) and microwave interferometry technology, and can obtain deformation information of a target area in a radar line-of-sight one-dimensional range domain. The ground-based interferometric radar system has the characteristics of less influence of cloud and bad environment and high sampling rates in time domain and space domain, and has good application prospects in deformation monitoring of linear targets such as bridges.

[0003] The ground-based interferometric radar extracts deformation phases by interferometric calculation on two radar echo signals obtained at different times, and then calculates deformation variables. The deformation variable of an object that can be detected by the ground-based interferometric radar depends on the phase difference of signals detected by the radar receiving end at two sampling times.

[0004] In an actual radar system, the known phase of the transmitted signal is the phase of the signal generated by the transmitting DAC, and the measured echo phase is the phase of the signal obtained by the receiving ADC. Therefore, the difference between the two phases not only has the phase change caused by the deformation of the measured object, but also has the transmission phase of the signal transmitting circuit and the signal receiving circuit.

[0005] If the transmission phase of the signal transmitting circuit and the signal receiving circuit is fixed, the phase difference between the measured transmitting and receiving signals is the deformation phase change of the measured object. However, in practice, the transmission phase of the signal transmitting circuit and the signal receiving circuit is not fixed, and in addition to the influence of external environmental factors such as temperature, the phase ambiguity caused by the internal clock frequency division of the chip also affects the transmission phase of the signal transmitting and receiving, so that the transmission phase of the signal transmitting and receiving randomly jumps at each power-on, thereby greatly reducing the deformation detection accuracy of the radar. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a clock phase fixing method and system of a ground-based interferometric radar system, so as to realize consistency of the transmission phase of the signal transmitting and receiving at each power-on in the radar system, and improve the deformation detection accuracy of the radar system.

[0007] To solve the above technical problems, the technical solutions of the present application are as follows:

[0008] The embodiment of the present application provides a clock phase fixing method of a ground-based interferometric radar system, comprising:

[0009] The data output clock DCO generated by the division of the digital-to-analog converter clock DACCLK chip of the ground-based interferometric radar system is phase-fixed relative to the data output clock of the analog-to-digital converter clock ADCCLK chip; the DACCLK and the ADCCLK are homologous and phase-aligned, and the data output clock of the ADCCLK chip is phase-fixed relative to the ADCCLK;

[0010] The DAC data generation clock DDS_CLK generated by the division of the DCO through the area clock buffer BUFR is phase-fixed relative to the DCO;

[0011] The DAC chip internal clock DACINT is phase-fixed relative to the input clock DCI and the DCO clock, respectively;

[0012] The rising edge of the repetition frequency pulse PRF generation clock PRF_CLK of the ground-based interferometric radar system is fixedly aligned with the rising edges of the DAC, the ADC, the DCO, and the DDS_CLK;

[0013] Based on the phase-fixed DAC, ADC, DCO, and DDS_CLK, a coherent time reference is provided for the transceiver link of the ground-based interferometric radar system.

[0014] Optionally, the data output clock DCO generated by the division of the digital-to-analog converter clock DACCLK chip of the ground-based interferometric radar system is phase-fixed relative to the data output clock of the analog-to-digital converter clock ADCCLK chip, comprising:

[0015] The sampling values of the sampling clock of the DCO and the sampling clock of the clock ADC_CLK1 of the same frequency as the DCO are obtained;

[0016] The same frequency clock ADC_CLK1 is generated based on the ADCCLK clock, and the phase is fixed;

[0017] The sampling values of the sampling clock of the DCO and the sampling clock of the ADC_CLK1 are subjected to exclusive OR operation, respectively, to obtain at least one operation result;

[0018] The at least one operation result is accumulated and summed to obtain a target statistical value;

[0019] According to the target statistical value and a preset threshold, the DCO is phase-fixed relative to the data output clock of the ADCCLK chip.

[0020] Optionally, the sampling values of the sampling clock of the DCO and the sampling clock of the clock ADC_CLK1 of the same frequency as the DCO are obtained, comprising:

[0021] In N phase comparison clock CLK0 periods, the values of the DCO and ADC_CLK1 are sampled respectively to obtain the sampling values of the DCO clock and the ADC_CLK1 clock; the N is a clock phase comparison period, and the phase comparison sampling clock CLK0 and ADCCLK, DACCLK are different sources and are not coherent.

[0022] Optionally, according to the target statistical value and a preset threshold, the data output clock phase of the DCO relative to the ADCCLK chip is fixed, including:

[0023] If the statistical value is less than or equal to the preset threshold, the data output clock phase of the DCO relative to the ADCCLK chip is fixed at a first phase value, otherwise, the DACCLK chip is reset, the new DCO is generated by re-dividing the DACCLK, the data output clock phase of the new DOC relative to the ADCCLK chip is fixed at the first phase value, and the reset of the DACCLK chip is stopped until the statistical value obtained according to the new DCO is less than or equal to the preset threshold.

[0024] Optionally, the DAC data generation clock DDS_CLK generated by the DCO through the region clock buffer BUFR is divided to fix the phase of the DCO, including:

[0025] The sampling values of the sampling clock of the DDS_CLK and the clock ADC_CLK2 which is coherent with the DDS_CLK are obtained;

[0026] The sampling clock of the DDS_CLK and the sampling clock of the ADC_CLK2 are based on the ADCCLK clock, and the phase is fixed; the sampling values of the sampling clock of the DDS_CLK and the sampling clock of the ADC_CLK2 are subjected to exclusive or operation respectively to obtain at least one operation result;

[0027] The at least one operation result is accumulated and summed to obtain a target statistical value;

[0028] According to the target statistical value and a preset threshold, the data output clock ADCCLK2 phase of the DDS_CLK relative to the chip ADCCLK is fixed.

[0029] Optionally, the sampling values of the DDS_CLK clock and the clock ADC_CLK2 which is coherent with the DDS_CLK are obtained, including:

[0030] In a phase comparison sampling clock CLK0 period, the values of the DDS_CLK and the ADC_CLK2 are sampled respectively to obtain the sampling values of the DDS_CLK clock and the ADC_CLK2 clock; the N is a clock phase comparison period, and the phase comparison sampling clock CLK0 and the DDS_CLK and the ADC_CLK2 are different sources and are not coherent.

[0031] Optionally, according to the target statistical value and a preset threshold, the phase of the DDS_CLK relative to the data output clock ADC_CLK2 of the chip ADCCLK is fixed, and the method comprises the following steps of:

[0032] If the statistical value is less than or equal to the preset threshold, the phase of the DDS_CLK relative to the data output clock of the ADC_CLK2 chip is fixed at a first phase value, otherwise, the BUFR is reset, the new DDS_CLK is generated by re-dividing the BUFR, the phase of the new DDS_CLK relative to the data output clock of the ADC_CLK2 chip is fixed at the first phase value, and the resetting of the BUFR chip is stopped until the statistical value obtained according to the new DDS_CLK is less than or equal to the preset threshold.

[0033] Optionally, the phase of a DAC chip internal clock DACINT and an input clock DCI relative to the DCO clock is fixed, and the method comprises the following steps of:

[0034] The target delay del_target is determined.

[0035] The actual return value del_actual of which the delay between the DAC internal clock DAC_INT generated by the DACCLK and the data input clock DCI of the DAC has the highest occurrence probability is obtained.

[0036] According to the del_actual and the del_target, the delay between the DAC_INT and the data input clock DCI of the DAC is fixed, and the phase relationship of the DAC output analog signal waveform relative to the DCO is fixed.

[0037] Optionally, according to the del_actual and the del_target, the delay between the DAC_INT and the data input clock DCI of the DAC is fixed, and the phase relationship of the DAC output analog signal waveform relative to the DCO is fixed, and the method comprises the following steps of:

[0038] When the DAC is powered on and initialized each time, the read del_actual is subjected to the following conditional judgment in the receiving controller configuration process.

[0039] If the del_actual and del_target satisfy:

[0040] del_target-del_guard≤del_actual≤del_target+del_guard, the next configuration is carried out, if not, another phase of the DACCLK is selected to judge until the condition is satisfied;

[0041] Wherein, 334 is the total range of DAC receiving controller delay line coding, 4ns corresponds to the total range of actual delay value of delay line, T DACCLK is the DACCLK clock period.

[0042] Optionally, the rising edge of the repetition frequency pulse PRF generation clock PRF_CLK of the ground-based interferometric radar system is fixedly aligned with the rising edge of the DAC, ADC, DCO and DDS_CLK, comprising:

[0043] The greatest common divisor of f DDS_CLK and f ADCCLK is f PRF_CLK ; f DDS_CLK is the clock frequency of DDS_CLK, f ADCCLK is the clock frequency of ADCCLK, and f PRF_CLK is the clock frequency of PRF_CLK;

[0044] According to f PRF_CLK , the rising edge of the repetition frequency pulse PRF generation clock PRF_CLK of the ground-based interferometric radar system is fixedly aligned with the rising edge of the DAC, ADC, DCO and DDS_CLK.

[0045] The application also provides a ground-based interferometric radar system, comprising:

[0046] A digital-to-analog converter clock DACCLK chip;

[0047] An analog-to-digital converter clock ADCCLK chip; and

[0048] A control circuit, which fixes the phase of the data output clock of the digital-to-analog converter clock DACCLK chip in the ground-based interferometric radar system relative to the data output clock of the analog-to-digital converter clock ADCCLK chip; the DACCLK and the ADCCLK are homologous and phase-aligned, the data output clock of the ADCCLK chip is phase-fixed with the ADCCLK, and the DAC data generation clock DDS_CLK generated by dividing the DCO through a region clock buffer BUFR is phase-fixed with the DCO;

[0049] fixing the phase of the DAC chip internal clock DACINT with the input clock DCI and the DCO clock respectively;

[0050] aligning the rising edge of the ground-based interferometric radar system repeated frequency pulse PRF generation clock PRF CLK with the rising edge of the DAC, ADC, DCO, DDS CLK;

[0051] controlling the ground-based interferometric radar system to provide a coherent time reference for the transceiver link based on the phase-fixed DAC, ADC, DCO, DDS CLK.

[0052] Optionally, the control circuit is a field programmable gate array FPGA circuit, and the FPGA circuit comprises:

[0053] The first clock phase fixing module is configured to: acquire sampling values of a sampling clock of the DCO and a sampling clock of a clock ADC CLK1 of the same frequency as the DCO; perform exclusive OR operation on the sampling values of the sampling clock of the DCO and the sampling clock of the ADC CLK1 respectively to obtain at least one operation result; perform accumulation summation on the at least one operation result to obtain a target statistical value; and fix the phase of the DCO relative to a data output clock of the ADC CLK chip according to the target statistical value and a preset threshold value.

[0054] The second clock phase fixing module is configured to: acquire sampling values of a sampling clock of the DDS CLK and a sampling clock of a clock ADC CLK2 of the same frequency as the DDS CLK; the clock ADC CLK2 of the same frequency is generated based on the ADC CLK clock and has a fixed phase; perform exclusive OR operation on the sampling values of the sampling clock of the DDS CLK and the sampling clock of the ADC CLK2 respectively to obtain at least one operation result; perform accumulation summation on the at least one operation result to obtain a target statistical value; and fix the phase of the DDS CLK relative to the data output clock ADC CLK2 of the chip ADC CLK according to the target statistical value and a preset threshold value.

[0055] The third clock phase fixing module is configured to determine a target delay del_target; acquire an actual return value del_actual of the delay between the DAC internal clock DAC INT generated by DAC CLK frequency division and the data input clock DCI of the DAC, the actual return value del_actual having the highest occurrence probability of the delay; and fix the delay between the DAC INT and the data input clock DCI of the DAC according to the del_actual and the del_target, and fix the phase relationship of the DAC output analog signal waveform relative to the DCO.

[0056] The fourth clock phase fixing module is configured to:DDS_CLK and f ADCCLK The greatest common divisor of f PRF_CLK , the f DDS_CLK is the clock frequency of DDS_CLK, the f ADCCLK is the clock frequency of ADCCLK, the f PRF_CLK is the clock frequency of PRF_CLK; according to f PRF_CLK The rising edge of the repetition frequency pulse PRF generation clock PRF_CLK of the ground-based interferometric radar system is aligned and fixed with the rising edges of the DAC, ADC, DCO, and DDS_CLK.

[0057] The above solution of the present invention includes at least the following beneficial effects:

[0058] The above-mentioned solution of the present invention is to fix the phase of the data output clock DCO generated by the internal frequency division of the digital-to-analog converter clock DACCLK chip of the ground-based interferometric radar system relative to the data output clock of the analog-to-digital converter clock ADCCLK chip; the DACCLK and the ADCCLK are of the same source and phase-aligned, and the phase of the data output clock of the ADCCLK chip and the ADCCLK is fixed; the phase of the DAC data generation clock DDS_CLK generated by the DCO through the regional clock buffer BUFR is fixed with the DCO; the phase of the internal clock DACINT of the DAC chip is fixed with the input clock DCI and the DCO clock respectively; the rising edge of the repetition frequency pulse PRF generation clock PRF_CLK of the ground-based interferometric radar system is aligned and fixed with the rising edge of the DAC, ADC, DCO, and DDS_CLK; and based on the phase-fixed DAC, ADC, DCO, and DDS_CLK, signals are transmitted on the transceiver link of the ground-based interferometric radar system. This can achieve transmission phase consistency of the signal transceiver link every time the radar system is powered on, effectively improving the deformation detection accuracy of the radar system. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 1 is a flow chart of a method for fixing a clock phase of a ground-based interferometric radar system according to the present invention;

[0060] Figure 2 Schematic diagram of the radar system clock phase relationship of the present invention;

[0061] Figure 3 It is a schematic diagram of the control circuit principle in the ground-based interferometric radar system of the present invention;

[0062] Figure 4 This is another specific flow chart of the method for fixing the clock phase of the ground-based interferometric radar system of the present invention;

[0063] Figure 5is a module schematic diagram of the control circuit of the present application. DETAILED DESCRIPTION

[0064] Exemplary embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood, and so that the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0065] As Figure 1 shown, the embodiment of the present application proposes a clock phase fixing method of a ground-based interferometric radar system, comprising:

[0066] Step 11, fixing the phase of a data output clock DCO (voltage controlled oscillator clock) generated by a division inside a digital to analog converter clock DACCLK (Digital to Analog Converter Clock) chip of the ground-based interferometric radar system relative to a data output clock of an analog to digital converter clock ADCCLK (Analog to Digital Converter Clock) chip; the DACCLK and the ADCCLK are homologous and phase-aligned, and the data output clock of the ADCCLK chip is phase-fixed with the ADCCLK;

[0067] Step 12, fixing the phase of a DAC (Digital to Analog Converter) data generation clock DDS_CLK (Direct Digital Synthesis Clock) generated by a division of the DCO through a regional clock buffer BUFR (Regional Clock Buffer) with the DCO;

[0068] Step 13, respectively fixing the phase of a DAC chip internal clock DACINT with an input clock DCI and the DCO clock;

[0069] Step 14, fixing the rising edge of a pulse repetition frequency PRF (Pulse Repetition Frequency) generation clock PRF_CLK (Pulse Repetition Frequency Clock) of the ground-based interferometric radar system with the rising edges of the DAC, ADC (Analog to Digital Converter), DCO and DDS_CLK;

[0070] Step 15, based on the phase-fixed DAC, ADC, DCO, DDS CLK, a coherent time reference is provided for the transceiver link of the ground-based interferometric radar system.

[0071] In this embodiment of the application, by fixing the phase of the ADCCLK chip data output clock DCO and the ADCCLK, fixing the phase of the DAC data generation clock DDS CLK and the DCO, respectively fixing the phase of the DACINT and the input clock DCI and the DCO clock, fixing the phase of the repetitive frequency pulse clock PRF CLK and the rising edge of the DAC, ADC, DCO, DDS CLK, and fixing the rising edge of the PRF CLK, DAC, ADC, DCO and DDS CLK, the transmission phase consistency of signal transmission and reception of the radar system is realized every time the power is turned on, which can effectively improve the deformation detection accuracy of the radar system.

[0072] It should be noted that, assuming that the ADCCLK and the DACCLK are homologous and phase-aligned, the phase of the ADC data output clock and the ADCCLK is fixed. The DACCLK is divided by the digital-to-analog converter clock DACCLK chip to generate a data output clock (DCO), and has the following relationship:

[0073]

[0074] wherein f DCO DCO clock frequency, f DACCLK DACCLK clock frequency. The frequency division of the digital-to-analog converter clock DACCLK chip inside causes the DCO rising edge to have four possible relative phases relative to the ADCCLK rising edge: φ0, φ1, φ2, and φ3.

[0075] In an optional embodiment of the application, step 11 can include:

[0076] Step 111, obtaining the sampling values of the sampling clock of the DCO and the sampling clock of the clock ADC_CLK1 of the same frequency as the DCO;

[0077] Step 112, the clock ADC_CLK1 of the same frequency is generated based on the ADCCLK clock, and the phase is fixed;

[0078] Step 113, performing exclusive OR operation on the sampling values of the sampling clock of the DCO and the sampling clock of the ADC_CLK1, respectively, to obtain at least one operation result;

[0079] Step 114, accumulating and summing the at least one operation result to obtain a target statistical value;

[0080] Step 115, according to the target statistical value and a preset threshold, fixing the data output clock phase of the DCO relative to the ADCCLK chip.

[0081] Here, step 111 can include:

[0082] Step 1111, sampling the values of the DCO and ADC_CLK1 respectively in a phase comparison sampling clock CLK0 period, obtaining the sampling values of the DCO clock and the ADC_CLK1 clock; the N is a clock phase comparison period, and the phase comparison sampling clock CLK0 and the ADCCLK and the DACCLK are different sources and not coherent.

[0083] Here, step 115 can include:

[0084] Step 1151, if the statistical value is less than or equal to the preset threshold, fixing the data output clock phase of the DCO relative to the ADCCLK chip at a first phase value, otherwise, resetting the DACCLK chip, making the DACCLK redivide to generate a new DCO, fixing the new DOC relative to the data output clock phase of the ADCCLK chip at the first phase value, until the statistical value obtained according to the new DCO is less than or equal to the preset threshold, and stopping resetting the DACCLK chip.

[0085] When the embodiment is implemented, the process of fixing the phase of the DCO and the ADCCLK can include:

[0086] The ADC data output clock frequency generation and the DCO same frequency clock ADCCLK1 can be generated by a clock phase comparison module using a clock CLK0 (such as an external crystal oscillator) which is different from the ADCCLK and the DACCLK and not coherent to sample the DCO and the ADCCLK1, if a clock phase period is N, then the sampling values of the DCO and the ADCCLK1 are XOR operated and then accumulated and summed in N CLK0 periods, obtaining a target statistical value SUM, the target statistical value SUM is distributed near the following four values: S0, Among them

[0087] The target statistical value SUM corresponds to the phase relationship between the DCO and the SDCCLK1.

[0088] A preset threshold is set: If the target statistical value SUM satisfies If the statistical value SUM obtained according to the new DCO meets the preset threshold value, the phase of the DCO relative to the data output clock of the ADC chip is fixed at the first phase value φ0; otherwise, the DACCLK chip is reset, and the new DCO is generated by re-dividing the DACCLK, until the statistical value SUM obtained according to the new DCO meets the preset threshold value. The resetting of the DACCLK chip is stopped, and the new DOC is fixed at the first phase value φ0 relative to the data output clock of the ADC chip. The phase of the DCO relative to the data output clock of the ADC is fixed.

[0089] In another optional embodiment of the present application, the step 12 can include:

[0090] Step 121: obtaining sampling values of a sampling clock of the DDS_CLK and a sampling clock of a clock ADC_CLK2 which is the same frequency as the DDS_CLK;

[0091] Step 122: the clock ADC_CLK2 which is the same frequency as the DDS_CLK is generated based on the ADCCLK clock, and the phase is fixed;

[0092] Step 123: the sampling values of the sampling clock of the DDS_CLK and the sampling clock of the ADC_CLK2 are respectively subjected to exclusive OR operation, and at least one operation result is obtained;

[0093] Step 124: the at least one operation result is subjected to accumulation summation, and a target statistical value is obtained;

[0094] Step 125: according to the target statistical value and a preset threshold value, the phase of the DDS_CLK relative to the data output clock ADCCLK2 of the chip ADCCLK is fixed.

[0095] Here, the step 121 can include:

[0096] Step 1211: the values of the DDS_CLK and the ADC_CLK2 are respectively sampled in a phase comparison sampling clock CLK0 period, and sampling values of the DDS_CLK clock and the ADC_CLK2 clock are obtained; the N is a clock phase comparison period, and the phase comparison sampling clock CLK0 and the DDS_CLK and the ADC_CLK2 are different sources and are not coherent.

[0097] Here, the step 125 can include:

[0098] Step 1251, if the statistical value is less than or equal to the preset threshold value, the DDS_CLK is fixed at a first phase value relative to the data output clock phase of the ADC_CLK2 chip, otherwise, the BUFR is reset, the new DDS_CLK is generated by re-dividing the BUFR, the new DDS_CLK is fixed at the first phase value relative to the data output clock phase of the ADC_CLK2 chip, until the statistical value obtained according to the new DDS_CLK is less than or equal to the preset threshold value, and the reset of the BUFR chip is stopped.

[0099] When the embodiment is implemented, the process of fixing the phase of the DDS_CLK relative to the data output clock ADCCLK2 of the chip ADCCLK can include:

[0100] The ADC data output clock frequency generation and the DDS_CLK same frequency clock ADCCLK2 can be generated by using a clock phase comparison module to sample the DDS_CLK and the ADCCLK2 by using a clock CLK0 (such as an external crystal oscillator) which is different from the ADCCLK and the DACCLK and is not in phase, if one clock phase period is N, the sampling values of the DDS_CLK and the ADCCLK2 in N CLK0 periods are XOR operated and then accumulated and summed to obtain a target statistical value SUM, the target statistical value SUM is distributed near the following four values: S0, Wherein

[0101] The target statistical value SUM corresponds to the phase relationship between the DDS_CLK and the SDCCLK2.

[0102] A preset threshold value is set: If the target statistical value SUM satisfies The DCO is fixed at a first phase value φ0 relative to the data output clock phase of the BUFR chip, otherwise, the BUFR chip is reset, the new DDS_CLK is generated by re-dividing the DACCLK, until the statistical value SUM obtained according to the new DDS_CLK satisfies The reset of the BUFR chip is stopped, and the new DDS_CLK is fixed at the first phase value φ0 relative to the data output clock phase of the BUFR chip. The phase of the DDS_CLK relative to the ADC data output clock is fixed.

[0103] In another optional embodiment of the application, step 13 can include:

[0104] Step 131, determining a target delay del_target.

[0105] Step 132, obtaining the actual return value del_actual of the delay between the DAC internal clock DAC_INT generated by DACCLK frequency division and the data input clock DCI of the DAC, which has the highest occurrence probability;

[0106] Step 133, fixing the delay between the DAC_INT and the data input clock DCI of the DAC according to the del_actual and del_target, and fixing the phase relationship of the DAC output analog signal waveform relative to the DCO. In this embodiment, the delay between the DAC_INT and the data input clock DCI of the DAC can be fixed, and the phase relationship of the DAC output analog signal waveform relative to the DCO can be fixed.

[0107] In another optional embodiment of the present application, step 133 can include:

[0108] Step 1331, when the DAC is powered on and initialized each time, the del_actual read out in the receiving controller configuration process is judged as follows: if the del_actual and del_target satisfy:

[0109] Step 1332, del_target-del_guard≤del_actual≤del_target+del_guard, then the next configuration is performed, and if not, another phase frequency division clock of DACCLK is selected for judgment until the condition is met.

[0110] Wherein, 334 is the total range of DAC receiving controller delay line encoding, 4ns corresponds to the total range of actual delay value of delay line, T DACCLK is the DACCLK clock period.

[0111] In this embodiment, the DCO phase can be fixed according to the del_actual and del_target, and the DAC data generation clock DDS_CLK generated by the DCO through the region clock buffer BUFR frequency division.

[0112] In the specific implementation of this embodiment, the process of respectively fixing the phase of the DAC chip internal clock DACINT, the input clock DCI and the DCO clock can include:

[0113] In the digital-to-analog converter clock DACCLK chip, in addition to the DCO generated by the DACCLK frequency division, there is also an internal clock DAC_INT generated by the DACCLK frequency division, which is used to detect the data input clock (DCI) of the DAC and synchronize the input data of the DAC. The DCI is generated by the DCO through the external control and data generation circuit of the digital-to-analog converter clock DACCLK chip, and when the external circuit is determined, the delay between DCI and DCO is fixed. When the internal clock DAC_INT of the DAC is blurred due to the DACCLK frequency division, the delay dci_del between DCI and DAC_INT is not fixed, which will cause the DAC output analog signal to have different phase relationships relative to the rising edge of DCI.

[0114] It is necessary to configure the DAC without any constraints and read the actual delay return value del_actual. After multiple configurations, it can be found that the return value may have the following several kinds: del1, del2, del3... Select the one with the highest probability of occurrence as the target delay del_target, and set the judgment condition:

[0115] del_target-del_guard≤del_actual≤del_target+del_guard

[0116] Wherein, 334 is the total range of the DAC receiving controller delay line encoding, 4ns corresponds to the total range of the actual delay value of the delay line, T DACCLK is the DACCLK clock period, that is, the relative delay between DAC_INT with different phase relationships generated by DACCLK frequency division.

[0117] When the DAC is powered on and initialized each time, the del_actual read out in the receiving controller configuration process is judged according to the above condition, and if it meets the condition, the next configuration is carried out, and if it does not meet the condition, the register clkdivph value is increased by 1 to select another phase frequency division clock of DACCLK, until the judgment condition is met. At this time, the phase relationship of DAC_INT, DCO and DCI is fixed, that is, the influence of the frequency division blur in the digital-to-analog converter clock DACCLK chip is removed, so that the phase relationship of the DAC output analog signal waveform relative to DCO is fixed.

[0118] In another optional embodiment of the application, step 14 can include:

[0119] Step 141, f DDS_CLK and the greatest common divisor of f ADCCLK is f PRF_CLK ; f DDS_CLK is the clock frequency of DDS_CLK, and f ADCCLKis the clock frequency of ADCCLK, the f PRF_CLK is the clock frequency of PRF_CLK;

[0120] Step 142, according to the f PRF_CLK , align and fix the repetition frequency pulse PRF generation clock PRF_CLK of the ground-based interferometric radar system with the rising edge of the DAC, ADC, DCO, and DDS_CLK.

[0121] In this embodiment, the repetition frequency pulse PRF of the ground-based interferometric radar system can be aligned with the rising edge of the DAC, ADC, DCO, and DDS_CLK to generate the clock PRF_CLK.

[0122] In a specific implementation of this embodiment, the process of aligning and fixing the rising edge of the repetition frequency pulse PRF generation clock PRF_CLK of the ground-based interferometric radar system with the rising edge of the DAC, ADC, DCO, and DDS_CLK may include:

[0123] The pulse repetition frequency (PRF) in a radar digital system is the reference for the entire system's transmission and reception. It marks the start of the DDS generating data, the DAC playing the transmit waveform, and the ADC sampling data packaging. Therefore, the rising edge of the PRF should have a fixed phase relationship with the rising edges of all clocks in the system's transmit and receive links. The frequencies of the DDS data generation clock, DAC data output clock, and ADC data output clock are different. The PRF generation clock PRF_CLK should be the slowest clock in the transmit and receive links. Since DDS_CLK is generated by the DCO frequency division, f is selected. DDS_CLK and f ADCCLK The greatest common divisor of f PRF_CLK , the f DDS_CLK is the clock frequency of DDS_CLK, the f ADCCLK is the clock frequency of ADCCLK, the f PRF_CLK is the clock frequency of PRF_CLK, so that the phase relationship between the rising edge of the PRF generated by PRF_CLK and the rising edges of the above clocks is fixed.

[0124] The following combination Figure 2 The specific implementation process of the above embodiment of the present invention is described as follows:

[0125] The phase relationship between the clocks in the radar digital system transmit and receive links may include:

[0126] DAC, ADC input clock DACCLK and ADCCLK adopt external homologous clock, DACCLK frequency division produces DCO four kinds of phase relations (four kinds of phase clock its rising edge is shown as dotted arrow), DCO in frequency division produces DDS_CLK four kinds of phase relations as well;

[0127] By obtaining the sampling value of the sampling clock of the DCO and the sampling clock of the clock ADC_CLK1 of the same frequency as the DCO;The sampling value of the sampling clock of the DCO and the sampling clock of the ADC_CLK1 is respectively operated by XOR operation, and at least one operation result is obtained;

[0128] The at least one operation result is accumulated and summed to obtain a target statistical value;According to the target statistical value and the preset threshold, the phase of the data output clock of the DCO relative to the ADCCLK chip is fixed at the position shown in Figure 2 ;

[0129] At the same time, by determining a target delay del_target;Obtain the actual return value del_actual of the delay between the DAC internal clock DAC_INT generated by DACCLK frequency division and the data input clock DCI of DAC;According to the del_actual and del_target, the delay between the DAC_INT and the data input clock DCI of the DAC is fixed, and the phase relationship of the DAC output analog signal waveform relative to the DCO is fixed at the position shown in Figure 2 ;

[0130] Finally, the greatest common divisor of f DDS_CLK And f ADCCLK As f PRF_CLK ;The f DDS_CLK Is the clock frequency of DDS_CLK, the f ADCCLK Is the clock frequency of ADCCLK, and the f PRF_CLK Is the clock frequency of PRF_CLK;According to the f PRF_CLK , the rising edge of the ground-based interferometric radar system pulse repetition frequency PRF generation clock PRF_CLK is aligned and fixed with the rising edge of the DAC, ADC, DCO and DDS_CLK;

[0131] In this way, the phase of all clocks on the system transmission and reception link is consistent, the waveform and PEF phase relationship of the radar system transmission are fixed at each power-on, the received echo signal is packaged and stored with PRF as reference delay, that is, the stored sampling waveform phase is fixed, and the consistency of the circuit transmission phase of the radar system is realized at multiple power-on.

[0132] As Figure 3As shown in the above embodiment of the present application, the above method can be implemented based on a control circuit in a ground-based interferometric radar system, which can be a field programmable gate array (FPGA) circuit. The FPGA is used as a system transmission and reception control core. The model of the DAC can be AD9739, and the model of the ADC can be AD9640. The ADCCLK and the DACCLK can use external 2G and 100M clock sources, respectively. The DACCLK is divided into two 500M clocks DAC_INT and DCO in a digital-to-analog converter clock DACCLK chip. The DCO is output to the FPGA for data synchronization. The DCO is divided into a 125M DDS_CLK in the FPGA through a BUFR for generating waveform data. The data clock output by the ADC is generated through a clock wizard (clock wizard) in the FPGA to generate ADCCLK1 (500M), ADCCLK2 (125M) and PRF_CLK (25M). The output phase of the clock wizard is limited to align the rising edges of the ADCCLK1, the ADCCLK2 and the PRF_CLK. Two clock phase comparison modules are designed in the FPGA to compare the clock phases of the ADCCLK1 and the DCO (500M clock phase comparison), and the ADCCLK2 and the DDS_CLK (125M clock phase comparison), respectively. The clock phase comparison modules use a 10M clock generated by an external crystal oscillator that is not the same as the non-coherent non-phase reference clock.

[0133] As shown in the above embodiment of the present application, the above method can be implemented based on a control circuit in a ground-based interferometric radar system, which can be a field programmable gate array (FPGA) circuit. The FPGA is used as a system transmission and reception control core. The model of the DAC can be AD9739, and the model of the ADC can be AD9640. The ADCCLK and the DACCLK can use external 2G and 100M clock sources, respectively. The DACCLK is divided into two 500M clocks DAC_INT and DCO in a digital-to-analog converter clock DACCLK chip. The DCO is output to the FPGA for data synchronization. The DCO is divided into a 125M DDS_CLK in the FPGA through a BUFR for generating waveform data. The data clock output by the ADC is generated through a clock wizard (clock wizard) in the FPGA to generate ADCCLK1 (500M), ADCCLK2 (125M) and PRF_CLK (25M). The output phase of the clock wizard is limited to align the rising edges of the ADCCLK1, the ADCCLK2 and the PRF_CLK. Two clock phase comparison modules are designed in the FPGA to compare the clock phases of the ADCCLK1 and the DCO (500M clock phase comparison), and the ADCCLK2 and the DDS_CLK (125M clock phase comparison), respectively. The clock phase comparison modules use a 10M clock generated by an external crystal oscillator that is not the same as the non-coherent non-phase reference clock. Figure 4 As shown in the above embodiment of the present application, the above method can be implemented based on a control circuit in a ground-based interferometric radar system, which can be a field programmable gate array (FPGA) circuit. The FPGA is used as a system transmission and reception control core. The model of the DAC can be AD9739, and the model of the ADC can be AD9640. The ADCCLK and the DACCLK can use external 2G and 100M clock sources, respectively. The DACCLK is divided into two 500M clocks DAC_INT and DCO in a digital-to-analog converter clock DACCLK chip. The DCO is output to the FPGA for data synchronization. The DCO is divided into a 125M DDS_CLK in the FPGA through a BUFR for generating waveform data. The data clock output by the ADC is generated through a clock wizard (clock wizard) in the FPGA to generate ADCCLK1 (500M), ADCCLK2 (125M) and PRF_CLK (25M). The output phase of the clock wizard is limited to align the rising edges of the ADCCLK1, the ADCCLK2 and the PRF_CLK. Two clock phase comparison modules are designed in the FPGA to compare the clock phases of the ADCCLK1 and the DCO (500M clock phase comparison), and the ADCCLK2 and the DDS_CLK (125M clock phase comparison), respectively. The clock phase comparison modules use a 10M clock generated by an external crystal oscillator that is not the same as the non-coherent non-phase reference clock.

[0134] After the system is powered on, the DAC completes the configuration and satisfies del_target-del_guard≤del_actual≤del_target+del_guard, the exclusive or value cumulative sum SUM1 (500M phase comparison result) and SUM2 (125M phase comparison result) of the two clock phase comparison modules are calculated in sequence. Taking N=16384 samples as a clock phase comparison period, whether SUM1 and SUM2 satisfy the judgment condition of the formula after each clock phase comparison period is determined. If SUM1 does not satisfy, the clock phase comparison module outputs a reset signal to trigger the DAC pin reset. After the pin reset, the DAC configuration needs to be performed again to satisfy del_target-del_guard≤del_actual≤del_target+del_guard again. If SUM2 does not satisfy, the clock phase comparison module outputs a reset signal to trigger the BUFR reset. If both satisfy, it is considered that the clock phase comparison is completed, and the system enters a waiting state.

[0135] In the above-described embodiments of the present invention, by designing and constraining the phase of the chip's internal clock, the starting phase of the system's output transmit signal waveform and the sampling instant of the received signal maintain a fixed phase relative to the system's reference pulse. This allows for simple and convenient phase consistency between transmitted and received signals at every power-up of the radar system, improving the radar system's deformation detection accuracy.

[0136] An embodiment of the present invention further provides a ground-based interferometric radar system, comprising:

[0137] Digital-to-analog converter clock DACCLK chip;

[0138] Analog-to-digital converter clock ADCCLK chip; and

[0139] A control circuit, wherein the control circuit fixes the phase of the data output clock DCO generated by internal frequency division of the digital-to-analog converter clock DACCLK chip of the ground-based interferometric radar system relative to the data output clock of the analog-to-digital converter clock ADCCLK chip; the DACCLK and the ADCCLK are of the same source and phase-aligned, and the data output clock of the ADCCLK chip and the ADCCLK are fixed in phase;

[0140] Fixing the phase of the DAC data generation clock DDS_CLK generated by the DCO through the regional clock buffer BUFR;

[0141] Fixing the phases of the DAC chip internal clock DACINT, the input clock DCI and the DCO clock respectively;

[0142] Align and fix the rising edge of the repetition frequency pulse PRF generation clock PRF_CLK of the ground-based interferometric radar system with the rising edge of the DAC, ADC, DCO, and DDS_CLK;

[0143] The ground-based interferometric radar system is controlled to provide a coherent time reference for the transceiver link based on the phase-fixed DAC, ADC, DCO, and DDS_CLK.

[0144] like Figure 5 As shown, the control circuit in the ground-based interferometric radar system is a field programmable gate array FPGA circuit 50, and the FPGA circuit 50 includes:

[0145] The first clock phase fixing module 51 is configured to acquire sampling values of a sampling clock of the DCO and a sampling clock of a clock ADC CLK1 of the same frequency as the DCO; perform exclusive OR operation on the sampling values of the sampling clock of the DCO and the sampling clock of the ADC CLK1 respectively to obtain at least one operation result; perform accumulation summation on the at least one operation result to obtain a target statistical value; and fix the phase of the DCO relative to a data output clock of the ADCCLK chip according to the target statistical value and a preset threshold value.

[0146] The second clock phase fixing module 52 is configured to acquire sampling values of a sampling clock of the DDS CLK and a sampling clock of a clock ADC CLK2 of the same frequency as the DDS CLK; the clock ADC CLK2 of the same frequency is generated based on the ADCCLK clock and has a fixed phase; perform exclusive OR operation on the sampling values of the sampling clock of the DDS CLK and the sampling clock of the ADC CLK2 respectively to obtain at least one operation result; perform accumulation summation on the at least one operation result to obtain a target statistical value; and fix the phase of the DDS CLK relative to a data output clock ADCCLK2 of the chip ADCCLK according to the target statistical value and a preset threshold value.

[0147] The third clock phase fixing module 53 is configured to determine a target delay del_target; acquire an actual return value del_actual of the highest occurrence probability of a delay between a DAC internal clock DAC INT generated by DACCLK frequency division and a data input clock DCI of the DAC; and fix the delay between the DAC INT and the data input clock DCI of the DAC according to the del_actual and the del_target, so as to fix the phase relationship of an analog signal waveform output by the DAC relative to the DCO.

[0148] The fourth clock phase fixing module 54 is configured to fix f DDS_CLK and f ADCCLK as f PRF_CLK , wherein f DDS_CLK is a clock frequency of the DDS CLK, f ADCCLK is a clock frequency of the ADCCLK, and f PRF_CLK is a clock frequency of the PRF CLK; and align and fix rising edges of a pulse repetition frequency PRF generation clock PRF CLK of a ground-based interferometric radar system with rising edges of the DAC, the ADC, the DCO and the DDS CLK according to f PRF_CLK .

[0149] Optionally, the data output clock DCO generated by the in-chip frequency division of the digital-to-analog converter clock DACCLK of the ground-based interferometric radar system is fixed in phase relative to the data output clock of the analog-to-digital converter clock ADCCLK chip, comprising:

[0150] obtaining sampling values of the sampling clock of the DCO and the clock ADC_CLK1 of the same frequency as the DCO;

[0151] The same frequency clock ADC_CLK1 is generated based on the ADCCLK clock, and the phase is fixed;

[0152] The sampling values of the sampling clock of the DCO and the sampling clock of the ADC_CLK1 are respectively subjected to exclusive OR operation to obtain at least one operation result;

[0153] The at least one operation result is accumulated and summed to obtain a target statistical value;

[0154] According to the target statistical value and the preset threshold, the DCO is fixed in phase relative to the data output clock of the ADCCLK chip.

[0155] Optionally, obtaining the sampling values of the sampling clock of the DCO and the clock ADC_CLK1 of the same frequency as the DCO comprises:

[0156] In N phase comparison sampling clock CLK0 periods, the values of the DCO and ADC_CLK1 are respectively sampled to obtain the sampling values of the DCO clock and the ADC_CLK1 clock; N is a clock phase comparison period, and the phase comparison sampling clock CLK0 and ADCCLK, DACCLK are different sources and not coherent.

[0157] Optionally, according to the target statistical value and the preset threshold, the DCO is fixed in phase relative to the data output clock of the ADCCLK chip, comprising:

[0158] If the statistical value is less than or equal to the preset threshold, the DCO is fixed in phase relative to the data output clock of the ADCCLK chip at a first phase value, otherwise, the DACCLK chip is reset, the new DCO is generated by the DACCLK re-division, the new DOC is fixed in phase relative to the data output clock of the ADCCLK chip at the first phase value, until the statistical value obtained according to the new DCO is less than or equal to the preset threshold, and the reset of the DACCLK chip is stopped.

[0159] Optionally, the DAC data generation clock DDS_CLK generated by the frequency division of the DCO through the region clock buffer BUFR is fixed in phase with the DCO, comprising:

[0160] acquiring sampling values of a sampling clock of the DDS_CLK and a sampling clock of a clock ADC_CLK2 which is the same frequency as the DDS_CLK;

[0161] the clock ADC_CLK2 is generated based on an ADCCLK clock and has a fixed phase;

[0162] the sampling values of the sampling clock of the DDS_CLK and the sampling clock of the ADC_CLK2 are subjected to exclusive OR operation respectively to obtain at least one operation result;

[0163] the at least one operation result is subjected to accumulation summation to obtain a target statistical value;

[0164] according to the target statistical value and a preset threshold, the phase of the DDS_CLK relative to a data output clock ADCCLK2 of the chip ADCCLK is fixed.

[0165] Optionally, the acquiring of the sampling values of the DDS_CLK clock and the clock ADC_CLK2 which is the same frequency as the DDS_CLK comprises:

[0166] the values of the DDS_CLK and the ADC_CLK2 are sampled respectively within a period of N phase comparison sampling clocks CLK0 to obtain the sampling values of the DDS_CLK clock and the ADC_CLK2 clock; the N is a period of one clock phase comparison, and the phase comparison sampling clock CLK0 is different from the DDS_CLK and the ADC_CLK2 in source and is not coherent.

[0167] Optionally, according to the target statistical value and a preset threshold, the phase of the DDS_CLK relative to a data output clock ADCCLK2 of the chip ADCCLK is fixed, comprising:

[0168] if the statistical value is less than or equal to the preset threshold, the phase of the DDS_CLK relative to the data output clock of the ADC_CLK2 chip is fixed at a first phase value, otherwise, the BUFR is reset, the new DDS_CLK is generated by the BUFR re-dividing, the phase of the new DDS_CLK relative to the data output clock of the ADC_CLK2 chip is fixed at the first phase value, until the statistical value obtained according to the new DDS_CLK is less than or equal to the preset threshold, and the reset of the BUFR chip is stopped.

[0169] Optionally, the phase of a DAC chip internal clock DACINT is fixed respectively with an input clock DCI and the DCO clock, comprising:

[0170] a target delay del_target is determined;

[0171] acquiring an actual return value del_actual of a highest probability of occurrence of a delay between a DAC internal clock DAC_INT generated by frequency division of the DACCLK and a data input clock DCI of the DAC;

[0172] fixing the delay between the DAC_INT and the data input clock DCI of the DAC according to the del_actual and a del_target, and fixing a phase relationship of an analog signal waveform output by the DAC relative to a phase of the DCO.

[0173] Optionally, fixing the delay between the DAC_INT and the data input clock DCI of the DAC according to the del_actual and the del_target, and fixing the phase relationship of the analog signal waveform output by the DAC relative to the phase of the DCO, comprises:

[0174] When the DAC is powered on and initialized each time, the del_actual read out in the receiving controller configuration process is judged as follows: if the del_actual and the del_target satisfy:

[0175] del_target-del_guard≤del_actual≤del_target+del_guard, a next configuration is performed, and if the condition is not satisfied, another phase of the frequency division clock of the DACCLK is selected for judgment until the condition is satisfied.

[0176] wherein, 334 is a total range of DAC receiving controller delay line encoding, 4ns corresponds to a total range of actual delay values of the delay line, T DACCLK is a clock period of the DACCLK.

[0177] Optionally, rising edges of a repetition frequency pulse PRF generation clock PRF_CLK of the ground-based interferometric radar system are aligned and fixed with rising edges of the DAC, the ADC, the DCO and the DDS_CLK, comprising:

[0178] a greatest common divisor of f DDS_CLK and f ADCCLK is taken as f PRF_CLK ; f DDS_CLK is a clock frequency of the DDS_CLK, f ADCCLK is a clock frequency of the ADCCLK, and f PRF_CLK is a clock frequency of the PRF_CLK.

[0179] According to the f PRF_CLKThe rising edge of a repetition frequency pulse PRF generation clock PRF_CLK of the ground-based interferometric radar system is aligned with the rising edges of the DAC, ADC, DCO, and DDS_CLK.

[0180] It should be noted that the system corresponds to the above method, and all implementation manners in the method embodiments are applicable to the system embodiments, and the same technical effects can also be achieved.

[0181] Embodiments of the application also provide a computer-readable storage medium comprising: storage instructions, when the storage instructions are run on a computer, causing the computer to execute the method described above. All implementation manners in the method embodiments are applicable to this embodiment, and the same technical effects can also be achieved.

[0182] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solutions. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0183] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0184] In the embodiments provided by the present application, it should be understood that the disclosed device and method can be implemented by other ways. For example, the device embodiments described above are only schematic, and the division of the units is only a logical function division, and there can be another division way in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0185] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., they can be located in one place, or can be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the present embodiment.

[0186] In addition, each functional unit in various embodiments of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0187] If the functions are realized in the form of software functional units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of software products. The computer software product is stored in a storage medium and includes a number of instructions for making a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a ROM, a RAM, a magnetic disk or an optical disk, and various program code storage media.

[0188] In addition, it should be noted that in the device and method of the present application, it is obvious that each component or each step can be decomposed and / or recombined. These decompositions and / or recombination should be considered as equivalent solutions of the present application. And the steps of executing the above series of processes can naturally be executed in time sequence according to the order of description, but it is not necessary to be executed in time sequence. Some steps can be executed in parallel or independently of each other. It can be understood by those skilled in the art that all or any steps or components of the method and device of the present application can be realized in hardware, firmware, software or their combination in any computing device (including processor, storage medium, etc.) or network of computing devices, which can be realized by those skilled in the art with their basic programming skills after reading the description of the present application.

[0189] Therefore, the purpose of the present application can also be realized by running a program or a group of programs on any computing device. The computing device can be a commonly known general-purpose device. Therefore, the purpose of the present application can also be realized only by providing a program product containing program code for realizing the method or device. That is, such a program product also constitutes the present application, and the storage medium storing such a program product also constitutes the present application. Obviously, the storage medium can be any commonly known storage medium or any storage medium developed in the future. It should be noted that in the device and method of the present application, it is obvious that each component or each step can be decomposed and / or recombined. These decompositions and / or recombination should be considered as equivalent solutions of the present application. And the steps of executing the above series of processes can naturally be executed in time sequence according to the order of description, but it is not necessary to be executed in time sequence. Some steps can be executed in parallel or independently of each other.

[0190] The above is the preferred embodiment of the present application, it should be noted that for those skilled in the art, without departing from the principles described in the present application, can also be made several improvements and refinements, these improvements and refinements should also be considered the scope of protection of the present application.

Claims

1. A method of clock phase fixing for a ground-based interferometric radar system, characterized by, The method comprises the following steps: The data output clock DCO generated by the division of the digital-to-analog converter clock DACCLK chip of the ground-based interferometric radar system is fixed in phase with the data output clock of the analog-to-digital converter clock ADCCLK chip; the input clock of the DACCLK chip and the input clock of the ADCCLK chip are the same in source and are aligned in phase, and the data output clock of the ADCCLK chip is fixed in phase with the input clock of the ADCCLK chip; The DAC data generation clock DDS_CLK generated by the division of the DCO through the regional clock buffer BUFR is fixed in phase with the DCO; The internal clock DACINT of the DAC chip is fixed in phase with the input clock DCI and the DCO clock respectively; The rising edge of the repetition frequency pulse PRF generation clock PRF_CLK of the ground-based interferometric radar system is fixed in alignment with the rising edges of the DAC, ADC, DCO, and DDS_CLK; Based on the phase-fixed DAC, ADC, DCO, and DDS_CLK, a coherent time reference is provided for the transceiver link of the ground-based interferometric radar system.

2. The method of claim 1, wherein The data output clock DCO generated by the division of the digital-to-analog converter clock DACCLK chip of the ground-based interferometric radar system is fixed in phase with the data output clock of the analog-to-digital converter clock ADCCLK chip, comprising: Obtaining the sampling values of the sampling clock of the DCO and the sampling clock of the clock ADC_CLK1 of the same frequency as the DCO; The clock ADC_CLK1 is generated based on the ADCCLK clock, and the phase is fixed; The sampling values of the sampling clock of the DCO and the sampling clock of the ADC_CLK1 are subjected to exclusive OR operation respectively to obtain at least one operation result; The at least one operation result is accumulated and summed to obtain a target statistical value; According to the target statistical value and the preset threshold, the DCO is fixed in phase with the data output clock of the ADCCLK chip.

3. The method of clock phase fixing for a ground-based interferometric radar system of claim 2, wherein, Obtaining the sampling values of the sampling clock of the DCO and the sampling clock of the clock ADC_CLK1 of the same frequency as the DCO, comprising: In N phase comparison sampling clock CLK0 periods, the values of the DCO and ADC_CLK1 are sampled respectively to obtain the sampling values of the DCO clock and the ADC_CLK1 clock; N is a clock phase comparison period, and the phase comparison sampling clock CLK0 is different in source and non-coherent with the ADCCLK and DACCLK.

4. The method of claim 2, wherein According to the target statistical value and the preset threshold, the DCO is fixed in phase with the data output clock of the ADCCLK chip, comprising: If the statistical value is less than or equal to the preset threshold, the data output clock phase of the DCO relative to the ADCCLK chip is fixed at a first phase value; otherwise, the DACCLK chip is reset, the new DCO is generated by re-dividing the DACCLK, the data output clock phase of the new DCO relative to the ADCCLK chip is fixed at the first phase value, until the statistical value obtained according to the new DCO is less than or equal to the preset threshold, and the reset of the DACCLK chip is stopped.

5. The method of claim 1, wherein The DAC data generation clock DDS_CLK generated by dividing the DCO through a region clock buffer BUFR is fixed relative to the DCO phase, comprising: Obtaining sampling values of a sampling clock of the DDS_CLK and a sampling clock of a clock ADC_CLK2 of the same frequency as the DDS_CLK; The clock ADC_CLK2 is generated based on an ADCCLK clock, and the phase is fixed relative to the ADCCLK clock; The sampling values of the sampling clock of the DDS_CLK and the sampling clock of the ADC_CLK2 are respectively subjected to exclusive OR operation to obtain at least one operation result; The at least one operation result is accumulated and summed to obtain a target statistical value; According to the target statistical value and a preset threshold, the data output clock ADCCLK2 of the DDS_CLK relative to the chip ADCCLK is fixed in phase.

6. The method of fixing the clock phase of a ground-based interferometric radar system according to claim 5, characterized in that Obtaining sampling values of the DDS_CLK clock and the clock ADC_CLK2 of the same frequency as the DDS_CLK, comprising: In N phase comparison sampling clock CLK0 periods, the values of the DDS_CLK and the ADC_CLK2 are respectively sampled to obtain the sampling values of the DDS_CLK clock and the ADC_CLK2 clock; the N is a clock phase comparison period, and the phase comparison sampling clock CLK0 and the DDS_CLK and the ADC_CLK2 are of different sources and are not coherent.

7. The method of claim 5, wherein the clock phase fixing is performed by a ground-based interferometric radar system. According to the target statistical value and a preset threshold, the data output clock ADCCLK2 of the DDS_CLK relative to the chip ADCCLK is fixed in phase, comprising: If the statistical value is less than or equal to the preset threshold, the data output clock phase of the DDS_CLK relative to the ADC_CLK2 chip is fixed at a first phase value; otherwise, the BUFR is reset, the new DDS_CLK is generated by re-dividing the BUFR, the data output clock phase of the new DDS_CLK relative to the ADC_CLK2 chip is fixed at the first phase value, until the statistical value obtained according to the new DDS_CLK is less than or equal to the preset threshold, and the reset of the BUFR chip is stopped.

8. The method of claim 1, wherein Fixing the phases of the internal clock DACINT of the DAC chip, the input clock DCI and the DCO clock respectively, comprising: Determining a target delay del_target; acquiring an actual return value del_actual of a highest occurrence probability of a delay between a DAC internal clock DAC_INT generated by DACCLK frequency division and a data input clock DCI of the DAC; fixing the delay between the DAC_INT and the data input clock DCI of the DAC according to the del_actual and a del_target, and fixing a phase relationship of a DAC output analog signal waveform relative to a phase of the DCO.

9. The method of clock phase fixing for a ground-based interferometric radar system of claim 8, wherein, fixing the delay between the DAC_INT and the data input clock DCI of the DAC according to the del_actual and the del_target, and fixing a phase relationship of a DAC output analog signal waveform relative to a phase of the DCO, including: When the DAC is powered on and initialized each time, the del_actual read out in the receiving controller configuration process is judged as follows: If the del_actual and the del_target satisfy: del_target-del_guard≤del_actual≤del_target+del_guard, the next configuration is performed, if not, another phase frequency division clock of the DACCLK is selected for judgment until the condition is met; wherein, 334 is the total range of DAC receive controller delay line encoding, 4ns corresponds to the total range of delay line actual delay value, T DACCLK is the DACCLK clock period.

10. The method of claim 1, wherein aligning and fixing rising edges of a repetitive frequency pulse PRF generation clock PRF_CLK of a ground-based interferometric radar system with rising edges of the DAC, the ADC, the DCO, and the DDS_CLK, including: The greatest common divisor of f DDS_CLK and f ADCCLK is f PRF_CLK ; f DDS_CLK is the clock frequency of DDS_CLK, f ADCCLK is the clock frequency of ADCCLK, and f PRF_CLK is the clock frequency of PRF_CLK. According to the f PRF_CLK The rising edge of a repetition frequency pulse PRF generation clock PRF CLK of the ground-based interferometric radar system is fixed in alignment with the rising edge of the DAC, ADC, DCO, DDS CLK.

11. A ground-based interferometric radar system, characterized by including: a digital-to-analog converter clock DACCLK chip; an analog-to-digital converter clock ADCCLK chip; and a control circuit that fixes a phase of a data output clock DCO generated by frequency division in the digital-to-analog converter clock DACCLK chip of the ground-based interferometric radar system relative to a data output clock of the analog-to-digital converter clock ADCCLK chip; an input clock of the DACCLK chip and an input clock of the ADCCLK chip are homologous and phase-aligned, and a data output clock of the ADCCLK chip and the input clock of the ADCCLK chip are phase-fixed; fixing a phase of a DAC data generation clock DDS_CLK generated by frequency division of the DCO through a region clock buffer BUFR relative to the DCO; fixing phases of a DAC chip internal clock DACINT relative to an input clock DCI and the DCO clock, respectively; aligning and fixing rising edges of a repetitive frequency pulse PRF generation clock PRF_CLK of a ground-based interferometric radar system with rising edges of the DAC, the ADC, the DCO, and the DDS_CLK; controlling the ground-based interferometric radar system to provide a phase-related time reference for a transceiver link based on the phase-fixed DAC, the ADC, the DCO, and the DDS_CLK. The control circuit is a field programmable gate array FPGA circuit, and the FPGA circuit includes:

12. The ground-based interferometric radar system of claim 11, wherein, ​ The first clock phase fixing module is configured to obtain sampling values of a sampling clock of the DCO and a sampling clock of a clock ADC CLK1 of the same frequency as the DCO; perform exclusive OR operation on the sampling values of the sampling clock of the DCO and the sampling clock of the ADC CLK1, respectively, to obtain at least one operation result; perform accumulation summation on the at least one operation result to obtain a target statistical value; and fix the phase of the DCO relative to a data output clock of the ADCCLK chip according to the target statistical value and a preset threshold value. The second clock phase fixing module is configured to obtain sampling values of a sampling clock of the DDS CLK and a sampling clock of a clock ADC CLK2 of the same frequency as the DDS CLK; the clock ADC CLK2 of the same frequency is generated based on the ADCCLK clock, and the phase is fixed; perform exclusive OR operation on the sampling values of the sampling clock of the DDS CLK and the sampling clock of the ADC CLK2, respectively, to obtain at least one operation result; perform accumulation summation on the at least one operation result to obtain a target statistical value; and fix the phase of the DDS CLK relative to a data output clock ADCCLK2 of the chip ADCCLK according to the target statistical value and a preset threshold value. The third clock phase fixing module is configured to determine a target delay del_target; obtain an actual return value del_actual of a delay between a DAC internal clock DAC_INT generated by DACCLK frequency division and a data input clock DCI of the DAC, in which the delay has the highest occurrence probability; and fix the delay between the DAC_INT and the data input clock DCI of the DAC according to the del_actual and the del_target, so as to fix the phase relationship of an analog signal waveform output by the DAC relative to the DCO. A fourth clock phase fixing module is configured to fix f DDS_CLK and the greatest common divisor of f ADCCLK as f PRF_CLK , f DDS_CLK is the clock frequency of DDS_CLK, f ADCCLK is the clock frequency of ADCCLK, f PRF_CLK is the clock frequency of PRF_CLK; the rising edge of the repetition frequency pulse PRF of the ground-based interferometric radar system is generated according to f PRF_CLK , and is fixed in alignment with the rising edges of the DAC, ADC, DCO and DDS_CLK.

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