Phase compensation method for secondary channel of adaptive narrowband active filter based on delay

Abstract

The invention discloses a phase compensation method for a secondary channel of an adaptive narrowband active filter based on delay, the method comprising the following steps: disconnecting an interference source simulation device and a simulated power grid load, generating a sine wave with a known phase in an FPGA; injecting the sine wave into a load resistor through an injection point as a modulation wave signal of a switch tube; using an interference current sensor to collect the interference current signal on the load side; filtering and amplifying the collected interference current signal through a preamplifier, and then sending it to the FPGA; opening a logic analyzer in the FPGA, comparing the generated sine wave signal with the signal obtained by preamplification, and obtaining the phase deviation of the frequency point; delaying the error signal by a method of fixing the delay of a register, and compensating the phase of the offset signal and the interference signal deviation. The invention has no impact on the power grid, is easy to operate and implement, and can realize the interference current suppression function of the adaptive narrowband active power filter for any frequency point within 1kHz to 20kHz.

Description

Technical Field

[0001] The invention relates to the technical field of adaptive narrowband active power filters applied to a DC power grid, and in particular to a phase compensation method for a secondary channel of an adaptive narrowband active filter based on delay. Background Art

[0002] Adaptive active filters can be divided into broadband filters and narrowband filters. Broadband filters need to suppress interference within a frequency band indiscriminately, occupying more hardware resources and high cost. However, the interference in the power grid is mainly concentrated in the fundamental wave and its multiples, so only narrowband filters are needed to suppress interference with higher amplitudes.

[0003] The main method for identifying secondary channels in traditional broadband filtering is the random noise injection method. This method designs a FIR digital filter to represent the characteristics of the secondary channel. Through an adaptive algorithm, the filter parameters are adjusted in real time according to the objective function. When the LMS algorithm converges, the filter coefficient of the FIR filter is the unit impulse response function of the secondary channel. Specifically, this method uses FPGA to generate Gaussian white noise, which is amplified by power and finally collected by the error sensor after passing through the secondary channel. The Gaussian white noise and the signal collected by the error sensor are used as the input of the algorithm, and the unit impulse response function of the secondary channel is obtained using the LMS algorithm.

[0004] However, the random noise injection method requires injecting random noise into the DC power grid, which is difficult to estimate the harm to the power grid. In addition, the use of adaptive algorithms to compensate for the influence of the secondary channel consumes a lot of computer resources, which is not conducive to implementation on narrowband adaptive filters. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a phase compensation method for a secondary channel of an adaptive narrowband active filter based on delay in view of the defects in the prior art.

[0006] The technical solution adopted by the present invention to solve its technical problem is:

[0007] The present invention provides a delay-based adaptive narrowband active filter, comprising an interference source simulation device, a simulated power grid internal resistance R1, an interference current sensor C1, an injection point 1, an interference current sensor C2, a load resistor R2, a spectrum analyzer, and an injection point 2, which are connected in series to form a loop; the interference current sensor C1 and the interference current sensor C2 are also connected to a preamplifier, and the preamplifier, the injection point 1, and the injection point 2 are all connected to a host of a harmonic suppression device; wherein:

[0008] The interference source simulation device includes a signal source and a power amplifier connected to each other, and generates interference signals of different frequencies and amplitudes by adjusting the frequency and amplitude of the signal source;

[0009] Interference current sensor C1 is used to detect the frequency of interference signals;

[0010] Interference current sensor C2, used to detect the amplitude and phase of the interference signal;

[0011] The preamplifier is used to filter the frequency, amplitude and phase of the interference current collected by the interference current sensor C1 and the interference current sensor C2 and then send them to the main unit of the harmonic suppression device;

[0012] The main unit of the harmonic suppression device is used to generate a cancellation signal with the same amplitude and opposite phase as the interference current, and inject it at injection point 1 and injection point 2 to suppress the interference current.

[0013] Furthermore, the harmonic suppression device of the present invention is provided with an FPGA in the host, and a delay-based phase compensation method of the secondary channel of the adaptive narrowband active filter is implemented through the FPGA, thereby realizing the interference current suppression function of the adaptive narrowband active power filter for any frequency point within 1kHz to 20kHz.

[0014] The present invention provides a delay-based phase compensation method for a secondary channel of an adaptive narrowband active filter, the method comprising the following steps:

[0015] Step 1, combining the output interference characteristics of the target DC power grid, setting the simulated power grid internal resistance and load resistance;

[0016] Step 2, disconnect the interference source simulation device and the simulated grid load, and generate a sine wave with a known phase in the FPGA;

[0017] Step 3, using the above sine wave as the modulation wave signal of the power amplifier, that is, amplifying the power of the sine wave signal, and injecting it into the load resistor through the injection point to form an interference current interference_current;

[0018] Step 4, using the interference current sensor C1 and the interference current sensor C2 to collect the interference current signal on the load side; filtering and amplifying the collected interference current signal through the preamplifier to eliminate high-frequency clutter interference, and then sending it to the FPGA to form signal_error;

[0019] Step 5, open the logic analyzer in the FPGA, compare the generated sine wave signal with the signal obtained by preamplification, and obtain the phase deviation at the frequency point;

[0020] Step 6, delaying the error signal by a register fixed delay method to compensate for the phase difference between the offset signal and the interference signal;

[0021] Step 7, connect the interference source simulation device, after the interference current detection sensor C1 detects the frequency point, then delay compensate the signal_error detected by the interference current detection sensor C2 according to the locked phase deviation;

[0022] Step 8, set the harmonic signal source frequency-by-frequency from 1kHz to 20kHz. The harmonic source is a single-frequency output. The signal source generates a sinusoidal interference signal of a certain frequency. Before the harmonic suppression device is started, the spectrum analyzer monitors the interference signal amplitude in the circuit; after the harmonic suppression device is started, the amplitude of the harmonic interference component in the circuit is reduced, and the harmonic interference amplitude is also reduced.

[0023] Further, the method in step 2 of the present invention comprises:

[0024] In FPGA, DDS signal is generated by IP core. When FPGA generates IP core, the one-to-one correspondence between phase and amplitude is like the relationship between address and storage content in memory. If the amplitude value corresponding to each phase in a cycle is stored in the memory, then for a sinusoidal signal of any frequency, at any time, as long as the phase is known, the address is also known, and the amplitude can be obtained by looking up the table, that is, a sinusoidal wave signal_out with a known phase is generated.

[0025] Further, the method in step 5 of the present invention comprises:

[0026] Open the logic analyzer in the FPGA, compare the generated sinusoidal signal signal_out with the signal signal_error obtained by preamplifying the interference current signal collected by the interference current sensor on the load side, and obtain the phase deviation φ caused by the secondary channel within the frequency point. Since both signal_error and signal_out are periodic signals, signal_error is regarded as leading the phase of signal_out by 180°-φ.

[0027] Further, the method in step 6 of the present invention comprises:

[0028] Signal_error is delayed in the form of a register. Since the clock cycle is 400K, signal_error can be delayed by 12.5us by swapping it into the next register. A certain degree of delay is performed according to the value of the leading phase of signal_error, so that the phase of signal_error is 180° ahead or behind that of signal_out.

[0029] The beneficial effects of the present invention are as follows: the phase compensation method of the secondary channel of the adaptive narrowband active filter based on delay of the present invention, (1) the method is applicable to the phase compensation method of the secondary channel of the adaptive narrowband active filter, has no impact on the power grid, is easy to operate and implement, and does not increase the hardware complexity and cost. (2) the adaptive narrowband active power filter can realize the interference current suppression function of any frequency point within 1kHz to 20kHz. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0031] Figure 1 This is the experimental schematic diagram of the active filter;

[0032] Figure 2 This is a schematic diagram of the IP generating a sine wave in the FPGA;

[0033] Figure 3 It is before 1kHz interference current suppression;

[0034] Figure 4 After 1kHz interference current suppression;

[0035] Figure 5 It is before 10kHz interference current suppression;

[0036] Figure 6 After 10kHz interference current suppression;

[0037] Figure 7 It is before 20kHz interference current suppression;

[0038] Figure 8 After 20kHz interference current suppression. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0040] The experimental schematic diagram and experimental arrangement diagram of the adaptive narrowband active power filter of the embodiment of the present invention are shown in the attached drawings. Figure 1 As shown, it mainly includes the following parts:

[0041] An interference source simulation device that generates interference signals, an interference current sensor C1 that detects the frequency of the interference signal, an interference current sensor C2 that detects the amplitude and phase of the interference signal, a preamplifier that amplifies and filters the signal detected by the sensor, a harmonic suppression device host that generates suppression current, a spectrum analyzer that simulates the internal resistance of the power grid R1, the load resistance R2, and detects the interference suppression effect.

[0042] The interference simulation device consists of a signal generator and a power amplifier. By adjusting the frequency and amplitude of the signal generator, interference signals of different frequencies and amplitudes can be generated. The preamplifier sends the frequency, amplitude and phase of the interference current collected by the interference current sensors C1 and C2 to the harmonic suppression device after preamplification and filtering. The harmonic suppression device generates a cancellation signal with the same amplitude and opposite phase as the interference current, which is injected at the injection point to suppress the interference current. However, when the cancellation signal reaches the injection point, it needs to pass through the entire secondary channel, which is composed of the internal digital-to-analog conversion of the FPGA, the dead zone of the switch tube, the frequency response characteristics of the filter circuit, etc. The secondary channel causes phase deviation, and the LMS algorithm has poor phase compensation. Therefore, there is a phase mismatch between the cancellation signal and the interference signal at the injection point, that is, the interference current cannot be effectively suppressed.

[0043] Based on the above shortcomings, the present invention designs a phase compensation method for the secondary channel of an adaptive narrowband active filter based on delay, so as to realize the interference current suppression function of the adaptive narrowband active power filter at any frequency point between 1kHz and 20kHz. The method comprises the following steps:

[0044] Step 1: disconnect the interference source simulation device and the simulated grid load, and generate a sine wave with a known phase in the FPGA;

[0045] Step 2: Use the sine wave as the modulation wave signal of the switch tube, that is, amplify the power of the signal and inject it into the load resistor through the injection point;

[0046] Step 3: Use an interference current sensor to collect the interference current signal on the load side;

[0047] Step 4: filter and amplify the collected interference current signal through the preamplifier, and then send it to the FPGA;

[0048] Step 5: Open the logic analyzer in the FPGA, compare the generated sine wave signal with the signal obtained by preamplification, and obtain the phase deviation at the frequency point;

[0049] Step six, delay the error signal by using a register fixed delay method to compensate for the phase deviation between the cancellation signal and the interference signal.

[0050] In another specific embodiment of the present invention, the following steps are included:

[0051] Step 1, combining the output interference characteristics of the target DC power grid, the simulated grid internal resistance and load resistance are both set to 100mΩ;

[0052] Step 2: Disconnect the interference source simulation device and the simulated power grid load, and generate a DDS signal in the FPGA through the IP core, as shown in the attached figure. Figure 2 As shown in the figure, the one-to-one correspondence between phase and amplitude when FPGA generates IP core is like the relationship between address and storage content in memory. If the amplitude value corresponding to each phase in a cycle is stored in the memory, then for a sinusoidal signal of any frequency, at any time, as long as the phase is known, the address is also known, and the amplitude can be obtained by looking up the table, that is, a sinusoidal wave signal_out with a known phase is generated;

[0053] Step 3, using the above sine wave as the modulation wave signal of the switch tube, that is, amplifying the power of the above signal, and injecting it into the load resistor through the injection point to form an interference current interference_current;

[0054] Step 4, use the interference current sensor to collect the interference current signal on the load side, filter and amplify the interference current signal collected by the preamplifier circuit to eliminate high-frequency clutter interference, and then send it to the FPGA to form signal_error;

[0055] Step 5, open the logic analyzer in the FPGA, compare the generated sinusoidal signal signal_out with the signal signal_error obtained by preamplifying the interference current signal collected by the interference current sensor on the load side, and obtain the phase deviation φ caused by the secondary channel within the frequency point. Since both signal_error and signal_out are periodic signals, signal_error can be regarded as leading the phase of signal_out by 180°-φ;

[0056] Step 6, delay signal_error through the form of a register. Since the clock cycle is 400K, signal_error can be delayed by 12.5us by swapping it into the next register. According to the value of the leading phase of signal_error, a certain degree of delay is performed accordingly, so that the phase of signal_error leads or lags signal_out by about 180°. The LMS algorithm can only compensate for a certain degree of phase offset.

[0057] Step 7, connecting the interference source simulation device, after the interference current detection sensor C1 detects the frequency point, the signal_error detected by the interference current detection sensor C2 is delayed and compensated according to the locked phase deviation.

[0058] Step 8: Set the harmonic signal source from 1kHz to 20kHz frequency by frequency. The harmonic source is output at a single frequency. Figure 3 , Attachment Figure 4 As shown in the figure, the signal source generates a 1kHz frequency sine wave interference signal. Before the harmonic suppression device is activated, the interference signal amplitude in the circuit monitored by the spectrum analyzer is 101.3dBuV. After the harmonic suppression device is activated, the 1kHz harmonic interference component amplitude in the circuit is reduced to 58.5dBuV, and the harmonic interference amplitude is reduced by 42.9dB.

[0059] As attached Figure 5 , Attachment Figure 6 As shown in the figure, the signal source generates a 10kHz frequency sine wave interference signal. Before the harmonic suppression device is activated, the interference signal amplitude in the circuit monitored by the spectrum analyzer is 114.5dBuV. After the harmonic suppression device is activated, the 10kHz harmonic interference component amplitude in the circuit is reduced to 88.3dBuV, and the harmonic interference amplitude is reduced by 26.2dB.

[0060] As attached Figure 7 , Attachment Figure 8 As shown, the signal source generates a 20kHz frequency sine wave interference signal. Before the harmonic suppression device is started, the interference signal amplitude in the circuit monitored by the spectrum analyzer is 114.1dBuV. After the harmonic suppression device is started, the 20kHz harmonic interference component amplitude in the circuit is reduced to 88.4dBuV, and the harmonic interference amplitude is reduced by 25.7dB.

[0061] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A phase compensation method for a secondary channel of an adaptive narrowband active filter based on delay, characterized in that: The method comprises the following steps: Step 1, combining the output interference characteristics of the target DC power grid, setting the simulated power grid internal resistance and load resistance; Step 2, disconnect the interference source simulation device and the simulated grid load, and generate a sine wave with a known phase in the FPGA; Step 3, using the above sine wave as the modulation wave signal of the power amplifier, that is, amplifying the power of the sine wave signal, and injecting it into the load resistor through the injection point to form an interference current interference_current; Step 4, using the interference current sensor C1 and the interference current sensor C2 to collect the interference current signal on the load side; filtering and amplifying the collected interference current signal through the preamplifier to eliminate high-frequency clutter interference, and then sending it to the FPGA to form signal_error; Step 5, open the logic analyzer in the FPGA, compare the generated sine wave signal with the signal obtained by preamplification, and obtain the phase deviation; Step 6, delaying the error signal by a register fixed delay method to compensate for the phase difference between the offset signal and the interference signal; Step 7, connect the interference source simulation device, after the interference current detection sensor C1 detects the frequency point, then delay compensate the signal_error detected by the interference current detection sensor C2 according to the locked phase deviation; Step 8, set the harmonic signal source frequency-by-frequency from 1kHz to 20kHz. The harmonic source is a single-frequency output. The signal source generates a sinusoidal interference signal of a certain frequency. Before the harmonic suppression device is started, the spectrum analyzer monitors the interference signal amplitude in the circuit; after the harmonic suppression device is started, the amplitude of the harmonic interference component in the circuit is reduced, and the harmonic interference amplitude is also reduced.

2. The phase compensation method for the secondary channel of the adaptive narrowband active filter based on delay according to claim 1 is characterized in that: The method in step 2 includes: The DDS signal is generated by the IP core in the FPGA. When the FPGA generates the IP core, the one-to-one correspondence between the phase and the amplitude is that for a sinusoidal signal of any frequency, at any time, as long as the phase is known, the amplitude can be obtained, that is, a sinusoidal wave signal_out with a known phase is generated.

3. The phase compensation method for the secondary channel of the adaptive narrowband active filter based on delay according to claim 2 is characterized in that: The method in step 5 includes: Open the logic analyzer in the FPGA, compare the generated sinusoidal signal signal_out with the signal signal_error obtained by preamplifying the interference current signal collected by the interference current sensor on the load side, and obtain the phase deviation φ caused by the secondary channel within the frequency point. Since both signal_error and signal_out are periodic signals, signal_error is regarded as leading the phase of signal_out by 180°-φ.

4. The phase compensation method for the secondary channel of the adaptive narrowband active filter based on delay according to claim 3 is characterized in that: The method in step 6 includes: Signal_error is delayed in the form of a register. Since the clock cycle is 400K, signal_error can be delayed by 12.5us by swapping it into the next register. A certain degree of delay is performed according to the value of the leading phase of signal_error, so that the phase of signal_error is 180° ahead or behind that of signal_out.

5. The phase compensation method for the secondary channel of the adaptive narrowband active filter based on delay according to claim 1 is characterized in that: The phase compensation of the method is realized by an adaptive narrowband active filter based on delay, including an interference source simulation device connected in series to form a loop, a simulated power grid internal resistance R1, an interference current sensor C1, an injection point 1, an interference current sensor C2, a load resistor R2, a spectrum analyzer, and an injection point 2; the interference current sensor C1 and the interference current sensor C2 are also connected to a preamplifier, and the preamplifier, the injection point 1, and the injection point 2 are all connected to the host of the harmonic suppression device; wherein: The interference source simulation device includes a signal source and a power amplifier connected to each other, and generates interference signals of different frequencies and amplitudes by adjusting the frequency and amplitude of the signal source; Interference current sensor C1 is used to detect the frequency of interference signals; Interference current sensor C2, used to detect the amplitude and phase of the interference signal; The preamplifier is used to filter the frequency, amplitude and phase of the interference current collected by the interference current sensor C1 and the interference current sensor C2 and then send them to the main unit of the harmonic suppression device; The main unit of the harmonic suppression device is used to generate a cancellation signal with the same amplitude and opposite phase as the interference current, and inject it at injection point 1 and injection point 2 to suppress the interference current.

6. The phase compensation method for the secondary channel of the adaptive narrowband active filter based on delay according to claim 5 is characterized in that: The main unit of the harmonic suppression device is equipped with an FPGA, which implements a delay-based phase compensation method for the secondary channel of the adaptive narrowband active filter, thereby realizing the interference current suppression function of the adaptive narrowband active power filter for any frequency point within the range of 1kHz to 20kHz.

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