A dual differential comparator circuit
By designing a dual differential comparator circuit, the problem of the inability to process fully differential signals in the existing technology is solved, and direct comparison of differential signals is realized. The circuit structure is simple and the cost is low.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-21
- Publication Date
- 2026-03-27
AI Technical Summary
Existing single-ended two-stage comparators cannot handle non-grounded fully differential signals and cannot perform direct comparisons of differential signals.
Design a dual differential comparator circuit, which includes two pairs of signal input terminals and one signal output terminal. The circuit structure composed of NMOS and PMOS transistors enables direct comparison of differential signals.
It enables direct comparison of fully differential signals, with a simple circuit structure and low cost.
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Figure CN114938220B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of integrated circuit, and particularly relates to a double differential comparator circuit. BACKGROUND
[0002] The single-ended two-stage comparator in the prior art is shown in Figure 1 The comparator compares the voltage VIN of the comparison input end VINN to ground with the voltage VREF of the input end VINP to ground. When VIN is greater than VREF, the comparator output end DO outputs low level. When VIN is less than VREF, the comparator output end DO outputs high level. The disadvantage of the comparator is that it can only compare two single-ended voltages to ground, and the VINN and VINP voltages must be voltages to ground GND. That is, it cannot process full differential signals not to ground. SUMMARY
[0003] The technical problem to be solved by the present application is to overcome the shortcomings of the prior art and provide a double differential comparator circuit that can directly compare and process full differential signals.
[0004] The technical scheme adopted by the present application to solve the technical problem is a double differential comparator circuit, characterized in that it comprises two pairs of signal input ends: VINP+, VINP- and VINN+, VINN-, and a signal output end: DO.
[0005] The signal input end VINP+ is connected to the gate of NMOS tube MN1A, the drain of MN1A is connected to the power supply VDD, the source is connected to one end of resistor R1A, and the other end of R1A is connected to the source of PMOS tube MP1A; the signal input end VINP- is connected to the gate of the PMOS tube MP1A, the drain of MP1A is connected to the gate, drain of NMOS tube MN2A and the gate of MN2B; the sources of MN2A and MN2B are connected to ground GND.
[0006] The signal end VINN+ is connected to the gate of NMOS tube MN1B, the drain of MN1B is connected to the gate, drain of PMOS tube MP2A and the gate of PMOS tube MP2B; the sources of MP2A and MP2B are connected to the power supply VDD; the source of MN1B is connected to one end of resistor R1B, and the other end of R1B is connected to the source of PMOS tube MP1B; the signal end VINN- is connected to the gate of the PMOS tube MP1B, the drain VO of the PMOS tube MP1B is connected to the drain of NMOS tube MN2B and the gate of NMOS tube MN3; the source of MN3 is connected to ground GND, and the drain is connected to the output end DO and the drain of PMOS tube MP2B.
[0007] Compared with the prior art, the present application has the advantages that the present application overcomes the shortcomings of the prior art that the single-ended comparator cannot compare and process the differential signal, and successfully realizes the direct comparison output of the differential large signal; the circuit structure is simple, and the cost is low. BRIEF DESCRIPTION OF DRAWINGS
[0008] Figure 1 is a circuit composition diagram of the single-ended two-stage comparator of the prior art;
[0009] Figure 2 is a circuit diagram of the double differential comparator of the first embodiment of the present application. DETAILED DESCRIPTION
[0010] The present application will be further described below in combination with the embodiments of the drawings:
[0011] Embodiment one
[0012] As shown in the drawings, a double differential comparator circuit includes two pairs of signal input terminals: VINP+, VINP- and VINN+, VINN-, and a signal output terminal: DO. Figure 2 The signal input terminal VINP+ is connected to the gate of NMOS tube MN1A, the drain of MN1A is connected to the power supply VDD, the source is connected to one end of resistor R1A, and the other end of R1A is connected to the source of PMOS tube MP1A; the signal input terminal VINP- is connected to the gate of the PMOS tube MP1A, the drain of MP1A is connected to the gate, drain of NMOS tube MN2A and the gate of MN2B; the sources of the NMOS tubes MN2A and MN2B are connected to the ground GND.
[0013] The signal terminal VINN+ is connected to the gate of NMOS tube MN1B, the drain of MN1B is connected to the gate, drain of PMOS tube MP2A and the gate of PMOS tube MP2B; the sources of the PMOS tubes MP2A and MP2B are connected to the power supply VDD; the source of the NMOS tube MN1B is connected to one end of resistor R1B, and the other end of R1B is connected to the source of PMOS tube MP1B; the signal terminal VINN- is connected to the gate of the PMOS tube MP1B, and the drain VO of the PMOS tube MP1B is connected to the drain of the NMOS tube MN2B and the gate of NMOS tube MN3; the source of the MN3 is connected to the ground GND, and the drain is connected to the output terminal DO and the drain of the PMOS tube MP2B.
[0014] The signal input terminals VINP+, VINP- and VINN+, VINN- are respectively the differential signal input terminals and reference voltage input terminals to be compared.
[0015]
[0016] When the signal input ends VINP+ and VINP- are used as the input ends of the signal VIN, and the signal input ends VINN+ and VINN- are used as the input ends of the reference voltage VREF, the differential signal VIN to be compared will generate a current IR1A on the resistor R1A during operation of the application:
[0017]
[0018] Similarly, the reference voltage VREF will generate a current IR1B on the resistor R1B:
[0019]
[0020] The current IR1B mirrors the input current I2 as a bias current of the output amplification stage through the PMOS transistors MP2A and MP2B;
[0021] The current IR1A mirrors the output current I1 through the NMOS transistors MN2A and MN2B, and if the channel sizes of the NMOS transistors MN2A and MN2B are the same,
[0022] I1 = IR1A … … (3)
[0023] The current I1 and the current IR1B are compared at the VO node: when I1 is greater than IR1B, the VO node voltage is pulled low, and the VO voltage is further inversely amplified through the output stage composed of the NMOS transistor MN3 and the PMOS transistor MP2B and output to the output end DO; when the gain of the comparator is large enough, the DO output is approximately the VDD level; otherwise, when I1 is less than IR1B, the DO output is approximately the GND level.
[0024] Therefore, we have:
[0025] When IR1A > IR1B, the DO output is close to the high level of VDD;
[0026] When IR1A < IR1B, the DO output is close to the low level of GND;
[0027] That is, when the DO output is close to the high level of VDD;
[0028] When the DO output is close to the low level of GND;
[0029] wherein VGS MN1A is the gate-source voltage of the NMOS transistor MN1A, VGS MP1A is the gate-source voltage of the PMOS transistor MP1A, and VGS MN1BVGS is the gate-source voltage of the NMOS transistor MN1B MP1B VGS is the gate-source voltage of the PMOS transistor MP1B
[0030] The NMOS transistors MN1A and MN1B have the same channel size; the PMOS transistors MP1A and MP1B have the same channel size; the resistors R1A = R1B
[0031] When the input differential voltage VIN is equal to the reference voltage VREF, IR1A = IR1B
[0032] When the input differential voltage VIN is greater than the reference voltage VREF, IR1A > IR1B
[0033] When the input differential voltage VIN is less than the reference voltage VREF, IR1A < IR1B
[0034] Thus, when the differential signal VIN input at the (VINP+, VINP-) port of the dual differential comparator is greater than the differential voltage VREF at the (VINN+, VINN-) port, the comparator output approaches the high level of VDD
[0035] When the differential signal VIN input at the signal input end VINP+, VINP- port of the dual differential comparator is less than the differential voltage VREF at the signal input end VINN+, VINN- port, the comparator output approaches the low level of GND
[0036] The working condition of the dual differential comparator is that the differential input signal voltage is greater than the difference between the gate-source voltages of the two input transistors, i.e.
[0037] VIN > VGS MN1A -VGS MP1A
[0038] VREF > VGS MN1B -VGS MP1B .
[0039] The above description is only the preferred embodiment of the present application, and is not intended to limit the present application in other forms. Any skilled person in the art can modify or change the above-mentioned technical content to equivalent embodiments. However, any simple modification, equivalent change and modification of the above-mentioned embodiments without departing from the technical solution of the present application, and according to the technical essence of the present application, still belongs to the protection scope of the present application.
Claims
1. A dual differential comparator circuit, characterized by: The signal input end VINP+ is connected with the gate of NMOS MN1A, the drain of MN1A is connected with the power supply VDD, the source is connected with one end of resistor R1A, the other end of R1A is connected with the source of PMOS MP1A; the signal input end VINP- is connected with the gate of PMOS MP1A, the drain of MP1A is connected with the gate, the drain of NMOS MN2A and the gate of MN2B; the sources of MN2A and MN2B are connected with the ground GND; The signal end VINN+ is connected with the gate of NMOS MN1B, the drain of MN1B is connected with the gate, the drain of PMOS MP2A and the gate of PMOS MP2B; the sources of MP2A and MP2B are connected with the power supply VDD; the source of MN1B is connected with one end of resistor R1B, the other end of R1B is connected with the source of PMOS MP1B; the signal end VINN- is connected with the gate of PMOS MP1B, the drain of MP1B VO is connected with the drain of NMOS MN2B and the gate of NMOS MN3; the source of MN3 is connected with the ground GND, the drain is connected with the output end DO and the drain of PMOS MP2B.
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