Display Panel

Abstract

Display panel. A display panel includes: a pixel connected to a gate line; and a gate driver that supplies a gate signal to at least one of the gate lines and includes a plurality of stages. Each stage includes: a pull-up transistor that applies a turn-on voltage of a first clock signal to an output terminal in response to a voltage at a Q node; a pull-down transistor that applies a turn-off voltage to the output terminal in response to a voltage at a QB node, the QB node maintaining the turn-on voltage during a period in which the output terminal is applied with the turn-off voltage; and a QB node control unit that applies the turn-on voltage to the QB node in response to a first clock signal and a second clock signal that is inverted from the first clock signal. Therefore, the display panel may include a gate driver capable of setting, resetting, and maintaining the voltage at the QB node.

Description

[0001] This application is a divisional application of the original invention patent application with application number 201810662028.X (application date: June 25, 2018, invention name: gate driver and display panel with the gate driver). Technical Field

[0002] The present disclosure relates to a gate driver and a display panel including the same, and more particularly, to a gate driver that can be directly formed in a display panel, thereby reducing a bezel of the display panel, and a display panel including the gate driver. Background Art

[0003] Currently, various display devices are being developed and released. For example, display devices include liquid crystal display devices (LCD), field emission display devices (FED), electrophoretic display devices (EPD), electrowetting display devices (EWD), organic light emitting display devices (OLED), and quantum dot display devices (QD).

[0004] The display device includes a display panel including a plurality of sub-pixels, a driver unit for driving the display panel, a power supply unit for supplying power to the display panel, etc. The driver unit includes a scan driver for supplying a scan signal (or a gate signal) to the display panel and a data driver for supplying a data signal to the display panel.

[0005] The display device may display an image by causing selected sub-pixels to emit light by supplying a scan signal, a data signal, etc. Therefore, a technology for improving the accuracy of a driver unit included in a display panel to accurately transmit signals to sub-pixels is being developed. Summary of the invention

[0006] One or more scan signals are used to drive a display panel. A display panel includes: an effective display area (active area), in which a pixel array as a sub-pixel set is set to display an image; and an invalid display area (non-active area), in which an image is not displayed. One or more scan signals are used to drive the sub-pixels. A gate driver for supplying a scan signal can be embedded in the display panel in the form of a thin film transistor together with the pixel array. Such a gate driver embedded in the display panel is called a GIP (gating in panel) circuit. The GIP circuit can be implemented as a shift register. The shift register includes a plurality of stages, and the plurality of stages generate an output when a start signal is received. The output can be shifted according to a clock signal. The gate driver includes stages each having a plurality of thin film transistors (or transistors). These stages are cascaded to generate outputs in sequence. The number of stages of the gate driver can be equal to the number of gate lines. Each of these stages can output a gate signal to a corresponding gate line.

[0007] Each of these stages includes a Q node for controlling a pull-up transistor and a QB node for controlling a pull-down transistor. Each of these stages may include a transistor that charges the Q node and discharges the QB node or discharges the Q node and charges the QB node in response to a start signal and a clock signal. The start signal may be an output signal from a previous stage.

[0008] When the QB node is charged, the Q node is discharged, and vice versa. For example, when a high level voltage is applied to the Q node, a low level voltage is applied to the QB node. When a low level voltage is applied to the Q node, a high level voltage is applied to the QB node. When the pull-up transistor and the pull-down transistor are turned on / off, a gate on / off signal can be provided to the pixel array. Since the on time of the pull-down transistor is longer than the off time, the on voltage must be stably applied to the QB node. For example, when the transistor of the gate driver is a p-type transistor, the on voltage is a gate low voltage and the off voltage is a gate high voltage. When the transistor included in the sub-pixel controlled by the gate signal is an n-type transistor, the gate-on signal is a gate high voltage. When the transistor included in the sub-pixel controlled by the gate signal is a p-type transistor, the gate-on signal is a gate low voltage. The types of transistors of the gate driver and the sub-pixel are not limited thereto.

[0009] Gate drivers can be implemented in various forms, and research is ongoing to develop optimal circuit configurations to improve reliability of operation.

[0010] In view of the above, the inventors of the present application have recognized the above problems and designed a gate driver with improved output signal accuracy and a display panel including the gate driver.

[0011] Accordingly, embodiments of the present disclosure are directed to a gate driver and a display panel having the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0012] An object of the present disclosure is to provide a gate driver including a QB node control unit for accurately providing a voltage to a QB node.

[0013] Another object of the present disclosure is to provide a display panel having a reduced bezel by forming a gate driver having improved output signal accuracy on the display panel.

[0014] Additional features and advantages will be described in the following description, and in part will become apparent from the description, or may be learned through the practice of the inventive concept provided herein. Other features and aspects of the inventive concept may be realized and obtained through the structures specifically pointed out in the written description, the contents derivable therefrom, and the claims and drawings.

[0015] To achieve these and other aspects of the inventive concept, as embodied and broadly described herein, a display panel includes: pixels connected to gate lines; and a gate driver that supplies a gate signal to at least one of the gate lines and includes a plurality of stages. Each stage includes: a pull-up transistor that applies a turn-on voltage of a first clock signal to an output terminal in response to a voltage at a Q node; a pull-down transistor that applies a turn-off voltage to the output terminal in response to a voltage at a QB node, the QB node maintaining the turn-on voltage during a period in which the output terminal is applied with the turn-off voltage; and a QB node control unit that applies the turn-on voltage to the QB node in response to a first clock signal and a second clock signal that is inverted from the first clock signal. Thus, the display panel may include a gate driver capable of setting, resetting, and maintaining a voltage at the QB node.

[0016] On the other hand, a gate driver includes: a QB node control unit, the QB node control unit controls a QB node, the QB node being a gate node of a pull-down transistor. The QB node control unit includes: a first transistor and a second transistor, each of the first transistor and the second transistor having an electrode connected to a QP node for controlling the QP node; a third transistor, the third transistor applying a gate high voltage to the QB node; and a fourth transistor having a gate connected to the QP node for applying a gate low voltage to the QB node. A gate driver with improved output signal accuracy can be implemented by a QB node control unit capable of controlling the QB node.

[0017] The details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

[0018] According to an embodiment of the present disclosure, the QB node control unit applies the on-voltage of the clock signal to the QP node by coupling using a capacitor so that a gate low voltage is applied to the QB node to turn on the pull-down transistor and output a gate-off voltage.

[0019] According to an embodiment of the present disclosure, the QB node control unit applies a gate high voltage to the QB node due to a start signal or a voltage at the Q1 node, so that the pull-down transistor is turned off and the pull-up transistor is turned on by the Q node control unit to output a gate-on voltage.

[0020] According to an embodiment of the present disclosure, the QB node control unit further includes a first capacitor between the input terminal of the input clock signal and the QP node, so that the QP node is coupled with the clock signal to periodically apply the gate low voltage to the QP node. Therefore, during the holding period, the gate low voltage can be periodically applied to the QP node.

[0021] According to an embodiment of the present disclosure, the QB node control unit also includes a third capacitor connected between the QB node and an input terminal of an input selection high voltage, so that the voltage charged between the first electrode and the second electrode of the third capacitor during the setting period can be maintained during the holding period.

[0022] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and together with the description are used to explain various principles. In the drawings:

[0024] Figure 1 is a diagram of a display device according to one embodiment of the present disclosure;

[0025] Figure 2 is a block diagram showing an example of a cascaded stage of gate drivers;

[0026] Figure 3 is a block diagram of a gate driver according to one embodiment of the present disclosure;

[0027] Figure 4A is a circuit diagram of a portion of a gate driver for applying a voltage to a QB node according to an embodiment of the present disclosure;

[0028] Figure 4B Is input to Figure 4A The circuit signal and the Figure 4A The waveform diagram of the signal output by the circuit;

[0029] Figure 5A This is an example of using the first embodiment according to the present disclosure Figure 4A A circuit diagram of a gate driver of the circuit shown in;

[0030] Figure 5B Is input to Figure 5A The circuit signal and the Figure 5A The waveform diagram of the signal output by the circuit;

[0031] Fig. 6A This is an example of using the second embodiment according to the present disclosure Figure 4A A circuit diagram of a gate driver of the circuit shown in;

[0032] Figure 6B Is input to Fig. 6A The circuit signal and the Fig. 6A The waveform diagram of the signal output by the circuit;

[0033] Fig. 7A This is an example of adopting the third embodiment according to the present disclosure. Figure 4A A circuit diagram of a gate driver of the circuit shown in FIG.

[0034] Figure 7B Is input to Fig. 7A The circuit signal and the Fig. 7A The waveform diagram of the signal output by the circuit. DETAILED DESCRIPTION

[0035] The advantages and features of the present disclosure and their implementation methods will become apparent from the following description of the embodiments with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed herein, but can be implemented in various different ways. These embodiments are provided so that the disclosure of the present disclosure is thorough and the scope of the present disclosure is fully conveyed to those skilled in the art. It should be noted that the scope of the present disclosure is limited only by the claims.

[0036] The figures, sizes, ratios, angles, and numbers of the elements given in the accompanying drawings are merely illustrative and non-restrictive. Throughout the specification, the same reference numerals represent the same elements. In addition, when describing the present disclosure, the description of the known technology may be omitted to avoid unnecessary confusion of the subject matter of the present disclosure. It should be noted that, unless otherwise specifically stated, the terms "including", "having", "comprising" used in the specification and claims should not be interpreted as being limited to the meanings listed thereafter. When using an indefinite or definite article such as "one", "an", "the" when referring to a singular noun, the singular noun includes the plural form of the noun unless otherwise specifically stated.

[0037] In describing these elements, they are construed as including an error margin even if not explicitly stated.

[0038] When describing positional relationships such as “element A is on element B”, “element A is above element B”, “element A is below element B” and “element A is next to element B”, another element C may be set between element A and element B unless the terms “directly” or “immediately” are explicitly used.

[0039] When describing temporal relationships, unless otherwise specified, terms such as “after,” “subsequently,” “next,” and “before,” are not limited to “immediately after,” “immediately followed,” “immediately down,” and “immediately before,” etc.

[0040] The terms first, second, third, etc. in the specification and claims are used to distinguish similar elements, and are not necessarily used to describe order or time sequence. These terms are only used to distinguish one element from another element. Therefore, as used herein, within the technical thinking of the present disclosure, the first element may be the second element. Because the claims list basic elements, the ordinal numbers used in the specific implementation may match the ordinal numbers of the elements used in the claims or may not match the ordinal numbers of the elements. For example, the "second capacitor" set forth in the claims may correspond to the "third capacitor C3" in the specific implementation, and the "third capacitor" set forth in the claims may correspond to the "second capacitor C2" in the specific implementation.

[0041] The features of various embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically possible. Various embodiments may be practiced individually or in combination.

[0042] Herein, the pixel circuit and the gate driver formed on the substrate of the display panel may be implemented as an n-type or p-type transistor. For example, the transistor may be implemented as a metal oxide semiconductor field effect transistor (MOSFET). A transistor is a three-electrode device including a gate, a source and a drain. The source is an electrode for supplying carriers to the transistor. In a transistor, carriers begin to flow from the source. The carriers leave the transistor via the drain. For example, carriers flow from the source to the drain in a transistor. For an n-type transistor, the carriers are electrons, so the level of the source voltage is lower than the level of the drain voltage, so that the electrons flow from the source to the drain. In an n-type transistor, since the electrons flow from the source to the drain, the current flows from the drain to the source. For a p-type transistor, the carriers are holes, so the level of the source voltage is higher than the level of the drain voltage, so that the holes flow from the source to the drain. In a p-type transistor, since the holes flow from the source to the drain, the current flows from the source to the drain. The source and drain of a transistor are not fixed but interchangeable depending on the voltage applied.

[0043] In the following description, the gate-on voltage may refer to the voltage of the gating signal used to turn on the transistor. The gate-off voltage may refer to the voltage used to turn off the transistor. In a p-type transistor, the gate-on voltage may be a gating low voltage (VL), and the gate-off voltage may be a gating high voltage (VH). In an n-type transistor, the gate-on voltage may be a gating high voltage (VH), and the gate-off voltage may be a gating low voltage (VL).

[0044] Hereinafter, a gate driver and a display panel including the same according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0045] Figure 1 is a diagram of a display device according to an embodiment of the present disclosure.

[0046] Reference Figure 1 , the display device 100 includes a display panel 110 , a gate driver 120 , a data driver 130 , and a timing controller 140 .

[0047] The display panel 110 includes sub-pixels P connected to the gate lines 20 and the data lines 30. The display panel 110 is sealed to protect at least one film or substrate and sub-pixels formed on the film or substrate from moisture or external air such as oxygen.

[0048] The display panel 110 includes a display area DA in which the sub-pixels P are formed and a non-display area NDA in which various signal lines, pads, etc. are formed, and the non-display area NDA is formed around the display area DA. Since the display area DA is used to display an image, the sub-pixels are arranged therein. Since the non-display area NDA does not display an image, a dummy sub-pixel is arranged therein or no sub-pixel is arranged therein.

[0049] The display area DA includes a plurality of sub-pixels P, and displays an image based on a grayscale represented by each of the sub-pixels P. The sub-pixels P are arranged along a first pixel row HL1 to an n-th pixel row HL(n). Each of the sub-pixels P is connected to a data line arranged along a column line and to a gate line arranged along the pixel row HL. Sub-pixels arranged in the same pixel row share the same gate line and are driven simultaneously. Herein, a sub-pixel P arranged in the first pixel row HL1 is defined as a first sub-pixel, and a sub-pixel P arranged in an n-th pixel row HL(n) is defined as an n-th sub-pixel. The first sub-pixel to the n-th sub-pixel are driven sequentially.

[0050] The sub-pixels P of the display panel 110 are arranged in a matrix to form a pixel array. However, it is to be understood that the present disclosure is not limited thereto. The sub-pixels P may be arranged in various ways such as to share pixels, or may be arranged in a stripe shape, a diamond shape, etc. other than a matrix shape.

[0051] The gate driver 120 is connected to the gate line 20 to supply a gate signal. For example, the gate driver 120 receives a gate control signal GDC including a clock signal and a start signal from a level shifter. The gate driver 120 generates a gate signal according to the clock signal and the start signal, and supplies the gate signal to the gate line 20.

[0052] The level shifter shifts the voltage levels of the clock signal and the start signal input from the timing controller 140 to the level of the gate-on voltage and the level of the gate-off voltage that can switch the transistor provided in the sub-pixel P. The level shifter supplies the level-shifted clock signal to the gate driver 120 through the clock signal line, and supplies the level-shifted start signal to the gate driver 120 through the start signal line. Although the level shifter is described as an element separate from the gate driver 120, it can also be integrated with the gate driver 120.

[0053] The data driver 130 is connected to the data line 30. The data driver 130 receives the digital image data DATA and the data control signal DDC from the timing controller 140. The data driver 130 converts the digital image data DATA into an analog data voltage according to the data control signal DDC. The data driver 130 supplies the analog data voltage to the data line 30.

[0054] The timing controller 140 receives digital image data and timing signals from an external system board. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal.

[0055] Based on the timing signal, the timing controller 140 generates a gate control signal GDC for controlling the operation timing of the gate driver 120 and a data control signal DDC for controlling the operation timing of the data driver 130 .

[0056] The gating control signal GDC may include but is not limited to a gating start signal, a gating clock signal, etc. The gating start signal is applied to the stage generating the first output to start the operation of the stage. The gating clock signal is a clock signal commonly input to each stage for shifting the gating start signal.

[0057] The data driver 130, the level shifter, and the timing controller 140 may be formed as a single driver integrated circuit (IC). In addition, the single driver IC may be disposed on the display panel 110. However, it is to be understood that the present disclosure is not limited thereto. Each of the data driver 130, the level shifter, and the timing controller 140 may be formed as a single driver IC.

[0058] Figure 2 is a block diagram illustrating an example of cascaded stages of gate drivers.

[0059] The gate driver may provide one or more scan signals (or gate signals) to the pixel circuit. A gate driver for generating one of the scan signals input to the pixel circuit will be described.

[0060] The gate driver includes a first stage SD1 to an nth stage SD(n) connected in cascade. The first stage SD1 generates a first scan signal SCAN1 and applies the first scan signal SCAN1 to a scan line of a first pixel row HL1. The second stage SD2 generates a second scan signal SCAN2 and applies the second scan signal SCAN2 to a scan line of a second pixel row HL2. The nth stage SD(n) generates an nth scan signal SCAN(n) and applies the nth scan signal SCAN(n) to a scan line of an nth pixel row HL(n).

[0061] The first stage SD1 operates by receiving the start signal VST. Each of the second stage SD2 to the n-th stage SD(n) operates by receiving an output signal from a previous stage.

[0062] In this case, the first to nth scan signals may be referred to as first to nth gate signals, respectively, and the scan lines may be referred to as gate lines.

[0063] Hereinafter, a circuit of each of the multiple stages will be described. In the following description, each of the multiple stages includes a plurality of transistors, and each of the plurality of transistors is a p-type transistor.

[0064] Figure 3 is a block diagram of a gate driver according to an embodiment of the present disclosure. Specifically, Figure 3 It is shown that the formation Figure 2 2 is a block diagram of a circuit of each of the first stage SD1 to the nth stage SD(n) shown in FIG.

[0065] Each of the multiple stages includes a pull-up portion 111 , a pull-down portion 112 , a Q node control unit 113 , and a QB node control unit 114 .

[0066] The pull-up part 111 outputs a turn-on voltage as an output signal Out by a voltage applied to the Q node Q. In this case, the turn-on voltage is a gate low voltage of the first clock signal CLK1.

[0067] The pull-down part 112 outputs a cut-off voltage as an output signal Out by a voltage applied to the QB node QB. In this case, the cut-off voltage is a gate high voltage VH.

[0068] When the output signal Out is an on voltage, the Q node control unit 113 applies a gate low voltage VL of the start signal VST to the Q node Q through the start signal VST. Also, when the output signal Out is an off voltage, a gate high voltage VH is applied to the Q node Q through the QB node QB.

[0069] When the output signal Out is the cut-off voltage, the QB node control unit 114 applies the gate low voltage VL of the second clock signal CLK2 to the QB node QB through the second clock signal CLK2. In this case, a capacitor can be used to apply the complete gate low voltage VL to the QB node QB. When the output signal Out is the on voltage, the QB node control unit 114 applies the gate high voltage VH to the QB node QB through the first clock signal CLK1 and the second clock signal CLK2 or the start signal VST.

[0070] The first clock signal CLK1 and the second clock signal CLK2 are in opposite phases. For reliability of operation, the first clock signal CLK1 and the second clock signal CLK2 may have different widths of on-voltage level time and off-voltage level time so that the voltage levels are not inverted at the same time.

[0071] Figure 4A is a circuit diagram of a portion of a gate driver for applying a voltage to a QB node according to an embodiment of the present disclosure. Specifically, Figure 4A Show Figure 2A portion of the circuit of each of the first stage SD1 to the nth stage SD(n) shown in FIG. Figure 4B Is input to Figure 4A The circuit signal and the Figure 4A The waveform diagram of the signal output by the circuit.

[0072] Each stage includes a pull-up transistor, a pull-down transistor, a Q node for controlling the pull-up transistor, and a QB node for controlling the pull-down transistor. Figure 4A is a circuit diagram showing a QB node control unit for applying a voltage to the QB node QB.

[0073] The QB node control unit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a first capacitor C1. The QB node control unit may include a QP node control unit, the QP node control unit includes a first transistor T1 and a second transistor T2, each of which has a first electrode connected to the QP node QP.

[0074] The gate of the first transistor T1 is connected to an input terminal to which the start signal VST is input, a first electrode thereof is connected to the QP node QP, and a second electrode thereof is connected to an input terminal to which the gate high voltage VH is input.

[0075] The gate of the second transistor T2 is connected to the first clock signal CLK1, the first electrode thereof is connected to the QP node QP, and the second electrode thereof is connected to the input terminal to which the gate high voltage VH is input.

[0076] The gate electrode of the third transistor T3 is connected to the input terminal to which the start signal VST is input, the first electrode thereof is connected to the QB node QB, and the second electrode thereof is connected to the input terminal to which the gate high voltage VH is input.

[0077] The gate electrode of the fourth transistor T4 is connected to the QP node QP, the first electrode thereof is connected to the input terminal to which the second clock signal CLK2 is input, and the second electrode thereof is connected to the QB node QB.

[0078] The first capacitor C1 is connected between an input terminal to which the second clock signal CLK2 is input and the QP node QP.

[0079] In the first period P1, the gate high voltage VH is applied to the QB node QB. The second transistor T2 is turned off due to the first clock signal CLK1 at the gate high voltage VH. The first transistor T1 and the third transistor T3 are turned on due to the start signal VST at the gate low voltage VL. Therefore, the gate high voltage VGH is applied to the QP node QP through the first transistor T1, and the gate high voltage VH is applied to the QB node QB through the third transistor T3. Then, the fourth transistor T4 is turned off due to the voltage applied to the QP node QP. Therefore, the gate high voltage VH is applied to the QB node QB due to the gate low voltage VL of the start signal VST. In this case, the first period P1 can be referred to as the reset period of the QB node QB.

[0080] In the second period P2, the gate low voltage VH is applied to the QB node QB. The first transistor T1 and the third transistor T3 are turned off due to the start signal VST at the gate high voltage VH, and the second transistor T2 is turned off due to the first clock signal CLK1 at the gate high voltage VH. Therefore, the QP node QP floats. As the second clock signal CLK2 applied to the first electrode of the first capacitor C1 is reduced from the gate high voltage VH to the gate low voltage VL, the voltage at the QP node QP connected to the second electrode of the first capacitor C1 is reduced to the gate low voltage VL due to coupling. Therefore, the gate low voltage VL can be applied to the QB node QB, so that the pull-down transistor can be turned on, thereby providing the output signal Out to the gate line of the pixel row. In this case, the second period P2 can be referred to as the setting period of the QB node QB.

[0081] Figure 5A This is an example of using the first embodiment according to the present disclosure Figure 4A The circuit diagram of the gate driver of the circuit shown in FIG. Figure 5A Show Figure 2 The circuit of each of the first stage SD1 to the nth stage SD(n) shown in FIG. Figure 5B Is input to Figure 5A The circuit signal and the Figure 5A The waveform diagram of the signal output by the circuit.

[0082] Each of the multiple stages includes a pull-up portion, a pull-down portion, a Q-node control unit, and a QB-node control unit.

[0083] The pull-up portion outputs the on-voltage of the first clock signal CLK1 as an output signal Out via the Q node. The pull-up portion may include a pull-up transistor Tu and a second capacitor C2. The gate of the pull-up transistor Tu is connected to the Q node (or the Q2 node). Its first electrode is connected to an input terminal for inputting the first clock signal CLK1, and its second electrode is connected to an output terminal for outputting the output signal Out via it. The first electrode of the second capacitor C2 is connected to the Q node (or the Q2 node), and the second electrode is connected to an output terminal for outputting the output signal Out via it.

[0084] The pull-down part outputs the gate high voltage VH as an output signal Out via the QB node QB. The pull-down part includes a pull-down transistor Td.

[0085] In the first period P1, the Q node control unit applies the gate low voltage VL to the Q node (or Q1 node). The Q node control unit applies the gate voltage of the start signal VST to the Q node (or Q1 node) through the start signal VST in the first period P1. Then, in the second period P2, the Q node control unit applies the gate high voltage VH to the Q node (or Q1 node). The Q node control unit includes a fifth transistor T5 and a sixth transistor T6.

[0086] The Q node control unit may further include a Q1 node stabilizing unit. The Q1 node stabilizing unit includes a seventh transistor T7. The Q node is divided into a Q1 node Q1 and a Q2 node Q2 by the Q1 node stabilizing unit, and the seventh transistor T7 is connected between the Q1 node Q1 and the Q2 node Q2. The gate low voltage VL is applied to the gate of the seventh transistor T7. The Q1 node stabilizing unit can suppress the sudden change of the voltage at the Q1 node Q1 while the Q2 node Q2 is bootstrapped by the second capacitor C2, thereby avoiding the voltage difference between the drain and source of the fifth transistor T5 and the voltage difference between the drain and source of the sixth transistor T6 to increase instantaneously. The electrical stress applied to the fifth transistor T5 and the sixth transistor T6 can be reduced by the Q1 node stabilizing unit.

[0087] A gate and a first electrode of the fifth transistor T5 are connected to an input terminal to which the start signal VST is input, and a second electrode thereof is connected to the Q1 node Q1.

[0088] The gate electrode of the sixth transistor T6 is connected to the QB node QB, the first electrode thereof is connected to the Q1 node Q1, and the second electrode thereof is connected to the input terminal to which the gate high voltage VH is input.

[0089] In the first period P1, the gate low voltage VL is applied to the Q1 node Q1 and the Q2 node Q2. The fifth transistor T5 is turned on due to the start signal VST at the gate low voltage VL, so that the gate low voltage VL is applied to the Q1 node Q1 through the fifth transistor T5. Since the seventh transistor T7 is always turned on, the gate low voltage VL is applied to the Q2 node Q2. The pull-up transistor Tu is turned on due to the gate low voltage VL applied to the Q2 node Q2. In this case, since the first clock signal CLK1 is at the level of the gate high voltage VH, the output signal Out is a cut-off voltage.

[0090] In the (1-1)th period P(1-1) after the first period P1, the output signal Out is a conduction voltage. The Q1 node Q1 becomes floating in the gate low voltage VL state due to the start signal VST in the gate high voltage VH. Since the first clock signal CLK1 becomes the gate low voltage VL, the gate low voltage VL is applied to the output signal Out, and the voltage at the Q2 node Q2 becomes lower than the gate low voltage VL due to the bootstrap of the second capacitor C2. The pull-up transistor Tu can stably output the output signal Out due to the voltage at the Q2 node Q2 that has become lower than the gate low voltage VL.

[0091] In the second period P2, the gate high voltage VH is applied to the Q1 node Q1 and the Q2 node Q2. The sixth transistor T6 is turned on by the gate low voltage VL applied to the QB node QB, and the gate high voltage VH is applied to the Q1 node Q1 through the sixth transistor T6. Therefore, the pull-up transistor Tu is turned off.

[0092] Hereinafter, operations of the QB node control unit in the first period P1, the (1-1)th period P(1-1), and the second period P2 will be described in detail.

[0093] The QB node control unit applies the gate low voltage VL to the QB node QB by applying the turn-on voltage of the second clock signal CLK2 to the QP node QP using the coupling of the first capacitor C1. Then, the gate high voltage VH is applied to the QB node QB due to the start signal VST.

[0094] The QB node control unit includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , and a first capacitor C1 .

[0095] The gate of the first transistor T1 is connected to an input terminal to which the start signal VST is input, a first electrode thereof is connected to the QP node QP, and a second electrode thereof is connected to an input terminal to which the gate high voltage VH is input.

[0096] The gate of the second transistor T2 is connected to the first clock signal CLK1, the first electrode thereof is connected to the QP node QP, and the second electrode thereof is connected to the input terminal to which the gate high voltage VH is input.

[0097] The gate electrode of the third transistor T3 is connected to the input terminal to which the start signal VST is input, the first electrode thereof is connected to the QB node QB, and the second electrode thereof is connected to the input terminal to which the gate high voltage VH is input.

[0098] The gate electrode of the fourth transistor T4 is connected to the QP node QP, the first electrode thereof is connected to the input terminal to which the second clock signal CLK2 is input, and the second electrode thereof is connected to the QB node QB.

[0099] A first electrode of the first capacitor C1 is connected to an input terminal to which the second clock signal CLK2 is input, and a second electrode thereof is connected to the QP node QP.

[0100] In the first period P1, the gate high voltage VH is applied to the QB node QB. The second transistor T2 is turned off due to the first clock signal CLK1 at the gate high voltage VH. The first transistor T1 and the third transistor T3 are turned on due to the start signal VST at the gate low voltage VL. Therefore, the gate high voltage VGH is applied to the QP node QP through the first transistor T1, and the gate high voltage VH is applied to the QB node QB through the third transistor T3. Then, the fourth transistor T4 is turned off due to the voltage applied to the QP node QP. Therefore, the gate high voltage VH is applied to the QB node QB due to the gate low voltage VL of the start signal VST. In this case, the first period P1 can be referred to as the reset period of the QB node QB. The gate high voltage VH applied to the QB node QB is maintained even during the (1-1)th period P(1-1).

[0101] In the second period P2, the gate low voltage VH is applied to the QB node QB. The first transistor T1 and the third transistor T3 are turned off due to the start signal VST in the gate high voltage VH, and the second transistor T2 is turned off due to the first clock signal CLK1 in the gate high voltage VH. Therefore, the QP node QP floats. As the second clock signal CLK2 applied to the first electrode of the first capacitor C1 is reduced from the gate high voltage VH to the gate low voltage VL, the voltage at the QP node QP connected to the second electrode of the first capacitor C1 is reduced to the gate low voltage VL due to coupling. Therefore, the fourth transistor T4 is turned on due to the voltage at the QP node QP, so that the gate low voltage VL can be fully applied to the QB node QB. Because the gate low voltage VL can be fully applied to the QB node QB, the pull-down transistor Td is turned on, so that the output signal Out of the gate high voltage VH can be applied to the gate line of the pixel row. In this case, the second period P2 can be referred to as the setting period of the QB node QB.

[0102] The third period P3 is a period after the second period P2 until the next frame. The pull-down transistor Td remains turned on so that the output signal Out is maintained at the gate high voltage VH. In this case, the QB node control unit may further include a third capacitor C3. The first electrode of the third capacitor C3 is connected to the QB node QB, and the second electrode thereof is connected to the input terminal of the input gate high voltage VH. During the third period P3, the third capacitor C3 may maintain the voltage charged between the first electrode and the second electrode in the second period P2, so that the voltage at the QB node QB is maintained at the gate low voltage VL. The voltage at the QP node QP is coupled by the second clock signal CLK2 that periodically becomes the gate low voltage VL during the third period P3, thereby reducing it to the gate low voltage VL. Therefore, the fourth transistor T4 is turned on due to the gate low voltage VL, so that the gate low voltage VL is applied to the QB node QB. In this case, the third period P3 may be referred to as the holding period of the QB node QB.

[0103] Therefore, the QB node control unit further includes a third capacitor C3 connected between the QB node QB and an input terminal inputting the gate high voltage VH so that the voltage charged between the first electrode and the second electrode during the setup period can be maintained during the maintenance period.

[0104] In addition, since the QP node QP is coupled with the second clock signal CLK2 through the first capacitor C1, the gate low voltage VL is periodically applied to the QP node QP. Therefore, during the holding period, the gate low voltage VL may be periodically applied to the QP node QP.

[0105] Fig. 6A This is an example of using the second embodiment according to the present disclosure Figure 4A The circuit diagram of the gate driver of the circuit is shown in FIG. Figure 6B Is input to Fig. 6A The circuit signal and the Fig. 6A The waveform diagram of the signal output by the circuit. Fig. 6A Shows Figure 5A This is a modification of the example shown in ; therefore, redundant description will be omitted.

[0106] Each of the multiple stages includes a pull-up portion, a pull-down portion, a Q-node control unit, and a QB-node control unit. Fig. 6A The pull-up and pull-down parts of Figure 5A The corresponding parts of Fig. 6A The Q node control unit and QB node control unit are respectively based on Figure 5A The Q node control unit and QB node control unit are modified from the above reference. Figure 5A As mentioned, the Q node control unit may also include a Q1 node stabilization unit, but it may also be omitted. Fig. 6A As shown in , the circuit includes a Q1 node stabilizing unit. Therefore, the Q node control unit will be referred to as a Q2 node control unit.

[0107] Reference Fig. 6A and Figure 6B , the Q2 node control unit applies the gate low voltage VL to the Q1 node Q1 in the first period P1. In the first period P1, the Q2 node control unit applies the gate voltage of the start signal VST to the Q1 node through the start signal VST. Then, in the second period P2, the Q2 node control unit applies the gate high voltage VH to the Q1 node. The Q2 node control unit includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0108] The gate of the fifth transistor T5 is connected to the input terminal to which the second clock signal CLK2 is input, the first electrode thereof is connected to the input terminal to which the start signal VST is input, and the second electrode thereof is connected to the Q1 node Q1.

[0109] The gate electrode of the sixth transistor T6 is connected to the QB node QB, the first electrode thereof is connected to the Q1 node Q1, and the second electrode thereof is connected to the input terminal to which the gate high voltage VH is input.

[0110] A gate of the seventh transistor T7 is connected to an input terminal to which the gate low voltage VL is input, a first electrode thereof is connected to the Q1 node Q1, and a second electrode thereof is connected to the Q2 node Q2.

[0111] In the first period P1, the gate low voltage VH is applied to the Q1 node Q1 and the Q2 node Q2. The fifth transistor T5 is turned on by the second clock signal CLK2 at the gate low voltage VL, so that the gate low voltage VL of the start signal VST is applied to the Q1 node Q1 through the fifth transistor T5. Since the seventh transistor T7 is always turned on, the gate low voltage VL is applied to the Q2 node Q2. The pull-up transistor Tu is turned on by the gate low voltage VL applied to the Q2 node Q2. In this case, since the first clock signal CLK1 is at the level of the gate high voltage VH, the output signal Out is a cut-off voltage.

[0112] In the (1-1)th period P(1-1) after the first period P1, the output signal Out is a conduction voltage. The Q1 node Q1 becomes floating in the gate low voltage VL state due to the second clock signal CLK2 in the gate high voltage VH. Since the first clock signal CLK1 becomes the gate low voltage VL, the gate low voltage VL is applied to the output signal Out, and the voltage at the Q2 node Q2 becomes lower than the gate low voltage VL due to the bootstrap of the second capacitor C2. The pull-up transistor Tu can stably output the output signal Out due to the voltage at the Q2 node Q2 that has become lower than the gate low voltage VL.

[0113] In the second period P2, the gate high voltage VH is applied to the Q1 node Q1 and the Q2 node Q2. The sixth transistor T6 is turned on by the gate low voltage VL applied to the QB node QB, and the gate high voltage VH is applied to the Q1 node Q1 through the sixth transistor T6. In addition, the fifth transistor T5 is turned on by the second clock signal CLK2 that becomes the gate low voltage VL, so that the gate high voltage VH of the start signal VST is applied to the Q1 node Q1. Therefore, the pull-up transistor Tu is turned off.

[0114] The QB node control unit applies a gate low voltage VL to the QB node QB by applying the turn-on voltage of the second clock signal CLK2 to the QP node QP using the coupling of the first capacitor C1. Then, the QB node control unit applies a gate high voltage VH to the QB node QB due to the gate signal or the Q1 node Q1.

[0115] The QB node control unit includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , and a first capacitor C1 .

[0116] The gate electrode of the first transistor T1 is connected to the Q1 node Q1, the first electrode thereof is connected to the QP node QP, and the second electrode thereof is connected to an input terminal to which the gate high voltage VH is input.

[0117] The gate of the second transistor T2 is connected to the first clock signal CLK1, the first electrode thereof is connected to the QP node QP, and the second electrode thereof is connected to the input terminal to which the gate high voltage VH is input.

[0118] The gate of the third transistor T3 is connected to the input terminal or the Q1 node to which the start signal VST is input, the first electrode thereof is connected to the QB node QB, and the second electrode thereof is connected to the input terminal to which the gate high voltage VH is input.

[0119] The gate electrode of the fourth transistor T4 is connected to the QP node QP, the first electrode thereof is connected to the input terminal to which the second clock signal CLK2 is input, and the second electrode thereof is connected to the QB node QB.

[0120] A first electrode of the first capacitor C1 is connected to an input terminal to which the second clock signal CLK2 is input, and a second electrode thereof is connected to the QP node QP.

[0121] In the first period P1, the gate high voltage VH is applied to the QB node QB. The second transistor T2 is turned off due to the first clock signal CLK1 at the gate high voltage VH. The first transistor T1 and the third transistor T3 are turned on due to the start signal VST or the Q1 node Q1 at the gate low voltage VL. Therefore, the gate high voltage VGH is applied to the QP node QP through the first transistor T1, and the gate high voltage VH is applied to the QB node QB through the third transistor T3. Then, the fourth transistor T4 is turned off due to the voltage applied to the QP node QP. Therefore, the gate high voltage VH is applied to the QB node QB due to the gate low voltage VL of the start signal VST. The gate high voltage VH applied to the QB node QB is maintained even during the (1-1)th period P(1-1).

[0122] In the second period P2, the gate low voltage VH is applied to the QB node QB. The first transistor T1 is turned off due to the Q1 node Q1 being at the gate high voltage VH. The third transistor T3 is turned off due to the start signal VST or the Q1 node Q1 being at the gate high voltage VH, and the second transistor T2 is turned off due to the first clock signal CLK1 being at the gate high voltage VH. Therefore, the QP node QP floats. As the second clock signal CLK2 applied to the first electrode of the first capacitor C1 is reduced from the gate high voltage VH to the gate low voltage VL, the voltage at the QP node QP connected to the second electrode of the first capacitor C1 is reduced to the gate low voltage VL due to coupling. Therefore, the fourth transistor T4 is turned on due to the voltage at the QP node QP, so that the gate low voltage VL can be fully applied to the QB node QB. Then, the pull-down transistor Td is turned on, so that the output signal Out of the gate high voltage VH can be provided to the gate line of the pixel row.

[0123] As described above with respect to the first embodiment, the third period P3 is a period after the second period P2 until the next frame. The pull-down transistor Td remains turned on so as to maintain the output signal Out at the gate high voltage VH. In this case, the QB node control unit may further include a third capacitor C3. During the third period P3, the third capacitor C3 maintains the voltage charged between the first electrode and the second electrode in the second period P2. The voltage at the QP node QP is coupled by the second clock signal CLK2, which is periodically changed to the gate low voltage VL, during the third period P3, thereby reducing it to the gate low voltage VL. Therefore, the fourth transistor T4 is turned on due to the gate low voltage VL, so that the gate low voltage VL is applied to the QB node QB.

[0124] Fig. 7A This is an example of adopting the third embodiment according to the present disclosure. Figure 4A The circuit diagram of the gate driver of the circuit is shown in FIG. Figure 7B Is input to Fig. 7A The circuit signal and the Fig. 7A The waveform diagram of the signal output by the circuit. Fig. 7A Shows Figure 5A This is a modification of the example shown in ; therefore, redundant description will be omitted.

[0125] Each of the multiple stages includes a pull-up portion, a pull-down portion, a Q-node control unit, and a QB-node control unit. Fig. 7A The pull-up part, pull-down part and Q node control unit are Figure 5A The corresponding parts of Fig. 7A The QB node control unit is based on Figure 5A The QB node control unit is modified from the above reference Figure 5A As mentioned, the Q node control unit may also include a Q1 node stabilization unit, but it may be omitted. Fig. 7A As shown in FIG. 1 , the circuit includes a Q1 node stabilizing unit. Therefore, the Q node control unit will be referred to as a Q2 node control unit. Figure 5A The Q node control units are the same; therefore, redundant descriptions will be omitted.

[0126] Reference Fig. 7A and Figure 7B The QB node control unit applies the gate low voltage VL to the QB node QB by applying the turn-on voltage of the second clock signal CLK2 to the QP node QP using the coupling of the first capacitor C1. Then, the QB node control unit applies the gate high voltage VH to the QB node QB due to the gate signal.

[0127] The QB node control unit includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , and a first capacitor C1 .

[0128] The gate of the first transistor T1 is connected to an input terminal to which the start signal VST is input, a first electrode thereof is connected to the QP node QP, and a second electrode thereof is connected to an input terminal to which the gate high voltage VH is input.

[0129] The gate of the second transistor T2 is connected to the first clock signal CLK1, the first electrode thereof is connected to the QP node QP, and the second electrode thereof is connected to the output terminal through which the output signal Out is output.

[0130] The gate electrode of the third transistor T3 is connected to the input terminal to which the start signal VST is input, the first electrode thereof is connected to the QB node QB, and the second electrode thereof is connected to the input terminal to which the gate high voltage VH is input.

[0131] The gate electrode of the fourth transistor T4 is connected to the QP node QP, the first electrode thereof is connected to the input terminal to which the second clock signal CLK2 is input, and the second electrode thereof is connected to the QB node QB.

[0132] A first electrode of the first capacitor C1 is connected to an input terminal to which the second clock signal CLK2 is input, and a second electrode thereof is connected to the QB node QB.

[0133] In the first period P1, the gate high voltage VH is applied to the QB node QB. The second transistor T2 is turned off due to the first clock signal CLK1 at the gate high voltage VH. The first transistor T1 and the third transistor T3 are turned on due to the start signal VST at the gate low voltage VL. Therefore, the gate high voltage VGH is applied to the QP node QP through the first transistor T1, and the gate high voltage VH is applied to the QB node QB through the third transistor T3. Then, the fourth transistor T4 is turned off due to the voltage applied to the QP node QP. Therefore, the gate high voltage VH is applied to the QB node QB due to the gate low voltage VL of the start signal VST.

[0134] The gate high voltage VH applied to the QB node QB is maintained even during the (1-1)th period P(1-1). The output signal Out is the gate low voltage VL. During the (1-1)th period P(1-1), the first transistor T1 and the third transistor T3 are turned off due to the start signal VST at the gate high voltage VH, and the second transistor T2 is turned on due to the first clock signal CLK1 at the gate low voltage VH. Therefore, the output signal Out is applied to the QP node QP. When the gate low voltage VL is applied to the QP node QP, the fourth transistor T4 is turned on, so that the second clock signal CLK2 at the gate high voltage VH is applied to the QB node QB. During the (1-1)th period P(1-1), the QP node QP becomes the gate low voltage VL due to the output signal Out input through the second transistor T2, so that the QB node QB may not float, but may maintain the gate high voltage VH.

[0135] In the second period P2, the gate low voltage VH is applied to the QB node QB. The first transistor T1 is turned off due to the start signal VST at the gate high voltage VH. The third transistor T3 is turned off due to the start signal VST at the gate high voltage VH, and the second transistor T2 is turned off due to the first clock signal CLK1 at the gate high voltage VH. Therefore, the QP node QP floats. As the second clock signal CLK2 applied to the first electrode of the first capacitor C1 is reduced from the gate high voltage VH to the gate low voltage VL, the voltage at the QP node QP connected to the second electrode of the first capacitor C1 is reduced to a voltage lower than the gate low voltage VL due to coupling. Therefore, the fourth transistor T4 is turned on due to the voltage at the QP node QP, so that the gate low voltage VL can be fully applied to the QB node QB. Then, the pull-down transistor Td is turned on, so that the output signal Out of the gate high voltage VH can be provided to the gate line of the pixel row.

[0136] As described above for the first embodiment, the third period P3 is the time after the second period P2 until the next frame. The pull-down transistor Td remains turned on so as to maintain the output signal Out at the gate high voltage VH. In this case, the QB node control unit may further include a third capacitor C3. The third capacitor C3 maintains the voltage charged between the first electrode and the second electrode in the second period P2. The voltage at the QP node QP is coupled by the second clock signal CLK2 that periodically becomes the gate low voltage VL during the third period P3, thereby reducing it to a voltage lower than the gate low voltage VL. Therefore, the fourth transistor T4 is turned on due to the gate low voltage VL, so that the gate low voltage VL is applied to the QB node QB.

[0137] The embodiments of the present disclosure may also be described as follows:

[0138] According to one aspect of the present disclosure, a gate driver and a display panel including the gate driver may be described as follows:

[0139] The display panel includes pixels connected to a gate line and a gate driver that supplies a gate signal to at least one of the gate lines and includes multiple stages. Each stage includes: a pull-up transistor that applies a turn-on voltage of a first clock signal to an output terminal in response to a voltage at a Q node; a pull-down transistor that applies a turn-off voltage to the output terminal in response to a voltage at a QB node, and the QB node maintains the turn-on voltage during a period in which the output terminal is applied with the turn-off voltage; and a QB node control unit that applies the turn-on voltage to the QB node in response to a first clock signal and a second clock signal that is inverted from the first clock signal. Therefore, the display panel may include a gate driver that can set, reset, and maintain the voltage at the QB node.

[0140] Each stage may further include: a Q-node control unit that applies the turn-on voltage to the Q-node in response to a start signal or the second clock signal.

[0141] The Q node may include a Q1 node and a Q2 node, and the Q node control unit may further include a Q node stabilizing unit connected between the Q1 node and the Q2 node.

[0142] The Q-node control unit may apply a gate high voltage to the Q-node in response to a voltage at the QB node.

[0143] The on-voltage may be a gate low voltage, and the off-voltage may be a gate high voltage.

[0144] Each stage may further include a capacitor connected between the QB node and an input terminal of the gate high voltage.

[0145] The QB node control unit may include a first capacitor having a first electrode to which the second clock signal is applied and a second electrode connected to the QP node coupled to the second clock signal.

[0146] The QB node control unit may further include a QP node control unit for controlling the QP node.

[0147] The QP node control unit may include a first transistor and a second transistor each having an electrode connected to the QP node.

[0148] According to another aspect of the present disclosure, a gating driver includes: a QB node control unit, the QB node control unit controls a QB node as a gate node of a pull-down transistor. The QB node control unit includes: a first transistor and a second transistor, each of which has an electrode connected to a QP node for controlling the QP node; a third transistor, the third transistor applying a gating high voltage to the QB node; and a fourth transistor, the fourth transistor having a gate connected to the QP node to apply a gating low voltage to the QB node. A gating driver with improved output signal accuracy can be implemented by a QB node control unit capable of controlling the QB node.

[0149] The QB node control unit may include a first capacitor connected between the QP node and an input terminal to which a second clock signal is input.

[0150] The QB node control unit may include a second capacitor connected between the QB node and an input terminal to which a gate high voltage is applied.

[0151] The first transistor may be controlled by a start signal, the second transistor may be controlled by a first clock signal, and an electrode of each of the first transistor and the second transistor may be connected to an input terminal to which a gate high voltage is applied.

[0152] The third transistor may be controlled by a start signal.

[0153] The gating driver may further include a pull-up transistor. The first transistor is controlled by a voltage applied to a gate of the pull-up transistor. The second transistor is controlled by a first clock signal. And an electrode of each of the first transistor and the second transistor is connected to an input terminal to which a gating high voltage is applied.

[0154] The third transistor may be controlled by a start signal or a voltage input to a gate of the pull-up transistor.

[0155] The first transistor can be controlled by a start signal, the second transistor can be controlled by a first clock signal, the electrode of the first transistor can be connected to an input terminal to which a selection high voltage is applied, and the electrode of the second transistor can be connected to an output terminal that outputs an output signal of the selection driver.

[0156] A gate of the third transistor may be connected to an input terminal to which a start signal is input or a gate of the pull-up transistor.

[0157] It is obvious to those skilled in the art that various modifications and variations can be made in the gate driver of the present disclosure and the display panel having the gate driver without departing from the technical concept or scope of the present disclosure. Therefore, the present disclosure is intended to cover the modifications and variations of the present disclosure as long as they fall within the scope of the attached claims and their equivalents.

[0158] CROSS-REFERENCE TO RELATED APPLICATIONS

[0159] This application claims the priority benefit of Korean Patent Application No. 10-2017-0123954 filed on September 26, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

Claims

1. A display panel, comprising: A QB node control unit, the QB node control unit is configured to control a QB node, the QB node is a gate node of a pull-down transistor, the QB node control unit comprises: a first transistor having a gate connected to a start signal input terminal, a first electrode connected to a QP node for controlling the QB node, and a second electrode connected to a gate-off voltage input terminal; a second transistor having a gate connected to the first clock input terminal, a first electrode connected to the QP node, and a second electrode connected to the gate-off voltage input terminal; a third transistor configured to apply a gate-off voltage to the QB node; a fourth transistor having a gate connected to the QP node, a first electrode connected to the QB node, and a second electrode connected to a second clock input terminal; and A first capacitor is connected between the QP node and the second clock input terminal.

2. The display panel according to claim 1, in, The third transistor has a gate connected to the start signal input terminal, a first electrode connected to the QB node, and a second electrode connected to the gate-off voltage input terminal.

3. The display panel according to claim 1, in, The QB node control unit further includes a second capacitor connected between the QB node and the gate-off voltage input terminal.

4. The display panel according to claim 1, further comprising: A fifth transistor having a gate connected to the start signal input terminal, a first electrode connected to the Q1 node for controlling the pull-up transistor, and a second electrode connected to the start signal input terminal.

5. The display panel according to claim 4, further comprising: a seventh transistor having a gate connected to a gate-on voltage input terminal, a first electrode connected to the pull-up transistor, and a second electrode connected to the fifth transistor.

6. The display panel according to claim 1, further comprising: A sixth transistor having a gate connected to the QB node, a first electrode connected to the Q1 node for controlling a pull-up transistor, and a second electrode connected to the gate-off voltage input terminal.

7. The display panel according to claim 1, in, While the start signal is a gate-on voltage, the first transistor is turned on so that a gate-off voltage is applied to the QP node, and the third transistor is turned on so that the gate-off voltage is applied to the QB node.

8. The display panel according to claim 1, in, While the output signal of the gate driver is the gate-on voltage, the second transistor is turned on so that the gate-off voltage is applied to the QP node.

9. A display panel, comprising: a plurality of stages, the plurality of stages being cascaded to each other and generating a plurality of scanning signals, Each of the plurality of stages comprises: a first transistor configured to apply a gate-off voltage to the QP node for controlling the QB node, wherein a gate of the first transistor is connected to the Q1 node, a second transistor having a gate connected to the first clock input terminal, a first electrode connected to the QP node, and a second electrode connected to a gate-off voltage input terminal, a third transistor having a gate connected to a start signal input terminal or the Q1 node for controlling a pull-up transistor, a first electrode connected to the QB node, and a second electrode connected to the gate-off voltage input terminal, a fourth transistor having a gate connected to the QP node, a first electrode connected to the QB node, and a second electrode connected to a second clock input terminal; and A fifth transistor having a gate connected to the second clock input terminal, a first electrode connected to the Q1 node, and a second electrode connected to the start signal input terminal.

10. The display panel according to claim 9, in, The first transistor has a gate connected to the Q1 node, a first electrode connected to the QP node, and a second electrode connected to the gate-off voltage input terminal.

11. The display panel according to claim 9, in, The QB node control unit also includes a first capacitor connected between the QP node and the second clock input terminal.

12. The display panel according to claim 9, in, The QB node control unit further includes a second capacitor connected between the QB node and the gate-off voltage input terminal.

13. The display panel according to claim 9, further comprising: A sixth transistor having a gate connected to the QB node, a first electrode connected to the Q1 node, and a second electrode connected to the gate-off voltage input terminal.

14. The display panel according to claim 9, further comprising: a seventh transistor having a gate connected to a gate-on voltage input terminal, a first electrode connected to the pull-up transistor, and a second electrode connected to the fifth transistor.

15. The display panel according to claim 9, in, When the start signal is the gate-on voltage, the first transistor is turned on so that the gate-off voltage is applied to the QP node, the third transistor is turned on so that the gate-off voltage is applied to the QB node, and the fifth transistor is turned on so that the gate-on voltage is applied to the Q1 node.

16. The display panel according to claim 9, in, When the output signal of the gate driver is the gate-on voltage, the first transistor is turned on so that the gate-off voltage is applied to the QP node, the second transistor is turned on so that the gate-off voltage is applied to the QP node, and the third transistor is turned on so that the gate-off voltage is applied to the QB node.

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