Electroluminescent Display

Abstract

Electroluminescent display. An organic light emitting display includes: a pixel connected to a gate line; and a gate drive circuit that supplies a gate signal to at least one gate line and includes a plurality of stages connected to each other in a cascade manner. The nth stage of the gate drive circuit includes: a Q1 node charging unit that charges the Q1 node to a turn-on voltage using an inverted first clock signal and a second clock signal; and a pull-up transistor that applies a turn-on voltage to an output terminal in response to the Q1 node voltage. The Q1 node charging unit includes: a first charging unit that charges the Q1 node voltage to a turn-on voltage using the second clock signal; and a second charging unit that charges a Q2 node connected to the Q1 node using the first clock signal in an interval in which the Q1 node has the turn-on voltage, wherein n is a positive integer.

Description

[0001] This application is a divisional application of an invention patent application with an application date of July 23, 2018, application number 201810811537.4, and invention name “Gate drive circuit and electroluminescent display using the gate drive circuit”. Technical Field

[0002] The present disclosure relates to a gate driving circuit with enhanced driving capability and an electroluminescent display using the gate driving circuit. Background Art

[0003] Due to its miniaturization and lightness, flat panel displays (FPDs) are widely used not only in monitors for desktop computers, but also in monitors for mobile computers such as laptop computers and tablet PCs and mobile phones. Recently, not only flat panel displays but also various types of displays including curved displays, flexible displays, rollable displays and wearable displays are being developed. These displays are, for example, liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), electroluminescent displays, organic light emitting diode displays (OLEDs), quantum dot displays (QDs), etc.

[0004] Among them, the electroluminescent display has a fast response speed and a wide viewing angle, and can generate brightness with high luminous efficiency. Generally, the electroluminescent display uses a transistor turned on by a scan signal to apply a data voltage to the gate of a driving transistor, and charges the data voltage supplied to the driving transistor into a storage capacitor. In addition, the electroluminescent device is enabled to emit light using an emission signal. The electroluminescent device may include an organic electroluminescent device and an inorganic electroluminescent device, and therefore, the electroluminescent display may be classified as an organic light-emitting display or an inorganic light-emitting display.

[0005] The electroluminescent display is driven using an emission signal and one or more scan signals. Typically, a gate drive circuit that generates an emission signal and a scan signal as a gate signal includes a shift register for sequentially outputting the gate signal. The gate drive circuit can be implemented in a border area of ​​a display panel in a gate-in-panel (GIP) manner consisting of a group of thin film transistors (TFTs), and the border area is a non-display area. The gate drive circuit in the GIP manner includes a plurality of stages whose number corresponds to the number of gate lines, wherein each of the plurality of stages outputs a gate pulse to be supplied to a corresponding gate line among the gate lines.

[0006] The shift register can be implemented in various ways, and efforts are being made to optimize the circuit configuration of the gate drive circuit in order to enhance the driving capability and reliability.

[0007] As mentioned above, the gate drive circuit can be implemented in a GIP manner, which is a technology that builds the gate drive circuit into the display panel together with the pixel array. This gate drive circuit can be referred to as a GIP circuit. The GIP circuit may include a shift register, and each stage in the shift register may generate an output in response to a start pulse and shift the generated output according to a clock signal. The gate drive circuit may include a stage having a plurality of transistors, and these stages may be connected to each other in a cascade manner and sequentially generate outputs. In this case, the transistor may include a TFT as a type of transistor.

[0008] These stages may each include a Q node for controlling a pull-up transistor and a QB (Qbar) node for controlling a pull-down transistor. For example, each of these stages may include a transistor, each of which charges and discharges the Q node and the QB node to a reverse voltage in response to a start voltage signal and a clock signal input from a previous stage.

[0009] The QB node is charged and discharged to a voltage that is opposite to the voltage of the Q node. When the Q node has a high potential voltage, the QB node has a low potential voltage. When the Q node has a low potential voltage, the QB node has a high potential voltage. The pull-up transistor or the pull-down transistor is turned on in response to the low potential voltage applied to the Q node or the QB node, and the pull-up transistor or the pull-down transistor is turned off in response to the high potential voltage applied to the Q node or the QB node, so the transistor connected to the gating line is turned on / off. Each of the pull-up transistor and the pull-down transistor has an electrode connected to the output terminal, and the output terminal is connected to the gating line for providing a gating signal to the pixel array.

[0010] As mentioned above, the output signal is applied to the output terminal by the Q node and the QB node. Therefore, if the Q node or the QB node becomes floating, the voltage of the Q node or the QB node may be variable, not fixed, and thus an erroneous output signal may be output.

[0011] The electroluminescent display is driven using an emission signal and one or more scan signals. In order to drive the electroluminescent display, not only a signal for scanning a data signal but also an emission signal for preventing the light emitting device from emitting light during the scanning period of the scan signal is required. In this case, the emission signal and the scan signal can be combined into a strobe signal.

[0012] Generally, the scan signal can be inverted to generate the emission signal. However, the emission generated by inverting the scan signal may be interfered with during the pulse width modulation drive of the electroluminescent display and the scanning of the scan signal. In addition, the increase in the load of the clock signal and the emission signal due to the high resolution of the display panel may reduce the operating margin, thereby possibly causing errors in the emission driver.

[0013] Therefore, in order to solve the above-mentioned problems, the inventors of the present specification have proposed a gate driving circuit having enhanced driving capability and reliability and an electroluminescent display using the gate driving circuit.

[0014] An object of the present disclosure is to provide a gate drive circuit and an electroluminescent display using the same, wherein the gate drive circuit has improved driving capability and reliability because a high potential voltage or a low potential voltage is applied without floating the Q node to prevent an erroneous output from being output from an output terminal.

[0015] Another object of the present disclosure is to provide a gate driving circuit and an electroluminescent display using the gate driving circuit, which can improve the driving capability of a transistor, maintain stable output characteristics and achieve a narrow frame.

[0016] Another object of the present disclosure is to provide a gate drive circuit and an electroluminescent display using the gate drive circuit, wherein the gate drive circuit avoids interference during a pulse width modulation drive period of the electroluminescent display and a scanning period of a scanning signal, thereby improving the accuracy of an emission signal.

[0017] Still another object of the present disclosure is to provide a gate driving circuit and an electroluminescent display using the same, which can operate without error despite an increase in loads of a clock signal and an emission signal due to a high resolution of the electroluminescent display.

[0018] The objects of the present disclosure should not be limited to the above-mentioned objects, and other unmentioned objects will be clearly understood by those skilled in the art from the following description. Summary of the invention

[0019] Accordingly, embodiments of the present disclosure are directed to a gate driving circuit and an electroluminescent display using the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0020] Additional features and aspects will be described in the following description, and in part will be apparent from the description, or can be understood by practicing the inventive concepts provided herein. Other features and aspects of the inventive concepts can be realized and obtained by the structures specifically pointed out in the written description, or structures derived therefrom, the claims of the present disclosure, and the accompanying drawings.

[0021] To achieve these and other aspects of the inventive concept, as specifically implemented and broadly described, an electroluminescent display includes: a pixel connected to a gate line; and a gate drive circuit that supplies a gate signal to at least one of the gate lines and includes a plurality of stages connected to each other in a cascade manner. The nth (n is a positive integer) stage of the gate drive circuit may include: a Q1 node charging unit that charges the Q1 node to a turn-on voltage using an inverted first clock signal and a second clock signal, and a pull-up transistor that applies a turn-on voltage to an output terminal in response to the Q1 node voltage. The Q1 node charging unit may include: a first charging unit that charges the Q1 node voltage to a turn-on voltage using the second clock signal, and a second charging unit that charges a Q2 node connected to the Q1 node using the first clock signal in an interval in which the Q1 node has a turn-on voltage.

[0022] On the other hand, the gating drive circuit includes a plurality of stages connected to each other in a cascade manner and is used to output a gating signal. Each of the plurality of stages outputs the gating signal using a first clock signal and a second clock signal. The nth (n is a positive integer) stage among the plurality of stages includes: a pull-up transistor, which applies a turn-on voltage to an output terminal in response to a voltage at a Q1 node; a first capacitor, which is connected between the Q1 node and the Q2 node; a first transistor, which includes a gate connected to an input terminal of the second clock signal, a source connected to an input terminal of a start signal, and a drain connected to the Q1 node; and a second transistor, which includes a gate connected to the Q1 node, a source connected to an input terminal of the first clock signal, and a drain connected to the Q2 node.

[0023] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are included to provide a further understanding of the present disclosure, are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0025] Figure 1 is a diagram illustrating a configuration of an electroluminescent display according to the present specification;

[0026] Figure 2 It is an example Figure 1 A block diagram of a pixel shown in FIG.

[0027] Figure 3 It is an example Figure 1 A diagram of an exemplary arrangement of a gate drive circuit shown in FIG.

[0028] Figure 4 is a block diagram illustrating a gate driving circuit provided on one side of a display panel according to an embodiment of the present specification;

[0029] Figure 5 It is an example Figure 4 A block diagram of a transmit driver is shown in FIG.

[0030] Figure 6 is a diagram illustrating a configuration of an nth emission driver in a gate driving circuit;

[0031] Figure 7 is a diagram illustrating a detailed configuration of an n-th emission driver according to the first embodiment of the present specification;

[0032] Figure 8 is an example of applying to Figure 7 ;

[0033] Fig. 9 is a diagram illustrating a transmission driver according to a second embodiment of the present specification;

[0034] Fig.10 is shown for driving Fig. 9 ;

[0035] Fig.11 is a block diagram illustrating a configuration of a transmission driver according to a comparative example;

[0036] Fig.12 It is an example Fig.11 A diagram of a circuit configuration of a transmit driver shown in FIG.

[0037] Fig.13 and Fig.14 is shown for illustration and Fig.12 A diagram of a circuit configuration and a driving waveform showing operation characteristics related to an inverter shown in FIG.

[0038] Fig.15 is a block diagram illustrating a configuration of an nth emission driver according to a third embodiment of the present specification;

[0039] Fig.16 It is an example Fig.15 A diagram of a circuit configuration of an output buffer shown in FIG.

[0040] Fig.17is a diagram illustrating a detailed circuit configuration of an n-th emission driver according to a third embodiment of the present specification;

[0041] Fig.18 It is an example Fig.17 The waveform diagram of the nth transmitting driver shown in FIG.

[0042] Fig.19 and Fig. 20 is an example used to illustrate Fig.17 A diagram of a circuit configuration and a driving waveform showing operation characteristics related to a QB2 node controller shown in FIG.

[0043] Fig.21 is a diagram of voltage waveforms measured at the QB1 node and the QB2 node of the n-th emission driver according to the third embodiment of the present specification;

[0044] Fig. 22 is a block diagram illustrating an nth emission driver according to a fourth embodiment of the present specification;

[0045] Fig.23 is a block diagram illustrating an nth emission driver according to a fifth embodiment of the present specification;

[0046] Fig.24 It shows Fig. 22 and Fig.23 A graph of an output waveform of the transmit driver shown in FIG.

[0047] Fig.25 is a circuit diagram of a QB node regulator according to a first embodiment of the present specification;

[0048] Fig.26 is a circuit diagram of a QB node regulator according to a second embodiment of the present specification;

[0049] Fig. 27 is a circuit diagram of a QB node regulator according to a third embodiment of the present specification;

[0050] Fig.28 is a circuit diagram of a QB node regulator according to a fourth embodiment of the present specification; and

[0051] Fig.29 is a diagram of a driving waveform of a QB node regulator according to an embodiment of the present specification. DETAILED DESCRIPTION

[0052] According to the embodiments described below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will become clear. However, the present disclosure is not limited to these embodiments, but can be implemented in various modified forms. These embodiments are provided only to fully disclose the present disclosure and to provide suggestions for those skilled in the art to which the present disclosure belongs. The present disclosure is limited only by the attached claims. Throughout the specification, the same reference numerals represent the same elements.

[0053] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the accompanying drawings are exemplary, and embodiments are not limited thereto. Throughout the specification, similar reference numerals refer to similar elements. In the following description of the embodiments, when determining the subject of the embodiments will be unnecessarily confused, a detailed description of known related technologies will be omitted. In the case where the terms "including", "having", "completing", etc. are used in this specification, other components may be added unless "only" is used. As used herein, the singular forms "one", "an", and "the" are also intended to include plural forms unless the context clearly indicates otherwise.

[0054] When construing constituent elements, they can be construed as including the error range even if they are not described separately.

[0055] In the case of describing a positional relationship, for example, if the positional relationship between two components is described as "on," "over," "below," or "beside," one or more other components may be located between the two components unless "just" or "just" is used.

[0056] When describing a time relationship, for example, if the time sequence is described by "after", "subsequently", "next", "before", etc., the discontinuous case is also included unless "just" or "exactly" is used.

[0057] Although "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the technical spirit of the embodiment, the first component mentioned below may be the second component.

[0058] It is to be understood that the features of the various embodiments may be partially or completely coupled or combined with each other, and that various interlocks and drives are technically possible, and the embodiments may be practiced independently of each other.

[0059] The switching element in the gate drive circuit of this specification can be implemented as an n-type or p-type transistor in a metal oxide semiconductor field effect transistor (MOSFET) structure. In the following embodiments, the switching element is illustrated by a p-type transistor, but the aspects of the present disclosure are not limited thereto. The transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode for supplying carriers to the transistor. The carriers flow out from the source of the transistor. The drain is the electrode through which the carriers flow out of the transistor. That is, the carriers in the MOSFET flow from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carriers are electrons, the source voltage is lower than the drain voltage, so that the carriers flow from the source to the drain. In the case of an n-type MOSFET, since the electrons flow from the source to the drain, the flow direction of the current is from the drain to the source. In the case of a p-type MOSFET (PMOS), since the carriers are holes, the source voltage is higher than the drain voltage, so that the holes flow from the source to the drain. Since holes flow from the source to the drain in a p-type MOSFET, current flows from the source to the drain. The source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can be changed according to the applied voltage. In the following embodiments, the present disclosure is not limited by the source and drain of the transistor.

[0060] Figure 1 is a diagram illustrating a configuration of a display according to the present specification. Figure 2 It is an example Figure 1 A block diagram of a pixel is shown in FIG. Figure 3 It is an example Figure 1 Schematic diagram of an exemplary arrangement of a gate drive circuit shown in FIG.

[0061] Reference Figure 1 , the electroluminescent display according to the present disclosure includes a display panel 10 in which pixels P are arranged in a matrix manner, a data driver 120, a gate driving circuit, an image processing unit 110, and a timing controller 111. In this case, the arrangement manner of the pixels P is not limited to the matrix manner, but may be any one of various forms such as a stripe manner and a diamond manner.

[0062] The display panel includes a display area 10A in which pixels P are arranged and an image is displayed, and a non-display area 10B in which a gate driving circuit is arranged and no image is displayed.

[0063] The display area 10A includes a plurality of pixels P, and displays an image based on the grayscale of the corresponding pixel P. The pixels P are arranged along the first pixel row HL1 to the n-th pixel row HLn. Each pixel P is connected to a data line DL aligned along a column line and a gate line GL aligned along the pixel row HL. The pixels aligned on the same pixel row share the same gate line GL, so they are driven simultaneously. When the pixel aligned on the first pixel row HL1 is defined as the first pixel P1 and the pixel aligned on the n-th pixel row HLn is defined as the n-th pixel Pn, the pixels are driven in the order from the first pixel P1 to the n-th pixel Pn. In addition, the sampling period for writing data into a gate line can be defined as a horizontal time 1H.

[0064] The image processing unit 110 outputs driving signals for driving various devices in addition to image data supplied from the outside. The driving signals output from the image processing unit 110 may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.

[0065] The timing controller 111 is used to control the driving timing of the data driver 120 and the gate driving circuit. To this end, the timing controller 111 can rearrange the digital video data RGB input from the outside to fit the resolution of the display panel 10, and supply the rearranged digital video data RGB to the data driver 120. In addition, the timing controller 111 generates a data control signal DDC for controlling the operation timing of the data driver 120 and a gate control signal GDC for controlling the operation timing of the gate driving circuit based on timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a dot clock signal, and a data enable signal.

[0066] The data driver 120 drives the data lines DL. To this end, the data driver 120 converts the digital video data RGB input from the timing controller 111 into analog data voltages based on the data control signal DDC and supplies the analog data voltages to the data lines DL. The data driver 120 may be formed as an integrated circuit (IC).

[0067] The gate driving circuit may include a level shifter 130 and a gate driving circuit 140. The level shifter 130 may be formed as an IC in a printed circuit board (PCB) connected to the display panel 10, and the gate driving circuit 140 may be formed as a GIP circuit in the non-display area 10B. In this case, the method of implementing the level shifter 130 and the gate driving circuit 140 is not limited thereto.

[0068] Under the control of the timing controller 111, the level shifter 130 shifts the voltage levels of the clock signal and the start signal VST, and then supplies the clock signal and the start signal VST to the gate driving circuit 140. The gate driving circuit 140 is formed as a combination of a plurality of thin film transistors (TFTs) (hereinafter referred to as transistors) in the non-display area 10B of the display panel 10 according to the GIP method.

[0069] The gate drive circuit 140 may include a scan driver for outputting a scan signal and an emission driver for outputting an emission signal. In this case, the emission signal may be referred to as an emission control signal, the scan signal and the emission signal may be referred to as a gate signal, and a component for outputting a gate signal may be referred to as a gate drive circuit. The scan driver and the emission driver may include a plurality of stages connected to each other in a cascade manner. Figure 1 As shown in , the gate driving circuit 140 can be arranged on one side of the display panel. Figure 3 , the gate driving circuit 140 may be formed as a GIP circuit in the non-display area 10B of the display panel 10 , and may be disposed on the left and right sides of the display panel.

[0070] Reference Figure 2 , the pixel P is connected to the gate line GL, the data line DL, the high potential voltage VEH and the low potential voltage VEL. The number of transistors and capacitors and the driving method of the pixel can be determined according to the configuration of the pixel circuit.

[0071] The pixel may include an organic light emitting diode, a switching transistor, a driving transistor, an emission control transistor, a capacitor, etc. However, the pixel is not limited thereto. In response to a scan signal, the switching transistor transmits a data voltage to the capacitor. The capacitor transmits the data voltage to the gate of the driving transistor. In response to the data voltage transmitted from the capacitor, the driving transistor generates a driving current for driving the light emitting device. The emission control transistor controls the light emitting time of the light emitting device in response to the emission signal.

[0072] In addition, the pixel P may be implemented in any of various structures such as 3T1C, 3T2C, 4T1C, 4T2C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, 8T1C, and 8T2C, depending on the number of transistors and capacitors additionally used to compensate for transistor degradation and a compensation method. Figure 2 Only one gate line GL is shown in FIG. 1 , and I (I is an integer equal to or greater than 2) gate lines may be provided according to the number of transistors included in a pixel and a compensation method. Figure 4 is a block diagram illustrating a gate driving circuit provided on one side of a display panel according to an embodiment of the present specification, Figure 5 It is an example Figure 4 A block diagram of the transmit driver is shown in FIG.

[0073] like Figure 4 As illustrated in FIG. 1 , the gate driving circuit 140 includes scan drivers SRD1 to SRD[n] that output scan signals SCAN1 to SCAN[n] and emission drivers EMD1 to EMD[n] that output emission signals EM1 to EM[n]. The scan drivers SRD1 to SRD[n] are connected to the first to n-th scan lines. The emission drivers EMD1 to EMD[n] are connected to the first to n-th emission lines.

[0074] The scan drivers SRD1 to SRD[n] and the emission drivers EMD1 to EMD[n] are configured as a plurality of stages for outputting signals in response to scan lines of the display panel. The first scan driver SRD1 and the first emission driver EMD1 may be defined as a first stage. The first stage SRD1 and EMD1 output a first scan signal SCAN1 and a first emission signal EM1 for driving a first pixel row HL1 of the display panel 10. The second scan driver SRD2 and the second emission driver EMD2 may be defined as a second stage. The second stage SRD2 and EMD2 output a second scan signal SCAN2 and a second emission signal EM2 for driving a second pixel row HL2 of the display panel 10.

[0075] like Figure 5 As illustrated in FIG. 1 , the first to n-th emission drivers EMD1 to EMD[n] generate first to n-th emission signals EM1 to EM[n] based on the first clock signal ECLK1 , the second clock signal ECLK2 , the start signal EVST, and the like, respectively.

[0076] The first clock signal ECLK1 and the second clock signal ECLK2 may swing between an emission high voltage and an emission low voltage and may be in anti-phase. In other words, the first emission clock signal ECLK1 and the second emission clock signal ECLK2 may be in anti-phase and may have different emission clock periods.

[0077] The low potential voltage VEL as the emission low voltage may be between -8V and -7V, and the high potential voltage VEH as the emission high voltage may be between 7V and 8V.

[0078] The first emission driver EMD1 to the nth emission driver EMD[n] adopt a structure in which each stage is connected to each other so that the signal of the previous stage is used for the next stage. The first emission driver EMD1 receives the start signal EVST through the start signal input terminal VP. Then, the second emission driver EMD2 to the nth emission driver EMD[n] respectively receive the first carry signal CRY1 to the n-1th carry signal CRY[n-1] generated from the emission driver of its corresponding previous stage.

[0079] Therefore, while the first emission driver EMD1 starts operation based on the start signal EVST received through the start signal input terminal VP, the second emission driver EMD2 starts operation based on the first carry signal CRY1 output from the first emission driver EMD1. Considering the input / output timing of the carry signal, a signal generated by an emission driver of a previous stage or a stage before that can be used as the carry signal, and therefore, the carry signal can be defined as a signal generated by an emission driver of a kth stage (k is an integer equal to or greater than 1).

[0080] Figure 6 is a diagram illustrating a configuration of an n-th emission driver in a gate driving circuit.

[0081] Reference Figure 6 , the nth emission driver EMD[n] includes Q1 node charging units 100 and 200 , a node controller 300 , a pull-up unit 400 , and a pull-down unit 500 .

[0082] The Q1 node charging units 100 and 200 may apply a turn-on voltage to the Q1 node Q1 using the first clock signal ECLK1 and the second clock signal ECLK2 applied alternately. The Q1 node charging units 100 and 200 may include a first charging unit 100 and a second charging unit 200, the first charging unit 100 charges the turn-on voltage to the Q1 node Q1 using the second clock signal ECLK, and the second charging unit 200 applies a turn-on voltage to the Q1 node Q1 using the first clock signal ECLK1.

[0083] The node controller 300 controls voltages of the Q1 node Q1 , the QB1 node QB1 , and the QB2 node QB2 .

[0084] The pull-up unit 400 outputs an emission signal in response to a voltage of the Q1 node Q1 .

[0085] The pull-down unit 500 controls the output terminal Nout to output a turn-off voltage in response to at least one of a voltage of the QB1 node ( QB1 ) or a voltage of the QB2 node ( QB2 ).

[0086] Hereinafter, the Figure 6 A detailed implementation of the transmit driver is shown in FIG.

[0087] Figure 7 is a diagram illustrating an n-th emission driver according to the first embodiment of the present specification.

[0088] Reference Figure 7 , the nth emission driver EMD[n] includes Q1 node charging units 100 and 200 , a node controller 300 , a pull-up unit 400 , and a pull-down unit 500 .

[0089] The Q1 node charging unit 100 and 200 includes a first charging unit 100 and a second charging unit 200. The first charging unit 100 (hereinafter, referred to as the first transistor T1) includes a gate connected to the second clock signal input terminal, a source connected to the start signal input terminal VP providing the start signal EVST, and a drain connected to the Q1 node Q1. The second clock signal input terminal CP2 receives the second clock signal ECLK2, and the start signal input terminal VP receives the start signal EVST or the carry signal. The carry signal may be an output signal from the n-1th emission driver EMD[n-1]. In the interval where both the start signal EVST and the second clock signal ECLK2 are in the on-voltage, the first transistor T1 charges the Q1 node Q1 to a low potential voltage VEL as the on-voltage.

[0090] The second charging unit 200 includes a second transistor T2 and a first capacitor C1. The second transistor T2 includes a gate connected to the Q1 node Q1, a source connected to the first clock signal input terminal CP1, and a drain connected to the Q2 node Q2. In the interval where both the Q1 node Q1 and the first clock signal ECLK1 are in the on-voltage, the second transistor T2 charges the Q2 node Q2 to a low potential voltage VEL as the on-voltage.

[0091] The first capacitor C1 is connected between the Q1 node Q1 and the Q2 node Q2. The first capacitor C1 bootstraps the voltage of the Q2 node Q2 in response to the voltage of the Q1 node Q1. Alternatively, the first capacitor C1 bootstraps the voltage of the Q1 node Q1 in response to the voltage of the Q2 node Q2.

[0092] The node controller 300 includes a Q1 holding unit (hereinafter, referred to as a third transistor) T3, a QP node controller (hereinafter, referred to as a fourth transistor) T4, a QB2 node controller (hereinafter, referred to as an eighth transistor) T8, a QB1 node controller (hereinafter, referred to as a ninth transistor) T9, a QB1 holding unit (hereinafter, referred to as a fifth transistor) T5, a QB2 holding unit (hereinafter, referred to as a tenth transistor) T10, and a second capacitor C2 and a third capacitor C3. The node controller 300 may be referred to as a Q1 node controller.

[0093] The third transistor T3 includes a gate connected to the QB node (QB2), a source connected to the Q1 node Q1, and a drain connected to the input terminal of the high potential voltage VEH. When the QB2 node QB2 has a turn-on voltage, the Q1 node controller 300 charges the Q1 node Q1 to the high potential voltage VEH as a turn-off voltage.

[0094] The QB node charging unit T4 , T8 , and T9 includes a fourth transistor T4 , an eighth transistor T8 , and a ninth transistor T9 .

[0095] The fourth transistor T4 includes a gate connected to the second clock signal input terminal CP2, a source connected to the n-1th QB2 node QB2(n-1), and a drain connected to the QP node QP. In an interval in which both the n-1th QB2 node QB2(n-1) and the second clock signal ECLK2 have a turn-on voltage, the fourth transistor T4 charges the QP node QP to a low potential voltage VEL as a turn-on voltage. The n-1th QB2 node QB2(n-1) indicates the QB2 node QB2 of the n-1th emission driver EMD[n-1].

[0096] The eighth transistor T8 includes a gate connected to the QP node QP, a source connected to the first clock signal input terminal CP1, and a drain connected to the QB2 node QB2. When the voltage of the QP node QP is a turn-on voltage, the eighth transistor T8 applies the voltage of the first clock signal ECLK1 to the QB2 node QB2.

[0097] Both electrodes of the second capacitor C2 are connected to the QP node QP and the QB2 node QB2, respectively. As a result, the QP node QP is bootstrapped according to the voltage variation of the QB2 node QB2.

[0098] The ninth transistor T9 includes a gate connected to the first clock signal input terminal CP1, a source connected to the QB2 node QB2, and a drain connected to the QB1 node QB1. The ninth transistor T9 switches a current path between the QB2 node QB2 and the QB1 node QB1 according to the voltage level of the first clock signal ECLK1.

[0099] The QB node controllers T5 and T10 include a fifth transistor T5 and a tenth transistor T10.

[0100] The fifth transistor T5 includes a gate connected to the Q1 node Q1, a source connected to the QB1 node QB1, and a drain connected to the high potential voltage VEH input terminal. When the voltage of the Q1 node is the on voltage, the fifth transistor T5 charges the voltage of the QB1 node QB1 to the high potential voltage VEH as the off voltage.

[0101] The tenth transistor T10 includes a gate connected to the Q1 node Q1, a source connected to the QB2 node QB2, and a drain connected to the high potential voltage VEH input terminal. When the voltage of the Q1 node Q1 is the on voltage, the tenth transistor T10 charges the voltage of the QB2 node QB2 to the high potential voltage VEH as the off voltage.

[0102] Both ends of the third capacitor C3 are connected to the QB1 node QB1 and the input terminal of the high potential voltage VEH, respectively. The third capacitor C3 may maintain the voltage of the QB1 node QB1 at a stable level, thereby enhancing the operational reliability of the pull-down transistor T7.

[0103] In response to the voltage of the Q1 node Q1, the pull-up unit 400 applies the low potential voltage VEL as a turn-on voltage to the output terminal Nout. The pull-up unit 400 may be implemented as a pull-up transistor T6 connected between the low potential voltage VEL input terminal and the output terminal Nout and having a gate connected to the Q1 node Q1.

[0104] The pull-down unit 500 includes a pull-down transistor T7 that applies a high potential voltage VEH as a cut-off voltage to the output terminal Nout in response to a voltage of a QB1 node QB1 .

[0105] Figure 8 is an example of applying to Figure 7 2 is a diagram showing the timing of the clock signal of the nth emission driver and the voltage changes of the main nodes.

[0106] Reference Figure 7 and Figure 8 , when the voltage of the Q1 node Q1 is a conduction voltage equal to or lower than the low potential voltage VEL, the pull-up transistor T6 charges the output terminal Nout to the low potential voltage VEL. The emission signal EM (n) at the conduction voltage is applied to the emission line of the nth pixel row (HLn) connected to the output terminal Nout. Due to the first clock signal ECLK1 and the second clock signal ECLK2 that alternately maintain the conduction voltage, the Q1 node Q1 node is maintained at the low potential voltage VEL. The first clock signal ECLK1 and the second clock signal ECLK2 are inverted, and their cycles are two horizontal time periods (2H). However, the first clock signal ECLK1 and the second clock signal ECLK2 may have pulse widths that are designed to slightly overlap each other in the interval where the voltage level is reversed for the operation margin.

[0107] In a section where the second clock signal ECLK2 is synchronized with the start signal EVST, the first transistor T1 is turned on to charge the Q1 node Q1 to the low potential voltage VEL.

[0108] In the interval where the first clock signal ECLK1 is at a low potential voltage, the second transistor T2 charges the Q2 node Q2 to the low potential voltage VEL. In response to the change in the voltage of the Q2 node Q2 caused by the first clock signal ECLK1, the Q1 node Q1 is bootstrapped to a bootstrap voltage (Vboot). As a result, the pull-up transistor T6 charges the output terminal Nout with the low potential voltage VEL as the on-voltage, and the output terminal Nout outputs the emission signal EM(n) as the on-voltage level.

[0109] In the interval where the Q1 node Q1 is at the on voltage level, the fifth transistor T5 charges the QB1 node QB1 to the high potential voltage VEH as the off voltage, and the tenth transistor T10 charges the QB2 node QB2 to the high potential voltage VEH as the off voltage. As a result, in the interval where the Q1 node Q1 is at the on voltage level, the pull-down transistor T7 is stably maintained in the off state.

[0110] At the first moment t1, the fourth transistor T4 applies the low potential voltage VEL applied from the n-1th QB node (QB2 (n-1)) to the QP node QP. At the first moment t1, the second clock signal ECLK2 is inverted into a turn-on voltage, and therefore, the first transistor T1 is turned on and the start signal EVST is inverted into a high potential voltage VEH. At the first moment t1, the Q1 node Q1 increases to a cut-off voltage, and therefore, the second transistor T2 maintains a cut-off state until the fourth moment t4 when the start signal EVST and the second clock signal ECLK2 are synchronized. When the second transistor T2 is in the cut-off state, the Q2 node Q2 can maintain the voltage at a constant level without being affected by the voltage change of the first clock signal ECLK1. Therefore, the voltage of the Q1 node Q1 connected to the A2 node (A2) through the first capacitor C1 can be stably maintained as a cut-off voltage.

[0111] At the second moment T2, the eighth transistor T8 applies the low potential voltage of the first clock signal ECLK1 to the QB2 node QB2. In this case, in response to the voltage change of the QB2 node QB2, the QP node QP is bootstrapped to a lower voltage level. In response to the first clock signal ECLK1 of the low potential voltage VEL, the ninth transistor T9 applies the voltage of the QB2 node QB2 to the QB1 node QB1.

[0112] The pull-down transistor T7 charges the output terminal Nout to a cut-off voltage in response to the voltage of the QB1 node QB1.

[0113] At the second time t2, the third transistor T3 applies the high potential voltage VEH to the Q1 node Q1 in response to the voltage of the QB2 node QB2, thereby helping the Q1 node Q1 to maintain the off voltage.

[0114] At the third time t3, the first clock signal ECLK1 is inverted to the high potential voltage VEH. Due to the high potential voltage VEH of the first clock signal ECLK1 applied via the eighth transistor T8, the voltage of the QB node (QB2) becomes the high potential voltage VEH. At the fourth time T4, the start signal EVST and the second clock signal ECLK2 are synchronized to the on voltage again, and as a result, the low potential voltage VEL is applied to the Q1 node Q1.

[0115] As described above, the emission driver according to the present specification uses the first clock signal and the second clock signal (ECLK1, ECLK2) to control the Q1 node Q1 as the gate of the pull-up transistor. The second transistor T2 controls the Q1 node Q1 by applying a turn-on voltage to the Q2 node Q2 coupled to the Q1 node Q1 instead of directly applying a turn-on voltage to the Q1 node Q1. In addition, the gate of the second transistor T2 is connected to the Q1 node Q1. Therefore, in the interval in which the pull-up transistor is turned off, the second transistor T2 is turned off, and therefore, due to the first clock signal ECLK1, no direct coupling occurs at the gate voltage of the pull-up transistor.

[0116] When the Q node is charged with the first signal and the second signal applied alternately, a general gate driving circuit applies the clock signal directly to the Q node. Therefore, the pull-up transistor is in a cut-off state, and therefore, even when the turn-on voltage is not applied to the Q node, the Q node is bootstrapped according to the voltage change of the clock signal, and thus an undesired gate signal is output.

[0117] On the contrary, the gate drive circuit according to the present specification does not directly apply the conduction voltage to the Q1 node Q1 as the gate of the pull-up transistor, but instead applies the conduction voltage to the Q1 node Q1 via the Q2 node Q2, thereby turning off the second transistor T2 connecting the Q2 node Q2 and the Q1 node Q1 when the pull-up transistor is in the off state. Therefore, when the pull-up transistor is in the off state, the voltage of the Q2 node Q2 is stably maintained at the off voltage, so that the pull-up transistor is prevented from malfunctioning.

[0118] Fig. 9 Components similar to those described in the above embodiment are denoted by similar reference numerals, and detailed descriptions thereof will be omitted or brief descriptions thereof will be provided.

[0119] Reference Fig. 9 , the nth emission driver EMD[n] includes Q1 node charging units 100 , 200 , and 210 , a node controller 300 , a pull-up unit 400 , and a pull-down unit 500 .

[0120] The Q1 node charging units 100 , 200 , and 210 include first and second charging units 100 and 200 and a Q2 node controller 210 .

[0121] The first charging unit 100 (hereinafter, referred to as a first transistor) includes a gate receiving the second clock signal ECLK2 , a source connected to a start signal input terminal VP providing a start signal EVST, and a drain connected to a Q1 node Q1 .

[0122] The second charging unit 200 includes a second transistor T2 and a first capacitor C1. The second transistor T2 includes a gate connected to the Q1 node Q1, a source connected to the first clock signal input terminal CP1, and a drain connected to the Q2 node Q2. The first capacitor C1 is connected between the Q1 node Q1 and the Q2 node Q2.

[0123] The first capacitor C1 bootstraps the voltage of the Q2 node Q2 in response to the voltage of the Q1 node Q1. Alternatively, the first capacitor C1 bootstraps the voltage of the Q1 node Q1 in response to the voltage of the Q2 node Q2.

[0124] In the interval where the Q1 node Q1 has the cut-off voltage, the Q2 node Q2 node controller 210 applies a potential voltage to the Q2 node Q2. A high potential voltage VEH may be used as the potential voltage. The Q2 node controller 210 may be a transistor including a gate connected to the second clock signal input terminal CP2, a drain connected to the Q2 node Q2, and a source connected to an input terminal of the high potential voltage VEH. In this case, the Q2 node controller 210 may be a 2a transistor T2a.

[0125] Fig.10 is shown for driving Fig. 9 2 is a diagram showing the timing of the clock signal of the transmit driver and the voltage changes of the main nodes. Fig.10 The timing of the first clock signal and the second clock signal shown in Figure 8 The timings of the first clock signal and the second clock signal shown in FIG. 1 are the same, and therefore, the driving timing of the emission driver according to the second embodiment is the same as that of the first embodiment.

[0126] Reference Fig. 9 and Fig.10 , using the Q2 node controller 210 , the emission driver according to the second embodiment can maintain the voltage of the Q2 node Q2 at the high potential voltage VEH in the section where the Q1 node Q1 maintains the high potential voltage VEH.

[0127] The Q2 node controller 210 of the second embodiment is different from the Q2 node controller 210 of the first embodiment in the following features.

[0128] exist Figure 7 In the first embodiment shown in FIG. 1 , the Q2 node Q2 is connected to the Q1 node Q1 via the first capacitor C1. Figure 8 As shown in , in the interval where the voltage of the Q1 node Q1 increases, due to the coupling phenomenon, the voltage of the Q2 node Q2 may increase to a voltage level higher than the high potential voltage VEH. The difference Vds between the drain voltage and the source voltage in the second transistor T2 corresponds to the difference between the voltage of the Q2 node Q2 and the voltage of the first clock signal ECLK1. If the voltage of the Q2 node Q2 increases to be higher than the high potential voltage VEH, the Vds of the second transistor T2 increases in the interval where the first clock signal ECLK1 is the low potential voltage VEL. This causes the second transistor T2 to deteriorate faster.

[0129] In addition, in the interval where the voltage of the Q1 node Q1 increases, the Q2 node controller 210 of the second embodiment applies a potential voltage (e.g., a high potential voltage VEH) to the Q2 node Q2. Therefore, even if the voltage of the Q1 node Q1 increases, a coupling phenomenon does not occur in the Q2 node Q2, and the Q2 node Q2 can be maintained at the high potential voltage VEH. With this feature, the second embodiment can prevent the second transistor T2 from being rapidly degraded.

[0130] Fig.11 is a block diagram illustrating a configuration of an n-th emission driver according to a comparative example, Fig.12 It is an example Fig.11 A diagram of a circuit configuration of an n-th emission driver shown in FIG. Fig.13 and Fig.14 is shown for illustration and Fig.12 FIG. 1 is a diagram of a circuit configuration and a driving waveform showing the operating characteristics related to an inverter.

[0131] like Fig.11 As shown in , the nth emission driver according to the comparative example may include a Q1 node controller 133, a bootstrap inverter 135, a QB1 node controller 137, a first output buffer T6, a second output buffer T7, etc. Main components of the nth emission driver according to the comparative example will be briefly described below.

[0132] The Q node controller 133 controls the Q node Q based on the start signal EVST transmitted via the start signal input terminal. The bootstrap inverter 135 controls the QB2 node QB2 based on the potential of the Q node Q. The QB1 node controller 137 controls the QB1 node QB1 based on the potential of the QB2 node QB2. The first output buffer T6 is turned on based on the potential of the Q node Q, and outputs a logic low emission signal through the output terminal Nout of the emission driver. The second output buffer T7 is turned on based on the potential of the QB1 node QB1, and outputs a logic high emission signal through the output terminal Nout of the emission driver.

[0133] like Fig.11 and Fig.12 As illustrated in , the nth emission driver according to the comparative example includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor CQ, a second capacitor CQP and a third capacitor CQB.

[0134] The bootstrap inverter 135 includes a fourth transistor T4, an eighth transistor T8, a tenth transistor T10, and a second capacitor CQP. The bootstrap inverter 135 inverts a signal or potential input based on the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, and the second capacitor CQP, and outputs the inverted signal or potential. Other devices except the devices included in the bootstrap inverter 135 correspond to devices related to the Q node controller 133, the QB1 node controller 137, the first output buffer T6, and the second output buffer T7.

[0135] In the following, refer to Fig.13 and Fig.14 , will be further described Fig.12 The bootstrap inverter 135 shown in FIG. 1 includes a fourth transistor T4 , an eighth transistor T8 , a tenth transistor T10 and a second capacitor CQP.

[0136] The fourth transistor T4 includes a gate connected to the second clock signal input terminal, a first electrode connected to the low potential voltage input terminal, and a second electrode connected to the QP node QP. The fourth transistor T4 is turned on in response to the second clock signal ECLK2 transmitted via the second clock signal input terminal. When the fourth transistor T4 is turned on, the low potential voltage VEL transmitted through the low potential voltage input terminal is applied to the QP node QP.

[0137] The tenth transistor T10 includes a gate connected to the Q node Q, a first electrode connected to the second clock signal input terminal, and a second electrode connected to the QP node QP. The tenth transistor T10 is turned on in response to a logic low potential q of the Q node Q. When the tenth transistor T10 is turned on, the second clock signal ECLK2 transmitted through the second clock signal input terminal is applied to the QP node QP.

[0138] The eighth transistor T8 includes a gate connected to the QP node QP, a first electrode connected to the first clock signal input terminal, and a second electrode connected to the QB2 node QB2. The eighth transistor T8 is turned on in response to the potential Qp of the QP node QP. When the eighth transistor T8 is turned on, the first clock signal ECLK1 transmitted through the first clock signal input terminal is applied to the QB2 node QB2.

[0139] The second capacitor CQP includes one end connected to the QP node QP and the other end connected to the QB2 node QB2. The second capacitor CQP functions as a bootstrap capacitor that allows one of two side terminals to have a different potential.

[0140] The bootstrap inverter of the comparative example receives the potential q of the Q node Q. For this reason, when the potential q of the Q node Q is logic low and logic high, the bootstrap inverter exhibits different operation and output characteristics as follows.

[0141] The tenth transistor T10 is kept in the on state in the interval in which the logic low potential is formed in the Q node Q. In this interval, the fourth transistor T4 is repeatedly turned on and off by the second clock signal ECLK2 changing between logic low and logic high.

[0142] Since the fourth transistor T4 is repeatedly turned on and off when the tenth transistor T10 is turned on, the potential of the QP node QP changes between logic high and logic low like the second clock signal ECLK2. On the other hand, due to the on / off of the eighth transistor T8, the QB2 node QB2 always maintains a logic high potential.

[0143] The tenth transistor T10 remains turned off in the interval in which the logic high potential is formed in the Q node Q. In this interval, the fourth transistor T4 is repeatedly turned on and off by the second clock signal ECLK2 changing between logic high and logic low.

[0144] Because the fourth transistor T4 is repeatedly turned on and off when the tenth transistor T10 is turned off, the QP node QP is maintained at the low potential voltage VEL, but due to the bootstrap effect of the second capacitor CQP, the voltage becomes lower than the low potential voltage. When the eighth transistor T8 remains turned on, the potential of the QB2 node QB2 becomes the same logic high level or logic low level as the first clock signal ECLK1. In this case, the voltage of the QB2 node QB2 is not bootstrapped to a low potential voltage by the second capacitor CQP, and therefore, the voltage of the QP node QP becomes lower. Therefore, the first clock signal ECLK1 can be transmitted to the QB2 node QB2 via the eighth transistor T8.

[0145] In this way, like an inverter circuit, the comparative example inverts the potential q of the Q node Q, thereby forming a potential to be applied to the QB2 node QB2. In addition, the potential Qb2 of the QB2 node QB2 is transmitted to the QB1 node QB1 via the turned-on ninth transistor T9. In addition, a circuit that enables a logic high output of the second output buffer T7 based on the potential formed in the QB1 node QB1 is realized.

[0146] Fig.15 is a block diagram illustrating a configuration of an n-th emission driver according to a third embodiment. Fig.16 It is an example Fig.15 Schematic diagram of the circuit configuration of the output buffer shown in FIG. Fig.17 is a diagram illustrating a detailed circuit configuration of an n-th emission driver according to a third embodiment. Fig.18 It is an example Fig.17 . The waveform diagram of the nth emission driver is shown in FIG. Fig.19 and Fig. 20 is an example used to illustrate Fig.17 FIG. 4 is a diagram of a circuit configuration and a driving waveform related to the operating characteristics of the QB2 node controller. Fig.21 is a diagram illustrating voltage waveforms measured at the QB1 node and the QB2 node according to the third embodiment.

[0147] like Fig.15 As illustrated in FIG. 1 , the nth emission driver according to the third embodiment of the present specification includes a Q node controller 133, a QB2 node controller 134, a QB1 node controller 137, a first output buffer T6, and second output buffers T7a and T7b. Main components of the nth emission driver according to the third embodiment of the present specification will be briefly described.

[0148] The Q node controller 133 controls the Q node Q based on the start signal EVST transmitted through the start signal input terminal. The QB2 node controller 134 controls the QB2 node QB2 based on the potential of the n-1th QB2 node (QB[n-1]). The QB1 node controller 137 controls the QB1 node QB1 based on the potential of the QB2 node QB2. The n-1th QB2 node QB2[n-1] is the QB2 node of the n-1th emission driver in the previous stage of the nth emission driver.

[0149] The first output buffer T6 is turned on based on the potential of the Q node Q, and outputs a logic low emission signal (first emission signal) through the output terminal Nout of the nth emission driver. The second output buffers T7a and T7b are turned on based on the potentials of different nodes, and output a logic high emission signal (second emission signal) through the output terminal Nout of the nth emission driver.

[0150] The second output buffers T7a and T7b include two transistors T7a and T7b in pairs. The two transistors T7a and T7b in pairs have a parallel connection structure in which the gates of the two transistors are connected to different nodes, and the first electrodes of the two transistors are only connected to each other and the second electrodes thereof are only connected to each other. The two transistors T7a and T7b in pairs are turned on in response to the potentials of different nodes, but output the same signal, and therefore, the two transistors T7a and T7b in pairs can be defined as a double buffer.

[0151] like Fig.16 , the second output buffers T7a and T7b include a pair of 2-a output buffers T7a and 2-2 output buffers T7b connected to different nodes. The 2-1 output buffer T7a operates in response to the potential of the QB1 node QB1. The 2-2 output buffer T7b operates in response to the potential of the QB2 node QB2. Subsequently, the effect of connecting the paired 2-1 output buffers T7a and 2-2 output buffers T7b to different nodes will be described.

[0152] like Fig.17 and Fig.18 As illustrated in FIG, the nth emission driver according to the third embodiment includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a 7-1 transistor T7a, a 7-2 transistor T7b, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor CQ, a second capacitor CQP, and a third capacitor CQB.

[0153] The first transistor T1 includes a gate connected to the second clock signal input terminal, a first electrode connected to the start signal input terminal, and a second electrode connected to the Q node Q. The first transistor T1 is turned on based on the second clock signal ECLK2 transmitted through the second clock signal input terminal. When the first transistor T1 is turned on, the start signal EVST is applied to the Q node Q. In this case, the Q node Q is charged by the start signal EVST.

[0154] The second transistor T2 includes a gate connected to the Q node Q, a first electrode connected to the first clock signal input terminal, and a second electrode connected to one end of the first capacitor CQ. The second transistor T2 is turned on based on the potential q of the Q node Q. When the second transistor T2 is turned on, the first clock signal ECLK1 is applied to one end of the first capacitor CQ. In this case, the first capacitor CQ is charged with a voltage for maintaining the Q node Q in a specific state.

[0155] The third transistor T3 includes a gate connected to the QB2 node QB2, a first electrode connected to the Q node Q, and a second electrode connected to the high potential voltage input terminal. The third transistor T3 is turned on in response to the potential Qb2 of the QB2 node QB2. When the third transistor T3 is turned on, the high potential voltage VEH is applied to the Q node Q. In this case, the Q node Q is discharged by the high potential voltage VEH.

[0156] The fourth transistor T4 includes a gate connected to the second clock signal input terminal, a first electrode connected to the n-1th QB2 node QB2[n-1], and a second electrode connected to the QP node QP. The fourth transistor T4 is turned on based on the second clock signal ECLK2 transmitted through the second clock signal input terminal. When the fourth transistor T4 is turned on, the potential Qb2[n-1] of the n-1th QB2 node QB2[n-1] is applied to the QP node QP. The n-1th QB2 node QB2[n-1] is the QB2 node of the n-1th emission driver in the previous stage of the nth emission driver.

[0157] The fifth transistor T5 includes a gate connected to the Q node Q, a first electrode connected to the QB2 node QB2, and a second electrode connected to the high potential voltage VEH input terminal. The fifth transistor T5 is turned on based on the potential q of the Q node Q. When the fifth transistor T5 is turned on, a high potential voltage is applied to the QB2 node QB2. In this case, the QB2 node QB2 is discharged by the high potential voltage.

[0158] The sixth transistor T6 includes a gate connected to the Q node Q, a first electrode connected to the low potential voltage input terminal, and a second electrode connected to the output terminal Nout of the nth emission driver. The sixth transistor T6 is turned on based on the potential q of the Q node Q. When the sixth transistor T6 is turned on, the low potential voltage VEL is applied to the output terminal Nout of the nth emission driver. In this case, the nth emission driver outputs a logic low emission signal through its own output terminal Nout.

[0159] The 7-1 transistor T7a includes a gate connected to the QB1 node QB1, a first electrode connected to the output terminal Nout of the nth emission driver, and a second electrode connected to the high potential voltage input terminal. The 7-1 transistor T7a is turned on based on the potential of the QB1 node QB1. When the 7-1 transistor T7a is turned on, the high potential voltage is applied to the output terminal Nout of the nth emission driver. In this case, the nth emission driver outputs a logic high emission signal through the output terminal Nout.

[0160] The 7-2 transistor T7b includes a gate connected to the QB2 node QB2, a first electrode connected to the output terminal Nout of the nth emission driver, and a second electrode connected to the high potential voltage input terminal. The 7-2 transistor T7b is turned on based on the potential of the nth emission driver. When the 7-2 transistor T7b is turned on, the high potential voltage is applied to the output terminal Nout of the nth emission driver. In this case, the nth emission driver outputs a logic high emission signal through its own output terminal Nout.

[0161] The eighth transistor T8 includes a gate connected to the QP node QP, a first electrode connected to the first clock signal input terminal, and a second electrode connected to the QB2 node QB2. The eighth transistor T8 is turned on based on the potential Qb2[n-1] of the n-1th QB2 node QB2[n-1] transmitted through the fourth transistor T4. When the eighth transistor T8 is turned on, the first clock signal ECLK1 is applied to the QB2 node QB2.

[0162] The ninth transistor T9 includes a gate connected to the first clock signal input terminal, a first electrode connected to the QB2 node QB2, and a second electrode connected to the QB1 node QB1. The ninth transistor T9 is turned on based on the first clock signal ECLK1 transmitted through the first clock signal input terminal. When the ninth transistor T9 is turned on, the QB2 node QB2 and the QB1 node QB1 become states in which current can flow. In this case, the QB1 node QB1 is affected by the potential Qb2 formed in the QB2 node QB2.

[0163] The tenth transistor T10 includes a gate connected to the Q node Q, a first electrode connected to the QB1 node QB1, and a second electrode connected to the high potential voltage VEH input terminal. The tenth transistor T10 is turned on based on the potential of the Q node Q. When the tenth transistor T10 is turned on, a high potential voltage is applied to the QB1 node QB1. In this case, the QB1 node QB1 is discharged by the high potential voltage VEH.

[0164] The first capacitor CQ includes one end connected to the second electrode of the second transistor T2 and the other end connected to the Q node Q and the first electrode of the third transistor T3. After outputting a logic low emission signal, the first capacitor CQ maintains the potential of the Q node Q at a logic high level.

[0165] The second capacitor CQP includes one end connected to the QP node QP and the other end connected to the QB2 node QB2. The second capacitor CQP maintains the logic low potential of the first clock signal ECLK1 at a low level based on the potential Qb2[n-1] of the n-1th QB2 node (QB[n-1]).

[0166] The third capacitor CQB includes one end connected to the QB1 node QB1 and the other end connected to the high potential voltage input terminal. After outputting the logic high transmit signal, the third capacitor CQB maintains the potential of the QB1 node QB1 at a logic high level.

[0167] The Q node controller (Q Control) includes a first transistor T1, a second transistor T2, a third transistor T3 and a first capacitor CQ. The QB1 node controller QB1 Control includes a fifth transistor T5, a tenth transistor T10 and a third capacitor CQB. The QB2 node controller QB2 Control includes a fourth transistor T4, an eighth transistor T8 and a second capacitor CQP. The first output buffer T6 includes a sixth transistor T6. The second output buffers T7a and T7b include a 7-1 transistor T7a and a 7-2 transistor T7b.

[0168] In the following, refer to Figures 19 to 21 , will be further described Fig.17 The QB2 node controller 134 includes a fourth transistor T4, an eighth transistor T8 and a second capacitor CQP.

[0169] In the third embodiment, the QB2 node controller 134 receives the input of the potential Qb2[n-1] of the n-1th QB2 node QB2[n-1]. For this reason, when the potential Qb2[n-1] of the n-1th QB2 node QB2[n-1] is at a logic high level and a logic low level, the QB2 node controller 134 exhibits different operation and output characteristics, and these will be described below.

[0170] In a section where a logic high potential Qb2[n-1] is formed in the n-1th QB2 node QB2[n-1], the fourth transistor T4 is repeatedly turned on and off by the second clock signal ECLK2 changing between logic high and logic low.

[0171] When the fourth transistor T4 is turned on, the logic high potential Qb2[n-1] of the n-1th QB2 node QB2[n-1] is applied to the QP node QP. In this interval, the eighth transistor T8 is turned off due to the logic high potential Qb2[n-1] of the n-1th QB2 node QB2[n-1]. In this case, the fifth transistor T5 connected to the QB2 node QB2 together with the eighth transistor T8 is turned on due to the logic low potential q of the Q node Q, and therefore, the fifth transistor T5 is maintained at a logic high level.

[0172] In the interval where the logic low potential Qb2[n-1] is formed in the n-1th QB2 node QB2[n-1], the eighth transistor T8 is turned on due to the logic low potential Qb2[n-1] of the n-1th QB2 node QB2[n-1]. As the eighth transistor T8 is turned on, the first clock signal ECLK1 is applied to the QB2 node QB2, and the QB2 node QB2 synchronized with the first clock signal ECLK1 changes the potential of the QB node QB to be lower than the previously formed logic low level. In this case, the fifth transistor T5 connected to the QB2 node QB2 together with the eighth transistor T8 is turned off due to the logic high potential q of the Q node Q, and therefore, the fifth transistor T5 is maintained at a logic low level. When these operations are performed, the QB2 node QB2 experiences the low potential voltage bootstrap effect of the second capacitor CQP, and therefore, the logic low potential of the second clock signal ECLK2 is more stably maintained.

[0173] As such, the above embodiment includes the QB2 node controller 134 that shifts the potential Qb2[n-1] of the n-1th QB2 node QB2[n-1] like a shift register and applies the potential Qb2[n-1] to the QB2 node QB2. In addition, the above embodiment enables a logic high output to be output through the 2-1 output buffer T7a based on the potential Qb1 of the QB1 node QB1, and enables a logic high output to be output through the 2-2 output buffer T7a based on the potential Qb2 of the QB2 node QB2.

[0174] like Fig.21As shown in , the potential Qb1 of the QB1 node QB1 is transmitted from the QB2 node QB2 through the turned-on ninth transistor T9, and therefore, the potential of the ninth transistor T9 drops. However, because the potential Qb2 of the QB2 node QB2 exists in the QB2 node QB2 without passing through the turned-on ninth transistor T9, there is no potential drop as large as the potential Qb1 of the QB1 node QB1. Therefore, the 2-2 output buffer T7b operates based on a potential that has not dropped compared to the 2-1 output buffer T7a. Therefore, in the above embodiment, even if the output characteristics of the 2-1 output buffer T7a deteriorate, the degradation can be compensated by the output of the 2-2 output buffer T7b.

[0175] The third embodiment includes second output buffers T7a and T7b based on at least two 7-1 transistors T7a and 7-2 transistors T7b. The second output buffer T7 according to the comparative example may include a second output buffer T7 with a slightly larger size (width and length or WL value) for stably outputting and maintaining a logic high signal. However, the second output buffers T7a and T7b according to the third embodiment include two transistors connected in parallel, and their size (width and length or WL value) may be smaller than that of the second output buffer T7.

[0176] Compared with the comparative example, the third embodiment can reduce the size (width and length or WL value) of the 7-1 transistor T7a and the 7-2 transistor T7b. In this case, the size reduction of the second output buffers T7a and T7b can be conducive to realizing a narrow frame of the display panel. In addition, the possibility of a reduction in the driving margin due to the shift of the threshold voltage of the second output buffers T7a and T7b can be eliminated, and therefore, even if the threshold voltage shift Vth Shift occurs in any one of the transistors in the second output buffers T7a and T7b, the threshold voltage shift of the other transistors can be offset and compensated.

[0177] In addition, in the emission driver based on the inverter circuit as in the comparative example, the fourth transistor T4 is repeatedly turned on and off in response to the second clock signal, so that charging and discharging occur in the second capacitor CQP affected by the fourth transistor T4 due to the constant voltage shift. However, in the emission driver based on the shift register as in the embodiment of the present disclosure, the second capacitor CQP is set to be unaffected by the second clock signal, so charging and discharging due to the voltage shift hardly occur. Therefore, since the charging and discharging of the second capacitor CQP of the present embodiment is not greatly affected by the load of the clock signal input terminal, the signal delay caused by the load of the clock signal input terminal can be solved.

[0178] Therefore, the present specification can improve the driving capability of the transistor and maintain the output characteristics of the transistor, and can provide a built-in gate drive circuit that is conducive to achieving a narrow frame. In addition, even if the threshold voltage of the transistor used as an output buffer shifts, the present specification can compensate for the threshold voltage and thus maintain a proper output, thereby improving driving reliability.

[0179] Fig. 22 1 is a block diagram illustrating an n-th emission driver according to a fourth embodiment of the present specification. The n-th emission driver EMD[n] will be described by taking an example. Fig. 22 .

[0180] Reference Fig. 22 The nth emission driver EMD[n] includes a pull-up unit 400, a pull-down unit 500, a Q-node controller 133, a Q-node stabilizer 144, a QB-node stabilizer 155, and an inverter 135. The Q-node stabilizer 144 and the QB-node stabilizer 155 may be omitted.

[0181] The pull-up unit 400 outputs the nth emission signal EM(n) in response to the voltage of the Q node Q, and the pull-down unit 500 controls the nth emission signal EM(n) to be a cut-off voltage in response to the voltage of at least one of the Q node Q or the QB node QB.

[0182] The Q-node controller 133 is a component for charging or discharging the Q-node Q, and the Q-node controller 133 applies a turn-on voltage to the Q-node Q by using the n-1th emission signal EM(n-1) as a start signal, and the n-1th emission signal EM(n-1) is an output signal of the n-1th emission driver EMD[n-1].

[0183] The inverter 135 receives a signal from the Q node controller 133, for example, a signal applied to the Q node Q, inverts the received signal and outputs the inverted signal to the QB node QB. When the Q node controller 133 outputs an on voltage to the Q node Q, the inverter 135 outputs an off voltage to the QB node QB. In addition, when the Q node controller 133 outputs an off voltage to the Q node Q, the inverter 135 outputs an on voltage to the QB node QB. The inverter 135 includes: a QB' node, which is controlled by the voltage of the Q node Q; and a QB' node, which is controlled by the voltage of the Q node Q to output a voltage to the QB node QB. The inverter 135 includes: a transistor having a gate connected to the Q' node, a drain connected to the QB' node, and a source to which an emission signal is applied; and a capacitor having one electrode connected to the gate and drain of the transistor. When the Q' node has a turn-on voltage, the emission low voltage of the emission clock signal is applied to the QB' node through the transistor. The voltage applied to the Q' node is controlled by the Q node to constantly swing between a logic high voltage and a logic low voltage, while the voltage applied to the QB' node remains at a logic high voltage. Therefore, the capacitor connected to the Q' node and the QB' node included in the inverter of the emission driver can be constantly charged and discharged. Therefore, in the interval in which the emission driver needs to stably output the gate high voltage, the voltage jitters. In addition, as the resolution of the display panel 10 increases, the load of the emission clock signal increases, and the emission clock signal is distorted due to the constant charging and discharging of the capacitor. In addition, when the emission clock signal line is formed in the display panel, if the display panel has a high resolution, the load of the emission clock signal will change greatly. Below, another embodiment of the present specification for solving this problem will be described.

[0184] When the nth emission signal EM(n) outputs a turn-off voltage, the Q-node stabilizer 144 applies a high potential voltage VEH to the Q-node Q, thereby stably maintaining the turn-off voltage.

[0185] When the nth emission signal EM(n) outputs a turn-on voltage, the QB node stabilizer 155 applies a high potential voltage VEH to the QB node QB, thereby stably maintaining the turn-off voltage. In this case, the high potential voltage VEH may be a logic high voltage VH.

[0186] Fig.23 1 is a block diagram illustrating an n-th emission driver according to a fifth embodiment of the present specification. The n-th emission driver EMD[n] constituting the n-th emission driver will be described by taking an example. Fig.23 .

[0187] Reference Fig.23The nth emission driver EMD[n] includes a pull-up unit 400, a pull-down unit 500, a Q-node controller 133, a Q-node stabilizer 144, a QB-node stabilizer 155, and a QB-node regulator 17. The Q-node stabilizer 144 and the QB-node stabilizer 155 may be omitted.

[0188] The pull-up unit 400 outputs the nth emission signal EM(n) in response to the voltage of the Q node Q, and the pull-down unit 500 controls the nth emission signal EM(n) to be a cut-off voltage in response to the voltage of at least one of the Q node Q or the QB node QB. For example, the pull-up unit 400 may include a single transistor or may include a transistor and a capacitor. The pull-down unit 500 may include a single transistor, may include a transistor and a capacitor, or may include a plurality of transistors and capacitors. In this case, the gate of the transistor included in the pull-up unit 400 is connected to the Q node Q, and the gate of the transistor included in the pull-down unit 500 is connected to the QB node QB.

[0189] The Q node controller 133 is a component for charging or discharging the Q node Q. The Q node controller 133 applies a turn-on voltage to the Q node Q using the n-1th emission signal EM(n-1) which is an output signal of the n-1th emission driver EMD[n-1].

[0190] The QB node regulator 17 receives a signal applied to the QB' node QB' (n-1) of the n-1th emission driver EMD [n-1], shifts the signal by as much time as the period of the emission clock signal, and outputs the signal to the QB' node. The QB node regulator 17 may include a shift register. When the QB' node QB' (n-1) of the n-1th emission driver maintains a cut-off voltage, the QB node regulator 17 discharges the QB' node and the QB node (QB) to the cut-off voltage. When the QB' node QB' (n-1) of the n-1th emission driver periodically changes between the cut-off voltage and the on-voltage, the QB node regulator 17 applies the voltage of the QB' node QB' (n-1) of the n-1th emission driver EMD [n-1] to the QB' node. In this case, the QB' node is a node included in the QB node regulator 17, and the QB' node and the QB node QB are connected to each other via a transistor. Similarly, the QB' node QB'(n-1) of the n-1th emission driver EMD[n-1] is a node included in the QB node regulator 17 constituting the previous stage. Since the QB node regulator 17 is configured, the problem of triggering due to the increase in the load of the emission clock signal can be solved, and the occurrence of distortion of the emission clock signal caused by constant charging and discharging of the capacitor can be reduced.

[0191] When the n-th emission signal EM(n) outputs a turn-off voltage, the Q-node stabilizer 144 applies a high potential voltage VEH to the Q-node, thereby stably maintaining the turn-off voltage.

[0192] When the nth emission signal EM(n) outputs a turn-on voltage, the QB node stabilizer 155 applies a high potential voltage VEH to the QB node QB, thereby stably maintaining the turn-off voltage. In this case, the high potential voltage VEH may be a logic high voltage VH.

[0193] According to the fifth embodiment of the present specification, the QB node is not inverted into a structure for controlling the QB node included in the emission driver. Instead, a QB node regulator is additionally configured to control the QB node and apply a voltage to the QB node. Therefore, the influence of the increase in the load of the emission clock signal can be reduced. In addition, because an inverter is not configured, the problem of voltage jitter in the interval where the emission driver needs to stably output the gate high voltage can be solved.

[0194] Fig.24 It shows Fig. 22 and Fig.23 A graph of the output waveform of the transmit driver is shown in FIG.

[0195] Reference Fig.24 ,from Fig. 22 The emission signal output by the emission driver is greatly distorted not only in the transient interval where the emission signal changes from a logic low voltage to a logic high voltage, but also in the normal interval where the emission signal remains at a logic high voltage. Fig. 22 The transmit signal output by the transmit driver is compared to that from another embodiment of the present specification Fig.23 The transmit driver outputs a transmit signal with less distortion. Fig. 22 and Fig.23 The emission signal EM output by the emission driver is a -9V on-voltage and a +7.5V off-voltage. Fig. 22 The emission signal output by the emission driver increases to a turn-on voltage of -10V and decreases to a turn-off voltage of +5V in the transient interval. Therefore, it is found that Fig.23 The transmit driver is effective in outputting a constant cutoff voltage.

[0196] Fig.25 1 is a circuit diagram of a QB node regulator according to a first embodiment of the present specification. The QB node regulator included in the nth emission driver EMD[n] will be described by taking an example. Fig.25 .

[0197] The QB node regulator 17-1 includes a Q'(n) node controller, a QB'(n) node controller, a QB(n) node controller, a QB(n) keeper, a QB'(n) keeper, and a capacitor CQ. Among them, the Q'(n) node controller, the QB'(n) node controller, and the QB(n) node controller may be collectively referred to as a QB(n) node charging unit.

[0198] The Q'(n) node regulator 17-1 is configured as a first transistor T1. The first transistor T1 includes a gate connected to the second clock signal line to which the second clock signal ECLK2 is input, a source connected to the n-1th QB' node QB'(n-1), and a drain connected to the n-th Q' node Q'(n). In the interval where the second clock signal ECLK2 and the n-1th QB' node QB'(n-1) have a turn-on voltage, the first transistor T1 charges the n-th Q' node Q'(n) to a low potential voltage VEL as a turn-on voltage.

[0199] The QB'(n) node controller is configured as a second transistor T2. The second transistor T2 includes a gate connected to the nth Q' node Q'(n), a source connected to the first clock signal line to which the first clock signal ECLK1 is input, and a drain connected to the nth QB' node QB'(n). When the nth Q' node Q'(n) has a turn-on voltage, the second transistor T2 applies the first clock signal ECLK1 to the nth QB' node QB'(n).

[0200] Two electrodes of the capacitor CQ' are connected to the nth Q' node Q'(n) and the nth QB' node QB'(n), respectively. The capacitor CQ' bootstraps the nth Q' node Q'(n) according to a voltage change of the nth QB' node QB'(n).

[0201] The QB(n) node controller is configured as a third transistor T3. The third transistor T3 includes a gate connected to the first clock signal line to which the first clock signal ECLK1 is input, a source connected to the nth QB' node QB'(n), and a drain connected to the nth QB node QB(n). The third transistor T3 controls the short circuit of the nth QB' node QB'(n) and the nth QB node QB(n) according to the first clock signal ECLK1.

[0202] The QB(n) node holding unit is configured as a fifth transistor T5. The fifth transistor T5 includes a gate connected to the nth Q node Q(n), a source connected to the nth QB node QB(n), and a drain connected to an emission high voltage line to which a high potential voltage VEH is input. When the nth Q node Q(n) has a turn-on voltage, the fifth transistor T5 discharges the nth QB node QB(n) to the high potential voltage VEH.

[0203] The QB'(n) node holding unit is configured as a fourth transistor T4. The fourth transistor includes a gate connected to the nth Q node Q(n), a source connected to the nth QB node QB'(n), and a drain connected to the emission high voltage line to which the high potential voltage VEH is input. When the nth Q node Q(n) has a turn-on voltage, the fourth transistor T4 discharges the nth QB node QB'(n) to the high potential voltage VEH.

[0204] Since the QB node regulator 17-1 according to the first embodiment of the present specification implements a shift circuit to which the signal of the previous stage QB' node is input in a bootstrap manner, it is possible to reduce the influence of the load increase of the transmission clock signal and stably perform the output of the QB node. Subsequently, a driving method of the QB node regulator 17-1 according to the first embodiment of the present specification will be described.

[0205] Fig.29 is a driving waveform diagram of the QB node regulator according to the first embodiment of this specification. In addition, Fig.29 yes Fig.25 Driving waveform diagram.

[0206] Reference Fig.25 and Fig.29In the first time period P1, in which the signal of the n-1 QB' node QB'(n-1) which is the QB' node in the previous stage EMD[n-1] is maintained at the logic high voltage VH, the first transistor T1 is periodically turned on by the second clock signal ECLK2 and applies the logic high voltage VH to the n-th Q' node Q'(n). Therefore, during the first time period P1, the first transistor T1 turns off the second transistor T2. In addition, in the first time period P1, the Q node controller 133 applies the turn-on voltage to the n-th Q node Q(n) according to the turn-on voltage alternately applied by the second clock signal ECLK2 and the first clock signal ECLK1, and therefore, the pull-up unit 400 is turned on. Since the pull-down unit 500 is turned off in the first time period P1, the n-th QB node QB(n) maintains the logic high voltage VH. Since the logic low voltage VL is applied to the nth Q node Q(n) in the first period P1, the fourth transistor T4 and the fifth transistor T5 are turned on, and the nth QB' node QB'(n) and the nth QB node QB(n) are discharged by the high potential voltage VEH. The second transistor T2 remains turned off for most of the first period P1, and therefore, by applying the high potential voltage VEH to the nth QB' node QB'(n) and the nth QB node QB(n) via the turned-on fourth transistor T4 and the fifth transistor T5, the nth QB' node QB'(n) and the nth QB node QB(n) can be prevented from floating for a long time, thereby stabilizing the emission driver.

[0207] In the 2-1 time period P2-1 during the second time period P2 in which the signal of the n-1th QB' node QB'(n-1) which is the QB' node in the previous stage EMD[n-1] periodically changes, the first transistor T1 is turned on by the second clock signal ECLK2 synchronized with the n-1th QB' node QB'(n-1) and pre-charges the nth Q' node Q'(n).

[0208] In the 2-2 period P2-2, if the second transistor T2 is turned on due to the nth Q' node Q'(n) pre-charged with the logic low voltage VL, the first clock signal ECLK1 is transmitted to the nth QB' node QB'(n). In this case, since the first clock signal ECLK1 is the logic low voltage VL and the second clock signal ECLK2 is the logic high voltage VH, the first transistor T1 is turned off. Due to the bootstrap effect of the capacitor CQ', the voltage change of the nth QB' node QB'(n) reduces the voltage of the nth Q' node Q'(n) to a voltage lower than the logic low voltage VL. In addition, since the third transistor T3 is turned on due to the first clock signal ECLK as the logic low voltage VL, the nth QB node QB(n) has the logic low voltage VL. In this case, a voltage lower than the logic low voltage VL is applied to the gate of the second transistor T2 due to a bootstrap effect, and thus the second transistor T2 can stably apply the first clock signal ECLK1 to the nth QB' node QB'(n).

[0209] In the 2-3 period P2-3, the second clock signal ECLK2 becomes the logic low voltage VL again, and the logic low voltage VL of the n-1 QB' node QB' (n-1) is applied to the n Q' node Q' (n) via the first transistor T1 turned on by the second clock signal ECLK2. The logic high voltage VH of the first clock signal ECLK1 is applied to the n QB' node QB' (n) via the second transistor T2 turned on by the n Q' node Q' (n). In this case, the third transistor T3 is turned off by the first clock signal ECLK1, and therefore, the n Qb node QB (n) maintains the voltage applied in the 2-2 period P2-2. In the 2-3 period P2-3, the voltage of the n QB node QB (n) is the logic low voltage VL.

[0210] In the 2-4 period P2-4, the second clock signal ECLK2 has a logic high voltage VH and the first clock signal ECLK1 has a logic low voltage VL, therefore, the first transistor T1 is turned off and the nth Q' node Q'(n) maintains the logic low voltage VL and the second transistor T2 is turned on. Because the first clock signal ECLK1 is applied to the nth QB' node QB'(n) via the turned-on second transistor T2, the nth Q' node Q'(n) has a voltage lower than the logic low voltage VL due to the bootstrap effect of the capacitor CQ'. Therefore, the second transistor T2 can be stably turned on and apply a complete logic low voltage to the nth QB' node QB'(n).

[0211] Since the nth Q node Q(n) maintains the logic high voltage VH in the second period P2, the fourth transistor T4 and the fifth transistor T5 remain turned off.

[0212] Therefore, the QB node regulator 17-1 according to the first embodiment of the present specification receives a signal from the n-1th QB' node QB'(n-1), shifts the signal by as much as the period of the emission control signal, and outputs the signal to the nth QB' node QB'(n). In addition, since the logic low voltage VL is applied to the nth QB node QB(n) by the third transistor T3 connected between the nth QB' node QB'(n) and the nth QB node QB(n), the pull-down unit 500 can be turned on and can output the nth emission signal EM(n) of the gate-off voltage. Therefore, according to the first embodiment of the present specification, the driving reliability of the emission driver including the QB node regulator can be improved.

[0213] Fig.26 is a circuit diagram of a QB node regulator according to a second embodiment of the present specification. Fig.26 1 is a circuit diagram in which a sixth transistor T6 is added to the QB node regulator 17-1 according to the first embodiment of the present specification. Fig.26 , the same components have the same effects and redundant descriptions will be omitted or briefly provided.

[0214] The QB node regulator 17-2 includes a Q'(n) node controller, a QB'(n) node controller, a QB(n) node controller, a QB(n) keeper, a QB'(n) keeper, a Q'(n) keeper, and a capacitor CQ'. Among them, the Q'(n) node controller, the QB'(n) node controller, and the QB(n) node controller may be combined and referred to as a QB(n) node charging unit.

[0215] The Q'(n) node controller is configured as a first transistor T1. The first transistor T1 includes a gate connected to the n-1th QB' node QB'(n-1), a source connected to the emission low voltage line to which the low potential voltage VEL is input, and a drain connected to the n-th Q' node Q'(n). In the interval where the voltage of the n-1th QB' node QB'(n-1) and the low potential voltage VEL are the turn-on voltages, the first transistor T1 charges the n-th Q' node Q'(n) to the low potential voltage VEL.

[0216] The QB'(n) node controller is configured as a second transistor T2. The second transistor T2 includes a gate connected to the nth Q' node Q'(n), a source connected to the first clock signal line to which the first clock signal ECLK1 is input, and a drain connected to the nth QB' node QB'(n). When the voltage of the nth Q' node Q'(n) is a turn-on voltage, the second transistor T2 applies the first clock signal ECLK1 to the nth QB' node QB'(n).

[0217] Two electrodes of the capacitor CQ' are connected to the nth Q' node Q'(n) and the nth QB' node QB'(n), respectively. The capacitor CQ' bootstraps the nth Q' node Q'(n) according to a voltage change of the nth QB' node QB'(n).

[0218] The QB(n) node controller is configured as a third transistor T3. The third transistor T3 includes a gate connected to the first clock signal line to which the first clock signal ECLK1 is input, a source connected to the nth QB' node QB'(n), and a drain connected to the nth QB node QB(n).

[0219] The QB(n) node holding unit is configured as a fifth transistor T5. The fifth transistor T5 includes a gate connected to the nth Q node Q(n), a source connected to the nth QB node QB(n), and a drain connected to an emission high voltage line to which a high potential voltage VEH is input. When the voltage of the nth Q node Q(n) is a turn-on voltage, the fifth transistor T5 discharges the nth QB node QB(n) to the high potential voltage VEH.

[0220] The QB'(n) node holding unit is configured as a fourth transistor T4. The fourth transistor T4 includes a gate connected to the nth Q node Q(n), a source connected to the nth QB' node QB'(n), and a drain connected to the emission high voltage line to which the high potential voltage VEH is input. When the voltage of the nth Q node Q(n) is the on-voltage, the fourth transistor T4 discharges the nth QB' node QB'(n) to the high potential voltage VEH.

[0221] The Q'(n) node holding unit is configured as a sixth transistor T6. The sixth transistor T6 includes a gate connected to the nth Q node Q(n), a source connected to the nth Q' node Q'(n), and a drain connected to the emission high voltage line to which the high potential voltage VEH is input. When the voltage of the nth Q node Q(n) is the on-voltage, the sixth transistor T6, together with the fourth transistor T4 and the fifth transistor T5, discharges the nth Q' node Q'(n) to the high potential voltage VEH.

[0222] By applying the high potential voltage VEH to the nth Q' node Q'(n) through the sixth transistor T6, the QB node regulator 17-2 according to the second embodiment of the present specification can prevent the second transistor from being turned off due to the nth Q' node Q'(n) dropping to a logic low voltage due to the first transistor T1 being kept turned off for a long time.

[0223] As a driving waveform diagram of the QB node regulator 17-2 according to the second embodiment of the present specification, the following diagram of the QB node regulator according to the embodiment of the present specification can be applied: Fig.29The same driving waveform as in .

[0224] Fig. 27 is a circuit diagram of a QB node regulator according to a third embodiment of the present specification. Fig. 27 1 is a circuit diagram in which the connection structure of the third transistor T3 in the QB node regulator 17-1 according to the first embodiment of the present specification is changed. Fig. 27 , the same components have the same effects, and redundant descriptions will be omitted or briefly provided.

[0225] The QB node regulator 17-3 includes a Q'(n) node controller, a QB'(n) node controller, a QB(n) node controller, a QB(n) keeper, a QB'(n) keeper, and a capacitor CQ'. Among them, the Q'(n) node controller, the QB'(n) node controller, and the QB(n) node controller may be combined and referred to as a QB(n) node charging unit.

[0226] The Q'(n) node controller is configured as a first transistor T1. The first transistor T1 includes a gate connected to the second clock signal line to which the second clock signal ECLK2 is input, a source connected to the n-1th QB' node QB'(n-1), and a drain connected to the n-1th Q' node Q'(n). In the interval where the second clock signal ECLK2 and the n-1th QB' node QB'(n-1) have a turn-on voltage, the first transistor T1 charges the n-th Q' node Q'(n) to a low potential voltage VEL.

[0227] The QB'(n) node controller is configured as a second transistor T2. The second transistor T2 includes a gate connected to the nth Q' node Q'(n), a source connected to the first clock signal line to which the first clock signal ECLK1 is input, and a drain connected to the nth QB' node QB'(n). When the voltage of the nth Q' node Q'(n) is a turn-on voltage, the second transistor T2 applies the first clock signal ECLK1 to the nth QB' node QB'(n).

[0228] Two electrodes of the capacitor CQ' are connected to the nth Q' node Q'(n) and the nth QB' node QB'(n), respectively. The capacitor CQ' bootstraps the nth Q' node Q'(n) according to a voltage change of the nth QB' node QB'(n).

[0229] The QB(n) node controller is configured as a third transistor T3. The third transistor T3 includes a gate connected to the nth QB' node QB'(n), a source connected to an emission low voltage line to which a low potential voltage VEL is input, and a drain connected to the nth QB node QB(n). When the voltage of the nth QB' node QB'(n) is a logic low voltage VL, the third transistor T3 is turned on and the low potential voltage VEL is applied to the nth QB node QB(n). In addition, when the nth QB' node QB'(n) has a logic high voltage VH, the third transistor T3 is turned off, so that the nth QB node QB(n) can maintain the previously applied voltage.

[0230] The QB(n) node holding unit is configured as a fifth transistor T5. The fifth transistor T5 includes a gate connected to the nth Q node Q(n), a source connected to the nth QB node QB(n), and a drain connected to an emission high voltage line to which a high potential voltage VEH is input. When the voltage of the nth Q node Q(n) is a turn-on voltage, the fifth transistor T5 discharges the nth QB node QB(n) to the high potential voltage VEH.

[0231] The QB'(n) node holding unit is configured as a fourth transistor T4. The fourth transistor T4 includes a gate connected to the nth Q node Q(n), a source connected to the nth QB' node QB'(n), and a drain connected to the emission high voltage line to which the high potential voltage VEH is input. When the voltage of the nth Q node Q(n) is the on-voltage, the fourth transistor T4 discharges the nth QB' node QB'(n) to the high potential voltage VEH.

[0232] The QB node regulator 17 - 3 according to the third embodiment of the present specification implements a shift circuit receiving input of a signal from a previous stage QB′ node in a bootstrap manner, thereby being able to reduce the influence of load increase of a transmission clock signal and stably perform output of the QB node.

[0233] As a driving waveform diagram of the QB node regulator 17-3 according to the third embodiment of the present specification, the following waveform diagram of the QB node regulator according to the embodiment can be applied: Fig.29 The driving waveform diagram is shown in FIG.

[0234] Fig.28 is a circuit diagram of a QB node regulator according to a fourth embodiment of the present specification. Fig.28 1 is a circuit diagram in which the connection structure of the third transistor T3 in the QB node regulator 17-1 according to the first embodiment of the present specification is changed and a sixth transistor T6 is added. Fig. 27 , the same components have the same effects, and redundant descriptions will be omitted or briefly provided.

[0235] The QB node regulator 17-4 includes a Q'(n) node controller, a QB'(n) node controller, a QB(n) node controller, a QB(n) keeper, a QB'(n) keeper, a Q'(n) keeper, and a capacitor CQ'. Among them, the Q'(n) node controller, the QB'(n) node controller, and the QB(n) node controller may be combined and referred to as a QB(n) node charging unit.

[0236] The Q'(n) node controller is configured as a first transistor T1. The first transistor T1 includes a gate connected to the second clock signal line to which the second clock signal ECLK2 is input, a source connected to the n-1th QB' node QB'(n-1), and a drain connected to the n-1th Q' node Q'(n). In the interval where the second clock signal ECLK2 and the n-1th QB' node QB'(n-1) have a turn-on voltage, the first transistor T1 charges the n-th Q' node Q'(n) to a low potential voltage VEL.

[0237] The QB'(n) node controller is configured as a second transistor T2. The second transistor T2 includes a gate connected to the nth Q' node Q'(n), a source connected to the first clock signal line to which the first clock signal ECLK1 is input, and a drain connected to the nth QB' node QB'(n). When the voltage of the nth Q' node Q'(n) is a turn-on voltage, the second transistor T2 applies the first clock signal ECLK1 to the nth QB' node QB'(n).

[0238] Two electrodes of the capacitor CQ' are connected to the nth Q' node Q'(n) and the nth QB' node QB'(n), respectively. The capacitor CQ' bootstraps the nth Q' node Q'(n) according to a voltage change of the nth QB' node QB'(n).

[0239] The QB(n) node controller is configured as a third transistor T3. The third transistor T3 includes a gate connected to the nth QB' node QB'(n), a source connected to an emission low voltage line to which a low potential voltage VEL is input, and a drain connected to the nth QB' node QB'(n). When the voltage of the QB' node QB'(n) is a logic low voltage, the third transistor T3 is turned on and the low potential voltage VEL is applied to the nth QB node QB(n). In addition, when the voltage of the nth QB' node QB'(n) is a logic high voltage VH, the third transistor T3 is turned off, so that the nth QB node QB(n) can maintain the previously applied voltage.

[0240] The QB(n) node holding unit is configured as a fifth transistor T5. The fifth transistor T5 includes a gate connected to the nth Q node Q(n), a source connected to the nth QB node QB(n), and a drain connected to the emission high voltage line to which the high potential voltage is input. When the voltage of the nth Q node Q(n) is the on-voltage, the fifth transistor T5 discharges the nth QB node QB(n) to the high potential voltage VEH.

[0241] The QB'(n) node holding unit is configured as a fourth transistor T4. The fourth transistor T4 includes a gate connected to the nth Q node Q(n), a source connected to the nth QB node QB'(n), and a drain connected to the emission high voltage line to which the high potential voltage VEH is input. When the voltage of the nth Q node Q(n) is the on-voltage, the fourth transistor T4 discharges the nth QB'node QB'(n) to the high potential voltage.

[0242] The Q'(n) node holding unit is configured as a sixth transistor T6. The sixth transistor includes a gate connected to the nth Q node Q(n), a source connected to the nth Q' node Q'(n), and a drain connected to an emission high voltage line to which a high potential voltage VEH is input. When the voltage of the nth Q node Q(n) is a turn-on voltage, the sixth transistor T6, together with the fourth transistor T4 and the fifth transistor T5, discharges the nth Q' node Q'(n) to a high potential voltage. Therefore, by applying the high potential voltage VEH to the nth Q' node Q'(n) through the sixth transistor T6, the second transistor can be prevented from being turned off because the nth Q' node Q'(n) drops to a logic low voltage due to the first transistor T1 being turned off for a long time.

[0243] The QB node regulator 17 - 4 according to the fourth embodiment of the present specification implements a shift circuit that receives an input of a signal from a previous stage QB′ node in a bootstrap manner, thereby being able to reduce the influence of a load increase of a transmission clock signal and stably perform output of the QB node.

[0244] As a driving waveform diagram of the QB node regulator 17-4 according to the fourth embodiment of the present specification, the following waveform diagram of the QB node regulator according to the embodiment can be applied. Fig.29 The same driving waveform as in .

[0245] The embodiments of the present specification can be described as follows.

[0246] An electroluminescent display according to the present specification includes: a pixel connected to a gate line; and a gate drive circuit that supplies a gate signal to at least one of the gate lines and includes a plurality of stages connected to each other in a cascade manner. The nth (n is a positive integer) stage of the gate drive circuit includes: a Q1 node charging unit that charges the Q1 node to a turn-on voltage using an inverted first clock signal and a second clock signal; and a pull-up transistor that applies a turn-on voltage to an output terminal in response to the Q1 node voltage. The Q1 node charging unit includes: a first charging unit that charges the Q1 node voltage to a turn-on voltage; and a second charging unit that charges a Q2 node connected to the Q1 node using the first clock signal in an interval in which the Q1 node has a turn-on voltage.

[0247] The first charging unit may be connected between the start signal input terminal and the Q1 node. The first charging unit may include a first transistor having a gate connected to the second clock signal input terminal.

[0248] The second charging unit may be connected between the first clock signal input terminal and the Q2 node. The second charging unit may include a second transistor having a gate connected to the Q1 node and a first capacitor connected between the Q1 node and the Q2 node.

[0249] The Q1 node charging unit may further include a Q2 node controller that applies a potential voltage to the Q2 node in a section in which the Q1 node has a cut-off voltage.

[0250] The Q2 node controller may include a gate connected to the second clock signal input terminal, a drain connected to the Q2 node, and a source connected to a high potential voltage input terminal.

[0251] The gate driving circuit may further include: a pull-down unit that controls the output terminal to output a cut-off voltage in response to a voltage of a QB1 node; and a node controller that controls the voltage of the QB1 node to a level opposite to a voltage level of the Q1 node.

[0252] The node controller may further include: a second capacitor connected between the QP node and the QB1 node; and a QP node controller connected to the QB2 node and the QP node of the n-1th stage.

[0253] The node controller may further include a QB2 node controller that applies a turn-on voltage of the first clock signal to the QB2 node in response to a voltage of the QP node.

[0254] The node controller may further include a QB1 node controller having a gate connected to a first clock signal input terminal to which the first clock signal is applied, the QB1 node controller applying a voltage of the QB2 node to the QB1 node.

[0255] The gating drive circuit according to the present specification includes a plurality of stages connected to each other in a cascade manner, and outputs a gating signal. Each of the plurality of stages outputs a gating signal using a first clock signal and a second clock signal. Among the plurality of stages, the nth (n is a natural number) stage includes: a pull-up transistor, which applies a turn-on voltage to an output terminal in response to a voltage at a Q1 node; a first capacitor, which is connected between the Q1 node and the Q2 node; a first transistor, which includes a gate connected to a second clock signal input terminal, a source connected to a start signal input terminal, and a drain connected to the Q1 node; and a second transistor, which includes a gate connected to the Q1 node, a source connected to the first clock signal input terminal, and a drain connected to the Q2 node.

[0256] The first clock signal and the second clock signal may be in anti-phase.

[0257] One cycle of each of the first clock signal and the second clock signal may be two horizontal time periods.

[0258] The start signal may be a strobe signal output from the n-1th stage.

[0259] The nth stage may further include a transistor including a drain connected to the Q2 node, a source connected to the high potential voltage input terminal, and a gate connected to the second clock signal input terminal.

[0260] The gate drive circuit according to an embodiment of the present disclosure includes: a first output buffer, which is turned on based on the potential of the Q node, thereby outputting a first emission signal; and a second output buffer, which is configured as a double buffer. The double buffer includes two transistors, and the two transistors include gates connected to different nodes and output the same second emission signal.

[0261] According to another feature of the present disclosure, the nth stage may further include: a QB2 node controller, which controls the QB2 node based on the potential of the Q node; and a QB1 node controller, which controls the QB1 node based on the potential of the QB2 node. The QB1 node and the QB2 node may have different potentials.

[0262] According to another feature of the present disclosure, the second output buffer may include: a 2-1 output buffer including a transistor operating in response to the potential of the QB1 node; and a 2-2 output buffer including a transistor operating in response to the potential of the QB2 node.

[0263] According to an embodiment of the present disclosure, a gating drive circuit may include: a Q-node controller, which controls the Q-node based on a start signal transmitted through a start signal line; a QB2-node controller, which controls the QB2-node based on the potential of the Q-node; a QB1-node controller, which controls the QB1-node based on the potential of the QB2-node; a first output buffer, which is turned on based on the potential of the Q-node to output a first emission signal; and a second output buffer, which has at least two transistors, which are turned on based on the potentials of different nodes to output a second emission signal.

[0264] According to another feature of the present disclosure, the first output buffer may output a logic low transmit signal, and the second output buffer may output a logic high transmit signal having a voltage higher than that of the logic low transmit signal.

[0265] According to another feature of the present disclosure, the second output buffer may have a parallel connection structure, in which the first electrodes of the at least two transistors are connected only to each other, the second electrodes of the at least two transistors are connected only to each other, and the gates of the at least two transistors are connected to different nodes.

[0266] According to another feature of the present disclosure, the second output buffer may include: a 2-1 output buffer including a transistor operating in response to a first potential; and a 2-2 output buffer including a transistor operating in response to a second potential different from the first potential.

[0267] According to another feature of the present disclosure, the first potential may be a potential of the QB1 node, and the second potential may be a potential of the QB2 node.

[0268] An electroluminescent display according to an embodiment of the present disclosure includes: a display panel that displays an image; and a gate drive circuit that includes a scan driver for outputting a scan signal to the display panel and an emission driver for outputting an emission signal to the display panel. Among the emission drivers, the nth (n is a positive number) emission driver includes: a first output buffer that is turned on based on the potential of the Q node, thereby outputting a first emission signal; and a second output buffer that includes a double buffer. The double buffer includes two transistors, and the two transistors include gates connected to different nodes and output the same second emission signal.

[0269] According to another feature of the present disclosure, the second output buffer may have a parallel connection structure in which the first electrodes of the at least two transistors are connected only to each other, the second electrodes thereof are connected only to each other, and the gates thereof are connected to different nodes.

[0270] According to another feature of the present disclosure, the second output buffer may include: a 2-1 output buffer including a transistor operating in response to a first potential; and a 2-2 output buffer including a transistor operating based on a second potential different from the first potential.

[0271] According to another feature of the present disclosure, the nth emission driver may further include: a QB2 node controller that controls the QB2 node based on the potential of the Q node; and a QB1 node controller that controls the QB1 node based on the potential of the QB2 node. The QB1 node and the QB2 node may have different potentials.

[0272] According to another feature of the present disclosure, the second output buffer may include: a 2-1 output buffer including a transistor operating based on the potential of the QB1 node; and a 2-2 output buffer including a transistor operating based on the potential of the QB2 node.

[0273] According to another feature of the present disclosure, the nth emission driver may include: a first transistor, the first transistor including a gate connected to a second clock signal line, a first electrode connected to a start signal line, and a second electrode connected to the Q node; a second transistor, the second transistor including a gate connected to the Q node and a first electrode connected to the first clock signal line; a third transistor, the third transistor including a gate connected to a QB2 node, a first electrode connected to the Q node, and a second electrode connected to a high potential voltage input terminal; a fourth transistor, the fourth transistor including a gate connected to the second clock signal line, a first electrode connected to an n-1QB2 node of the n-1th emission driver, and a second electrode connected to a QP node; a fifth transistor, the fifth transistor including a gate connected to the Q node, a first electrode connected to the QB2 node, and a second electrode connected to a high potential voltage input terminal; a sixth transistor, the sixth transistor including a gate connected to the Q node, a first electrode connected to a low potential voltage input terminal, and a second electrode connected to a QB2 node. a first electrode connected to the output terminal of the n-th emission driver, and a second electrode connected to the output terminal of the n-th emission driver; a 7-1 transistor, the 7-1 transistor including a gate connected to the QB1 node, a first electrode connected to the output terminal of the n-1 emission driver, and a second electrode connected to the high potential voltage input terminal; a 7-2 transistor, the 7-2 transistor including a gate connected to the QB2 node, a first electrode connected to the output terminal of the n-th emission driver, and a second electrode connected to the high potential voltage input terminal; an eighth transistor, the eighth transistor including a gate connected to the QP node, a first electrode connected to the first clock signal line, and a second electrode connected to the QB2 node; a ninth transistor, the ninth transistor including a gate connected to the first clock signal line, a first electrode connected to the QB2 node, and a second electrode connected to the QB1 node; and a tenth transistor, the tenth transistor including a gate connected to the Q node, a first electrode connected to the QB1 node, and a second electrode connected to the high potential voltage input terminal.

[0274] According to another feature of the present disclosure, the nth emission driver may further include: a first capacitor including one end connected to the second electrode of the second transistor and the other end connected to the Q node and the first electrode of the third transistor; a second capacitor including one end connected to the QP node and the other end connected to the QB2 node; and a third capacitor including one end connected to the QB1 node and the other end connected to the high potential voltage input terminal.

[0275] According to another feature of the present disclosure, the first transistor, the second transistor, the third transistor and the first capacitor may be included in a Q-node controller for controlling the Q-node; the fifth transistor, the tenth transistor and the third transistor may be included in a QB1-node controller for controlling the QB1-node; the fourth transistor, the eighth transistor and the second capacitor may be included in a QB2-node controller for controlling the QB2-node; the sixth capacitor may be included in a first output buffer for outputting a first transmission signal; and the 7-1 transistor and the 7-2 transistor may be included in a second output buffer for outputting a second transmission signal.

[0276] An electroluminescent display according to an embodiment of the present disclosure may include: a display panel; and a gate drive circuit, the gate drive circuit including a scan driver for outputting a scan signal to the display panel and an emission driver for outputting an emission signal to the display panel. Among the emission drivers, an nth (n is a positive integer) emission driver includes: a Q node controller, the Q node controller controls the Q node based on a start signal transmitted through a start signal line; a QB2 node controller, the QB2 node controller controls the QB2 node based on the potential of the Q node; a QB1 node controller, the QB1 node controller controls the QB1 node based on the potential of the QB2 node; a first output buffer, the first output buffer is turned on based on the potential of the Q node, thereby outputting a first emission signal; and a second output buffer, the second output buffer having at least two transistors, the at least two transistors are turned on based on the potential of different nodes, thereby outputting a second emission signal.

[0277] According to another feature of the present disclosure, at least two transistors of the second output buffer of the present disclosure may have a parallel connection structure, in which the first electrodes of the at least two transistors are only connected to each other, the second electrodes of the at least two transistors are only connected to each other, and the gates of the at least two transistors are connected to different nodes.

[0278] According to another feature of the present disclosure, the second output buffer may include: a 2-1 output buffer including a transistor operating in response to a potential of the QB1 node; and a 2-2 output buffer including a transistor operating based on a potential of the QB2 node.

[0279] According to another feature of the present disclosure, the nth emission driver may include: a first transistor, the first transistor including a gate connected to a second clock signal line, a first electrode connected to a start signal line, and a second electrode connected to the Q node; a second transistor, the second transistor including a gate connected to the Q node and a first electrode connected to the first clock signal line; a third transistor, the third transistor including a gate connected to a QB2 node, a first electrode connected to the Q node, and a second electrode connected to a high potential voltage input terminal; a fourth transistor, the fourth transistor including a gate connected to the second clock signal line, a first electrode connected to an n-1QB2 node of the n-1th emission driver, and a second electrode connected to a QP node; a fifth transistor, the fifth transistor including a gate connected to the Q node, a first electrode connected to the QB2 node, and a second electrode connected to the high potential voltage input terminal; a sixth transistor, the sixth transistor including a gate connected to the Q node, a first electrode connected to a low potential voltage input terminal, and a second electrode connected to a QB2 node of the n-1th emission driver. a first electrode connected to the output terminal of the nth emission driver and a second electrode connected to the output terminal of the nth emission driver; a 7-1 transistor, the 7-1 transistor including a gate connected to the QB1 node, a first electrode connected to the output terminal of the nth emission driver and a second electrode connected to the high potential voltage input terminal; a 7-2 transistor, the 7-2 transistor including a gate connected to the QB2 node, a first electrode connected to the output terminal of the nth emission driver and a second electrode connected to the high potential voltage input terminal; an eighth transistor, the eighth transistor including a gate connected to the QP node, a first electrode connected to the first clock signal line and a second electrode connected to the QB2 node; a ninth transistor, the ninth transistor including a gate connected to the first clock signal line, a first electrode connected to the QB2 node and a second electrode connected to the QB1 node; and a tenth transistor, the tenth transistor including a gate connected to the Q node, a first electrode connected to the QB1 node and a second electrode connected to the high potential voltage input terminal.

[0280] An electroluminescent display according to an embodiment of the present disclosure includes: a pixel connected to an emission line; and an emission driver that supplies an emission signal to the emission line and includes a plurality of stages. Among the plurality of stages, the nth (n is a positive integer equal to or greater than 2) stage includes: a pull-up unit controlled by a Q node to output an emission signal having a turn-on voltage; a pull-down unit controlled by the Q node or the QB node to output a cut-off voltage; a QB node controller interposed between the QB node and the QB' node; and a QB node regulator that shifts the voltage of the QB' node of the n-1th stage and applies the shifted voltage to the QB' node. Therefore, it is possible to reduce the influence of the load increase of the emission clock signal and stably perform the output of the QB node, thereby improving the reliability of the emission driver.

[0281] The nth stage of the electroluminescent display may further include a Q-node controller that controls a voltage of the Q-node using an emission signal from the n-1th stage.

[0282] Each of the pixels may include a light emitting device and a pixel driving circuit, and each of the emission lines may be connected to an emission transistor included in the pixel driving circuit.

[0283] The QB node regulator may include a Q′ node controller, a QB′ node controller, a QB node holding unit, a QB′ node holding unit, and a capacitor.

[0284] The Q' node controller may be controlled by a first emission clock signal to apply a voltage of a QB' node of the n-1th stage to the Q' node. The QB' node controller may be controlled by the Q' node to apply a second emission clock signal to the QB' node. The QB' node holding unit may be controlled by the Q node to discharge the QB node to an emission high voltage. The QB' node holding unit may be controlled by the Q node to discharge the QB' node to an emission high voltage. A capacitor may be connected between the Q' node and the QB' node. The QB node controller may control a short circuit between the QB' node and the QB node according to a second emission clock signal, or may be controlled by the QB' node to apply an emission low voltage to the QB node.

[0285] The first transmit clock signal and the second transmit clock signal may be in anti-phase.

[0286] The QB node regulator may further include a Q′ node holding unit.

[0287] The Q' node controller may be controlled by a first emission clock signal to apply a voltage of a QB' node of the n-1th stage to the Q' node. The QB' node controller may be controlled by the Q' node to apply a second emission clock signal to the QB' node. The QB node holding unit may be controlled by the Q node to discharge the QB node to an emission high voltage. The QB' node holding unit may be controlled by the Q node to discharge the QB' node to an emission high voltage. The QB' node holding unit may be controlled by the Q node to discharge the Q' node to an emission high voltage. A capacitor may be connected between the Q' node and the QB' node. The QB node controller may control the short circuit of the QB' node and the QB node based on a second emission clock signal, or may be controlled by the QB' node to apply an emission low voltage to the QB node.

[0288] According to an embodiment of the present specification, when it comes to a gating driving circuit including n (n is a positive integer equal to or greater than 2) stages, the kth (1≤k≤n) stage includes a pull-up unit, a pull-down unit, a Q node controller for controlling a Q node connected to the pull-up unit, and a QB node regulator for controlling a QB node connected to the pull-down unit. The QB node regulator includes a Q' node controller, a QB' node controller, a QB node controller, a QB' node holding unit, and a QB node holding unit. The QB node regulator shifts the level of the voltage of the QB' node of the k-1th stage, and applies the level-shifted voltage to the QB' node. Therefore, it is possible to reduce the influence of the load increase of the emission clock signal and enable the QB node to stably perform output, thereby improving the reliability of the emission driver.

[0289] The QB node regulator may be applied with an emission low voltage, an emission high voltage, a first emission clock signal, and a second emission clock signal. The emission low voltage is a voltage lower than the emission high voltage. The first emission clock signal and the second emission clock signal may swing between the emission low voltage and the emission high voltage.

[0290] The QB node regulator may further include a capacitor. The Q' node controller may include a first transistor. The QB' node controller may include a second transistor. The QB node controller may include a third transistor. The QB' node holding unit may include a fourth transistor. The QB node holding unit may include a fifth transistor. A capacitor may be connected to the Q' node and the QB' node.

[0291] The first transistor may include a gate connected to the second clock signal line, a first electrode connected to the QB' node of the k-1th level, and a second electrode connected to the Q' node. The second transistor may include a gate connected to the Q' node, a first electrode connected to the first clock signal line, and a second electrode connected to the QB' node. The third transistor may include a gate connected to the first clock signal line, a first electrode connected to the QB' node, and a second electrode connected to the QB node. The fourth transistor may include a gate connected to the Q node, a first electrode connected to the QB' node, and a second electrode connected to the emission high voltage line. The fifth transistor may include a gate connected to the Q node, a first electrode connected to the QB node, and a second electrode connected to the emission high voltage line.

[0292] The QB node regulator may further include a Q' node holding unit, and the Q' node holding unit may be configured as a sixth transistor. The sixth transistor may include a gate connected to the Q node, a first electrode connected to the Q' node, and a second electrode connected to the emission high voltage line.

[0293] The first transistor may include a gate connected to the second clock signal line, a first electrode connected to the QB' node of the k-1th level, and a second electrode connected to the Q' node. The second transistor may include a gate connected to the Q' node, a first electrode connected to the first clock signal line, and a second electrode connected to the QB' node. The third transistor may include a gate connected to the QB' node, a first electrode connected to the emission low voltage line, and a second electrode connected to the QB node. The fourth transistor may include a gate connected to the Q node, a first electrode connected to the QB' node, and a second electrode connected to the emission high voltage line. The fifth transistor may include a gate connected to the Q node, a first electrode connected to the QB node, and a second electrode connected to the emission high voltage line.

[0294] The QB node regulator may further include a Q' node holding unit, and the Q' node holding unit may be configured as a sixth transistor. The sixth transistor may include a gate connected to the Q node, a first electrode connected to the Q' node, and a second electrode connected to the emission high voltage line.

[0295] The embodiments of the present specification stably maintain the voltage of a node controlling a pull-up transistor of a gate driving circuit, thereby improving the driving capability and reliability of the gate driving circuit and enabling an electroluminescent display to correctly display an image.

[0296] In addition, the embodiments of the present specification provide a gate driving circuit that can improve the driving capability of a transistor and maintain stable output characteristics, thereby enabling a narrow frame of an electroluminescent display including the gate driving circuit.

[0297] In addition, the embodiments of the present specification implement a gate drive circuit including an output buffer implemented as a double buffer. Therefore, even when the threshold voltage of the transistor operating as the output buffer shifts, the shift can be compensated, thereby achieving stable output characteristics, thereby improving the driving reliability of the gate drive circuit.

[0298] In addition, the embodiments of the present specification include a transmission driver based on a shift register, thereby solving the signal delay caused by the load in the clock signal line.

[0299] In addition, the embodiments of the present specification do not invert the Q node into a structure for controlling the QB node included in the emission driver and then apply a voltage to the QB node: instead, a QB node regulator is additionally provided to control the QB node, thereby reducing the impact of the load increase of the emission clock signal.

[0300] In addition, according to the embodiment of the present specification, the QB node regulator 17 - 4 implements a shift circuit that receives an input of a signal from the QB′ node of the previous stage in a bootstrap manner, thereby being able to reduce the influence of the load increase of the transmission clock signal and stably perform the output of the QB node.

[0301] In addition, according to an embodiment of the present specification, the QB node regulator may include a QB' node and a transistor connected to the QB node, and apply an emission high voltage to the QB' node and the QB node to prevent the QB' node and the QB node from floating for a long time, thereby stabilizing the emission driver.

[0302] In addition, according to an embodiment of the present specification, the QB node regulator may include a transistor that applies an emission high voltage to the Q' node so as to prevent a transistor having a gate connected to the Q' node from being turned on due to the Q' node dropping to a logic low voltage due to the transistor being turned off for a long time.

[0303] It is obvious to those skilled in the art that various modifications and changes can be made to the gate drive circuit of the present invention and the electroluminescent display using the gate drive circuit without departing from the technical concept or scope of the present invention. Therefore, the present invention is intended to cover the modifications and changes of the present invention that fall within the scope of the attached claims and their equivalents.

[0304] This application claims the benefit of Korean Patent Application No. 10-2017-0111475, filed on August 31, 2017, Korean Patent Application No. 10-2017-0155014, filed on November 20, 2017, and Korean Patent Application No. 10-2017-0119848, filed on September 18, 2017, which are hereby incorporated by reference in their entirety for all purposes as if fully set forth herein.

Claims

1. An electroluminescent display, comprising: A pixel connected to the emission line; as well as a transmit driver that supplies a transmit signal to the transmit line and includes a plurality of stages connected to each other in a cascade manner, Wherein, n is an integer equal to or greater than 2, and the nth level among the plurality of levels comprises: A pull-up unit, the pull-up unit being controlled by the Q node to output a transmission signal having a conduction voltage; a pull-down unit, the pull-down unit being controlled by the Q node or the QB node to output a cut-off voltage; A QB node controller, the QB node controller being between the QB node and the QB' node; and a QB node regulator that shifts the level of the voltage of the QB' node of the n-1th stage by as much time as the period of the first transmission clock signal to thereby apply the level-shifted voltage to the QB' node, The QB node controller controls the short circuit of the QB node and the QB′ node according to the second transmission clock signal, or the QB node controller is controlled by the QB′ node to apply a transmission low voltage to the QB node.

2. The electroluminescent display according to claim 1, wherein: The nth stage further includes a Q-node controller that controls a voltage of the Q-node using a transmission signal from the n-1th stage.

3. The electroluminescent display according to claim 1, wherein: Each of the pixels includes a light emitting device and a pixel driving circuit, and wherein each of the emission lines is connected to an emission transistor included in the pixel driving circuit.

4. The electroluminescent display according to claim 1, wherein: The QB node regulator includes a Q' node controller, a QB' node controller, a QB node holding unit, a QB' node holding unit and a capacitor, The Q' node controller is controlled by the first transmission clock signal to apply the voltage of the QB' node of the n-1th stage to the Q' node. wherein the QB' node controller is controlled by the Q' node to apply the second transmit clock signal to the QB' node, wherein the QB node holding unit is controlled by the Q node to discharge the QB node to an emission high voltage, The QB' node holding unit is controlled by the Q node to discharge the QB' node to an emission high voltage. The capacitor is connected between the Q' node and the QB' node.

5. The electroluminescent display according to claim 4, wherein: The first transmit clock signal and the second transmit clock signal are in anti-phase.

6. The electroluminescent display according to claim 4, wherein: The QB node regulator further includes a Q' node holding unit.

7. The electroluminescent display according to claim 6, wherein: The Q′ node holding unit is controlled by the Q node to discharge the Q′ node to an emission high voltage.

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