Semiconductor package with interposer and passive components

Abstract

Disclosed herein is a semiconductor assembly including: an interposer including an electrically insulating substrate, a plurality of upper contact pads disposed on an upper surface of the substrate, and a plurality of lower contact pads disposed on a lower surface of the substrate; a semiconductor package including a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body; a first passive electrical element including a first terminal and a second terminal; a first electrical connection via the interposer between the first terminal of the first passive electrical element and a first one of the lower contact pads; a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals; and a third electrical connection via the interposer between a second one of the package terminals and a second one of the lower contact pads.

Description

Background Technology

[0001] Power modules are used in many applications, such as automotive and industrial applications. A power module may include power devices rated to control large voltages and / or currents, and driver devices configured to control the power devices, such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), IGBTs (Insulated-Gate Bipolar Transistors), diodes, etc. Power modules may also include passive electrical components, such as inductors and capacitors, which improve performance, such as power efficiency and switching speed. It is desirable to provide a power module that exhibits high performance, such as high peak efficiency and high load efficiency, while maintaining a small footprint and robust electrical interconnects. Summary of the Invention

[0002] A semiconductor assembly is disclosed. According to an embodiment, the semiconductor assembly includes: an interposer including an electrically insulating substrate, a plurality of upper contact pads disposed on an upper surface of the substrate, and a plurality of lower contact pads disposed on a lower surface of the substrate opposite to the upper surface; a semiconductor package including a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body; a first passive electrical element including a first terminal and a second terminal; a first electrical connection via the interposer between the first terminal of the first passive electrical element and a first lower contact pad in the lower contact pads; a second electrical connection between the second terminal of the first passive electrical element and a first package terminal in the package terminal; and a third electrical connection via the interposer between the second package terminal in the package terminal and a second lower contact pad in the lower contact pads.

[0003] Individually or in combination, a semiconductor package is mounted on an interposer such that the package terminals face and are electrically connected to a set of upper contact pads.

[0004] Individually or in combination, the first passive electrical component is a discrete passive electrical component disposed on and overlapping with the semiconductor package.

[0005] Individually or in combination, the first electrical connection includes a first conductive connector that extends vertically between a first upper contact pad in the upper contact pad and the lower surface of the first passive electrical component, and the first upper contact pad in the upper contact pad is electrically connected to a first lower contact pad in the lower contact pad via an inserter.

[0006] Individually or in combination, the second electrical connection includes a second conductive connector that extends vertically between a second upper contact pad in the upper contact pad and the lower surface of the first passive electrical component, and wherein the second upper contact pad in the upper contact pad is electrically connected to a first package terminal in the package terminal via an interposer.

[0007] Individually or in combination, the first package terminal in the package is disposed on the upper side of the semiconductor package away from the interposer.

[0008] Individually or in combination, a semiconductor package includes a first outer edge side and a second outer edge side opposite to each other, wherein a first package terminal in the package terminals is positioned closer to the second outer edge side, and the first outer edge side faces a first conductive connector.

[0009] Individually or in combination, a semiconductor package includes a first outer edge side and a second outer edge side opposite to each other, wherein a first package terminal in the package terminals is positioned closer to the second outer edge side, and the second outer edge side faces a first conductive connector.

[0010] Individually or in combination, the second electrical connection includes a second conductive connector that extends vertically between a second upper contact pad in the upper contact pad and the lower surface of the first passive electrical component, and the second upper contact pad in the upper contact pad is electrically connected to a first package terminal in the package terminal via a first conductive clip disposed outside the semiconductor package.

[0011] Individually or in combination, the second electrical connection includes a second conductive connector that directly contacts the first package terminal in the package terminal, and the second conductive connector includes a lateral portion extending across a first outer edge side of the semiconductor package and a vertical portion extending from the lateral portion to the lower surface of the first passive electrical element.

[0012] Individually or in combination, the semiconductor assembly also includes a second passive electrical element mounted on the upper surface of the semiconductor package, and a first passive electrical element disposed above and spaced apart from the second passive electrical element.

[0013] The first passive electrical component is integrally formed in the interposer, either alone or in combination.

[0014] Individually or in combination, the semiconductor package includes a pair of power switching devices forming a high-side switch and a low-side switch of a half-bridge circuit, and a driver chip configured to control the power switching devices, and the first passive electrical element is an inductor connected in series between the output of the half-bridge circuit and the circuit carrier.

[0015] Individually or in combination, a semiconductor package includes a conductive metal clip disposed on an upper surface of the semiconductor package opposite to an interposer, and the conductive metal clip forms an electrical interconnect between two terminals of the semiconductor package.

[0016] According to another embodiment, the semiconductor assembly includes: a circuit carrier including an electrically insulating substrate and a plurality of bonding pads disposed on a main surface of the circuit carrier; an interposer including an electrically insulating substrate, a plurality of upper contact pads disposed on an upper surface of the substrate, and a plurality of lower contact pads disposed on a lower surface of the substrate opposite to the upper surface; a semiconductor package including a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body; and a first passive electrical component, wherein the interposer is mounted on the circuit carrier and the lower contact pads face and are electrically connected to the bonding pads, wherein the semiconductor package is mounted on the interposer and the package terminals face and are electrically connected to the upper contact pads, and wherein both the semiconductor package and the first passive electrical component are electrically connected to the circuit carrier via the interposer.

[0017] Individually or in combination, the first passive electrical component is a discrete passive electrical component disposed on and overlapping with the semiconductor package.

[0018] Individually or in combination, the first passive electrical component includes a first terminal and a second terminal, the first terminal being electrically connected to a circuit carrier via an interposer, and the second terminal being electrically connected to a first package terminal in a package terminal.

[0019] A method for manufacturing a semiconductor component is disclosed. According to an embodiment, the method includes: providing an interposer including an electrically insulating substrate, a plurality of upper contact pads disposed on an upper surface of the substrate, and a plurality of lower contact pads disposed on a lower surface of the substrate opposite to the upper surface; providing a semiconductor package including a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body; providing a first passive electrical component including a first terminal and a second terminal; forming a first electrical connection between the first terminal of the first passive electrical component and a first lower contact pad in the lower contact pads via the interposer; forming a second electrical connection between a second terminal of the first passive electrical component and a first package terminal in the package terminal; and forming a third electrical connection between a second package terminal in the package terminal and a second lower contact pad in the lower contact pads via the interposer.

[0020] Alone or in combination, the method further includes mounting a semiconductor package onto an interposer such that package terminals face and are electrically connected to a set of upper contact pads, and wherein at least some of the package terminals from the set are electrically connected to lower contact pads via the interposer.

[0021] Individually or in combination, the first passive electrical component is a discrete passive electrical component, and the method further includes mounting the first passive electrical component on a semiconductor package such that the discrete passive electrical component overlaps with the semiconductor package.

[0022] Forming the first electrical connection portion individually or in combination includes providing a first conductive connector that extends vertically between a first upper contact pad in the upper contact pad and the lower surface of a first passive electrical component, the first conductive connector mechanically supporting the first electrical connection portion and electrically connecting a first terminal of the first conductive connector to the first upper contact pad in the upper contact pad, and the first upper contact pad in the upper contact pad being electrically connected via an inserter to a first lower contact pad in the lower contact pad. Attached Figure Description

[0023] The elements in the accompanying drawings are not necessarily proportional to each other. Similar reference numerals denote corresponding similar parts. Features of various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the accompanying drawings and described in detail below.

[0024] Figure 1 An interpolator according to an embodiment is shown.

[0025] Figure 2 A semiconductor assembly according to an embodiment is shown, comprising a circuit carrier, an interposer mounted on the circuit carrier, and a semiconductor package and discrete passive electrical components mounted on the interposer.

[0026] Figure 3 A semiconductor assembly according to an embodiment is shown, comprising a circuit carrier, an interposer mounted on the circuit carrier, a semiconductor package mounted on the interposer, and a passive electrical component monolithically integrated in the interposer.

[0027] Figure 4-9 Each of the embodiments illustrates a semiconductor assembly including a circuit carrier, an interposer mounted on the circuit carrier, and a semiconductor package and discrete passive electrical components mounted on the interposer.

[0028] Figure 10 include Figure 10 A, Figure 10 B Figure 10 C and Figure 10 D shows a plan view of a semiconductor package, including a metal clip and which can be incorporated into a semiconductor assembly, according to various embodiments. Detailed Implementation

[0029] This document describes embodiments of a semiconductor assembly including an interposer, a semiconductor package, and passive electrical components. The interposer is configured as an intermediate structure between the semiconductor package and a circuit carrier (e.g., a PCB (printed circuit board)). This semiconductor assembly can form a power module with several advantages over existing designs. These advantages include improved space efficiency on the circuit carrier, as the interposer enables vertical stacking and / or overlap between the semiconductor package and the passive electrical components. These advantages also include reduced parasitic effects, such as parasitic inductance, due to the short interconnects between the semiconductor package and the passive electrical components. These advantages further include increased reliability of electrical connections compared to other interconnect solutions, such as bonding wires and metal clips. These advantages also include increased compatibility with specific semiconductor packages, as the interposer can be configured to adjust the I / O footprint of semiconductor packages on many different circuit carriers.

[0030] refer to Figure 1 The diagram depicts an interposer 100 according to an embodiment. The interposer 100 includes an electrically insulating substrate 102, a plurality of upper contact pads 104 disposed on an upper surface of the substrate 102, and a plurality of lower contact pads 106 disposed on a lower surface of the substrate 102 opposite to the upper surface. The interposer 100 is designed to be mounted on a circuit carrier, such as a PCB (printed circuit board), a DBC (direct-bonded copper) substrate, an AMB (active metal brazing) substrate, etc. In this mounting location, the interposer 100 is designed to accommodate one or more electronic components (e.g., passive components, semiconductor dies, etc.) mounted on the upper surface of the substrate 102. The interposer 100 is configured to provide all necessary electrical connections between the electronic components mounted thereon and the circuit carrier. For this purpose, the interposer 100 includes an internal network of interconnects 108 and vias 110 disposed between the upper and lower surfaces of the substrate 102. These interconnects 108 and vias 110 provide a low-resistance electrical connection between the upper contact pad 104 and the lower contact pad 106. A simple example of this concept is shown below. Figure 1 As shown, one of the upper contact pads 104 is electrically connected to two of the lower contact pads 106, and each of the two upper contact pads 104 is independently electrically connected to one of the lower contact pads 106. Typically, any number of upper contact pads 104 can be electrically connected to any number of lower contact pads 106, and the location and wiring of these electrical connections can be appropriately adjusted to meet the I / O and performance requirements of a specific application.

[0031] Generally, the various elements of the interposer 100 can be constructed from any material suitable for semiconductor applications and formed according to any technology suitable for semiconductor applications. For example, the substrate 102 can be formed from or include an electrically insulating material such as ceramic, epoxy resin, plastic, glass, oxide, nitride, pre-impregnated material, etc. The substrate 102 can also include semiconductor materials such as silicon, carbon, germanium, etc. The conductive features of the interposer 100, including the upper contact pad 104 and lower contact pad 106, interconnect 108, and via 110, can be formed from or include any conductive metal from a variety of conductive metals, such as copper, aluminum, zinc, tungsten, nickel, etc., and alloys thereof. According to an embodiment, the interconnect 108 and / or via 110 include a metal plating of a corrosion-resistant metal such as copper. This metal plating can be provided, for example, by electroplating or chemical plating. This metal plating can make the electrical connection more robust against failure compared to the corresponding electrical connection provided by a bonding wire.

[0032] The specific materials used for the interposer 100 and the processing techniques employed to form it can depend on a variety of considerations, such as cost, performance, and ease of manufacture. In one example, the interposer 100 can be constructed using PCB technology, where the substrate 102 includes a pre-impregnated material such as FR-4, having a structured metallization layer that provides bonding pads and internal interconnects. In another example, the interposer 100 can be constructed from a bulk semiconductor such as silicon, and the various electrical structures are formed using standard semiconductor processing techniques.

[0033] The interposer 100 can be specifically configured as a passive device providing a low-resistance electrical connection between the upper contact pad 104 and the lower contact pad 106. That is, the interposer 100 may not contain any other electrical components. Alternatively, the interposer 100 may include one or more active or passive electrical components monolithically integrated therein. For example, passive electrical components, such as resistors, capacitors, inductors, etc., can be formed in the interposer 100 through intentional geometry of the interconnects 108 and / or vias 110. Additionally or alternatively, the interposer 100 may include semiconductor devices, such as diodes, transistors, etc.

[0034] refer to Figure 2The image depicts a semiconductor assembly 200 including an interposer 100. The interposer 100 is mounted on a circuit carrier 300. The circuit carrier 300 includes an electrically insulating substrate 302 and a plurality of bonding pads 304 disposed on the main surface of the circuit carrier 300. The interposer 100 is mounted on the circuit carrier 300, and the lower contact pad 106 of the interposer 100 faces and is electrically connected to the corresponding contact pad 304 of the circuit carrier 300. A conductive intermediate material such as solder, sinter, or adhesive may be disposed between the lower contact pad 106 and the contact pad 304 to achieve these electrical connections.

[0035] Generally, the circuit carrier 300 can be any electronic substrate 102 configured to mechanically support multiple electronic components, such as semiconductor packages, passive devices, heat sinks, etc., and to accommodate electrical connections between these electronic components. In one embodiment, the circuit carrier 300 is a printed circuit board (PCB). In this case, the electrically insulating substrate 302 may include a pre-impregnated material such as FR-4, CEM-1, G-10, etc., and the bonding pad 304 may be a portion of a structured metallization layer (e.g., a copper metallization layer) that also includes signal traces. In another embodiment, the circuit carrier 300 can be a DBC (directly bonded copper) substrate. In this case, the electrically insulating substrate 302 may include ceramic, and the bonding pad 304 may be a portion of a structured metallization layer (e.g., a copper metallization layer) bonded to the ceramic material by an oxidation technique. In other embodiments, the circuit carrier 300 is another type of power electronics substrate, such as an AMB (active metal brazing) substrate or an IMS (insulating metal substrate) substrate.

[0036] The semiconductor assembly 200 also includes a semiconductor package 400 mounted on the interposer 100. The semiconductor package 400 includes one or more semiconductor dies 402 embedded within a package body 404 and a plurality of package terminals 406 exposed from the package body 404. The package terminals 406 are disposed on the main (lower) surface of the semiconductor package 400, and the semiconductor package 400 is mounted on the interposer 100 such that these package terminals 406 face and are electrically connected to corresponding upper contact pads 104 of the interposer 100. A conductive intermediate material such as solder, sinter, or adhesive may be provided between the lower contact pads 106 and the bonding pads 304 to achieve these electrical connections.

[0037] According to an embodiment, the semiconductor package 400 is a laminated or so-called "chip-embedded" package. Compared to molded package types that include a monolithic region of a molding compound encapsulating a semiconductor die, a chip-embedded package comprises an encapsulation body formed by multiple constituent layers of dielectric material, which are laminated (stacked) on top of each other. Each constituent laminated layer typically includes any dielectric material suitable for encapsulating a semiconductor device. Examples of such dielectric materials include epoxy materials, hybrid epoxy and glass fiber materials (e.g., FR-4, FR-5, CEM-4, etc.), and resin materials (e.g., bismaleimide triazine (BT) resin). A chip-embedded package typically also includes multiple metallization layers, such as copper, aluminum, etc., and alloys thereof, formed on top of at least some of the constituent laminated layers. These metallization layers can be configured to form internal interconnects within the package body 404 and package terminals 406 exposed on the outer surface of the package body 404. Conductive vias (e.g., vias including tungsten, copper, etc.) can be provided in openings extending through the constituent layers of dielectric material to provide vertical electrical interconnects. Due to the electrical interconnects provided by the internal structured metallization, the chip-embedded package does not require a lead frame. Therefore, the semiconductor package 400 may not have die pads accommodating the semiconductor die 402 and / or may not have conductive leads formed by the same lead frame structure as the die pads.

[0038] Generally, the semiconductor die 404 embedded within the package body 404 can have various device configurations, such as discrete device configurations like MOSFETs, IGBTs, diodes, etc., and integrated circuit configurations like controllers. The semiconductor die 404 can include type IV semiconductor materials (e.g., silicon, silicon germanium, silicon carbide, etc.) and / or type III-V semiconductor materials (e.g., gallium nitride, gallium arsenide, etc.). One or more semiconductor dies 404 can be configured as vertical devices configured to control current flow between a main surface and an opposing back surface, or as lateral devices configured to control current flow parallel to the main surface. One or more of the semiconductor dies 404 can be discrete power devices. Discrete power devices are discrete components rated to accommodate voltages of at least 100V, and more commonly about 500V or higher, and / or currents of at least 1A, and more commonly about 10A or higher. For example, discrete power devices include MOSFETs (metal-oxide-semiconductor field-effect transistors), IGBTs (insulated-gate bipolar transistors), and HEMTs (high electron mobility transistors).

[0039] According to an embodiment, semiconductor package 400 is configured as a power module. This type of device includes power switching devices (e.g., MOSFETs, IGBTs, HEMTs) and driver dies that control the switching operation of these power switching devices. Therefore, semiconductor package 400 may include one or two semiconductor dies in semiconductor die 404 configured as power switching devices and forming a half-bridge circuit with high-side and low-side switches connected in series, and a third semiconductor die in semiconductor die 404 configured as a driver device (e.g., a CMOS logic device) to control the switching operation of the high-side and low-side switches.

[0040] The semiconductor assembly 200 also includes a first passive electrical element 500, which includes first and second terminals 502, 504. The first passive electrical element 500 can be any device that provides a defined impedance (e.g., resistor, capacitor, inductor) between the first and second terminals 502, 504.

[0041] In the depicted embodiment, the first passive electrical component 500 is configured as a discrete component, i.e., a separate device providing a defined impedance between the first and second terminals 502, 504. The first passive electrical component 500 is mounted on the interposer 100 such that it is disposed above and overlaps the semiconductor package 400. In other words, the first passive electrical component 500 is located directly above the upper surface of the semiconductor package 400 opposite to the upper surface of the interposer 100.

[0042] Intercalator 100 includes multiple internal conduction paths 112. These conduction paths are in Figure 2 The internal conductive paths 112 are schematically represented by dashed lines. These internal conductive paths 112 can be formed by constructing interconnects 108 and vias 110, as shown in the reference. Figure 1 Generally, these internal conduction paths 112 can be between the upper contact pad 104, the lower contact pad 106, or any combination of the two. Figure 1 Only one specific example of possible internal wiring is shown, and its details will be described in further detail later.

[0043] According to an embodiment, the semiconductor component 200 includes a first electrical connection 202 via an interposer 100 between a first terminal 502 of a first passive electrical component 500 and at least one of the lower contact pads 106. As shown, the first terminal 502 of the first passive electrical component 500 is electrically connected to a first upper contact pad 114 in an upper contact pad 104, which in turn is electrically connected to a set of lower contact pads 106 via one of internal conductive paths 112. Furthermore, the set of lower contact pads 106 is electrically connected to a corresponding set of bonding pads 304 from a carrier.

[0044] In the depicted embodiment, the first electrical connection 202 includes a first conductive connector 204 extending from a first terminal 502 of the first passive electrical element 500 to a first upper contact pad 114 in the upper contact pad 104. The first conductive connector 204 may be a metal interconnect structure, such as a copper pillar or stud, designed to provide necessary vertical spacing and mechanical support between the first passive electrical element 500 and the inserter 100. In another embodiment, the first passive electrical element 500 may include elongated leads forming the first terminal 502 of the first passive electrical element 500 and directly contacting the first upper contact pad 114 in the upper contact pad 104.

[0045] According to an embodiment, the semiconductor assembly 200 includes a second electrical connection 206 between a second terminal 504 of the first passive electrical component 500 and a first package terminal in package terminal 406. In the depicted embodiment, the second electrical connection 206 is provided via an interposer 100. More specifically, the second terminal 504 of the first passive electrical component 500 is electrically connected to a second upper contact pad 116 in the upper contact pad 104, which in turn is electrically connected to a third upper contact pad 118 in the upper contact pad 104 via one of the internal conductive paths 112 of the interposer 100. The semiconductor assembly 200 may also include a second conductive connector 208 extending from the second terminal 504 of the first passive electrical component 500 to the second upper contact pad 116 in the upper contact pad 104. The second conductive connector 208 may be a metal interconnect structure, such as a copper pillar or stud, designed to provide the necessary vertical spacing and mechanical support between the first passive electrical component 500 and the interposer 100. In another embodiment, the first passive electrical component 500 may include elongated leads that form a second terminal 504 of the first passive electrical component 502 and directly contact the second upper contact pad 116 in the upper contact pad 104.

[0046] According to an embodiment, the semiconductor assembly 200 includes at least one third electrical connection 210 via an interposer 100 between one of the package terminals 406 and the lower contact pads 106. As shown, the semiconductor assembly 200 includes a plurality of third electrical connections 210. Generally, the third electrical connections 210 may correspond to some or all of the necessary electrical connections between the semiconductor package 400 and the circuit carrier 300.

[0047] In an embodiment where the semiconductor package 400 is configured as a semiconductor assembly 200 of a power module, the electrical connections of the assembly 200 may be as follows: A first passive electrical element 500 may be an inductor connected in series between the output of the power module and the circuit carrier 300. The output of the power module is provided at a first package terminal in package terminal 406, which is electrically connected to a second terminal 504 of the first passive electrical element 500 via a second electrical connection 206. A first terminal 502 of the first passive electrical element 500 is electrically connected to the circuit carrier 300 via a first electrical connection 202. The semiconductor assembly 200 includes a plurality of third electrical connections 210 providing all other necessary connections between the semiconductor die 402 and the circuit board. For example, the second package terminal 120 in package terminal 406 can be electrically connected to a set of bonding pads 304 that provide input voltage (Vin) to the high-side switch through one of the internal conduction paths 112 of the interposer 100; the third package terminal 122 in package terminal 406 can be electrically connected to a set of bonding pads 304 that provide reference potential (GND) or negative voltage to the low-side switch through one of the internal conduction paths 112 of the interposer 100; and the fourth package terminal 124 in package terminal 406 can be electrically connected to a bonding pad 304 in bonding pad 304 that provides a switching signal to the driver die through one of the internal conduction paths 112 of the interposer 100.

[0048] Optionally, the semiconductor package 400 may further include one or more second passive electrical components 408 mounted on the upper surface of the semiconductor package 400 opposite to the interposer 100. A first passive electrical component 500 is disposed above and spaced apart from the second passive electrical components 408. For this purpose, the vertical heights of the first and second conductive connectors 204, 208 can be selected such that a gap exists between the bottom of the first passive electrical component 500 and the second passive electrical component 408.

[0049] The second passive electrical component 408 can be any type of passive device, such as a resistor, capacitor, inductor, etc. The second passive electrical component 408 can be electrically connected to the semiconductor die 404 embedded within the package body 404 via internal connections of the semiconductor package 400. In the case of chip-embedded packaging, a structured metallization layer can be disposed on the upper surface of the semiconductor package 400 configured to house these second passive electrical components 408. Generally, the second passive electrical component 408 can be used to regulate the operation of the semiconductor package 400 in a variety of different ways. For example, the second passive electrical component 408 can be a capacitor configured to provide input current buffering or supply current buffering to power transistors or driver devices.

[0050] refer to Figure 3 The image depicts a semiconductor component 200 according to another embodiment. In this embodiment, a first passive electrical element 500 is an integrally formed component of the interposer 100. The first and second terminals 502, 504 of the first passive electrical element 500 can be connected to a reference... Figure 2 The same connection method is described. This embodiment represents another way to combine the semiconductor package 400 with passive electrical components using the interposer 100 and form the necessary electrical connection with the circuit board in a space-efficient and low-parasitic manner.

[0051] refer to Figure 4 The image depicts a semiconductor assembly 200 according to another embodiment. In this embodiment, a first package terminal in a package terminal 406 is disposed on the upper side of the semiconductor package 400 away from the interposer 100. In doing so, the second electrical connection 206 may include a second conductive connector 208 directly connected to the first package terminal in the package terminal 406. The second conductive connector 208 may be a conductive stud, bump, or solder ball configured to create the necessary vertical spacing. Figure 4 The semiconductor component 200 eliminates the need for wiring within the interposer 100 to connect the first passive electrical component 500 to the semiconductor package 400. As a result, a reduction in the size of the interposer 100 is possible, which in turn enables a reduction in the area required for the circuit carrier 300.

[0052] refer to Figure 5 The image depicts a semiconductor assembly 200 according to another embodiment. In this embodiment, the first passive electrical component 500 is rearranged, and the interposer 100 is reconfigured. Figure 4 In one embodiment, the first outer edge 410 of the package body 404 faces the first conductive connector 204. The first outer edge 410 of the package body 404 is further away from the first package terminal in the package terminal 406 that is connected to the first terminal 504 of the first passive electrical component 500. In contrast, in... Figure 5In this embodiment, the second outer edge 412 of the package body 404, which is closer to the first package terminal in the package terminal 406 that is connected to the first terminal 504, faces the first conductive connector 204. Compared to the previous embodiment, Figure 5 The semiconductor component 200 has less overlap between the first passive electrical component 500 and the semiconductor package 400, and requires a larger lateral footprint to accommodate the interposer 100 compared to previous embodiments. However, in some cases, this increased area can be beneficial by reducing congestion of the internal conduction paths 112 within the interposer 100. This can reduce manufacturing costs and / or allow for larger and therefore more robust electrical connections.

[0053] refer to Figure 6 The image depicts a semiconductor component 200 according to another embodiment. Figure 6 This embodiment and Figure 5 The embodiment is essentially the same, except that the first package terminal in package terminal 406, which is connected to the first terminal 504, is reoriented closer to the first outer edge side 410 of the package body 404, away from the first conductive connector 204. In this arrangement, the first passive electrical element 500 can extend substantially across the entire length of the semiconductor package 400, thus having more overlap. This may be as described in the reference... Figure 5 The embodiments described provide some improvements to the congestion and / or wiring complexity of the internal conduction path 112, while also improving space efficiency.

[0054] refer to Figure 7 The image depicts a semiconductor component 200 according to another embodiment. Figure 7 Implementation examples and Figure 6 The embodiments are essentially the same, except that the semiconductor package 400 is moved closer to the first conductive connector 204. For example, the semiconductor package 400 may be arranged such that the distance between the first upper contact pad 114 in the upper contact pad 104 connected to the first conductive connector 204 and the closest upper contact pad in the upper contact pad 104 connected to one of the package terminals 406 corresponds to a minimum separation distance selected by the process for forming the interposer 100. In this arrangement, the first passive electrical component 500 may extend laterally beyond the first outer edge side 410 of the semiconductor package 400.

[0055] The second electrical connection 206 is provided by a second conductive connector 208, which is electrically connected to the second terminal 504 of the first passive electrical component 500 and electrically contacts the first package terminal in the package terminal 406. The second conductive connector 208 includes a lateral portion 214 extending across a first outer edge side 410 of the semiconductor package 400, and a vertical portion 216 extending from the lateral portion 214 to the lower surface of the first passive electrical component 500. The second conductive connector 208 may be an interconnect structure, such as a metal clip, which is connected to the second terminal 504 of the first passive electrical component 500 and the first package terminal in the package terminal 406 by a conductive adhesive such as solder. Alternatively, the second conductive connector 208 may be a lead structure, which is part of the first passive electrical component 500 itself and is directly connected to the first package terminal in the package terminal 406 by a conductive adhesive such as solder.

[0056] refer to Figure 8 The image depicts a semiconductor component 200 according to another embodiment. Figure 8 Implementation examples and Figure 7 The embodiments are essentially the same, except that the second electrical connection 206 includes a second conductive connector 208 electrically connected to a second upper contact pad 116 in the upper contact pad 104, which in turn is electrically connected to a first package terminal in the package terminal 406 via a conductive metal clip 218 disposed outside the semiconductor package 400. Therefore, the second electrical connection 206 is implemented without using the interconnects 108 and / or vias 110 within the interposer 100. The second conductive connector 208 and the metal clip 218 can be formed using a conductive adhesive such as solder to create the necessary electrical connection. This represents another way to implement the second electrical connection 206 while avoiding increased congestion of the internal conductive paths 112 within the interposer 100.

[0057] refer to Figure 9 The image depicts a semiconductor component 200 according to another embodiment. Figure 9 Implementation examples and Figure 6The embodiments are essentially the same, except that a conductive metal clip 220 is provided on top of the semiconductor package 400. The conductive metal clip 220 may comprise or be formed of a conductive metal such as copper, aluminum, or alloys thereof. As shown, the conductive metal clip 220 is arranged around one of the second passive electrical components 408. The conductive metal clip 220 may be electrically connected between two bonding pads disposed on the upper surface of the semiconductor package 400 opposite the interposer 100. For example, if the semiconductor package 400 is configured as a chip-embedded package, these bonding pads may be formed in a structured metallization layer formed on top of the laminate. The metal clip 220 may form an electrical interconnect between two internal terminals of the semiconductor package 400 to provide enhanced electrical and / or thermal performance compared to arrangements where the electrical connection is provided by internal interconnects of the semiconductor package 400. For example, in an embodiment where the semiconductor package 400 is configured as a power module, the metal clip 220 may form a portion of a drain-source connection, thereby resulting in improved Ro. DSON (Drain-source on-resistance).

[0058] refer to Figure 10 It shows from the perspective of the plan. Figure 9 Various configurations of the conductive metal clip 220 in the semiconductor component 200. Figure 10 A and Figure 10 B depicts two possible arrangements in which the semiconductor package 400 includes a second passive electrical element 408 mounted on its upper surface, and a conductive metal clip 220 is arranged around the second passive electrical element 408. Figure 10 C and Figure 10 D depicts two possible arrangements, in which the upper surface of the semiconductor package 400 includes only the conductive metal clip 220, which covers a portion of the upper surface of the semiconductor package 400 (in...). Figure 10 In the case of D) or almost all (in the case of D) Figure 10 (In case of C). These embodiments can be used to obtain the maximum thermal and / or electrical performance of the conductive metal clip 220.

[0059] As used herein, the term "electrical connection" describes a low-resistance conductive path provided by one or more conductive structures. An "electrical connection" may include several different conductive structures, such as bonding pads 304, solder structures, and interconnects 108.

[0060] Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device other than those depicted in the figures. Furthermore, terms such as “first” and “second” are also used to describe various elements, regions, parts, etc., and are not intended to be limiting. Similar terms refer to similar elements throughout the description.

[0061] As used herein, the terms “having,” “comprising,” “including,” etc., are open-ended terms that indicate the presence of the said element or feature but do not exclude additional elements or features. The articles “a” and “said” are intended to include both plural and singular unless the context clearly indicates otherwise.

[0062] Given the variations and applications described above, it should be understood that the present invention is not limited to the foregoing description or the accompanying drawings. Rather, the invention is limited only to the appended claims and their legal equivalents.

Claims

1. A semiconductor assembly comprising: an interposer comprising an electrically insulating substrate, a plurality of upper contact pads disposed on an upper surface of the substrate, and a plurality of lower contact pads disposed on a lower surface of the substrate opposite the upper surface; a semiconductor package comprising a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body; a first passive electrical element comprising a first terminal and a second terminal; a first electrical connection via the interposer between the first terminal of the first passive electrical element and a first one of the lower contact pads; a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals; and a third electrical connection via the interposer between a second one of the package terminals and a second one of the lower contact pads, wherein the first passive electrical element is vertically stacked with and at least partially horizontally overlaps the semiconductor package, wherein the first passive electrical element is a discrete passive electrical element. the semiconductor package is mounted on the interposer such that the package terminals face and are electrically connected with a set of the upper contact pads.

2. The semiconductor assembly of claim 1, wherein, the first passive electrical element is disposed on and overlaps the semiconductor package.

3. The semiconductor component of claim 1, wherein, the first electrical connection comprises a first electrically conductive connector extending vertically between a first one of the upper contact pads and a lower surface of the first passive electrical element, and wherein the first one of the upper contact pads is electrically connected to the first one of the lower contact pads via the interposer.

4. The semiconductor component of claim 3, wherein, the second electrical connection comprises a second electrically conductive connector extending vertically between a second one of the upper contact pads and the lower surface of the first passive electrical element, and wherein the second one of the upper contact pads is electrically connected to the first one of the package terminals via the interposer.

5. The semiconductor assembly of claim 4, wherein, the first one of the package terminals is disposed on an upper side of the semiconductor package facing away from the interposer.

6. The semiconductor assembly of claim 4, wherein, the semiconductor package comprises first and second outer edge sides opposite each other, wherein the first one of the package terminals is disposed closer to the second outer edge side, and wherein the first outer edge side faces the first electrically conductive connector.

7. The semiconductor assembly of claim 6, wherein, the semiconductor package comprises first and second outer edge sides opposite each other, wherein the first one of the package terminals is disposed closer to the second outer edge side, and wherein the second outer edge side faces the first electrically conductive connector.

8. The semiconductor assembly of claim 6, wherein, ​ 9. The semiconductor assembly of claim 6, wherein, The second electrical connection includes a second conductive connector extending vertically between a second one of the upper contact pads and the lower surface of the first passive electrical element, and wherein the second one of the upper contact pads is electrically connected to the first one of the package terminals by a first conductive clip disposed outside the semiconductor package.

10. The semiconductor assembly of claim 6, wherein, The second electrical connection includes a second conductive connector directly contacting the first one of the package terminals, and wherein the second conductive connector includes a lateral portion extending across a first outer edge side of the semiconductor package and a vertical portion extending from the lateral portion to the lower surface of the first passive electrical element.

11. The semiconductor assembly of claim 3, further comprising a second passive electrical element mounted on an upper surface of the semiconductor package, and wherein, The first passive electrical element is disposed on and spaced apart from the second passive electrical element.

12. The semiconductor component of claim 1, wherein, The first passive electrical element is integrally formed in the interposer.

13. The semiconductor component of claim 1, wherein, The semiconductor package includes a pair of power switching devices forming a high-side switch and a low-side switch of a half-bridge circuit and a driver die configured to control the power switching devices, and wherein the first passive electrical element is an inductor connected in series between an output of the half-bridge circuit and a circuit carrier.

14. The semiconductor component of claim 1, wherein, The semiconductor package includes a conductive metal clip disposed on an upper surface of the semiconductor package opposite the interposer, and wherein the conductive metal clip forms an electrical interconnection between two terminals of the semiconductor package.

15. A semiconductor assembly, comprising: a circuit carrier including an electrically insulating substrate and a plurality of bond pads disposed on a major surface of the circuit carrier; an interposer including an electrically insulating substrate, a plurality of upper contact pads disposed on an upper surface of the substrate, and a plurality of lower contact pads disposed on a lower surface of the substrate opposite the upper surface; a semiconductor package including a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body; and a first passive electrical element; wherein the interposer is mounted on the circuit carrier with the lower contact pads facing and electrically connected to the bond pads, wherein the semiconductor package is mounted on the interposer with the package terminals facing and electrically connected to the upper contact pads, wherein the semiconductor package and the first passive electrical element are both electrically connected to the circuit carrier via the interposer, and wherein the first passive electrical element is vertically stacked with and at least partially horizontally overlapped by the semiconductor package, wherein the first passive electrical element is a discrete passive electrical element. The first passive electrical element is disposed on and overlapped by the semiconductor package.

16. The semiconductor assembly of claim 15, wherein, The first passive electrical element includes a first terminal and a second terminal, wherein the first terminal is electrically connected to the circuit carrier via the interposer, and wherein the second terminal is electrically connected to a first one of the package terminals.

17. The semiconductor component of claim 15, wherein, 18. A method of producing a semiconductor assembly, comprising: ​ An interposer is provided, the interposer comprising an electrically insulating substrate, a plurality of upper contact pads disposed on an upper surface of the substrate, and a plurality of lower contact pads disposed on a lower surface of the substrate opposite the upper surface; A semiconductor package is provided, the semiconductor package comprising a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body; A first passive electrical element is provided, the first passive electrical element comprising a first terminal and a second terminal; A first electrical connection is formed between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer; A second electrical connection is formed between the second terminal of the first passive electrical element and a first one of the package terminals; And A third electrical connection is formed between a second one of the package terminals and a second one of the lower contact pads via the interposer, wherein the first passive electrical element is vertically stacked with and at least partially horizontally overlaps the semiconductor package, wherein the first passive electrical element is a discrete passive electrical element.

19. The method of claim 18, further comprising mounting the semiconductor package on the interposer such that the package termination faces and is electrically connected with a set of the upper contact pads, and wherein, At least some of the package terminals facing the set of the upper contact pads are electrically connected to the lower contact pads via the interposer.

20. The method of claim 18, further comprising mounting the first passive electrical element over the semiconductor package such that the discrete passive electrical element overlaps the semiconductor package.

21. The method of claim 20, wherein, Forming the first electrical connection comprises providing a first electrically conductive connector extending vertically between a first one of the upper contact pads and a lower surface of the first passive electrical element, wherein the first electrically conductive connector mechanically supports the first electrical connection, and electrically connects the first terminal of the first electrically conductive connector to the first one of the upper contact pads, and wherein the first one of the upper contact pads is electrically connected to the first one of the lower contact pads via the interposer.

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