Silicon carbide power device with integrated resistors and corresponding manufacturing process

Abstract

Silicon carbide power devices with integrated resistors and corresponding manufacturing processes are disclosed. A silicon carbide power device has a die with a functional layer of silicon carbide and a border region and an active region surrounded by the border region; a gate structure formed on a top surface of the functional layer in the active region; and a gate contact pad for biasing the gate structure. The device further has an integrated resistor with a doped region of a first conductivity type arranged at a front surface of the functional layer in the border region; wherein the integrated resistor defines an insulating resistance in the functional layer between the gate structure and the gate contact pad.

Description

Technical Field

[0001] This disclosure relates to silicon carbide power devices with integrated resistors and corresponding manufacturing processes. Background Technology

[0002] Electronic semiconductor devices are known, particularly MOSFET (metal-oxide-semiconductor field-effect transistor) transistors used in power electronics applications, which are manufactured from silicon carbide substrates.

[0003] These devices are advantageous due to the favorable chemical and physical properties of silicon carbide. For example, silicon carbide generally has a wider bandgap than silicon, which is commonly used in electronic devices. Therefore, even with relatively small thicknesses, silicon carbide has a higher breakdown voltage than silicon, and is thus advantageous for high-voltage, high-power, and high-temperature applications.

[0004] In particular, silicon carbide with hexagonal polymorphism (4H-SiC) can be used for power electronics applications due to its crystal quality and large-scale availability. Summary of the Invention

[0005] This solution provides a technique for manufacturing silicon carbide power devices with integrated resistors and improved characteristics.

[0006] Therefore, this solution provides silicon carbide devices and corresponding manufacturing processes. Attached Figure Description

[0007] To better understand this disclosure, preferred embodiments of the disclosure will now be described by way of non-limiting example and with reference to the accompanying drawings, in which:

[0008] Figure 1A This is a schematic plan view of a portion of a known type of silicon carbide device;

[0009] Figure 1B yes Figure 1A A cross-sectional view of a portion of the device along section line II;

[0010] Figure 2A This is a schematic plan view of a silicon carbide device according to an embodiment of this solution;

[0011] Figure 2B yes Figure 2A A cross-sectional view of a portion of the device along section line II-II;

[0012] Figure 3 and Figure 4 A corresponding cross-sectional view of a portion of a silicon carbide device according to a corresponding embodiment of this solution is shown; and

[0013] Figures 5A-5G yes Figures 2A-2B Cross-sectional view of silicon carbide devices in subsequent steps of the corresponding manufacturing process. Specific Implementation

[0014] When devices (especially MOSFET transistors) are used in high-power applications, many devices are coupled in parallel to reduce the on-state resistance (so-called RON).

[0015] However, this method may lead to an imbalance between parallel devices, resulting in efficiency loss.

[0016] To avoid imbalance, a resistor with an appropriate value can be inserted in series with the gate contact of the MOSFET device to add a controlled resistance when biasing the gate structure of the MOSFET device.

[0017] For example, discrete resistors (i.e., those not manufactured using integration technology within the die of the MOSFET device during manufacturing) can be separately mounted on the printed circuit to which the MOSFET device is coupled.

[0018] For example, a series resistor can be integrated into the die of a MOSFET device, which can be produced by photolithographic definition of the corresponding gate layer in polysilicon near the gate contact pad.

[0019] Introducing series resistance via discrete resistors before the gate contact has the following drawbacks: higher manufacturing costs and efficiency losses.

[0020] Imagine a solution that adds photolithographically defined polysilicon resistors between the produced wafers and is subject to high diffusion as the operating temperature changes.

[0021] As will be described in detail herein, one aspect of this solution envisions using the characteristics of the silicon carbide device manufacturing process for the integrated manufacturing of the aforementioned series resistors.

[0022] In some embodiments, considering that the activation of the doped region implanted in the silicon carbide substrate is carried out at a high temperature (about 1800°C) that is incompatible with any material produced on the substrate itself, the implanted doped region is produced before defining the active region and forming the gate structure and the corresponding contact structure and metallization.

[0023] Because of this characteristic, the doped region can be located virtually anywhere desired within the silicon carbide substrate.

[0024] According to one aspect of this solution, this feature will be utilized to arrange appropriately doped regions within the silicon carbide substrate that provide insulation resistance at the edge region of the device.

[0025] In some embodiments, the resistor is used as an integrated series resistor inserted before the gate contact of the device.

[0026] refer to Figure 1A and 1B First, a silicon carbide device is shown (in schematic and simplified plan views and in corresponding cross-sectional views, respectively), which in some embodiments is a standard type of power MOSFET device without the aforementioned integrated series resistor; in a manner not shown here, the series resistor is, for example, a discrete component on a printed circuit board to which the MOSFET device is coupled.

[0027] The power MOSFET device, represented by 1, is fabricated in a die 2, which comprises a semiconductor material including silicon carbide. In a plan view, die 2 has an overall rectangular or square shape in the horizontal plane xy, with its edges and corners corresponding to so-called scribbled lines (one of which is in…). Figure 1A (Indicated by LT), at the marked line, the starting wafer of the semiconductor material has been cut.

[0028] The die 2 includes a silicon carbide (SiC) functional layer 4 (substrate or epitaxial layer formed on the same substrate layer), the functional layer having a first conductivity type (e.g., N-type) and having a top surface 4a.

[0029] The peripheral or edge region 2a adjacent to the scribing line LT is defined in functional layer 4 and is designed to accommodate the edge termination structure of the power MOSFET device 1; the central or active region 2b is also defined in functional layer 4, wherein the power MOSFET device 1 is physically manufactured, comprising, for example, multiple basic units or cells 3, which in some embodiments are MOSFET transistors (for simplicity, ...). Figure 1B Only one of these basic units 3 is shown in the image.

[0030] In the case of a vertical conduction configuration, the functional layer 4 constitutes a drain region shared by multiple basic units 3 for forming a power MOSFET device 1.

[0031] The aforementioned edge termination structure includes an annular edge termination region 5 (hereinafter simply referred to as an annular region 5), which in some embodiments is a region of the second conductivity type, doped with a low concentration of P-type, formed in the surface portion of the functional layer 4. The annular region 5 is formed in the edge region 2a and completely surrounds the active region 2b (precisely forming a ring around the active region).

[0032] A body well 6 of the second conductivity type with P-type is disposed in the active region 2b and on the surface portion of the functional layer 4. A body well is used for a basic unit 3 of the power MOSFET device 1.

[0033] Within each body well 6, a source region 8 is formed, having an N-type first conductivity type, and is arranged below the corresponding gate structure 3'; and a doped enrichment region 7 is also formed, which is P-type. + The type (with high dopant concentration) is designed to provide electrical contacts toward the common body and source metallization of the power MOSFET device 1.

[0034] In some embodiments, in the overlapping region between the active region 2b and the edge region 2a, the outermost volume trap (represented by 6′) is connected to P. + The doped connection region 9 (also highly doped) is connected to the ring region 5.

[0035] Furthermore, on the front surface 4a of the functional layer 4, the power MOSFET device 1 includes: a first thin dielectric layer 12 (e.g., made of silicon oxide), from which the gate oxide region of the basic unit 3 of the power MOSFET device 1 is formed in the active region 2b; and a thick oxide region 13, at the edge region 2a, on the annular region 5.

[0036] A gate layer 14 (of polysilicon or other conductive material) existing on the first dielectric layer 12 and the thick oxide region 13 is defined on the gate oxide region to provide the electrode region of the gate structure (denoted by 3') of the basic unit 3 of the power MOSFET device 1. The gate layer 14 extends continuously on the thick oxide region 13 in the edge region 2a.

[0037] A second dielectric layer 15 (e.g., field oxide) covers the gate layer 14. The second dielectric layer 15 has an opening 15′ at the edge region 2a and is covered by gate contact pads 18 made of metallic material, which contact the gate layer 14 through these openings 15′. The gate contact pads 18 can be externally contacted from the power MOSFET device 1 and electrically coupled to the gate wire 17 by soldering for biasing and transmitting signals from and toward the gate structure 3′ of the power MOSFET device 1.

[0038] Furthermore, the second dielectric layer 15 and the aforementioned first dielectric layer 12 overlap and intersect each other in the active region 2b through the source metallization portion 16, which extends to contact and short-circuit the source regions 8 of the body well 6 and the various basic units 3 of the power MOSFET device 1.

[0039] In some embodiments, contact region 19 (e.g., silicide) provides electrical contact between the source metallization portion 16 and the source region 8 and body well 6.

[0040] In some embodiments, such as Figure 1AAs shown, the power MOSFET device also includes a gate metallization 20, which is connected to the gate contact pad 18 at the edge region 2a and has a linear extension in the active region 2b (in this example, along the first axis x of the horizontal plane xy), wherein the gate metallization contacts the gate structure 3' of the basic unit 3 intersecting with the second dielectric layer 15 (in a manner not shown in detail, the basic unit 3 typically has an extension orthogonal to the linear extension of the gate metallization 20, in this example, along the second axis y of the horizontal plane xy).

[0041] refer to Figure 2A and Figure 2B Now (again with the above) Figure 1A and Figure 1B Similar schematic and simplified plan and cross-sectional views show silicon carbide devices, in some embodiments of which power MOSFET devices (denoted here as 100) have an integrated series resistor before the gate contact.

[0042] The power MOSFET device 100 is typically fabricated in a manner corresponding to the power MOSFET device 1 described above (therefore the corresponding elements are indicated by the same reference numerals), but the difference is that the power MOSFET device 100 includes an integrated resistor 30 at and within the edge region 2a, between the gate contact pad 18 and the gate structure 3' (arranged in series with the gate contact pad 18).

[0043] In detail, the integrated resistor 30 is defined by a doped region 32, which, in the N+ type (with a high dopant concentration) example, is generated, for example, by injecting dopant atoms at the front surface 4a of the functional layer 4.

[0044] like Figure 2A As shown, in one possible embodiment, in a plan view (in the horizontal plane xy above), the doped region 32 may have an annular structure with a horizontal extension surrounding the gate contact pad 18.

[0045] exist Figure 2B In the illustrated embodiment, the doped region 32 is formed within an insulating well 34. In this example, P-type dopant (similar to the bulk well 6 described above) is sequentially arranged within the annular region 5. In the illustrated embodiment, the thickness of the insulating well 34 (along the axis z orthogonal to the horizontal plane xy described above) is less than the corresponding thickness of the annular region 5.

[0046] According to one aspect of this solution, in this case, the gate contact pad 18 is not in direct contact with the gate layer 14, and the gate contact pad 18 is not directly connected to the gate metallization portion 20.

[0047] In some embodiments, the gate contact pad 18 contacts the first end of the integrated resistor 30 and the corresponding doped region 32 through a corresponding first contact region 36a of silicide within an opening 13' created by the thick oxide region 13.

[0048] The second end of the integrated resistor 30 and the corresponding doped region 32 are electrically connected to the gate metallization 20 via, for example, a corresponding second contact region 36b of silicide arranged in the opening 13'.

[0049] In this case, the gate metallization 20 contacts the gate layer 14 through a single opening 15' through the second dielectric layer 15 (in the illustrated embodiment).

[0050] In this configuration, the gate wire 17 also contacts the gate contact pad 18. However, beneath the gate contact pad, there is no gate layer 14; instead, only the second dielectric layer 15 and the thick oxide region 13 exist. In other words, the entire horizontal extension of the gate contact pad 18 is directly disposed on the dielectric region formed by the thick oxide region 13 and the second dielectric layer 15.

[0051] In fact, in this embodiment, the gate layer 14 stops at the initial region of the edge region 2a before the second end of the integrated resistor 30.

[0052] Furthermore, in this case, the gate contact pad 18 and the gate metallization portion 20 are electrically insulated and separated on the top surface 4a of the substrate 4 through the separation portion 38 of the second dielectric layer 15.

[0053] In this embodiment, the resistance value of the integrated resistor 30 may, for example, be in the range of 0.1Ω to 200Ω.

[0054] like Figure 3 As shown, a variant embodiment of the power MOSFET device 100 envisions that the aforementioned doped region 32 of the integrated resistor 30 is formed in a region having P + The highly doped connection region 9 is formed within the aforementioned doped region 9 rather than in the corresponding well, and this doped connection region connects the outermost body well 6' to the annular region 5.

[0055] In this case, the doped connection region 9 extends within the annular region 5 (in this example, along the first axis x) until it reaches the region dedicated to forming the integrated resistor 30.

[0056] In this embodiment, the resistance value of the integrated resistor 30 can be higher than 200Ω.

[0057] like Figure 4 As shown, another variant embodiment of the power MOSFET device 100 envisions the doped region 32 of the integrated resistor 30 being formed directly in the annular region 5, without the presence of a dedicated well.

[0058] In this embodiment, the resistance value of the integrated resistor 30 may, for example, be in the range of 0.001Ω and 0.1Ω.

[0059] First refer to Figure 5A The possible manufacturing process of the power MOSFET device 100 is now described, with particular reference to Figure 2A and 2B The illustrated embodiments (however, as will be apparent, can be considered similarly) Figure 3 and Figure 4 (Example).

[0060] This manufacturing process deviates from the standard process flow, for example... Figure 1A and Figure 1B The process flow shown in the figure for manufacturing the power MOSFET device 1 forms the aforementioned integrated resistor 30 in the edge region 2a without requiring substantial changes to the process flow.

[0061] In detail, such as Figure 5A As shown, a P-type volume implant is first formed through a front mask 40 and then appropriately patterned using photolithography to form a volume trap 6 in the active region 2b within the functional layer 4, including the outermost volume trap 6′ designed to connect to the annular region 5 (to be formed later).

[0062] According to one aspect of this solution, during the implantation step and through the front mask 40, an insulating well 34 with P-type doping (similar to the volume well 6 described above) is also formed in the edge region 2a.

[0063] Then, in Figure 5B Through the front mask 40, using different appropriate patterning, an N+ type source injector is formed to set the source region 8 in the active region 2b within the corresponding volume trap 6.

[0064] According to one aspect of this solution, during the implantation step and through the front mask 40, a doped region 32 of the integrated resistor 30 is also formed in the edge region 2a (in this case, within the insulating trap 34).

[0065] Next, in Figure 5C Through the front mask 40, using different appropriate patterning, a P+ type implant (with higher doping than the body well 6) is formed to provide an enriched doped region 7 in the corresponding body well 6 in the active region 2b, and also to form a doped connection region 9 between the active region 2b and the edge region 2a.

[0066] Then, in Figure 5DBy using a front mask 40 and different appropriate patterning, a P-type implant with low doping (less than the doping of the body well 6) is formed to provide an annular region 5. According to this solution, the annular region surrounds the aforementioned insulating well 34 in the edge region 2a, and the doped region 32 of the integrated resistor 30 is formed in the insulating well.

[0067] Therefore, the manufacturing process proceeds with the removal of the front mask 40 and the activation of the previously implanted dopant, and in some embodiments, is heated at a high temperature (approximately 1800°C).

[0068] Next, as Figure 5E As shown, the gate structure 3′ of the basic unit 3 of the power MOSFET device 1 is formed in the active region 2b by forming and appropriately photolithographically patterning the first dielectric layer 12, the gate layer 14, and the second dielectric layer 15. A silicide contact region 19 is also formed within each body well 6.

[0069] According to one aspect of this solution, during the same process step, at the edge region 2a, the thick oxide region 13 and the subsequent gate layer 14 and second dielectric layer 15 are photolithographically defined to form an opening 13'; within this opening 13', a first contact region 36a and a second contact region 36b, also made of silicide, are formed, which respectively contact the first end and the second end of the doped region 32. The first contact region 36a and the second contact region 36b are separated and electrically insulated by the separation portion 38 of the aforementioned second dielectric layer 15.

[0070] Next, in Figure 5F Through photolithography, before the second contact area 36b, at the beginning of the edge area 2a, a single opening 15' is defined through the second dielectric layer 15 to approach the underlying gate layer 14.

[0071] Then, in Figure 5G The manufacturing method continues to deposit a metal layer (e.g., an aluminum-silicon-copper alloy (AlSiCu)) and perform photolithographic definition for forming the gate contact pad 18, the source metallization 16, and the gate metallization 20.

[0072] This results in the formation of a power MOSFET device 100, such as Figure 5G and the above Figure 2A and Figure 2B As shown.

[0073] The advantages of this solution are obvious from the preceding description.

[0074] In any case, it is emphasized again that this solution allows for improved efficiency, performance, and reliability of power devices, in some embodiments of which are MOSFET transistors fabricated from silicon carbide substrates.

[0075] Specifically, this solution allows for an integrated resistor connected in series with the gate contact, having a very precise and controllable resistance value controlled by the characteristics of the implanted N-type silicon carbide. In some embodiments, temperature characteristics are controlled by very stable physical properties.

[0076] This resistance value also exhibits very low variation from die to die and relative to manufacturing batch.

[0077] Advantageously, the resistance value can be precisely adjusted according to the geometry of the doped region 32; for example, the doped region 32 may not have a completely ring-shaped structure, such as... Figure 2A As shown, the resistance value can be limited to certain portions of the ring. Furthermore, as previously indicated, this resistance value can be adjusted by changing the confinement and insulation arrangement of the doped region 32 in regions with low or high dopant concentrations (so that it has low or high resistance values ​​respectively, as previously referenced). Figure 3 and Figure 4 (as emphasized by the variant).

[0078] Advantageously, this solution requires no additional steps in the manufacturing process, as it only requires limited modifications to the steps of a standard type of manufacturing process.

[0079] Furthermore, the possibility of coupling the gate line 17 to the gate contact pad 18 in areas without underlying polysilicon (thus limiting defects in the gate layer 14) is advantageous.

[0080] Therefore, the resulting MOSFET transistor devices manufactured according to this solution can be advantageously used in a variety of applications, such as in power supplies and UPS with power factor correction (PFC), in photovoltaic systems, energy distribution systems, industrial engines, and electric vehicles.

[0081] Finally, it is clear that modifications and variations may be made to the content described and shown herein without departing from the scope of this disclosure as defined in the appended claims.

[0082] In some embodiments, it should be emphasized that this solution can be advantageously used in various silicon carbide MOSFET transistor devices, such as VDMOS signal or power devices, IGBTs (including MOSFET transistors), and IP (intelligent power) MOSFET devices, for example, in automotive applications, typically in both N-channel and P-channel MOSFET transistors.

[0083] A silicon carbide power device (100) can be summarized as including a silicon carbide functional layer (4) including an edge region (2a) and an active region (2b) surrounded by the edge region (2a); a gate structure (3′) formed on the top surface (4a) of the functional layer (4) in the active region (2b); and a gate contact pad (18) for biasing the gate structure (3′), characterized in that it further includes an integrated resistor (30) including a doped region (32) of a first conductivity type (N+) disposed at the front surface (4a) of the functional layer (4) in the edge region (2a), wherein the integrated resistor (30) is configured to define an insulation resistance in the functional layer (4) between the gate contact pad (18) and the gate structure (3′).

[0084] The gate contact pad (18) may be disposed at the edge region (2a) and electrically contact the first end of the doped region (32) through the corresponding first contact region (36a); in addition, it may include a gate metallization portion (20), which may be configured to contact the gate structure (3') in the active region (2b) and electrically contact the second end of the doped region (32) through the corresponding second contact region (36b).

[0085] The device may include an edge termination region (5) in the edge region (2a), which is composed of a doped region having a second conductivity type (P) and a first doping level and is arranged near the top surface (4a) of the functional layer (4).

[0086] The doped region (32) can be confined within an insulating well (34) having a second conductivity type (P) and a second doping level higher than the first doping level; the insulating well (34) is arranged within an edge termination region (5).

[0087] The doped region (32) can be confined within the edge termination region (5).

[0088] The device may further include: a body well (6) having a second conductivity type formed within the functional layer (4) in the active region (2b); wherein the annular region (5) can be connected to the body well (6') which is further outward and closer to the edge region (2a) relative to the active region (2b) via a doped connection region (9); the doped connection region (9) has the second conductivity type and a third doping level higher than the first doping level; wherein the doped region (32) can be confined within the doped connection region (9).

[0089] The device may include an external dielectric region (13, 15) disposed on the front surface (4a) of the functional layer (4) at an edge region (2a); wherein an opening (13′) may intersect with the external dielectric region (13, 15), and the first contact region and the second contact region (36a, 36b) may be electrically separated from each other at the opening (13′).

[0090] The entire horizontal extension of the gate pad (18) can be directly arranged on the outer dielectric region (13, 15).

[0091] The device may include a conductive gate layer (14) that is connected to the gate structure (3') in the active region (2b) and extends to the edge region (2a) and terminates before the opening (13').

[0092] The doped region (32) may have an annular extension around the gate pad (18) in a horizontal plane (xy) parallel to the front surface (4a) of the functional layer (4).

[0093] The device may include a plurality of MOSFET transistor basic units (3) arranged in the active region (2b), each basic unit may include a corresponding gate structure in the gate structure (3′), a corresponding body well (6) having a second conductivity type formed in the functional layer (4), and at least one corresponding source region (8) having the first conductivity type formed in the body well (6) below the corresponding gate structure (3′).

[0094] A process for manufacturing a silicon carbide power device (100) can be summarized as including: forming a silicon carbide functional layer (4) including an edge region (2a) and an active region (2b) surrounded by the edge region (2a); forming a gate structure (3′) on the top surface (4a) of the functional layer (4) in the active region (2b); forming a gate contact pad (18) for biasing the gate structure (3′), characterized in that it further includes forming an integrated resistor (30) including a doped region (32) of a first conductivity type (N+) disposed at the front surface (4a) of the functional layer (4) in the edge region (2a), the integrated resistor (30) defining an insulation resistance in the functional layer (4) between the gate contact pad (18) and the gate structure (3′).

[0095] Forming an integrated resistor (30) may include: implanting a dopant of a first conductivity type (N+) to form a doped region (32); and thermally activating the dopant prior to forming a gate structure (3').

[0096] The process may include forming a body well (6) having a second conductivity type (P) and a first doping level within a functional layer (4) in an active region (2b), and forming a source region (8) having a first conductivity type below a corresponding gate structure (3′) within the body well (6); wherein the doped region (32) and the source region (8) may be formed in the same dopant implantation step.

[0097] Forming the doped region (32) may include forming the doped region such that it is confined within an insulating well (34) having the second conductivity type (P); wherein the insulating well (34) and the body well (6) may be formed in the same respective dopant implantation step.

[0098] The process may further include forming an edge termination region (5) in the edge region (2a), the edge termination region being composed of a doped region disposed near the top surface (4a) of the functional layer (4) having the second conductivity type (P) and a second doping level lower than the first doping level.

[0099] Forming a doped region (32) may include forming the doped region such that it is confined within the edge termination region (5).

[0100] The process may also include forming a doped connection region (9) having a second conductivity and a third doping level higher than the first doping level, for connecting the annular region (5) to a body well (6') that is further outward and closer to the edge region (2a) relative to the active region (2b); wherein forming the doped region (32) may include forming the doped region such that it is confined within the doped connection region (9).

[0101] The process may include forming a gate contact pad (18) at an edge region (2a); wherein forming the gate contact pad (18) may include electrically contacting a first end of a doped region (32) through a corresponding first contact region (36a); furthermore, it may include forming a gate metallization (20) configured to contact the gate structure (3') at an active region (2b) and contact a second end of the doped region (32) through a corresponding second contact region (36b).

[0102] The process may include: forming an outer dielectric region (13, 15) on the front surface (4a) of the functional layer (4) at the edge region (2a); and forming an opening (13') through the outer dielectric region (13, 15), wherein a first contact region and a second contact region (36a, 36b) are electrically separated from each other at the opening (13').

[0103] The various embodiments described above can be combined to provide other embodiments. If desired, aspects of the embodiments can be modified to employ the concepts of various embodiments to provide additional embodiments.

[0104] In view of the above detailed description, these and other changes may be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents conferred by these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A silicon carbide power device, comprising: A silicon carbide layer, including an edge region and an active region surrounded by the edge region; A gate structure is formed on the first surface of the silicon carbide layer in the active region; A resistor, comprising a first doped region of a first conductivity type disposed at the first surface of the silicon carbide layer in the edge region; The gate contact pad is configured to bias the gate structure. The resistor is located between the gate contact pad and the gate structure; The gate contact pad is disposed at the edge region and electrically contacts the first end of the first doped region through the first contact region; and The device further includes a gate metallization portion that is electrically contacted with the gate structure in the active region, the gate metallization portion being contacted with a second end of the first doped region through a second contact region; The first doped region has an annular extension surrounding the gate contact pad in a horizontal plane parallel to the first surface of the silicon carbide layer.

2. The device of claim 1, further comprising an edge termination region in the edge region, the edge termination region comprising a second doped region having a second conductivity type and a first doping level near the first surface of the silicon carbide layer.

3. The device of claim 2, wherein the first doped region is defined within an insulating well having the second conductivity type and a second doping level higher than the first doping level, the insulating well being located within the edge termination region.

4. The device of claim 2, wherein the first doped region is located within the edge termination region.

5. The device according to claim 2, further comprising: In the active region, a volume well having the second conductivity type is formed within the silicon carbide layer; as well as A third doped region is located between and adjacent to each of the edge-terminating regions and the body wells that are further outward from the active region and closer to the edge region. The third doped region has the second conductivity type and a third doping level higher than the first doping level. The first doped region is confined within the third doped region.

6. The device according to claim 1, comprising: An external dielectric region is disposed on the first surface of the silicon carbide layer at the edge region; as well as An opening that extends perpendicularly through the outer dielectric region. The first contact area and the second contact area are arranged in the opening, and the first contact area and the second contact area are electrically separated from each other.

7. The device of claim 6, wherein the gate contact pad is located directly on the outer dielectric region and overlaps the entire horizontal extension of the outer dielectric region.

8. The device of claim 6, further comprising a conductive gate layer connected to the gate structure in the active region and extending to the edge region, and terminating before the opening.

9. The device of claim 1, comprising a MOSFET transistor basic unit in the active region, the MOSFET transistor basic unit comprising the gate structure, a body well having a second conductivity type formed within the silicon carbide layer, and a source region having the first conductivity type formed below the gate structure and within the body well.

10. A method for manufacturing a silicon carbide power device, comprising: A silicon carbide layer is formed, the silicon carbide layer including an edge region and an active region surrounded by the edge region; A gate structure is formed on the first surface of the silicon carbide layer in the active region; A gate contact pad is formed, the gate contact pad being configured to bias the gate structure; as well as A resistor comprising a doped region of a first conductivity type is formed at the first surface of the silicon carbide layer in the edge region and between the gate contact pad and the gate structure; The gate contact pad is formed at the edge region and electrically contacts the first end of the doped region through the first contact region; and The method further includes: A gate metallization portion is formed, which is electrically contacted with the gate structure in the active region and contacts the second end of the doped region through a second contact region; The doped region has an annular extension around the gate contact pad in a horizontal plane parallel to the first surface of the silicon carbide layer.

11. The method of claim 10, wherein forming the resistor comprises: The implantation of a dopant of the first conductivity type is performed to form the doped region; as well as The dopant is thermally activated before the gate structure is formed.

12. The method of claim 10, comprising: A volume well having a second conductivity type and a first doping level is formed within the silicon carbide layer in the active region. as well as A source region having the first conductivity type is formed within the body well and below the corresponding gate structure. The doped region and the source region are formed in the same dopant implantation step.

13. The method of claim 12, wherein forming the doped region comprises: The doped region is formed within an insulating well containing a dopant of the second conductivity type, wherein the insulating well and the body well are formed in the same dopant implantation process.

14. The method of claim 12, further comprising forming an edge termination region in the edge region, the edge termination region comprising a dopant of the second conductivity type, a second doping level lower than the first doping level, and close to the first surface of the silicon carbide layer.

15. The method of claim 14, wherein forming the doped region comprises forming the doped region within the edge termination region.

16. The method of claim 14, further comprising forming a doped connection region having the second conductivity and a third doping level higher than the first doping level, the doped connection region being adjacent to the edge termination region and the body well in the body well positioned further outward and closer to the edge region relative to the active region. The formation of the doped region includes forming the doped region within the doped connection region.

17. A silicon carbide power device, comprising: The silicon carbide layer includes an active region and an edge region surrounding the active region; A transistor, in the active region, the transistor includes a gate structure on a first surface of the silicon carbide layer in the active region; A resistor, in the edge region, includes a doped region of a first conductivity type adjacent to the first surface of the silicon carbide layer; as well as A gate contact pad, wherein the resistor is coupled between the gate contact pad and the gate structure; The gate contact pad is disposed at the edge region and electrically contacts the first end of the doped region through the first contact region; and The device further includes a gate metallization portion that is electrically contacted with the gate structure in the active region, the gate metallization portion being contacted with the second end of the doped region through a second contact region; The doped region has an annular extension around the gate contact pad in a horizontal plane parallel to the first surface of the silicon carbide layer.

18. The device of claim 17, comprising: A first contact structure is coupled between the doped region and the gate structure; A second contact structure is coupled between the doped region and the gate contact pad; as well as A dielectric layer separates the first contact structure from the second contact structure. Each of the first contact structure, the second contact structure, and the dielectric layer extends over the doped region.

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