Three-dimensional memory devices with drain-select gate cutouts and methods of forming and operating the same

Abstract

Embodiments of 3D memory devices and methods of forming and operating the same are disclosed. In an example, a 3D memory device includes a memory stack, a plurality of memory strings, a plurality of bit line contacts each in contact with a respective one of the plurality of memory strings. The memory stack includes interleaved conductive layers and dielectric layers. Each of the memory strings extends vertically through the memory stack. The conductive layers include a plurality of drain select gate (DSG) lines configured to control drains of the plurality of memory strings. The plurality of memory strings is divided into a plurality of regions that are the smallest repeating units of the memory stack in a plan view. Each of the plurality of memory strings is adjoined to at least one of the DSG lines.

Description

[0001] This application is a divisional application. The original application was filed with the China Patent Office on July 23, 2020 (international filing date was June 12, 2020), with application number 202080001331.0 and invention title "Three-dimensional memory device with drain-selective gate notch and method of forming and operating thereof". Background Technology

[0002] Embodiments of this disclosure relate to three-dimensional (3D) memory devices and methods of manufacturing and operating thereof.

[0003] Planar memory cells can be scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells is approaching its upper limit.

[0004] 3D memory architecture can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention

[0005] This invention discloses embodiments of 3D memory devices and methods for their formation and operation.

[0006] In one example, a 3D memory device includes a memory stack layer, a plurality of memory strings, and a plurality of bit line contacts, each bit line contacting a corresponding memory string among the plurality of memory strings. The memory stack layer includes staggered conductive and dielectric layers. Each memory string extends vertically through the memory stack layer. The conductive layers include a plurality of drain-select-gate (DSG) lines configured to control the drains of the plurality of memory strings. In a planar view, the plurality of memory strings are divided into multiple regions, which are the smallest repeating units of the memory stack layer. Each of the plurality of memory strings is adjacent to at least one of the DSG lines.

[0007] In another example, a method for forming a 3D memory device is disclosed. A dielectric stack layer including interleaved sacrificial layers and dielectric layers is formed over a substrate. A first channel structure and a second channel structure are formed, both extending vertically through the dielectric stack layer. A portion of the uppermost sacrificial layer in the sacrificial layer and the top portion of the removed portion of the uppermost sacrificial layer of the second channel structure are removed, such that the first channel structure extends vertically through a first region of the dielectric stack layer including the remaining portion of the uppermost sacrificial layer, and the remaining portion of the second channel structure extends vertically through a second region of the dielectric stack layer without the uppermost sacrificial layer.

[0008] In another example, a method for operating a 3D memory device is disclosed. A 3D memory device is provided, comprising a first memory string, a second memory string, a first drain-select-gate (DSG) line adjacent to the first memory string at a first cell, and second DSG lines adjacent to the first and second memory strings at second and third cells, respectively. Threshold voltages for the first, second, and third cells are set such that the threshold voltage of the first cell is higher than the threshold voltage of the second cell, and the threshold voltage of the third cell is higher than the threshold voltage of the second cell. The first voltage and the second voltage are applied to the first and second DSG lines, respectively, such that when the first voltage is higher than the threshold voltage of the first cell, and the second voltage is higher than the threshold voltage of the second cell but lower than the threshold voltage of the third cell, the first memory string is selected and the second memory string is deselected. Attached Figure Description

[0009] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the present disclosure and, together with the textual description, further serve to explain the principles of the present disclosure and to enable those skilled in the art to make and use the present disclosure.

[0010] Figure 1A and Figure 1B A plan view and a side view of a cross-section of a 3D memory device with a DSG notch are shown.

[0011] Figure 2A and Figure 2B Plan view and cross-sectional side view of an exemplary 3D memory device with a DSG notch according to some embodiments of the present disclosure are shown.

[0012] Figure 3A and Figure 3B A plan view and a side view of a cross section of another exemplary 3D memory device with a DSG notch according to some embodiments of the present disclosure are shown.

[0013] Figure 4A A side view of a cross-section of yet another exemplary 3D memory device with a DSG notch, according to some embodiments of the present disclosure, is shown.

[0014] Figure 4B A side view of a cross-section of yet another exemplary 3D memory device with a DSG notch, according to some embodiments of the present disclosure, is shown.

[0015] Figure 5A and Figure 5B A plan view and a side view of a cross section of another exemplary 3D memory device with a DSG notch according to some embodiments of the present disclosure are shown.

[0016] Figures 6A-6FThe present disclosure illustrates a manufacturing process for forming an exemplary 3D memory device with DSG notches according to some embodiments of the present disclosure.

[0017] Figures 7A-7H Manufacturing processes for forming other exemplary 3D memory devices with DSG notches are illustrated according to some embodiments of the present disclosure.

[0018] Figure 8 A flowchart is shown of a method for forming an exemplary 3D memory device with DSG notches according to some embodiments of the present disclosure.

[0019] Figure 9 A flowchart is shown of a method for forming another exemplary 3D memory device with DSG notches according to some embodiments of the present disclosure.

[0020] Figure 10 A flowchart is shown of a method for operating an exemplary 3D memory device with a DSG notch, according to some embodiments of the present disclosure.

[0021] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0022] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used for a variety of other applications.

[0023] Note that references to "an embodiment," "an embodiment," "an example embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0024] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0025] It should be readily understood that the meanings of “above,” “on top,” and “above” in this disclosure should be interpreted in the broadest sense, such that “above” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “on top” or “above” means not only “above” or “above” something but also includes “above” or “above” something without an intermediate feature or layer therebetween (i.e., directly on something).

[0026] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and another element(s)(s)(s) as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and accordingly, the spatial relative descriptors used herein may be interpreted similarly.

[0027] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or left unpatterned. Furthermore, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may also be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0028] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire upper or lower structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnects, and / or via contacts are formed) and one or more dielectric layers.

[0029] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter for component or process operation set during the design phase of a product or process, and a range of values ​​higher and / or lower than the expected value. This range of values ​​may arise due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a given quantity value that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate a given quantity value that varies, for example, within 10%–30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0030] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND memory strings) on a laterally oriented substrate, such that the memory strings extend vertically relative to the substrate. As used herein, the term "vertically / perpendicularly" refers to nominally perpendicular to the lateral surface of the substrate.

[0031] In some 3D memory devices (e.g., 3D NAND memory devices), DSG cutouts (e.g., Top Select Gate (TSG) cutouts) can be used to further divide each memory block into multiple regions (e.g., fingers) for better control of the memory cells within the memory block. NAND memory strings divided into different regions by the TSG cutouts can be individually selected or deselected, allowing various operations to be performed in desired areas (e.g., fingers) of the 3D NAND memory device.

[0032] Figure 1A and Figure 1B A plan view and a side view of a cross-section of a 3D memory device 100 with a DSG notch are shown. Note that... Figure 1AThe diagram includes an x-axis and a y-axis to show two orthogonal directions in the wafer plane. The x-direction is the word line direction, and the y-direction is the bit line direction. The 3D memory device 100 includes a memory block 102 having a plurality of memory strings 110. In the plan view, the memory block 102 represents the smallest repeating unit of the memory stack layer 122 of the 3D memory device 100. The memory stack layer 122 includes a plurality of smallest repeating units (e.g., memory block 102). It should be understood that the smallest repeating unit can be referred to by any suitable term other than "memory block" as used herein. Figure 1A As shown, the 3D memory device 100 includes a DSG cutout 108 extending laterally in the x-direction (word line direction), which divides the memory block 102 into two memory fingers 104, such that the memory strings 110 in the different memory fingers 104 can be selected or deselected individually.

[0033] like Figure 1B As shown, it is a 3D memory device 100 along Figure 1A A side view of a cross-section of the AA plane, the 3D memory device 100 includes a memory stack layer 122 above a substrate 120. Note that... Figure 1B The x, y, and z axes are included to further illustrate the spatial relationships of components in the 3D memory device 100. The substrate 120 includes two lateral surfaces extending laterally in the xy plane: a top surface on the front side of the wafer, on which the 3D memory device 100 may be formed; and a bottom surface on the back side of the wafer opposite the front side. The z-axis is perpendicular to the x and y axes. As used herein, when the substrate (e.g., substrate 120) of a semiconductor device (e.g., 3D memory device 100) is positioned in the lowest plane of the semiconductor device in the z-direction (a direction perpendicular to the xy plane), the z-direction relative to the substrate determines whether one component (e.g., layer or device) of the semiconductor device is “on,” “above,” or “below” another component (e.g., layer or device). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0034] The memory stack layer 122 includes a conductive layer 126 and a dielectric layer 124 that are vertically interleaved in the z-direction. The conductive layer 126 includes DSG lines 128 and 130 (e.g., the uppermost conductive layer separated by DSG notches 108), which are configured to control the drain of the memory string 110 in the corresponding memory fingers 104. The conductive layer 126 also includes a source select gate (SSG) line 132 (sometimes referred to as a bottom select gate (BSG), e.g., Figure 1B (The lowest conductive layer in the memory), SSG line 132 is configured as the common source of the memory string 110 in the memory block 102. For example... Figure 1BAs shown, each memory string 110 includes a channel structure 134 and a channel plug 136 above and in contact with the channel structure 134. The 3D memory device 100 also includes a plurality of bit line contacts 140 and a plurality of bit lines 142, each bit line contact 140 above and in contact with a corresponding channel plug 136 of the memory string 110, and each bit line 142 above and in contact with a corresponding bit line contact 140. Therefore, each memory string 110 is a functional memory string because its drain is electrically connected to a corresponding bit line 142 via a corresponding bit line contact 140 for individual addressing, and it is adjacent to DSG lines 128 or 130 to control its drain. Conversely, the 3D memory device 100 also includes a plurality of dummy memory strings 112, which are inactive due to the DSG cutout 108. Figure 1B As shown, the dummy memory string 112 is not adjacent to any DSG line and is not electrically connected to any bit line, and therefore cannot be addressed and controlled.

[0035] The presence of a dummy memory string 112 due to the DSG cutout 108 reduces the effective device area and memory cell density of the 3D memory device 100. Furthermore, since the dummy memory string 112 remains adjacent to the SSG line 132 during read and verify operations, the voltage of the SSG line 132 can be applied to the dummy memory string 112, thereby introducing parasitic capacitance between the conductive layer 126 (e.g., as a word line) and the dummy memory string 112. This can affect the electrical performance of the 3D memory device 100 during read and verify operations.

[0036] 3D memory devices with improved DSG notch layouts and their design, fabrication, and operation methods are provided according to various embodiments of this disclosure. Each memory string in the smallest repeating unit (e.g., a memory block) of the 3D memory device disclosed herein may be adjacent to at least one of the DSG lines and electrically connected to the corresponding bit line to avoid any dummy memory strings caused by the DSG notch. In some embodiments, different numbers of DSG lines are formed in different regions within the smallest repeating unit. In some embodiments, each memory string nominally has the same height to reduce fabrication complexity. By combining the voltage applied to the DSG lines at a desired level, the threshold voltages of various DSG cells in the memory strings of the 3D memory device can be set to desired levels to accommodate the novel device architecture disclosed herein. As a result, the effective device area and memory cell density of the 3D memory device can be increased, and electrical performance can be improved.

[0037] Figure 2A and Figure 2B A plan view and a side view of a cross-section of an exemplary 3D memory device 200 with a DSG notch according to some embodiments of the present disclosure are shown. Figure 2B The 3D memory device 200 is shown. Figure 2A A side view of a cross-section of the BB plane. The 3D memory device 200 may include a substrate 220 and a memory stack layer 222 above the substrate 220. The substrate 220 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some embodiments, the substrate 220 is a thinned substrate (e.g., a semiconductor layer) thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof.

[0038] In some embodiments, 3D memory device 200 is part of a monolithic 3D memory device, wherein components of the monolithic 3D memory device (e.g., memory cells and peripheral devices) are formed on a single substrate (e.g., substrate 220). Peripheral devices (not shown) (e.g., any suitable digital, analog, and / or mixed-signal peripheral circuitry for facilitating the operation of 3D memory device 200) may be formed over memory stack layer 222. In some embodiments, 3D memory device 200 is part of a non-monolithic 3D memory device, wherein components are formed separately on different substrates and then bonded in a face-to-face, face-to-back, or back-to-back manner. Peripheral devices (not shown) may be formed on a separate substrate different from substrate 220. As part of the bonded non-monolithic 3D memory device, substrate 220 may be a thinned substrate (e.g., a semiconductor layer that is not a substrate of the bonded non-monolithic 3D memory device), and back-end process (BEOL) interconnects of the non-monolithic 3D memory device may be formed on the back side of the thinned substrate 220.

[0039] However, the 3D memory device 200 can be part of a monolithic or non-monolithic 3D memory device, regardless of whether the 3D memory device 200 is above or below peripheral devices (not shown). For ease of reference, Figure 2A and Figure 2B A state of 3D memory device 200 is depicted, wherein substrate 220 is positioned below memory stack 222 in the z-direction, regardless of whether substrate 220 is a thinned substrate on which memory stack 222 of 3D memory device 200 can be formed. The same concepts used to describe spatial relationships are applied in this disclosure.

[0040] In some embodiments, the 3D memory device 200 is a NAND flash memory device, wherein the memory cells are provided in the form of an array of NAND memory strings 210, each NAND memory string extending vertically through a memory stack layer 222 above the substrate 220, such as... Figure 2B As shown in the side view. Figure 2AAs shown in the plan view, according to some embodiments, the memory stack layer 222 includes a plurality of regions 204 and 206 as minimum repeating units 202 of the memory stack layer 222, the plurality of regions 204 and 206 including DSG cutout regions 206 and non-DSG cutout regions 204. That is, in the plan view, the 3D memory device 200 may include a plurality of minimum repeating units 202, for example, staggered DSG cutout regions 206 and non-DSG cutout regions 204. In some embodiments, one minimum repeating unit 202 corresponds to a memory block of the 3D memory device 200. In some embodiments, a plurality of minimum repeating units 202 (e.g., two or three minimum repeating units 202) correspond to a memory block of the 3D memory device 200. It should be understood that in some examples, memory blocks may be separated by gate slots (GLS, not shown), each GLS in the word line direction (e.g., Figure 2A The DSG cutout region 206 can also extend laterally parallel to the GLS in the word line direction. The array of memory strings 210 can be divided into regions 204 and 206 of the memory stack layer 222. In some embodiments, the size of the DSG cutout region 206 is nominally the same as the size of the non-DSG cutout region 204, and the number of memory strings 210 in the DSG cutout region 206 is nominally the same as the number of memory strings 210 in the non-DSG cutout region 204. In other words, the memory strings 210 can be uniformly divided into regions 204 and 206 of the memory stack layer 222.

[0041] like Figure 2BAs shown in the side view, the memory stack layer 222 of the 3D memory device 200 may include multiple pairs, each pair including a conductive layer 226 and a dielectric layer 224. That is, according to some embodiments, the memory stack layer 222 includes conductive layers 226 and dielectric layers 224 that are vertically interleaved in the z-direction. The conductive layers 226 and dielectric layers 224 in the memory stack layer 222 may alternate in the vertical direction. The number of pairs of conductive layers 226 and dielectric layers 224 in the memory stack layer 222 (e.g., 32, 64, 96, 128, 144, 160, 176, 192, 208, 224, 240, 256, etc.) determines the number of memory cells in the 3D memory device 200. It should be understood that in some examples, the memory stack layer 222 may have a multi-stack architecture (not shown), which includes multiple memory stacks stacked on top of each other. The number of pairs of conductive layers 226 and dielectric layers 224 in each memory stack may be the same or different. The conductive layer 226 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or any combination thereof. The dielectric layer 224 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0042] In some embodiments, the outermost conductive layer of conductive layer 226 includes multiple DSG lines 228 and 230 and an SSG line 232. The remaining portion of conductive layer 226, vertically positioned between SSG line 232 and DSG lines 228 and 230, may include gate lines extending laterally around memory string 210 as word lines. Figure 2B As shown, according to some embodiments, DSG line 228 is the first uppermost conductive layer, DSG line 230 is the second uppermost conductive layer, and SSG line 232 is the lowermost conductive layer. In some embodiments, each memory string 210 is adjacent to SSG line 232, and SSG line 232 is configured as the common source of the memory strings 210 in the smallest repeating unit 202 of the memory stack layer 222. Since SSG line 232 is Figure 2BThe SSG line 232 is the lowest conductive layer in the matrix, so it is also referred to herein as a BSG line. In some embodiments, each memory string 210 is adjacent to at least one of DSG lines 228 and 230, which are configured to control the drain of the memory string 210. According to some embodiments, each memory string 210 in the non-DSG cutout region 204 is adjacent to both DSG lines 228 and 230, such that the drain of the memory string 210 in the non-DSG cutout region 204 is controlled by both DSG lines 228 and 230. Due to the DSG cutout 208, each memory string 210 in the DSG cutout region 206 is adjacent to DSG line 230 but not to DSG line 228, such that the drain of the memory string 210 in the DSG cutout region 206 is controlled by DSG line 230 but not by DSG line 228. Since DSG lines 228 and 230 are... Figure 2B The uppermost conductive layer in the structure, therefore DSG lines 228 and 230 are also referred to as TSG lines in this paper.

[0043] like Figure 2B As shown, a portion of the DSG line 228 (e.g., the first uppermost conductive layer) in the DSG notch region 206 is removed by the DSG notch 208. That is, the DSG lines 228 and 230 may have different lateral dimensions, for example, in the y-direction (bit line direction). According to some embodiments, the DSG line 230 is a continuous conductive plate extending laterally in the xy plane, while the DSG line 228 is disconnected in the y-direction by the DSG notch 208 at each DSG notch region 206 of the memory stack layer 222 of the 3D memory device 200. As a result, according to some embodiments, the number of DSG lines 228 and 230 in the non-DSG notch region 204 (e.g., 2) is greater than the number of DSG lines 230 in the DSG notch region 206 (e.g., 1). The layout and design of the 3D memory device 200 avoids any dummy memory strings (e.g., ...) resulting from the DSG notches. Figure 1A and Figure 1B (As shown in the diagram). For example, the DSG cutout region 206 of the 3D memory device 200 may not have dummy memory strings, and each memory string 210 in the minimum repeating unit 202 of the memory stack layer 222 may be a functional memory string. Therefore, compared to the 3D memory device 100, the effective device area and memory cell density of the 3D memory device 200 can be increased, and the electrical performance can be improved.

[0044] In some embodiments, the memory strings 210 in the non-DSG cutout region 204 have the same nominal height, and the memory strings 210 in the DSG cutout region 206 also have the same nominal height. According to some embodiments, the height of each memory string 210 in the non-DSG cutout region 204 is greater than the height of each memory string 210 in the DSG cutout region 206. For example, in the vertical direction, the upper end of the memory string 210 in the non-DSG cutout region 204 may be above the DSG line 228 (e.g., the first uppermost conductive layer 226), and the upper end of the memory string 210 in the DSG cutout region 206 may be between the DSG line 228 and the DSG line 230 (e.g., the second uppermost conductive layer 226). That is, according to some embodiments, the memory string 210 in the DSG cutout region 206 does not extend beyond the DSG line 228.

[0045] like Figure 2B As shown, each memory string 210 may include a channel structure 212 and a channel plug 236 at the upper end of the memory string 210. As used herein, when the substrate 220 is positioned in the lowest plane of the 3D memory device 200, the “upper end” of a component (e.g., memory string 210) is the end further away from the substrate 220 in the z-direction, and the “lower end” of a component (e.g., memory string 210) is the end closer to the substrate 220 in the z-direction. The channel structure 212 may include channel holes filled with a semiconductor layer (e.g., as a semiconductor channel) and a composite dielectric layer (e.g., as a memory film). In some embodiments, the semiconductor channel comprises silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the memory film is a composite layer comprising a tunneling layer, a storage layer (also referred to as a “charge trapping layer”), and a barrier layer. The remaining space of the channel structure 212 may be partially or completely filled with a capping layer comprising a dielectric material (e.g., silicon oxide) and / or air gaps. The channel structure 212 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the capping layer, semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar outwards. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof.

[0046] The channel plug 236 may be above and in contact with the upper end of the semiconductor channel of the channel structure 212. The channel plug 236 may comprise a semiconductor material (e.g., polysilicon). By covering the upper end of the channel structure 236 during the fabrication of the 3D memory device 200, the channel plug 236 may serve as an etch stop layer to prevent etching of the dielectric filling the channel structure 212. In some embodiments, the channel plug 236 may serve as part of the drain of the memory string 210. In some embodiments, each channel plug 236 of the memory string 210 in the minimum repeating unit 202 (including both the DSG notch region 206 and the non-DSG notch region 204) has a nominally identical height. That is, the height of the channel plug 236 may be nominally identical across the different regions 204 and 206. In some embodiments, the lower end of the channel plug 236 in the non-DSG notch region 204 is above the DSG line 228 (e.g., the first uppermost conductive layer 226). In some embodiments, the lower end of the channel plug 236 in the DSG cutout region 206 is higher than the DSG line 230 (e.g., the second uppermost conductive layer 226), and the upper end of the channel plug 236 in the DSG cutout region 206 (the upper end of the memory string 210) is lower than the DSG line 228. That is, according to some embodiments, the channel plug 236 in the DSG cutout region 206 is vertically positioned between the DSG lines 228 and 230.

[0047] Each memory string 210 may include a plurality of cells at the intersection of the conductive layer 226 and the channel structure 212. Each cell may be a transistor having a threshold voltage, which may be set from its intrinsic threshold voltage to a desired level by, for example, a manufacturer and / or a user, after the fabrication of the 3D memory device 200, using programming and / or erasing operations. The cells may include memory cells controlled for data storage via gate lines / word lines of the conductive layer 226. The cells may also include DSG cells 214, 216, and 218 controlled via DSG lines 228 and 230 for controlling the drain of the memory string 210. The cells may also include SSG cells controlled via SSG line 232 for controlling the common source of the memory string 210. In some embodiments, each memory string 210 in the non-DSG cutout region 204 includes a first DSG cell 214 at the intersection of DSG line 228 adjacent to the memory string 210 and a second DSG cell 216 at the intersection of DSG line 230 adjacent to the memory string 210. As described in the following detailed description of the operation of the 3D memory device 200, the threshold voltages of the first DSG cell 214 and the second DSG cell 216 can be set to appropriate levels and the first voltage V at the appropriate level can be... dsg0 and the second voltage V dsg1Memory strings 210 in non-DSG cutout regions 204 are selected or deselected by applying DSG lines 228 and 230 respectively. In some embodiments, each memory string 210 in the DSG cutout region 206 includes a third DSG cell 218 at the intersection of DSG line 230 adjacent to the memory string 210. As described in detail below with respect to the operation of the 3D memory device 200, this can be achieved by setting a threshold voltage of the third DSG cell 218 to an appropriate level and applying a second voltage V at an appropriate level. dsg1 Apply to DSG line 230 to select or deselect memory string 210 in DSG cutout region 206.

[0048] like Figure 2B As shown, the 3D memory device 200 also includes bit line contacts 240, each bit line contact 240 above and in contact with a corresponding one of the memory strings 210 in the smallest repeating unit 202 of the memory stack layer 222. In some embodiments, each bit line contact 240 is formed on top of the upper end (i.e., the channel plug 236) of the corresponding memory string 210. The bit line contact 240 is part of a “local contact” (also referred to as “C1”) that directly contacts the structure (e.g., the memory string 210) in the memory stack layer 222. The bit line contact 240 may include a conductive material, including but not limited to Cu, Al, W, Co, silicides, or any combination thereof. In some embodiments, the upper ends of each bit line contact 240 are flush with each other. According to some embodiments, since the upper end of the memory string 210 in the non-DSG cutout region 204 is higher than the upper end of the memory string 210 in the DSG cutout region 206, the height of each bit line contact 240 in the DSG cutout region 206 is greater than the height of each bit line contact 240 in the non-DSG cutout region 204.

[0049] like Figure 2B As shown, the 3D memory device 200 also includes bit lines 242, each bit line 242 above and in contact with a corresponding bit line contact 240 in the smallest repeating unit 202 of the memory stack layer 222. The bit lines 242 may include conductive materials, including but not limited to Cu, Al, W, Co, silicides, or any combination thereof. According to some embodiments, different Figure 1B The 3D memory device 100 includes a virtual memory string 112 that does not have corresponding bit line contacts and bit lines. Figure 2B Each memory string 210 of the 3D memory device 200 is a functional memory string that contacts a corresponding bit line contact 240 and is electrically connected to a corresponding bit line 242 for individual addressing.

[0050] It should be understood that the number of regions in the smallest repeating unit of the memory stack of a 3D memory device is not limited to 2 (e.g., a DS-cut region 206 and a non-DSG-cut region 204 in the smallest repeating unit 202 of the 3D memory device 200), and can be any other suitable number (e.g., 3). For example, Figure 3A and Figure 3B A plan view and a side view of a cross section of another exemplary 3D memory device 300 with a DSG notch according to some embodiments of the present disclosure are shown. Figure 3B The 3D memory device 300 is shown. Figure 3A A side view of the cross-section of the CC plane. (e.g.) Figure 3A As shown, the smallest repeating unit 302 of the 3D memory device 300 includes three regions: a DSG cutout region 306 between two non-DSG cutout regions 304 and 305 in the y-direction (bit line direction) of the planar view. It should be understood that details of similar structures (e.g., materials, manufacturing processes, functions, etc.) in both 3D memory devices 200 and 300 may not be repeated below.

[0051] The 3D memory device 300 may include a substrate 320 and a memory stack layer 322 above the substrate 320. In some embodiments, the 3D memory device 300 is a NAND flash memory device, wherein the memory cells are provided in the form of an array of NAND memory strings 310, each NAND memory string extending vertically through the memory stack layer 322 above the substrate 320, such as... Figure 3B As shown in the side view, the array of memory strings 310 can be divided into regions 304, 305, and 306 of the memory stacking layers 322. In some embodiments, the size of each non-DSG cutout region 304 or 305 is nominally the same as the size of the DSG cutout region 306, and the number of memory strings 310 in each non-DSG cutout region 304 or 305 is nominally the same as the number of memory strings 310 in the DSG cutout region 306. In other words, the memory strings 310 can be uniformly divided into regions 304, 305, and 306 of the memory stacking layers 322 (i.e., minimum repeating unit 302).

[0052] According to some embodiments, the memory stack layer 322 includes conductive layers 326 and dielectric layers 324 that are vertically interleaved in the z-direction. In some embodiments, the outermost conductive layer in the conductive layer 326 includes a plurality of DSG lines 328, 329, and 330 and an SSG line 332. The remaining portion of the conductive layer 326 vertically located between the SSG line 332 and the DSG lines 328, 329, and 330 may include gate lines that extend laterally around the memory string 310 as word lines. Figure 3BAs shown, according to some embodiments, DSG lines 328 and 329 are both first uppermost conductive layers 326 separated by DSG notches 308, and DSG line 330 is a second uppermost conductive layer 326. In some embodiments, each memory string 310 is adjacent to at least one of DSG lines 328, 329, and 330, and DSG lines 328, 329, and 330 are configured to control the drain of the memory string 310. According to some embodiments, each memory string 310 in the non-DSG notch region 304 is adjacent to both DSG lines 328 and 330, such that the drain of the memory string 310 in the non-DSG notch region 304 is controlled by both DSG lines 328 and 330. Similarly, according to some embodiments, each memory string 310 in the non-DSG notch region 305 is adjacent to both DSG lines 329 and 330, such that the drain of the memory string 310 in the non-DSG notch region 305 is controlled by both DSG lines 329 and 330. Because of the DSG cutout 308, each memory string 310 in the DSG cutout region 306 is adjacent to the DSG line 330, but not adjacent to the DSG lines 328 or 329, such that the drain of the memory string 310 in the DSG cutout region 306 is controlled by the DSG line 330 instead of the DSG lines 328 or 329.

[0053] In some embodiments, the memory strings 310 in non-DSG cutout regions 304 and 305 have the same nominal height, and the memory strings 310 in DSG cutout region 306 also have the same nominal height. According to some embodiments, the height of each memory string 310 in non-DSG cutout regions 304 and 305 is greater than the height of each memory string 310 in DSG cutout region 306. For example, in the vertical direction, the upper ends of the memory strings 310 in non-DSG cutout regions 304 and 305 may be above DSG lines 328 and 329 (e.g., the first uppermost conductive layer 326), and the upper ends of the memory strings 310 in DSG cutout region 306 may be between DSG line 230 (e.g., the second uppermost conductive layer 326) and DSG lines 328 and 329. That is, according to some embodiments, the memory strings 310 in DSG cutout region 306 do not extend beyond DSG lines 328 and 329.

[0054] like Figure 3BAs shown, the memory string 310 may include a channel structure 312 and a channel plug 336 at the upper end of the memory string 310. In some embodiments, each channel plug 336 of the memory string 310 in the minimum repeating unit 302 (including the DSG cut-out region 306 and the non-DSG cut-out regions 304 and 305) has a nominally identical height. That is, the height of the channel plug 336 may be nominally identical across the different regions 304, 305, and 306. In some embodiments, the lower end of the channel plug 336 in the non-DSG cut-out regions 304 and 305 is above the DSG lines 328 and 329 (e.g., the first uppermost conductive layer 326), and the lower end of the channel plug 336 in the DSG cut-out region 306 is above the DSG line 330 (e.g., the second uppermost conductive layer 326).

[0055] Each memory string 310 may include a plurality of cells at the intersection of the conductive layer 326 and the channel structure 312. The cells may include memory cells controlled for data storage via gate lines / word lines of the conductive layer 326. The cells may also include DSG cells 314, 315, 316, 317, and 318 controlled via DSG lines 328, 329, and 330 for controlling the drain of the memory string 310. The cells may also include SSG cells controlled via SSG line 332 for controlling the common source of the memory string 310. In some embodiments, each memory string 310 in the non-DSG cutout region 304 includes a first DSG cell 314 at the intersection of DSG line 328 adjacent to the memory string 310 and a second DSG cell 315 at the intersection of DSG line 330 adjacent to the memory string 310. As described in the following detailed description of the operation of the 3D memory device 300, the threshold voltages of the first DSG cell 314 and the second DSG cell 315 can be set to appropriate levels, and the first voltage V at the appropriate level can be... dsg0 Second voltage V dsg1 Memory strings 310 in non-DSG cutout regions 304 are selected or deselected by applying DSG lines 328 and 330, respectively. Similarly, in some embodiments, each memory string 310 in non-DSG cutout regions 305 includes a fifth DSG cell 318 at the intersection of DSG line 329 and memory string 310, and a fourth DSG cell 317 at the intersection of DSG line 330 and memory string 310. As described in detail below with respect to the operation of the 3D memory device 300, this can be achieved by setting the threshold voltages of the fourth DSG cell 317 and the fifth DSG cell 318 to an appropriate level and setting a third voltage V at an appropriate level. dsg2 Second voltage V dsg1Memory strings 310 in non-DSG cutout regions 305 are selected or deselected by applying DSG lines 329 and 330 respectively. In some embodiments, each memory string 310 in the DSG cutout region 306 includes a third DSG cell 316 at the intersection of the DSG line 330 adjacent to the memory string 310. As described in detail below with respect to the operation of the 3D memory device 300, this can be achieved by setting the threshold voltage of the third DSG cell 316 to an appropriate level and applying a second voltage V at an appropriate level. dsg1 Apply to DSG line 330 to select or deselect memory string 310 in DSG cutout region 306.

[0056] like Figure 3B As shown, the 3D memory device 300 may further include bit line contacts 340, each bit line contact 340 above and contacting a corresponding one of the memory strings 310 in the minimum repeating unit 302 of the memory stack layer 322. In some embodiments, each bit line contact 340 is formed on top of the upper end of the corresponding memory string 310 (i.e., the channel plug 336). According to some embodiments, since the upper ends of the memory strings 310 in the non-DSG cutout regions 304 and 305 are higher than the upper ends of the memory strings 310 in the DSG cutout region 306, the height of each bit line contact 340 in the DSG cutout region 306 is greater than the height of each bit line contact 340 in the non-DSG cutout regions 304 and 305. The 3D memory device 300 may further include bit lines 342, each bit line 342 above and contacting a corresponding one of the bit line contacts 340 in the minimum repeating unit 302 of the memory stack layer 322.

[0057] Figure 4A A side view of a cross-section of another exemplary 3D memory device 400 with a DSG notch according to some embodiments of the present disclosure is shown. Figure 4A This could be illustrated by a 3D memory device 200 along... Figure 2A Another example of a side view of a cross-section of the BB plane. That is, Figure 4A A side view of the smallest repeating unit of the memory stack layer 422 in the 3D memory device 400 is shown, which is related to... Figure 2A The smallest repeating unit 202 is the same. It should be understood that the details of similar structures (e.g., materials, manufacturing processes, functions, etc.) in both 3D memory devices 200 and 400 may not be repeated below.

[0058] 3D memory device 400 may include a substrate 420 and a memory stack layer 422 above the substrate 420. In some embodiments, 3D memory device 400 is a NAND flash memory device, wherein memory cells are provided in the form of an array of NAND memory strings 210, each NAND memory string extending vertically through the memory stack layer 422 above the substrate 420. In a plan view, the array of memory strings 210 may be divided into a non-DSG cutout region 204 and a DSG cutout region 206 of the memory stack layer 422. In some embodiments, the dimensions of the non-DSG cutout region 204 are nominally the same as the dimensions of the DSG cutout region 206, and the number of memory strings 210 in the non-DSG cutout region 204 is nominally the same as the number of memory strings 210 in the DSG cutout region 206. In other words, the memory strings 210 may be uniformly divided into regions 204 and 206 of the memory stack layer 422 (i.e., minimum repeating unit 202).

[0059] According to some embodiments, the memory stack layer 422 includes conductive layers 426 and dielectric layers 424 that are vertically interleaved in the z-direction. In some embodiments, the outermost conductive layer in the conductive layer 426 includes a plurality of DSG lines 428 and 430 and an SSG line 432. The remaining portion of the conductive layer 426 vertically between the SSG line 432 and the DSG lines 428 and 430 may include gate lines that extend laterally around the memory string 210 as word lines. According to some embodiments, DSG line 428 is a first uppermost conductive layer 426, DSG line 430 is a second uppermost conductive layer 426, and SSG line 432 is a lowermost conductive layer 426. In some embodiments, each memory string 210 is adjacent to at least one of the DSG lines 428 and 430 configured to control the drain of the memory string 210. According to some embodiments, each memory string 210 in the non-DSG cutout region 204 is adjacent to both DSG lines 428 and 430, such that the drain of the memory string 210 in the non-DSG cutout region 204 is controlled by both DSG lines 428 and 430. Due to the DSG cutout 208, each memory string 210 in the DSG cutout region 206 is adjacent to DSG line 430 but not to DSG line 428, such that the drain of the memory string 210 in the DSG cutout region 206 is controlled by DSG line 430 but not by DSG line 428.

[0060] like Figure 4AAs shown, a portion of the DSG line 428 (e.g., the first uppermost conductive layer 426) in the DSG notch region 206 is removed by the DSG notch 208. That is, the DSG lines 428 and 430 can, for example, have different lateral dimensions in the y-direction (bit line direction). As a result, in some embodiments, the number of DSG lines 428 and 430 differs between the DSG notch region 206 and the non-DSG notch region 204 due to the DSG notch 208. For example, two DSG lines 428 and 430 may exist in the non-DSG notch region 204, but only one DSG line 430 exists in the DSG notch region 206. In other words, the number of DSG lines 428 and 430 through which the memory string 210 extends vertically differs between the DSG notch region 206 and the non-DSG notch region 204. For example, memory string 210 in non-DSG cutout region 204 extends vertically through two DSG lines 428 and 430, while memory string 210 in DSG cutout region 206 extends vertically through only one DSG line 430. The layout and design of 3D memory device 400 avoids any dummy memory strings (e.g., due to DSG cutouts) Figure 1A and Figure 1B (As shown in the diagram). For example, the DSG cutout region 206 of the 3D memory device 400 may not have dummy memory strings, and each memory string 210 in the minimum repeating unit 202 of the memory stack layer 422 may be a functional memory string. Therefore, compared to the 3D memory device 100, the effective device area and memory cell density of the 3D memory device 400 can be increased, and the electrical performance can be improved.

[0061] According to some embodiments, different Figure 2B The memory strings 210 in the DSG cutout region 206 and the non-DSG cutout region 204 contain 3D memory devices 200 with different heights. Figure 4A In the 3D memory device 400, each memory string 210 in the DSG cutout region 206 and the non-DSG cutout region 204 has the same nominal height. For example, the upper ends of the memory strings 210 in both the non-DSG cutout region 204 and the DSG cutout region 206 may be above the DSG line 428 (e.g., the first uppermost conductive layer 426). In some embodiments, the upper ends of the memory strings 210 in both the non-DSG cutout region 204 and the DSG cutout region 206 are flush with each other. As described below with respect to the manufacturing process, manufacturing complexity can be reduced by making each memory string 210 in the minimum repeating unit 202 of the memory stack layer 422 have a uniform height.

[0062] The memory string 210 may include a channel structure 412 and channel plugs 436 at the upper end of the memory string 210. In some embodiments, the channel plugs 436 in the non-DSG cutout region 204 have nominally the same height, and the channel plugs 436 in the DSG cutout region 206 have nominally the same height. According to some embodiments, the height of the channel plugs 436 differs between the non-DSG cutout region 204 and the DSG cutout region 206. For example, the height of each channel plug 436 in the DSG cutout region 206 may be greater than the height of each channel plug 436 in the non-DSG cutout region 204. For example, in the vertical direction, the lower end of the channel plug 436 in the non-DSG cut-out region 204 may be above the DSG line 428 (e.g., the first uppermost conductive layer 426), and the lower end of the channel plug 436 in the DSG cut-out region 206 may be between the DSG line 430 (e.g., the second uppermost conductive layer 426) and the DSG line 428.

[0063] The 3D memory device 400 also includes bit line contacts 440, each bit line contact 440 above and contacting a corresponding one of the memory strings 210 in the minimum repeating unit 202 of the memory stack layer 422. In some embodiments, each bit line contact 440 is formed on top of the upper end of the corresponding memory string 210 (i.e., the channel plug 436). According to some embodiments, since the upper ends of the memory strings 210 in each region 204 or 206 are flush with each other, the height of each bit line contact 440 in the minimum repeating unit 202 is nominally the same. As described below with respect to the manufacturing process, manufacturing complexity can be reduced by making each bit line contact 440 in the minimum repeating unit 202 of the memory stack layer 422 have a uniform height. The 3D memory device 400 may also include bit lines 442, each bit line 422 above and contacting a corresponding one of the bit line contacts 440 in the minimum repeating unit 202 of the memory stack layer 422.

[0064] although Figure 4A The channel plug 436 of the 3D memory device 400 has different heights between the non-DSG cutout region 204 and the DSG cutout region 206, but it should be understood that in some examples, the channel plug may have the same nominal height between different regions. For example, Figure 4B A side view of a cross-section of another exemplary 3D memory device 401 with a DSG notch according to some embodiments of the present disclosure is shown. Figure 4B This could be illustrated by a 3D memory device 200 along... Figure 2A Another example of a side view of a cross-section of the BB plane. For example... Figure 4BAs shown, according to some embodiments, the height of the channel plug 437 is nominally the same between different regions (e.g., between the non-DSG cutout region 204 and the DSG cutout region 206). That is, each channel plug 437 in the 3D memory device 401 can be nominally identical in the smallest repeating unit 202 of the memory stack layer 422. In some embodiments, the lower end of each channel plug 437 lies between the DSG line 428 (e.g., the first uppermost conductive layer 426) and the DSG line 430 (e.g., the second uppermost conductive layer 426). It should be understood that, for ease of description, details of other identical structures in both 3D memory devices 400 and 401 are not repeated.

[0065] It should be understood that the number of regions in the smallest repeating unit of the memory stack of a 3D memory device is not limited to 2 (e.g., a DSG cutout region 206 and a non-DSG cutout region 204 in the smallest repeating unit 202), and can be any other suitable number (e.g., 3 or more). For example, Figure 5A and Figure 5B A plan view and a side view of a cross section of another exemplary 3D memory device 500 with a DSG notch according to some embodiments of the present disclosure are shown. Figure 5B The 3D memory device 500 is shown. Figure 5A A side view of the cross-section of the DD plane. (e.g.) Figure 5A As shown, the smallest repeating unit 502 of the 3D memory device 500 includes three regions: a non-DSG cutout region 504 in the y-direction (bit line direction) of the planar view and two DSG cutout regions 505 and 506. It should be understood that details of similar structures (e.g., materials, manufacturing processes, functions, etc.) in both 3D memory devices 400 and 500 may not be repeated below.

[0066] like Figure 5B As shown, the 3D memory device 500 may include a substrate 520 and a memory stack layer 522 above the substrate 520. In some embodiments, the 3D memory device 500 is a NAND flash memory device, wherein the memory cells are provided in the form of an array of NAND memory strings 510, each NAND memory string extending vertically through the memory stack layer 522 above the substrate 520, as shown. Figure 5BAs shown in the side view, the array of memory strings 510 can be divided into regions 504, 505, and 506 of the memory stack layer 522. In some embodiments, each region 504, 505, or 506 is nominally the same size, and the number of memory strings 510 in each region 504, 505, or 506 is nominally the same. In other words, the memory strings 510 can be uniformly divided into regions 504, 505, or 506 of the memory stack layer 522 (i.e., minimum repeating unit 502).

[0067] According to some embodiments, the memory stack layer 522 includes conductive layers 526 and dielectric layers 524 that are vertically interleaved in the z-direction. In some embodiments, the outermost conductive layer in the conductive layer 526 includes a plurality of DSG lines 528, 530, and 531 and an SSG line 532. The remaining portion of the conductive layer 526 vertically located between the SSG line 532 and the DSG lines 528, 530, and 531 may include gate lines that surround the memory string 510 and extend laterally as word lines. Figure 5B As shown, according to some embodiments, DSG line 528 is a first uppermost conductive layer 526, DSG line 530 is a second uppermost conductive layer 526, and DSG line 531 is a third uppermost conductive layer 526. In some embodiments, each memory string 510 is adjacent to at least one of DSG lines 528, 530, and 531, and DSG lines 528, 530, and 531 are configured to control the drain of the memory string 510. According to some embodiments, each memory string 510 in the non-DSG cutout region 504 is adjacent to DSG lines 528, 530, and 531, such that the drain of the memory string 510 in the non-DSG cutout region 504 is controlled by the three DSG lines 528, 530, and 531. Due to DSG cutout 507, each memory string 510 in DSG cutout region 505 is adjacent to DSG lines 530 and 531, but not to DSG line 528, such that the drain of the memory string 510 in DSG cutout region 505 is controlled by two DSG lines 530 and 531, but not by DSG line 528. Due to DSG cutouts 507 and 508, each memory string 510 in DSG cutout region 506 is adjacent to DSG line 531, but not to DSG lines 528 and 530, such that the drain of the memory string 510 in DSG cutout region 506 is controlled by DSG line 531, but not by DSG lines 528 and 530.

[0068] In some embodiments, a portion of the DSG line 528 (e.g., the first uppermost conductive layer 526) in DSG cut-out regions 505 and 506 is removed by DSG cut-outs 507 and 508, and a portion of the DSG line 530 (e.g., the second uppermost conductive layer 526) in DSG cut-out region 506 is removed by DSG cut-out 508. That is, the DSG lines 528, 530, and 531 may, for example, have different lateral dimensions in the y-direction (bit line direction). According to some embodiments, the DSG lines 528, 530, and 531 form a stepped structure. As a result, in some embodiments, the number of DSG lines 528, 530, and 531 differs between regions 504, 505, and 506 due to DSG cut-outs 507 and 508. For example, there may be three DSG lines 528, 530, and 531 in the non-DSG cutout region 504, two DSG lines 530 and 531 in the DSG cutout region 505, and one DSG line 531 in the DSG cutout region 506. In other words, the number of DSG lines 528, 530, and 531 that the memory string 510 extends vertically through differs between regions 504, 505, and 506. The layout and design of the 3D memory device 500 avoids any dummy memory strings (e.g., due to DSG cutouts) caused by the DSG cutouts. Figure 1A and Figure 1B (As shown in the diagram). For example, the DSG cutout regions 505 and 506 of the 3D memory device 500 may not have dummy memory strings, and each memory string 510 in the minimum repeating unit 502 of the memory stack layer 522 may be a functional memory string. Therefore, compared to the 3D memory device 100, the effective device area and memory cell density of the 3D memory device 500 can be increased, and the electrical performance can be improved.

[0069] like Figure 5BAs shown, the memory string 510 may include a channel structure 512 and a channel plug 536 at the upper end of the memory string 510. The 3D memory device 500 may also include bit line contacts 540, each bit line contact 540 above and contacting a corresponding one of the memory strings 510 in the minimum repeating unit 502 of the memory stack layer 522. In some embodiments, each bit line contact 540 is formed on top of the upper end of the corresponding memory string 510 (i.e., the channel plug 536). The 3D memory device 500 may also include bit lines 542, each bit line 542 above and contacting a corresponding one of the bit line contacts 540 in the minimum repeating unit 502 of the memory stack layer 522. It should be understood that the number of DSG cuts and the number of resulting DSG regions are not limited to the examples of the 3D memory devices 400 and 500 described above, and the number of regions in the minimum repeating unit can be greater than 3. For example, two or more uppermost conductive layers can be cut by two or more DSG cuts to form three or more DSG lines in the y direction (bit line direction), and the stepped structure formed by the DSG lines can be extended.

[0070] Figures 6A-6F The present disclosure illustrates a manufacturing process for forming an exemplary 3D memory device with DSG notches according to some embodiments of the present disclosure. Figure 8 A flowchart of a method 800 for forming an exemplary 3D memory device with DSG notches according to some embodiments of the present disclosure is shown. Figures 6A-6F and Figure 8 Examples of 3D memory devices depicted include Figure 2A and Figure 2B The 3D memory device 200 depicted in the image will be described together. Figures 6A-6F and Figure 8 It should be understood that the operations shown in method 800 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 8 The different execution orders shown.

[0071] refer to Figure 8 Method 800 begins with operation 802, wherein a dielectric stack layer comprising an interleaved sacrificial layer and a dielectric layer is formed over a substrate. The substrate may be a silicon substrate. (Reference) Figure 6AA dielectric stack 604 comprising multiple pairs of sacrificial layers 606 and dielectric layers 608 is formed over a silicon substrate 602. According to some embodiments, the dielectric stack 604 comprises staggered sacrificial layers 606 and dielectric layers 608. The dielectric layers 608 and sacrificial layers 606 may be deposited alternately on the silicon substrate 602 to form the dielectric stack 604. In some embodiments, each dielectric layer 608 comprises a silicon oxide layer, and each sacrificial layer 606 comprises a silicon nitride layer. That is, multiple silicon nitride layers and multiple silicon oxide layers may be deposited alternately over the silicon substrate 602 to form the dielectric stack 604. The dielectric stack 604 may be formed by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0072] Method 800 proceeds to operation 804, such as... Figure 8 As shown, a first channel structure and a second channel structure are formed, each extending vertically through the dielectric stack. Figure 6B As shown, a via is an opening extending vertically through a dielectric stack 604. In some embodiments, multiple openings are formed through the dielectric stack 604, such that each opening serves as a location for growing an individual channel structure 610 or 611 in a later process. In some embodiments, the fabrication process for forming the vias of the channel structures 610 or 611 includes wet etching and / or dry etching (e.g., deep ion reactive etching (DRIE)). In some embodiments, the via of each channel structure 610 or 611 further extends through a top portion of the silicon substrate 602. The etching process through the dielectric stack 604 may not stop at the top surface of the silicon substrate 602 and may continue etching portions of the silicon substrate 602. A memory film (including a barrier layer, a storage layer, and a tunneling layer, not shown) and a semiconductor channel are formed along the sidewalls of the via of each channel structure 610 or 611. In some embodiments, a memory film is first deposited along the sidewalls of the via, and then a semiconductor channel is deposited on top of the memory film. The barrier layer, storage layer, and tunneling layer can be deposited sequentially in this order using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form a memory film. A semiconductor channel can then be formed by depositing polysilicon on the tunneling layer using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0073] Method 800 proceeds to operation 806, such as... Figure 8As shown, a portion of the uppermost sacrificial layer in the sacrificial layer is removed, and the top portion of the removed portion of the uppermost sacrificial layer of the second channel structure is removed, such that the first channel structure extends vertically through a first region of the dielectric stack layer including the remaining portion of the uppermost sacrificial layer, and the remaining portion of the second channel structure extends vertically through a second region of the dielectric stack layer without the uppermost sacrificial layer.

[0074] like Figure 6C As shown, an etching mask 612 is patterned to cover a portion of the dielectric stack 604, a portion of the first uppermost sacrificial layer 606, and the underlying channel structure 610. The etching mask 612 may include a soft etching mask (e.g., a photoresist layer) and / or a hard etching mask (e.g., a metal layer) formed on a portion of the dielectric stack 604. In some embodiments, the manufacturing process for patterning the etching mask 612 includes photolithography, development, dry etching, and / or wet etching. By patterning the etching mask 612, the dielectric stack 604 can be laterally divided in the y-direction (e.g., the bit line direction) into a non-DSG cutout region 603 covered by the etching mask 612 and a DSG cutout region 605 not covered by the etching mask 612. According to some embodiments, the channel structures 610 and 611 are thus divided into the non-DSG cutout region 603 and the DSG cutout region 605, respectively.

[0075] like Figure 6D As shown, the unetched mask 612 of the first uppermost sacrificial layer 606 is removed by wet etching and / or dry etching (e.g., RIE). Figure 6C The portion of the first uppermost sacrificial layer 606 adjacent to the removed portion of the channel structure 611 in the DSG notch region 605 (shown) is covered. Etching can be stopped between the first and second uppermost sacrificial layers 606, such that the upper end of the channel structure 611 is above the second uppermost sacrificial layer 606. Etching can be controlled by controlling the etching rate and / or etching time, or by stopping etching when the first uppermost sacrificial layer 606 (including silicon nitride) is etched. Due to the protection of the etching mask 612, the remaining portion of the first uppermost sacrificial layer 606 and the channel structure 610 in the non-DSG notch region 603 can remain intact. According to some embodiments, a DSG notch 614 is thus formed in the DSG notch region 605. Then, after the DSG notch 614 is formed, the etching mask 612 can be removed using ashing, wet etching, and / or dry etching.

[0076] Method 800 proceeds to operation 808, such as... Figure 8As shown, a first channel plug is formed in the top portion of the first channel structure, and a second channel plug is formed in the top portion of the remaining portion of the second channel structure. In some embodiments, the lower end of the first channel plug is higher than the remaining portion of the uppermost sacrificial layer, and the upper end of the second channel plug is lower than the remaining portion of the uppermost sacrificial layer.

[0077] like Figure 6E As shown, a channel plug 616 is formed in the top portion of the channel structure 610 in the non-DSG notch region 603, and a channel plug 617 is formed in the top portion of the remaining portion of the channel structure 611 in the DSG notch region 605. In some embodiments, a recess is formed in the top portion of the channel structure 610 or 611 by wet etching and / or dry etching portions of the memory film, semiconductor channel, and capping layer in the top portion of the channel structure 610 or 611. The channel plugs 616 and 617 can then be formed by depositing semiconductor material (e.g., polysilicon) into the recess using one or more thin-film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof). Thus, a dielectric stack layer 604, including the remaining portion of the first uppermost sacrificial layer 606 in the non-DSG notch region 603, forms a memory string 626, each including a respective channel structure 610 and a channel plug 616. Thus, a memory string 627, each including a corresponding channel structure 611 and a channel plug 617, is formed through the dielectric stack 604 in the DSG notch region 605 where there is no first uppermost sacrificial layer 606. In some embodiments, the removed top portion of the dielectric stack 604 in the DSG notch region 605 is filled again with a dielectric material (e.g., silicon oxide) using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) followed by a planarization process (e.g., CMP). Figure 6D (as shown in the image).

[0078] Method 800 proceeds to operation 810, such as Figure 8 As shown, a memory stack consisting of interlaced conductive and dielectric layers is formed by replacing the sacrificial layer of the dielectric stack with a conductive layer (i.e., a so-called "gate replacement" process). Figure 6F As shown, sacrificial layer 606 (as Figure 6EThe layer 608 (shown) is replaced by a conductive layer 620, thereby forming a memory stack layer 618 comprising interlaced conductive layers 620 and dielectric layers 608. In some embodiments, lateral recesses (not shown) are first formed by removing a sacrificial layer 606 via a slit opening (not shown). In some embodiments, the sacrificial layer 606 is removed by applying an etching solution via the slit opening, such that the sacrificial layer 606 is removed, thereby creating interlaced lateral recesses between the dielectric layers 608. The etching solution may include any suitable etchant that selectively etches the sacrificial layer 606 relative to the dielectric layers 608. Figure 6F As shown, the conductive layer 620 is deposited into the lateral recess through a slit opening. In some embodiments, a gate dielectric layer (not shown) is deposited into the lateral recess prior to the conductive layer 620, such that the conductive layer 620 is deposited on the gate dielectric layer. The conductive layer 620 (e.g., a metal layer) can be deposited using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). According to some embodiments, DSG lines 628 and 629 are thus formed, replacing the remainders of the first uppermost sacrificial layer 606 and the second uppermost sacrificial layer 606, respectively.

[0079] Method 800 proceeds to operation 812, such as Figure 8 As shown, the first bit contact and the second bit contact are respectively formed above the first channel plug and the second channel plug and are in contact with the first channel plug and the second channel plug. In some embodiments, multiple bit lines are respectively formed above the first bit contact and the second bit contact and are in contact with the first bit contact and the second bit contact.

[0080] like Figure 6FAs shown, bit line contacts 622 are formed above and contact the channel plugs 616 of the memory string 626 in the non-DSG cutout region 603, and bit line contacts 623 are formed above and contact the channel plugs 617 of the memory string 627 in the DSG cutout region 605. According to some embodiments, due to the DSG cutout 614, the height of each bit line contact 623 in the DSG cutout region 605 is greater than the height of each bit line contact 622 in the non-DSG cutout region 603. In some embodiments, to form the bit line contacts 622 and 623, wet etching / dry etching (e.g., RIE) is used to form bit line contact openings through the dielectric layer on the memory stack layer 618. In some embodiments, the etching process stops at the upper ends of the channel plugs 616 and 617 of the memory strings 626 and 627 to expose the upper ends of the channel plugs 616 and 617. Bit line contacts 622 and 623 can then be formed by depositing conductive material into the bit line contact openings using a thin film deposition process (e.g., ALD, CVD, PVD, any other suitable process or any combination thereof) followed by a CMP process.

[0081] like Figure 6F As shown, bit lines 624 are formed above and in contact with bit line contacts 622 and 623 in the non-DSG cutout region 603 and the DSG cutout region 605, respectively. According to some embodiments, the height of each bit line 624 is nominally the same. In some embodiments, to form bit lines 624, bit line openings are formed through a dielectric layer on the bit line contacts 622 and 623 using wet etching / dry etching (e.g., RIE). In some embodiments, the etching process stops at the upper ends of the bit line contacts 622 and 623. The bit lines 624 can then be formed by depositing conductive material into the bit line openings using a thin film deposition process (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) followed by a CMP process.

[0082] Figures 7A-7H Manufacturing processes for forming other exemplary 3D memory devices with DSG notches are illustrated according to some embodiments of the present disclosure. Figure 9 A flowchart of a method 900 for forming other exemplary 3D memory devices having DSG notches, according to some embodiments of the present disclosure, is shown. Figures 7A-7H and Figure 9 Examples of 3D memory devices depicted include Figure 4A and Figure 4B The 3D memory devices 400 and 401 depicted in the figure will be described together. Figures 7A-7H and Figure 9It should be understood that the operations shown in method 900 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 9 The different execution orders shown.

[0083] refer to Figure 9 Method 900 begins with operation 902, wherein a dielectric stack layer comprising an interleaved sacrificial layer and a dielectric layer is formed over a substrate. The substrate may be a silicon substrate. (See reference) Figure 7A A dielectric stack 704 comprising multiple pairs of sacrificial layers 706 and dielectric layers 708 is formed over a silicon substrate 702. According to some embodiments, the dielectric stack 704 comprises staggered sacrificial layers 706 and dielectric layers 708. The dielectric layers 708 and sacrificial layers 706 may be deposited alternately on the silicon substrate 702 to form the dielectric stack 704. In some embodiments, each dielectric layer 708 comprises a silicon oxide layer, and each sacrificial layer 706 comprises a silicon nitride layer. That is, multiple silicon nitride layers and multiple silicon oxide layers may be deposited alternately over the silicon substrate 702 to form the dielectric stack 704. The dielectric stack 704 may be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0084] Method 900 proceeds to operation 904, such as... Figure 9 As shown, this involves removing a portion of the topmost sacrificial layer from the sacrificial layers. Figure 7A As shown, an etching mask 709 is patterned to cover a portion of the dielectric stack 704 and a portion of the underlying uppermost sacrificial layer 706. The etching mask 709 may include a soft etching mask (e.g., a photoresist layer) and / or a hard etching mask (e.g., a metal layer) formed on a portion of the dielectric stack 704. In some embodiments, the manufacturing process for patterning the etching mask 709 includes photolithography, development, dry etching, and / or wet etching. By patterning the etching mask 709, the dielectric stack 704 can be laterally divided in the y-direction (e.g., the bit line direction) into a non-DSG cutout region 703 covered by the etching mask 709 and a DSG cutout region 705 not covered by the etching mask 709.

[0085] like Figure 7B As shown, the unetched mask 709 is removed by wet etching and / or dry etching (e.g., RIE). Figure 7AA portion of the first uppermost sacrificial layer 706 (shown) is covered. Etching can be stopped between the first uppermost sacrificial layer 706 and the second uppermost sacrificial layer 706, leaving the second uppermost sacrificial layer 706 intact. The etching depth can be controlled by controlling the etching rate and / or etching time. Due to the protection of the etching mask 709, the remaining portion of the first uppermost sacrificial layer 706 in the non-DSG notch region 703 can remain intact. According to some embodiments, a DSG notch 714 is thus formed in the DSG notch region 705. Then, after the DSG notch 714 is formed, the etching mask 709 can be removed using ashing, wet etching, and / or dry etching. In some embodiments, the removed top portion of the dielectric stack 704 in the DSG notch region 705 is again filled with a dielectric material (e.g., silicon oxide) using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) followed by a planarization process (e.g., CMP).

[0086] Method 900 proceeds to operation 906, such as... Figure 9 As shown, a first memory string and a second memory string, each having the same nominal height, are formed. In some embodiments, the first memory string extends vertically through a first region of the dielectric stack, including the remainder of the uppermost sacrificial layer, and the second memory string extends vertically through a second region of the dielectric stack without the uppermost sacrificial layer. In some embodiments, to form the first memory string and the second memory string, a first channel structure and a second channel structure extending vertically through the first and second regions of the dielectric stack are formed simultaneously. A riser layer is formed on the first region of the dielectric stack but not on the second region. A first recess extending through the riser layer into the top portion of the first channel structure and a second recess extending into the top portion of the second channel structure are formed. A first channel plug and a second channel plug are formed simultaneously in the first and second recesses, respectively. The depth of the second recess may be nominally the same as the depth of the first recess. In some embodiments, to form the first memory string and the second memory string, the first channel plug and the second channel plug are planarized such that the upper ends of the first memory string and the second memory string are flush with each other on the top surface of the dielectric stack. In some embodiments, after planarization, the height of the second channel plug is greater than the height of the first channel plug. In some embodiments, the lower end of the first channel plug is higher than the remaining portion of the uppermost sacrificial layer, and the lower end of the second channel plug is lower than the remaining portion of the uppermost sacrificial layer.

[0087] like Figure 7CAs shown, a via is an opening extending vertically through a dielectric stack 704. In some embodiments, multiple openings are formed through the dielectric stack 704, such that each opening serves as a location for growing an individual channel structure 710 or 711 in a later process. In some embodiments, the fabrication process for forming the vias of the channel structures 710 or 711 includes wet etching and / or dry etching (e.g., DRIE). In some embodiments, the via of each channel structure 710 or 711 further extends through a top portion of the silicon substrate 702. The etching process through the dielectric stack 704 may not stop at the top surface of the silicon substrate 702 and may continue etching portions of the silicon substrate 702. A memory film (including a barrier layer, a storage layer, and a tunneling layer, not shown) and a semiconductor channel are formed along the sidewalls of the via of each channel structure 710 or 711. In some embodiments, a memory film is first deposited along the sidewalls of the via, and then a semiconductor channel is deposited on top of the memory film. The barrier layer, storage layer, and tunneling layer can be deposited sequentially in this order using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form a memory film. A semiconductor channel can then be formed by depositing polysilicon on the tunneling layer using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). (Refer to the above) Figure 6D and Figure 8 Compared to the manufacturing process described above, in which a portion of the channel structure 611 in the DSG notch region 605 is removed via the DSG notch 614, the channel structure 711 in the DSG notch region 705 is not etched, thereby reducing manufacturing complexity.

[0088] like Figure 7D As shown, a riser layer 715 is formed on the non-DSG notch region 703 of the dielectric stack layer 704. The riser layer 715 may comprise any suitable material (e.g., silicon oxide or polysilicon). In some embodiments, the fabrication process for forming the riser layer 715 includes depositing material (e.g., silicon oxide) on the dielectric stack layer 704 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, electroplating, electroless plating, or any combination thereof), and patterning the deposited material using photolithography, development, dry etching, and / or wet etching to cover the non-DSG notch region 703, but not the DSG notch region 705.

[0089] like Figure 7DAs shown, a recess 717 is formed simultaneously in the top portion of the channel structure 710 entering the non-DSG notch region 703 through the riser layer 715, and a recess 719 is formed in the top portion of the channel structure 711 entering the DSG notch region 705. An etching mask (not shown) may first be patterned to expose the regions aligned with the channel structures 710 and 711. In some embodiments, the recesses 717 and 719 are formed simultaneously by wet etching and / or dry etching portions of the memory film, semiconductor channel, and capping layer in the top portion of the channel structures 710 or 711 via the etching mask. According to some embodiments, etching first passes through the riser layer 715 in the non-DSG notch region 703 before etching of the channel structure 710 begins. In some embodiments, the depth of the recess 717 in the non-DSG notch region 703 is nominally the same as the depth of the recess 719 in the DSG notch region 705. Due to the riser layer 715, the lower end of the recess 717 in the non-DSG notch region 703 can be higher than the lower end of the recess 719 in the DSG notch region 705. By controlling the properties of the riser layer 715 (e.g., thickness and / or material) and / or etching conditions (e.g., etching rate, cycle time and / or time), etching can be stopped when the lower end of the recess 717 in the non-DSG notch region 703 is higher than the first uppermost sacrificial layer 706 and the lower end of the recess 719 in the DSG notch region 705 is between the first sacrificial layer 706 and the second sacrificial layer 706.

[0090] like Figure 7E As shown, semiconductor material (e.g., polycrystalline silicon) is then deposited onto recesses 717 and 719 respectively using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof). Figure 7DAs shown, channel plugs 716 and 728 are formed simultaneously. A planarization process (e.g., CMP, wet etching, and / or dry etching) can then be applied to planarize the channel plugs 716 and 728 such that the upper ends of the channel plugs 716 and 728 are flush with each other on the top surface of the dielectric stack 704. Before forming the channel plugs 716 and 728, the riser layer 715 can be removed by the planarization process or in the etching process. As a result, according to some embodiments, after planarization, the height of the channel plug 728 in the DSG notch region 705 is greater than the height of the channel plug 716 in the non-DSG notch region 703. In some embodiments, the lower end of the channel plug 716 in the non-DSG cutout region 703 is higher than the remainder of the first uppermost sacrificial layer 706, and the lower end of the channel plug 728 in the DSG cutout region 705 is lower than the remainder of the first uppermost sacrificial layer 706 (e.g., between the first uppermost sacrificial layer 706 and the second uppermost sacrificial layer 706). Thus, memory strings 726, each including a corresponding channel structure 710 and channel plug 716, can be formed through the dielectric stack layer 704 including the remainder of the first uppermost sacrificial layer 706 in the non-DSG cutout region 703. Thus, memory strings 727, each including a corresponding channel structure 711 and channel plug 728, can be formed through the dielectric stack layer 704 in the DSG cutout region 705 without the first uppermost sacrificial layer 706.

[0091] Method 900 proceeds to operation 908, such as... Figure 9 As shown, a memory stack consisting of interlaced conductive and dielectric layers is formed by replacing the sacrificial layer of the dielectric stack with a conductive layer (i.e., a so-called "gate replacement" process). Figure 7F As shown, sacrificial layer 706 (as Figure 7E The layer 706 (shown) is replaced by a conductive layer 720, thereby forming a memory stack layer 718 comprising interleaved conductive layers 720 and dielectric layers 708. In some embodiments, lateral recesses (not shown) are first formed by removing a sacrificial layer 706 via a slit opening (not shown). In some embodiments, the sacrificial layer 706 is removed by applying an etching solution via the slit opening, such that the sacrificial layer 706 is removed, thereby creating interleaved lateral recesses between the dielectric layers 708. The etching solution may include any suitable etchant that selectively etches the sacrificial layer 706 relative to the dielectric layers 708. Figure 7FAs shown, the conductive layer 720 is deposited into the lateral recess through a slit opening. In some embodiments, a gate dielectric layer (not shown) is deposited into the lateral recess prior to the conductive layer 720, such that the conductive layer 720 is deposited on the gate dielectric layer. The conductive layer 720 (e.g., a metal layer) can be deposited using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). According to some embodiments, DSG lines 730 and 731 are thus formed, which respectively replace the remainders of the first uppermost sacrificial layer 706 and the second uppermost sacrificial layer 706.

[0092] Method 900 proceeds to operation 910, such as Figure 9 As shown, the first bit line contact and the second bit line contact are respectively formed above the first memory string and the second memory string and are in contact with the first memory string and the second memory string. In some embodiments, multiple bit lines are respectively formed above the first bit line contact and the second bit line contact and are in contact with the first bit line contact and the second bit line contact.

[0093] like Figure 7F As shown, bit line contacts 722 are formed above and contact the channel plugs 716 of the memory string 726 in the non-DSG cutout region 703 and the channel plugs 728 of the memory string 727 in the DSG cutout region 705, respectively. According to some embodiments, since the upper ends of the channel plugs 716 and 728 are flush with each other, each bit line contact 722 has the same nominal height. As a result, compared with the above regarding… Figure 6F and Figure 8 Compared to the example described, which requires bit line contacts 622 and 623 to be formed at different heights between the non-DSG cutout region 603 and the DSG cutout region 605, this reduces manufacturing complexity. In some embodiments, to form bit line contacts 722, a wet etching / dry etching (e.g., RIE) is used to form a bit line contact opening through a dielectric layer on the memory stack layer 718. In some embodiments, the etching process stops at the upper ends of the channel plugs 716 and 728 of the memory strings 726 and 727 to expose the upper ends of the channel plugs 716 and 728. The bit line contacts 722 can then be formed by depositing conductive material into the bit line contact opening using a thin film deposition process (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) followed by a CMP process.

[0094] like Figure 7FAs shown, bit lines 724 are formed above and in contact with bit line contacts 722 in the non-DSG cutout region 703 and the DSG cutout region 705, respectively. According to some embodiments, the height of each bit line 724 is nominally the same. In some embodiments, to form the bit lines 724, a bit line opening is formed through a dielectric layer on the bit line contact 722 using wet etching / dry etching (e.g., RIE). In some embodiments, the etching process stops at the upper end of the bit line contact 722. The bit lines 724 can then be formed by depositing conductive material into the bit line opening using a thin film deposition process (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) followed by a CMP process.

[0095] It should be understood that Figure 9 Operation 906 of method 900 can be performed as follows: Figure 7G and Figure 7H Another example is shown for implementation. In some embodiments, to form the first memory string and the second memory string, a first channel structure and a second channel structure are formed, respectively extending vertically through the first region and the second region of the dielectric stack layer. A first recess entering the top portion of the first channel structure and a second recess entering the top portion of the second channel structure are also formed, and a first channel plug and a second channel plug are simultaneously formed in the first recess and the second recess, respectively. In some embodiments, to form the first memory string and the second memory string, the first channel plug and the second channel plug are planarized such that the upper ends of the first memory string and the second memory string are flush with each other with the top surface of the dielectric stack layer. In some embodiments, after planarization, the height of the second channel plug is nominally the same as the height of the first channel plug. In some embodiments, the lower ends of the first channel plug and the second channel plug are lower than the remainder of the uppermost sacrificial layer.

[0096] After completion Figure 7C The process shown does not form Figure 7DIn the case of the riser layer 715, recesses (not shown) are simultaneously formed in the top portion of the channel structure 710 entering the non-DSG notch region 703 and in the top portion of the channel structure 711 entering the DSG notch region 705. An etching mask (not shown) may first be patterned to expose the regions aligned with the channel structures 710 and 711. In some embodiments, the recesses are formed simultaneously by wet etching and / or dry etching portions of the memory film, semiconductor channel, and capping layer in the top portion of the channel structures 710 or 711 via the etching mask. According to some embodiments, in the absence of the riser layer 715, the depth of each recess in the non-DSG notch region 703 is nominally the same as the depth of each recess in the DSG notch region 705. The lower end of the recess in the non-DSG notch region 703 may be flush with the lower end of the recess in the DSG notch region 705. By controlling etching conditions (e.g., etching rate, cycle, and / or time), etching can be stopped when the lower end of the recess in the non-DSG notch region 703 and the DSG notch region 705 is between the first uppermost sacrificial layer 706 and the second uppermost sacrificial layer 706.

[0097] like Figure 7G As shown, channel plugs 736 and 728 can be simultaneously formed by depositing semiconductor material (e.g., polysilicon) into the recesses in the non-DSG notch region 703 and the DSG notch region 705, respectively, using one or more thin-film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof). A planarization process (e.g., CMP, wet etching, and / or dry etching) can then be applied to planarize the channel plugs 736 and 728 such that the upper ends of the channel plugs 736 and 728 are flush with each other with the top surface of the dielectric stack layer 704. As a result, according to some embodiments, after planarization, the height of the channel plug 728 in the DSG notch region 705 is nominally the same as the height of the channel plug 736 in the non-DSG notch region 703. In some embodiments, the lower end of each channel plug 736 or 738 is below the remainder of the first uppermost sacrificial layer 706 (e.g., between the first uppermost sacrificial layer 706 and the second uppermost sacrificial layer 706). Thus, memory strings 738, each including a corresponding channel structure 710 and a channel plug 736, can be formed through the dielectric stack layer 704, including the remaining portion of the first uppermost sacrificial layer 706 in the non-DSG cutout region 703. Similarly, memory strings 727, each including a corresponding channel structure 711 and a channel plug 728, can be formed through the dielectric stack layer 704 in the DSG cutout region 705, which does not contain the first uppermost sacrificial layer 706.

[0098] like Figure 7HAs shown, bit line contacts 722 are formed above and in contact with the channel plugs 736 of the memory string 738 in the non-DSG cutout region 603 and the channel plugs 728 of the memory string 727 in the DSG cutout region 705, respectively. Bit lines 724 can be formed above and in contact with the bit line contacts 722 in the non-DSG cutout region 703 and the DSG cutout region 705, respectively.

[0099] Figure 10 A flowchart illustrating a method 1000 for operating an exemplary 3D memory device having a DSG notch, according to some embodiments of the present disclosure, is shown. Although the following will be related to... Figure 2B and Figure 3B Examples of 3D memory devices 200 and 300 depicted in the text are described together. Figure 10 However, it should be understood that any other suitable examples of the 3D memory devices disclosed herein (e.g., Figure 4A , Figure 4B and Figure 5B Method 1000 can be implemented similarly to the 3D memory devices 400, 401, or 501 depicted in the diagram. It should also be understood that the operations shown in method 1000 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 10 The different execution orders shown.

[0100] refer to Figure 10 Method 1000 begins at operation 1002, wherein a 3D memory device is provided, the 3D memory device including a first memory string, a second memory string, a first DSG line adjacent to the first memory string at a first cell, and second DSG lines adjacent to the first memory string and the second memory string at second cells and third cells, respectively. In some embodiments, the first DSG line is not adjacent to the second memory string. In some embodiments, the first cell and the second cell are configured to control the drain of the first memory string, and the third cell is configured to control the drain of the second memory string.

[0101] like Figure 2BAs shown, according to some embodiments, the 3D memory device 200 includes a first memory string 210 in a non-DSG cutout region 204, a second memory string 210 in a DSG cutout region 206, a first DSG line 228 adjacent to the first memory string 210 in the non-DSG cutout region 204 at a first DSG cell 214, and second DSG lines 230 adjacent to the first memory string 210 and the second memory string 210 in the non-DSG cutout region 204 and the DSG cutout region 206, respectively, at a second DSG cell 216 and a third DSG cell 218. In some embodiments, due to the DSG cutout 208, the first DSG line 228 is not adjacent to the second memory string 210 in the DSG cutout region 206. In some embodiments, the first DSG unit 214 and the second DSG unit 216 are configured to control the drain of the first memory string 210 in the non-DSG cutout region 204, and the third DSG unit 218 is configured to control the drain of the second memory string 210 in the DSG cutout region 206.

[0102] Method 1000 proceeds to operation 1004, such as... Figure 10 As shown, threshold voltages are set for the first unit, the second unit, and the third unit such that the threshold voltage of the first unit is higher than the threshold voltage of the second unit, and the threshold voltage of the third unit is higher than the threshold voltage of the second unit. In some embodiments, the threshold voltages of the first unit and the third unit are nominally the same.

[0103] like Figure 2B As shown, the threshold voltage V of the first DSG unit 214 is set. t1 The threshold voltage V of the second DSG unit 216 t2 and the threshold voltage V of the third DSG unit 218 t3 This causes the threshold voltage V of the first DSG unit 214 to be... t1 The threshold voltage V of the second DSG unit 216 is higher than t2 And the threshold voltage V of the third DSG unit 218 t3 The threshold voltage V of the second DSG unit 216 is higher than t2 That is, V t1 >V t2 And V t3 >V t2 In some embodiments, the threshold voltage V of the first DSG unit 214 t1 With the threshold voltage V of the third DSG unit 218 t3 The nominal locations are the same, that is, V t1 =V t3 >V t2Each DSG cell 214, 216, or 218 can be a transistor having an intrinsic threshold voltage determined by, for example, the size and properties (e.g., carrier concentration and carrier mobility) of the semiconductor material (and dopants, if present) in the semiconductor channel of the respective channel structure 212. The threshold voltage V of each DSG cell 214, 216, or 218 can be changed by, for example, a manufacturer and / or a user using, for example, programming and / or erasing operations after the fabrication of the 3D memory device 200. t1 V t2 or V t3 Set its intrinsic threshold voltage to the desired level.

[0104] Method 1000 proceeds to operation 1006, such as... Figure 10 As shown, a first voltage and a second voltage are applied to the first DSG line and the second DSG line, respectively, so that when the first voltage is higher than the threshold voltage of the first cell and the second voltage is higher than the threshold voltage of the second cell but lower than the threshold voltage of the third cell, the first memory string is selected and the second memory string is deselected.

[0105] like Figure 2B As shown, according to some embodiments, the first voltage V dsg0 Apply to the first DSG line 228, and apply the second voltage V dsg1 It is applied to the second DSG line 230. According to some embodiments, when the first voltage V... dsg0 The threshold voltage V of the first DSG unit 214 is higher than t1 And the second voltage V dsg1 The threshold voltage V of the second DSG unit 216 is higher than t2 However, it is lower than the threshold voltage V of the third DSG unit 218. t3 At that time, that is, V dsg0 >V t1 And V t3 >V dsg1 >V t2 At this time, both the first DSG unit 214 and the second DSG unit 216 of the first memory string 210 in the non-DSG cut-out region 204 are turned on, while the third DSG unit 218 of the second memory string 210 in the DSG cut-out region 206 is turned off. As a result, the first memory string 210 in the non-DSG cut-out region 204 can be selected, while the second memory string 210 in the DSG cut-out region 206 can be deselected.

[0106] Method 1000 proceeds to operation 1008, such as... Figure 10As shown, a first voltage and a second voltage are applied to the first DSG line and the second DSG line, respectively, so that when the first voltage is lower than the threshold voltage of the first cell and the second voltage is higher than the threshold voltage of the third cell, the first memory string is deselected and the second memory string is selected.

[0107] like Figure 2B As shown, according to some embodiments, the first voltage V dsg0 Apply to the first DSG line 228, and apply the second voltage V dsg1 It is applied to the second DSG line 230. According to some embodiments, when the first voltage V... dsg0 The voltage V below the threshold voltage of the first DSG unit 214 t1 And the second voltage V dsg1 The threshold voltage V of the third DSG unit 218 is higher than that of the third DSG unit 218. t3 At that time, that is, V dsg0 <V t1 And V dsg1 >V t3 At this time, the first DSG unit 214 is turned on, the second DSG unit 216 is turned off, and the third DSG unit 218 is turned on. As a result, the first memory string 210 in the non-DSG cutout region 204 can be deselected (because the second DSG unit 216 is turned off), while the second memory string 210 in the DSG cutout region 206 can be selected.

[0108] It should be understood that the above text regarding Figure 2B and Figure 10 The disclosed operating methods can be applied in a similar manner. Figure 3B The 3D memory device 300, as described above, may include two non-DSG cutout regions 304 and 305 and a memory string 310, three DSG lines 328, 329 and 330, and five DSG cells 314, 315, 316, 317 and 318 in a DSG cutout region 306. According to the following exemplary Table I, the threshold voltage V of the first DSG cell 314, the second DSG cell 315, the third DSG cell 316, the fourth DSG cell 317 and the fifth DSG cell 318 are set. t1 V t2 V t3 V t4 and V t5 A first voltage V is applied to the first DSG line 328, the second DSG line 330, and the third DSG line 329, respectively. dsg0 Second voltage V dsg1 and the third voltage V dsg2The first memory string, the second memory string, and the third memory string 310 in each region 304, 305, or 306 can be selected individually.

[0109] Table I

[0110] String region DSG Unit 1 DSG Unit 2 / 4 DSG Unit 3 DSG Unit 5 Choose 304 <![CDATA[Conduction: V dsg0 >V t1 > <![CDATA[Conduction: V dsg1 >V t2 / 4 > <![CDATA[Cut-off: V dsg1 <V t3 > <![CDATA[Cut-off: V dsg2 <V t5 > Choose 305 <![CDATA[Cut-off: V dsg0 <V t1 > <![CDATA[Conduction: V dsg1 >V t2 / 4 > <![CDATA[Cut-off: V dsg1 <V t3 > <![CDATA[Conduction: V dsg2 >V t5 > Choose 306 <![CDATA[Cut-off: V dsg0 <V t1 > <![CDATA[Conduction: V dsg1 >V t2 / 4 > <![CDATA[Conduction: V dsg1 >V t3 > <![CDATA[Cut-off: V dsg2 <V t5 >

[0111] According to one aspect of this disclosure, a 3D memory device includes a memory stack layer, a plurality of memory strings, and a plurality of bit line contacts, each bit line contacting a corresponding memory string among the plurality of memory strings. The memory stack layer includes staggered conductive layers and dielectric layers. Each memory string extends vertically through the memory stack layer. The conductive layers include a plurality of drain-select-gate (DSG) lines configured to control the drains of the plurality of memory strings. In a plan view, the plurality of memory strings are divided into a plurality of regions, the plurality of regions being the smallest repeating unit of the memory stack layer. Each of the plurality of memory strings is adjacent to at least one of the DSG lines.

[0112] In some embodiments, the multiple regions include DSG incision regions and non-DSG incision regions, and the number of DSG lines in the non-DSG incision regions is greater than the number of DSG lines in the DSG incision regions.

[0113] In some embodiments, the number of memory strings in the non-DSG cutout region is the same as the number of memory strings in the DSG cutout region.

[0114] In some embodiments, the DSG cutout region does not have a dummy memory string.

[0115] In some embodiments, the height of each memory string in the non-DSG cutout region is greater than the height of each memory string in the DSG cutout region.

[0116] In some embodiments, the height of each bit line contact in the DSG notch region is greater than the height of each bit line contact in the non-DSG notch region.

[0117] In some embodiments, in a plan view, multiple regions include a DSG incision region between two non-DSG incision regions.

[0118] In some embodiments, each of the memory strings includes a channel plug at one end that contacts a corresponding bit line contact.

[0119] In some embodiments, the channel plug in the DSG cut area is vertically positioned between at least two of the DSG lines.

[0120] In some embodiments, the 3D memory device further includes a GLS that extends laterally in the word line direction, and a DSG cutout region that extends laterally in the word line direction parallel to the GLS.

[0121] In some embodiments, the DSG line includes the outermost conductive layer in the conductive layer.

[0122] In some embodiments, the memory string in the DSG cutout region does not extend beyond the outermost conductive layer.

[0123] In some embodiments, the DSG line has different lateral dimensions.

[0124] According to another aspect of this disclosure, a method for forming a 3D memory device is disclosed. A dielectric stack layer comprising interleaved sacrificial layers and dielectric layers is formed over a substrate. A first channel structure and a second channel structure are formed, both extending vertically through the dielectric stack layer. A portion of the uppermost sacrificial layer in the sacrificial layer and the top portion of the second channel structure adjacent to the removed uppermost sacrificial layer are removed, such that the first channel structure extends vertically through a first region of the dielectric stack layer including the remaining portion of the uppermost sacrificial layer, and the remaining portion of the second channel structure extends vertically through a second region of the dielectric stack layer without the uppermost sacrificial layer.

[0125] In some embodiments, in order to simultaneously form a first memory string and a second memory string, a first channel structure and a second channel structure are simultaneously formed, which extend vertically through a first region and a second region of the dielectric stack layer, respectively. A dielectric rise layer is formed on the first region of the dielectric stack layer but not on the second region. A first recess is formed that passes through the dielectric rise layer into the top portion of the first channel structure and a second recess is formed that enters the top portion of the second channel structure. A first channel plug and a second channel plug are simultaneously formed in the first recess and the second recess, respectively.

[0126] In some embodiments, a first channel plug is formed in the top portion of the first channel structure, and a second channel plug is formed in the top portion of the remaining portion of the second channel structure.

[0127] In some embodiments, a memory stack layer comprising interleaved conductive and dielectric layers is formed by replacing the sacrificial layer of the dielectric stack layer with a conductive layer, and a first bit contact and a second bit contact are formed above and in contact with the first and second channel plugs, respectively.

[0128] In some embodiments, the lower end of the first channel plug is higher than the remaining portion of the uppermost sacrificial layer, and the upper end of the second channel plug is lower than the remaining portion of the uppermost sacrificial layer.

[0129] According to another aspect of this disclosure, a method for operating a 3D memory device is disclosed. A 3D memory device is provided, comprising a first memory string, a second memory string, a DSG line adjacent to the first memory string at a first cell, and second DSG lines adjacent to the first and second memory strings at second and third cells, respectively. Threshold voltages for the first, second, and third cells are set such that the threshold voltage of the first cell is higher than the threshold voltage of the second cell, and the threshold voltage of the third cell is higher than the threshold voltage of the second cell. The first voltage and the second voltage are applied to the first and second DSG lines, respectively, such that when the first voltage is higher than the threshold voltage of the first cell, and the second voltage is higher than the threshold voltage of the second cell but lower than the threshold voltage of the third cell, the first memory string is selected and the second memory string is deselected.

[0130] In some embodiments, a first voltage and a second voltage are applied to a first DSG line and a second DSG line, respectively, to deselect the first memory string and select the second memory string when the first voltage is lower than the threshold voltage of the first cell and the second voltage is higher than the threshold voltage of the third cell.

[0131] In some embodiments, the threshold voltages of the first unit and the third unit are nominally the same.

[0132] In some embodiments, the first unit and the second unit are configured to control the drain of the first memory string, and the third unit is configured to control the drain of the second memory string.

[0133] In some embodiments, the first DSG line is not adjacent to the second memory string.

[0134] The above description of specific embodiments will therefore fully reveal the general nature of this disclosure, enabling others to readily modify and / or adapt such specific embodiments for various applications using knowledge within the scope of the art, without excessive experimentation and without departing from the general concept of this disclosure. Therefore, based on the teachings and guidance presented herein, such modifications and adaptations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology used herein is for illustrative purposes and not for limitation, and thus the terminology or terminology of this specification will be interpreted by those skilled in the art in accordance with the teachings and guidance presented.

[0135] The embodiments of this disclosure have been described above using functional building blocks, which exemplify implementations of specified functions and their relationships. The boundaries of these functional building blocks are arbitrarily defined herein for ease of description. Alternative boundaries may be defined, provided that the specified functions and their relationships are appropriately performed.

[0136] The summary and abstract may set forth one or more exemplary embodiments of the present disclosure as conceived by the inventors, but not necessarily all exemplary embodiments, and therefore are not intended to limit the present disclosure and the appended claims in any way.

[0137] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, and should be defined solely by the following claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device, comprising: A memory stack layer, the memory stack layer comprising vertically interleaved conductive layers and dielectric layers; Multiple memory strings, each extending vertically through the memory stack layer; as well as Multiple bit line contacts, each of which is in contact with a corresponding memory string among the multiple memory strings. The conductive layer includes multiple drain-select gate (DSG) lines configured to control the drains of the plurality of memory strings. In the plan view, the plurality of memory strings are divided into multiple regions by gate slots (GLS) extending laterally in the word line direction, and these multiple regions are the smallest repeating unit of the memory stack; and Each of the plurality of memory strings is adjacent to at least one of the DSG lines, and each of the plurality of regions includes at least one DSG cut-out region and at least one non-DSG cut-out region, and the number of DSG lines differs between each of the at least one DSG cut-out region and the at least one non-DSG cut-out region. Each of the memory strings includes a channel plug at one end that contacts a corresponding bit line contact, and wherein the lower end of the channel plug in the non-DSG cut-out region is above the plurality of DSG lines, and the lower end of the channel plug in the DSG cut-out region is above the lowest DSG line among the plurality of DSG lines.

2. The 3D memory device according to claim 1, wherein, The number of DSG lines in the non-DSG incision area is greater than the number of DSG lines in the DSG incision area.

3. The 3D memory device according to claim 2, wherein, The number of memory strings in the non-DSG cutout region is the same as the number of memory strings in the DSG cutout region.

4. The 3D memory device according to claim 2 or 3, wherein, The DSG cutout area does not have a dummy memory string.

5. The 3D memory device according to any one of claims 2 to 4, wherein, The height of each of the memory strings in the non-DSG cutout region is greater than the height of each of the memory strings in the DSG cutout region.

6. The 3D memory device according to any one of claims 2 to 5, wherein, The height of each of the bit line contacts in the DSG cutout region is greater than the height of each of the bit line contacts in the non-DSG cutout region.

7. The 3D memory device according to any one of claims 2 to 6, wherein, In the plan view, the plurality of regions include the DSG incision region between two non-DSG incision regions.

8. The 3D memory device according to claim 1, wherein, The channel plug in the DSG cut area is vertically positioned between at least two of the DSG lines.

9. The 3D memory device according to any one of claims 2 to 8, wherein, The DSG cutout area extends laterally parallel to the GLS in the word line direction.

10. The 3D memory device according to any one of claims 1 to 9, wherein, The DSG line includes the outermost conductive layer of the conductive layer.

11. The 3D memory device according to claim 10, wherein, The memory string in the DSG cutout region does not extend beyond the outermost conductive layer.

12. The 3D memory device according to any one of claims 1 to 11, wherein, The DSG lines have different lateral dimensions.

13. The 3D memory device according to any one of claims 1 to 11, wherein, In each of the plurality of regions, each bit line makes contact with a corresponding one of the plurality of bit line contacts.

14. A method for forming a three-dimensional (3D) memory device, comprising: A dielectric stack layer comprising an interleaved sacrificial layer and a dielectric layer is formed over the substrate; A first channel structure and a second channel structure are formed, both of which extend vertically through the dielectric stack layer. as well as A portion of the uppermost sacrificial layer in the sacrificial layer and the top portion of the second channel structure adjacent to the removed portion of the uppermost sacrificial layer are removed, such that the first channel structure extends vertically through a first region of the dielectric stack including the remaining portion of the uppermost sacrificial layer, and the remaining portion of the second channel structure extends vertically through a second region of the dielectric stack without the uppermost sacrificial layer. A memory stack layer comprising interlaced conductive layers and dielectric layers is formed by replacing the sacrificial layer of the dielectric stack layer with a conductive layer; In the planar diagram, the first and second channel structures are divided into multiple regions by gate slots (GLS) extending laterally in the word line direction. These multiple regions are the smallest repeating unit of the memory stack layer. The conductive layer includes multiple drain-select gate (DSG) lines, each of the multiple regions including at least one first region and at least one second region, and the number of DSG lines differs between each of the at least one first region and the at least one second region. Each of the first channel structure and the second channel structure includes a channel plug at one end, wherein the lower end of the channel plug of the first channel structure is above the plurality of DSG lines, and the lower end of the channel plug of the second channel structure is above the lowermost DSG line of the plurality of DSG lines.

15. The method of claim 14, further comprising: A first channel plug is formed in the top portion of the first channel structure, and a second channel plug is formed in the top portion of the remaining portion of the second channel structure.

16. The method of claim 15, further comprising: A first bit line contact and a second bit line contact are formed. The first bit line contact and the second bit line contact are respectively above the first channel plug and the second channel plug and respectively in contact with the first channel plug and the second channel plug. Furthermore, each bit line contacts the first channel structure and the second channel structure through a corresponding one of the first bit line contact and the second bit line contact.

17. The method according to claim 15 or 16, wherein, The lower end of the first channel plug is higher than the remaining portion of the uppermost sacrificial layer, and the upper end of the second channel plug is lower than the remaining portion of the uppermost sacrificial layer.

18. A method for operating a three-dimensional (3D) memory device, comprising: A 3D memory device is provided according to any one of claims 1-13, the 3D memory device comprising a first memory string in the non-DSG cutout region, a second memory string in the DSG cutout region, a first DSG line adjacent to the first memory string at a first cell, and second DSG lines adjacent to the first memory string and the second memory string at a second cell and a third cell, respectively. The threshold voltages of the first unit, the second unit, and the third unit are set such that the threshold voltage of the first unit is higher than the threshold voltage of the second unit, and the threshold voltage of the third unit is higher than the threshold voltage of the second unit; as well as A first voltage and a second voltage are applied to the first DSG line and the second DSG line, respectively, so that when the first voltage is higher than the threshold voltage of the first unit and the second voltage is higher than the threshold voltage of the second unit but lower than the threshold voltage of the third unit, the first memory string is selected and the second memory string is deselected.

19. The method of claim 18, further comprising applying the first voltage and the second voltage to the first DSG line and the second DSG line respectively, to deselect the first memory string and select the second memory string when the first voltage is lower than the threshold voltage of the first unit and the second voltage is higher than the threshold voltage of the third unit.

20. The method according to claim 18 or 19, wherein, The threshold voltages of the first unit and the third unit are nominally the same.

21. The method according to any one of claims 18 to 20, wherein, The first unit and the second unit are configured to control the drain of the first memory string, and the third unit is configured to control the drain of the second memory string.

22. The method according to any one of claims 18 to 21, wherein, The first DSG line is not adjacent to the second memory string.

23. The method according to claim 18, wherein, Each bit line contacts the first memory string and the second memory string through a corresponding one of a plurality of bit line contacts.

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