Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device in which, even if the silicon-based semiconductor material is different, the on-off loss can be made the same if the on voltage is the same. The present invention also relates to a manufacturing method of a semiconductor device. The semiconductor device according to the present invention includes: a semiconductor substrate having a first main surface and a second main surface; a drift layer of a first conductivity type formed on the semiconductor substrate; a first impurity diffusion layer of a second conductivity type formed on the first main surface side of the drift layer; and a buffer layer of the first conductivity type formed on the second main surface side of the drift layer, the peak impurity concentration of which is higher than that of the drift layer, the drift layer having: a first well whose energy level is lower than that of the conduction band bottom by 0.246 eV; a second well whose energy level is lower than that of the conduction band bottom by 0.349 eV; and a third well whose energy level is lower than that of the conduction band bottom by 0.470 eV, the well density of the second well being greater than or equal to 2.0 x 1014 cm-2. 11 ‑3 ​​

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, and particularly to a semiconductor device for power use. BACKGROUND

[0002] As a basic performance of a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) and a freewheeling diode (FWD), a trade-off characteristic between an on-voltage and an on-off loss is cited. The trade-off characteristic is controlled, for example, by a method of controlling a carrier lifetime by implanting charged particles such as electrons, protons, helium, or heavy metals such as platinum into a semiconductor layer. For a large-diameter wafer of which a diameter is greater than or equal to 200 mm, which is a recent technical trend of a power semiconductor element, implantation of protons into an N-type buffer layer, which is a structural element of an IGBT and an FWD, is studied, and a relationship with silicon (Si) as a wafer material is discussed.

[0003] For example, in Patent Literature 1, a structure in which a donor layer, that is, a proton donor layer, which is made of a crystal defect donor by proton irradiation, is formed in a power semiconductor element is disclosed. In Patent Literature 1, a relationship between a dose at the time of proton irradiation for forming the proton donor layer and a trap level of a recombination defect in the proton donor layer is disclosed in view of the recombination defect in the proton donor layer.

[0004] Patent Literature 1: International Publication No. 2013 / 073623

[0005] In Patent Literature 1, in view of the recombination defect in the proton donor layer, the recombination defect is formed, thereby efficiently making the crystal defect a donor, and an increase in an on-voltage and a leakage current is suppressed, but a trade-off characteristic between the on-voltage and the on-off loss is not disclosed. SUMMARY

[0006] The present application is made to solve the above-described problems, and has an object to provide a semiconductor device which can make an on-off loss the same if an on-voltage is the same even in a case where a silicon-based semiconductor material is different.

[0007] The semiconductor device according to the present application includes a semiconductor substrate having a first main surface and a second main surface, a drift layer of a first conductivity type formed on the semiconductor substrate, a first impurity diffusion layer of a second conductivity type formed on the first main surface side of the drift layer, and a buffer layer of the first conductivity type formed on the second main surface side of the drift layer, the buffer layer having a higher peak impurity concentration than the drift layer, the drift layer having a first well having an energy level lower than that of a conduction band bottom by 0.234 eV, a second well having an energy level lower than that of the conduction band bottom by 0.349 eV, and a third well having an energy level lower than that of the conduction band bottom by 0.470 eV, the second well having a well density of 2.0 x 1012 / cm2 or more. 11 cm -3 .

[0008] Effects of the Invention

[0009] According to the semiconductor device according to the present application, even in a case where a silicon-based semiconductor material is different, in trade-off characteristics of on-voltage and turn-off loss, if the on-voltage is the same, the turn-off loss can be made the same. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a plan view of the semiconductor device according to the present application.

[0011] Figure 2 is a cross-sectional view of the RFC diode according to Embodiment 1 and a graph showing the impurity concentration distribution in the depth direction.

[0012] Figure 3 is a cross-sectional view showing the structure of the outer peripheral portion of the semiconductor device having the RFC diode according to Embodiment 1.

[0013] Figure 4 is a graph showing the effects of the RFC diode according to Embodiment 1.

[0014] Figure 5 is a graph showing the relationship between the dose and the well density of the recombination defects VOH when an electron beam is irradiated to the RFC diode according to Embodiment 1.

[0015] Figure 6 is a graph showing the relationship between the on-voltage of the RFC diode according to Embodiment 1 and the well density of the recombination defects VOH caused by irradiation of an electron beam.

[0016] Figure 7 is a graph showing the trade-off characteristics of the on-voltage and the recovery loss of the RFC diode according to Embodiment 1.

[0017] Figure 8is a graph showing the relationship between the turn-off voltage and the operating temperature at the time of the recovery operation in the fast mode of the RFC diode according to Embodiment 1.

[0018] Figure 9 is a graph showing the relationship between the reverse recovery charge amount and the operating temperature in the fast mode of the RFC diode according to Embodiment 1.

[0019] Figure 10 is a graph showing the relationship between the turn-off current density and the electron beam density at the time of the recovery operation in the large current mode of the RFC diode according to Embodiment 1.

[0020] Figure 11 is a graph showing the reliability evaluation result of the RFC diode according to Embodiment 1.

[0021] Figure 12 is a graph for explaining a manufacturing method of a semiconductor device having the RFC diode according to Embodiment 1.

[0022] Figure 13 is a graph for explaining a manufacturing method of a semiconductor device having the RFC diode according to Embodiment 1.

[0023] Figure 14 is a graph for explaining a manufacturing method of a semiconductor device having the RFC diode according to Embodiment 1.

[0024] Figure 15 is a graph for explaining a manufacturing method of a semiconductor device having the RFC diode according to Embodiment 1.

[0025] Figure 16 is a graph for explaining a manufacturing method of a semiconductor device having the RFC diode according to Embodiment 1.

[0026] Figure 17 is a graph for explaining a manufacturing method of a semiconductor device having the RFC diode according to Embodiment 1.

[0027] Figure 18 is a graph for explaining a manufacturing method of a semiconductor device having the RFC diode according to Embodiment 1.

[0028] Figure 19 is a graph for explaining a manufacturing method of a semiconductor device having the RFC diode according to Embodiment 1.

[0029] Figure 20 is a graph for explaining a manufacturing method of a semiconductor device having the RFC diode according to Embodiment 1.

[0030] Figure 21 is a flowchart showing a procedure of controlling the trap density of the recombination defects in the drift layer of the RFC diode according to Embodiment 1.

[0031] Figure 22 is a graph showing the relationship between the lifetime and the 2nd annealing temperature in the drift layer of the RFC diode according to Embodiment 1.

[0032] Figure 23 is a graph showing the relationship between the PL intensity of the recombination defects in the drift layer of the RFC diode according to Embodiment 1 and the 4th annealing temperature.

[0033] Figure 24 is a graph showing the relationship between the PL intensity of the recombination defects in the drift layer of the RFC diode according to Embodiment 1 and the 4th annealing time.

[0034] Figure 25 is a cross-sectional view of a PiN diode according to Embodiment 2.

[0035] Figure 26 is a cross-sectional view showing the configuration of the outer peripheral portion of a semiconductor device having the PiN diode according to Embodiment 2.

[0036] Figure 27 is a cross-sectional view of a trench gate type IGBT according to Embodiment 3.

[0037] Figure 28 is a cross-sectional view showing the configuration of the outer peripheral portion of a semiconductor device having the trench gate type IGBT according to Embodiment 3.

[0038] Figure 29 is a cross-sectional view showing the configuration of a modification example of the outer peripheral portion of a semiconductor device having the trench gate type IGBT according to Embodiment 3.

[0039] Figure 30 is a cross-sectional view of a trench gate type RC-IGBT according to Embodiment 4.

[0040] Figure 31 is a cross-sectional view of a trench gate type RC-IGBT according to Embodiment 5.

[0041] Figure 32 is a cross-sectional view of an RFC diode according to Embodiment 6.

[0042] Figure 33 is a cross-sectional view of a PiN diode according to Embodiment 6.

[0043] Figure 34is a cross-sectional view of a trench gate type IGBT to which Embodiment 6 is applied.

[0044] Figure 35 is a graph showing the analysis result of the buffer layer of the RFC diode to which Embodiment 6 is applied, obtained by the PL method.

[0045] Figure 36 is a flowchart showing the manufacturing process of the buffer layer of the RFC diode to which Embodiment 6 is applied.

[0046] Figure 37 is a graph showing the relationship between the PL intensity and the annealing time of the lattice defects of the second buffer layer of the RFC diode to which Embodiment 6 is applied.

[0047] Figure 38 is a cross-sectional view of a trench gate type RC-IGBT to which Embodiment 7 is applied.

[0048] Figure 39 is a cross-sectional view of a trench gate type RC-IGBT to which Embodiment 8 is applied. DETAILED DESCRIPTION

[0049] <INTRODUCTION>

[0050] In the following embodiments, IGBT, a freewheeling diode (FWD) are shown as representative examples of power semiconductor elements constituting a semiconductor device for power use. Further, in the following, "diode" means FWD. However, the technology to which the present application is applied also achieves the same effects for power semiconductor elements such as RC (Reverse Conducing)-IGBT, RB (Reverse Blocking)-IGBT, MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and the like.

[0051] Further, in each of the embodiments, Si is used as a semiconductor material, but not only Si, but also semiconductor elements using wide band gap materials such as SiC (silicon carbide), GaN (gallium nitride), and the like will achieve the same effects. Further, in each of the embodiments, as a Si material, a Si wafer (FZ wafer) manufactured by the FZ (Floating Zone) method is shown as a representative example, but a Si wafer manufactured by the MCZ (Magnetic field applied Czochralski) method, which has a higher residual oxygen concentration than the FZ wafer, and an oxygen content of 10 17 cm -3 orders of magnitude can also be used. Further, in each of the embodiments, semiconductor devices of 1200 V, 4.5 kV voltage classes are exemplified, but the same effects will be achieved regardless of the voltage class.

[0052] <Embodiment 1>

[0053] <Device Structure>

[0054] In Embodiment 1, as a power semiconductor element, an RFC (Relaxed Field of Cathode) diode having a configuration in which a cathode layer is partially replaced with a P-type region is shown.

[0055] Figure 1 is a plan view of a semiconductor device to which Embodiment 1 is applied. As shown in Figure 1 , a plurality of strip-shaped active cell regions R1 are provided in a central portion of the semiconductor device, surface gate wiring portions R11 are provided between adjacent two active cell regions R1, and gate pad portions R12 are provided in a part of the central portion. Further, an intermediate region R2 is provided in a manner of surrounding the active cell regions R1, the gate pad portions R12, and the surface gate wiring portions R11, and an edge termination region R3 is provided in a manner of surrounding the intermediate region R2. In a diode, the gate pad portions R12 and the surface gate wiring portions R11 are sometimes not present. Further, plan views of semiconductor devices of Embodiments 2 to 8 to be described later are also the same as Figure 1 .

[0056] The active cell regions R1 are element formation regions that guarantee basic performance of the semiconductor device. The intermediate region R2 and the edge termination region R3 are regions for voltage holding. Among them, the intermediate region R2 is a region that joins the active cell regions R1 and the edge termination region R3, guarantees a breakdown resistance at the time of dynamic operation of the semiconductor device, and supports the original performance of the semiconductor elements formed in the active cell regions R1. Further, the edge termination region R3 undertakes voltage holding in a static state of the semiconductor device, stability of voltage holding characteristics and guarantee of reliability, and suppression of a breakdown resistance failure at the time of dynamic operation of the semiconductor device, and supports the original performance of the semiconductor elements formed in the active cell regions R1.

[0057] Figure 2 is a cross-sectional view of an RFC diode that constitutes a semiconductor device to which Embodiment 1 is applied, and corresponds to a cross section along the A1-A2 line of Figure 1 . Further, Figure 3 is a cross-sectional view showing an example of a configuration of an outer peripheral portion of a semiconductor device having the RFC diode to which Embodiment 1 is applied, Figure 3 and corresponds to a cross section along the A1-A2 line of Figure 1The cross-sections along lines A3-A4 are equivalent. Here, the upper surface of the semiconductor substrate in the cross-sectional view is defined as the "first principal surface," and the lower surface is defined as the "second principal surface." Sometimes the first principal surface is referred to as the "upper surface" or "surface," and the second principal surface is referred to as the "lower surface" or "back side."

[0058] First, refer to Figure 2 The structure of the RFC diode formed in the active cell region R1 will be described. The semiconductor substrate constituting the RFC diode has a first main surface (front side) and a second main surface (back side), and an N-type (first conductivity type) N-type diode is formed thereon. - Drift layer 14. On the N-type semiconductor substrate... - Below the drift layer 14, there is formed a layer with N - The drift layer 14 is compared to the N-type N-buffer layer 15, which has a higher peak impurity concentration. Details of the N-buffer layer 15 will be described later.

[0059] Beneath the N-buffer layer 15 of the semiconductor substrate, N-type N-type structures with a higher peak impurity concentration than the N-buffer layer 15 are formed adjacent to each other. + Cathode layer 17 (first cathode layer) and P-type (second conductivity type) P-cathode layer 18 (second cathode layer). N + Cathode layer 17 and P-cathode layer 18 are formed on the surface portion of the back side (second main surface side) of the semiconductor substrate, above the back side of the semiconductor device, to interact with N-cathode layer 18. + A cathode electrode 19 is formed by contacting the cathode layer 17 and the P-cathode layer 18.

[0060] In the N of the semiconductor substrate - A P-type P-anode layer 10 (first impurity diffusion layer) is formed on top of the drift layer 14. In the RFC diode, the P-anode layer 10 and the N-type P-anode layer 10 are... - The drift layer 14 is the main junction. The P anode layer 10 is formed on the surface portion of the upper surface (first main surface) of the semiconductor substrate, and an anode electrode 5 is formed on the upper surface of the semiconductor substrate in contact with the P anode layer 10.

[0061] like Figure 2 As shown, P anode layer 10, N - Drift layer 14, N buffer layer 15 and N + Cathode layer 17 forms region R21 of PiN (P-intrinsic-N) diode, P anode layer 10, N - Drift layer 14, N-buffer layer 15, and P-cathode layer 18 constitute the PNP transistor region R22. That is, in terms of the RFC diode, if represented by an equivalent circuit, it becomes a structure of a PiN diode and a PNP transistor connected in parallel. Furthermore, regarding the N... -Regarding drift layer 14, if the RFC diode becomes on, the carrier concentration changes due to conductivity modulation, therefore the N... - The drift layer 14 becomes a variable resistance region. In addition, the structure from the main junction to the cathode electrode 19 is called the longitudinal structure 35.

[0062] Compared to PiN diodes, RFC diodes exhibit characteristic effects in diode performance, such as field mitigation, which reduces the electric field strength on the cathode side. Specifically, during the latter half of the recovery operation, the electric field strength on the cathode side is mitigated by promoting hole injection from the P-cathode layer 18. This suppresses the snap-off phenomenon (voltage jump) at the end of the recovery operation and subsequent oscillations, thereby improving the damage tolerance during recovery.

[0063] In the RFC diode according to Embodiment 1, the parameters of the diffusion layer are set as follows. N - Drift layer 14 is composed of impurity concentration (C) n- ) greater than or equal to 1.0 × 10 12 cm -3 And less than or equal to 5.0 × 10 14 cm -3 A Si wafer (FZ wafer) is formed using the FZ method. Furthermore, the oxygen concentration of this FZ wafer is less than or equal to 3.0 × 10⁻⁶. 15 cm -3 The carbon concentration is greater than or equal to 1.0 × 10⁻⁶. 14 cm -3 And less than or equal to 5.0 × 10 15 cm -3 Additionally, N - The drift layer 14 can also be formed on a Si wafer fabricated by the MCZ method (MCZ wafer). In the case of an MCZ wafer, the oxygen concentration is less than or equal to 7.0 × 10⁻⁶. 17 cm -3 The carbon concentration is greater than or equal to 1.0 × 10⁻⁶. 14 cm -3 And less than or equal to 5.0 × 10 15 cm -3 .

[0064] The final device thickness (t) device The surface impurity concentration of the P anode layer 10 is set to be greater than or equal to 40 μm and less than or equal to 700 μm. 16 cm -3 The peak impurity concentration is greater than or equal to 2.0 × 10⁻⁶. 16 cm -3 And less than or equal to 1.0 × 10 18cm -3 The depth is greater than or equal to 2.0 μm and less than or equal to 10.0 μm. The N-buffer layer 15 is configured to contain N-type impurities such as phosphorus and arsenic, with a peak impurity concentration (C0). nb1，p ) greater than or equal to 1.0 × 10 16 cm -3 And less than or equal to 5.0 × 10 16 cm -3 Depth (X) j，nb1 (N) Greater than or equal to 1.2 μm and less than or equal to 5.0 μm. + The cathode layer 17 is configured with a surface impurity concentration greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 And less than or equal to 1.0 × 10 21 cm -3 The depth is greater than or equal to 0.3 μm and less than or equal to 0.8 μm. The P-cathode layer 18 is set to have a surface impurity concentration greater than or equal to 1.0 × 10⁻⁶. 16 cm -3 And less than or equal to 1.0 × 10 20 cm -3 The depth is greater than or equal to 0.3 μm and less than or equal to 0.8 μm.

[0065] In addition, Figure 2 The diagram also records the impurity concentration distribution along the depth direction of line B-B' in the longitudinal structure 35. In the impurity concentration distribution, the horizontal axis is represented in arbitrary units (arb.unit) by the thickness of the device (t). device The standardized depth, with the vertical axis expressed in arbitrary units (arb.unit) from N - Impurity concentration (C) of drift layer 14 n- Normalized concentration.

[0066] exist Figure 2 In the impurity concentration distribution, the region from the depth (0.05) of the main junction to the depth 0.40 is the DLTS evaluation region R10, which was evaluated by deep level transient spectroscopy (DLTS).

[0067] Next, refer to Figure 3 The construction of the middle region R2 and the edge termination region R3 of the RFC diode is explained.

[0068] N - Drift layer 14 is formed across the active unit region R1, the intermediate region R2, and the edge termination region R3. In the intermediate region R2, N... -A P-type guard ring 22 is formed in the surface layer portion of the drift layer 14 deeper than the P anode layer 10. The guard ring 22 extends to the active cell region Rl side and is connected to the P anode layer 10. Further, in the edge termination region R3, an N - A P-type field limiting ring 23 is selectively formed in the surface layer portion of the drift layer 14.

[0069] Further, outside the field limiting ring 23, an N - A channel stopper layer 24 of an N + type is selectively formed in the surface layer portion of the drift layer 14. The channel stopper layer 24 is provided for the purpose of stopping the extension of the depletion layer extending from the guard ring 22 and the field limiting ring 23 to the N - buffer layer 15. The more the number of field limiting rings 23 increases, the higher the withstand voltage level of the RFC diode.

[0070] An insulating film 25 is formed on the upper surface of the semiconductor substrate in the intermediate region R2 and the edge termination region R3, and an interlayer insulating film 26 is formed on the insulating film 25. On the interlayer insulating film 26, an FLR electrode 27 connected to the field limiting ring 23 through a contact hole and a channel stopper electrode 28 connected to the channel stopper layer 24 through a contact hole are formed. Further, the FLR electrode 27 and the channel stopper electrode 28 can be formed at the same time as the anode electrode 5 of the active cell region Rl.

[0071] Further, a passivation film 29, i.e., a protective film covering the FLR electrode 27 and the channel stopper electrode 28, is formed across the intermediate region R2 and the edge termination region R3, and a passivation film 30 is formed on the passivation film 29.

[0072] As shown in FIG. 6, there is a longitudinal structure 35 in which the N - drift layer 14, the N + buffer layer 15, the N Figure 3 cathode layer 17, and the P cathode layer 18 are laminated. The region in which the longitudinal structure 35 is formed is referred to as a "longitudinal structure region".

[0073] The longitudinal structure 35 is a region that ensures the performance of the total loss, i.e., the sum of the loss in the on state, the loss in the on state, the loss in the off state, the stability of the withstand voltage characteristics in the static state, the leakage characteristics (off loss) at the time of voltage holding in the high temperature, the reliability, and the controllability, the breakdown resistance, and the like in the dynamic operation, and supports the basic performance of the semiconductor device.

[0074] Figure 4 is a diagram illustrating the effects in the case where the semiconductor device having the longitudinal structure 35 shown in FIG. 6 is formed by the manufacturing method described later. In Figure 2 the longitudinal structure 35 shown in FIG. 6 is formed by the manufacturing method described later. InFigure 4 The middle shows Figure 2 N in the impurity concentration distribution - The analytical results obtained by the DLTS method for the DLTS evaluation region R10 of drift layer 14.

[0075] In this analysis, diodes were manufactured using both FZ (FZ-sub) and MCZ (MCZ-sub) wafers as Si wafers. Four samples were evaluated: those annealed at 400°C during manufacturing (with 400°C) and those not annealed at 400°C (without 400°C). As described later, the four evaluated diodes underwent electron beam irradiation to control their basic performance.

[0076] The DLTS method is as follows: [The text abruptly ends here, likely due to an incomplete sentence or a formatting Figure 2 The main junction of the longitudinal structure 35 shown is reverse biased to cause the depletion layer to extend toward the cathode side. The response of the electrostatic capacitance change caused by the extension of the depletion layer when the applied voltage is changed is detected, and the trap in the bandgap is measured.

[0077] Specifically, using -100V, which is approximately 10% of the rated withstand voltage of 1200V, as the reverse bias (V R Under the applied state, a pulse bias (V) is applied. P ) is -0.1V, pulse width (T) P A pulse voltage lasting 10 ms. This is the rate window (T). W The result was 192 msec, measured at temperatures ranging from 80 to 300 K.

[0078] exist Figure 4 The vertical axis represents trap concentration, i.e., trap density, and the horizontal axis represents the measurement temperature.

[0079] Figure 2 N in the impurity concentration distribution - The DLTS evaluation region R10 of drift layer 14 is a region with a constant impurity concentration, according to Figure 4 It can be seen that becoming has the existence of N - DLTS spectrum of three characteristic peaks caused by impurity defects in drift layer 14.

[0080] The three characteristic peaks are due to the presence of N -The energy levels formed by wells E1 (first well), E2 (second well), and E3 (third well) in drift layer 14. Well E1 has an energy level 0.234 eV lower than the bottom of the conduction band (Ec - 0.234 eV), well E2 has an energy level 0.349 eV lower than the bottom of the conduction band (Ec - 0.349 eV), and well E3 has an energy level 0.470 eV lower than the bottom of the conduction band (Ec - 0.349 eV). C -0.470eV). The detected wells E1 and E3 are energy levels originating from the recombination defect V2O, while well E2 is an energy level originating from the recombination defect VOH.

[0081] Thus, N, which constitutes the diode in Embodiment 1 of this invention - Drift layer 14 is a semiconductor layer with three wells. The detected impurity defects (recombination defects) are formed by reacting with impurities in Si through the following steps (a) to (e).

[0082] If electrons are introduced into the silicon by irradiating the diode with charged particles, such as an electron beam, then

[0083] Step (a): Reaction with impurities (hydrogen atoms (H), oxygen atoms (O), and carbon atoms (C)) to form holes (V) and interstitial Si pairs (I). si ) and other lattice defects,

[0084] Step (b): The formed lattice defects diffuse and self-aggregate to form aggregated defects (V2). Simultaneously,

[0085] Step (c): The carbon atoms (C atoms) present at the lattice sites occur. s ) and interstitial Si pairs (I si The substitution reaction of carbon (C) forms interstitial carbon (C). i ),

[0086] Step (d): Interstitial carbon (C) i Lattice defects such as (V) and holes diffuse, generating lattice site substitution carbon (C) at room temperature. s ) and interstitial Si pairs (I si The reaction between the silicon and impurities (oxygen, carbon, hydrogen) generates impurity defects such as VOH (composite defects).

[0087] Step (e): Aggregated defects (V2) formed by the self-aggregation of lattice defects diffuse and react with impurities (oxygen, carbon, hydrogen) in Si at a high temperature of less than or equal to 300°C to generate impurity defects (composite defects) such as V2O.

[0088] In the description of steps (a) to (e) above, the subscript i indicates interstitial and s indicates substitutional.

[0089] according to Figure 4 Without annealing at 400℃, the well density of MCZ wafers with high impurity concentration in Si is higher than that of FZ wafers. However, it is known that by annealing at 400℃, well formation is promoted in FZ wafers, resulting in extreme changes in well density, exceeding that in MCZ wafers. It is also known that among the three wells E1 to E3, well E2, which originates from the diffusion of aggregate defects V2 formed through self-aggregation and reacts with impurities (oxygen, carbon, hydrogen) in Si to form composite defects VOH, shows a greater change in well E1 and E3, which originate from composite defects V2O, depending on whether or not annealing at 400℃ has been performed. Therefore, focusing on composite defects VOH and... Figure 2 The relationship between the performance of the diodes shown is explained.

[0090] Figure 5 This is a graph showing the relationship between the electron beam dose when irradiating a diode and the well density of recombination defect VOHs detected by DLTS. Figure 5 In the diagram, the vertical axis represents defect density, and the horizontal axis represents normalized electron beam concentration in arbitrary units (arb.unit). Furthermore, the type of Si wafer, whether annealing was performed, and... Figure 4 same.

[0091] according to Figure 5 It is known that the defect density, or well density, of recombination defects (VOHs) increases with the increase in electron beam irradiation dose, i.e., electron beam density. Regarding the well density of recombination defects (VOHs), MCZ wafers with different Si wafer materials and high impurity concentrations have a higher well density than FZ wafers. However, according to... Figure 5 It is known that annealing at 400°C reduces the difference in well density caused by the Si wafer material. This phenomenon is important for producing the effects of this invention.

[0092] Figure 6 It means Figure 2 The diode's on-state voltage (V) is shown. F A graph showing the relationship between the density of VOH (a composite defect caused by electron beam irradiation) and the density of VOH. Figure 6 In the diagram, the vertical axis represents the forward current density J. F 337A / cm 2 V at a temperature of 150℃ F (V), the horizontal axis represents the defect density (×10).12 cm -3 ). Moreover, the kind of Si wafer, the implementation of annealing or not, and Figure 4 are the same.

[0093] According to Figure 6 , it is known that the on voltage V F becomes higher as the trap density of the recombination defect VOH increases, that is, as the electron beam density increases. Figure 6 The point data of each sample of Figure 5 correspond to the condition of the horizontal axis of each sample in Figure 5 , and the trap density of the recombination defect VOH increases as the increase in the electron beam density. By implementing annealing at 400°C, N - of the drift layer 14 is improved and stabilized, and the on voltage V F of the recombination defect VOH is reduced regardless of the kind of Si wafer, whereby the on voltage V F of the Si wafer material at the same trap density becomes smaller. This phenomenon is an important phenomenon that produces the effect of the present application. According to Figure 5 and Figure 6 , the technology of the present embodiment makes the trap density of the recombination defect VOH higher density even if the electron beam density is the same as compared with the case where 400°C annealing is not performed, expands the control range of the on voltage (V F ) and makes the relationship of the trap density sensitive, and reduces the Si wafer material dependency. In order to achieve this behavior, according to Figure 6 , the N - of the diode of the present embodiment 1 needs to be more than or equal to 2.0 x 1011cm-2in the drift layer 14, which cannot be achieved if 400°C annealing is not performed. In order to achieve this behavior, according to Figure 6 , the N - of the diode of the present embodiment 1 needs to be more than or equal to 2.0 x 1011cm-2in the drift layer 14, which cannot be achieved if 400°C annealing is not performed. 11 cm -3 .

[0094] Figure 7 is a graph showing the trade-off characteristics of the on voltage (V F ) and the off-state loss, that is, the recovery loss (E REC ) of the diode shown in Figure 2 . In Figure 7 , the vertical axis shows E CC for the case where the power supply voltage V F is 600 V, the forward current density J 2 is 337 A / cm REC , and the temperature is 150°C, and the horizontal axis shows V F (V) for the case where the forward current density J 2 is 337 A / cm F , and the temperature is 150°C. Moreover, the kind of Si wafer, the implementation of annealing or not, andFigure 4 same.

[0095] according to Figure 7 Without annealing at 400℃, the dependence of Si material on the electron beam becomes significantly more pronounced with the increase in electron beam dose (i.e., electron beam density) at the same on-state voltage V. F and recovery loss E REC On the trajectory of the trade-off characteristics, the FZ wafer and the MCZ wafer are positioned differently. On the other hand, it can be seen that by implementing annealing at 400°C, due to the use of... Figure 6 The described on-state voltage V F The effect of reduced dependence on Si wafer material, independent of Si wafer material, at the same on-state voltage V F and recovery loss E REC The trade-off characteristics are concentrated at the same point on the trajectory. That is, even when using various Si-based semiconductor materials, as long as the trade-off characteristics of turn-on voltage and turn-off loss are at the same point, i.e., the same turn-on voltage, the recovery loss can be the same.

[0096] Figure 8 It means Figure 2 The diode shown is capable of cutting off the power supply voltage V during recovery operation in its low-current mode, i.e., fast mode. CC A graph showing the relationship between (V) and operating temperature. Figure 8 In the diagram, the vertical axis represents the forward current density J. F 33.7 A / cm 2 (×0.1J A ), dj / dt is 1200A / cm 2 μs, dV / dt is 13000V / μs, stray inductance L S V at 2.0 μH CC (V), with the horizontal axis representing the operating temperature (°C). Additionally, the type of Si wafer, whether or not annealing was performed, and... Figure 4 same.

[0097] according to Figure 8 It is known that without annealing at 400℃, device damage occurs at operating temperatures of -60℃ to -40℃. However, by performing annealing at 400℃, such as... Figure 5 As shown, this increases the trap density of composite defect VOH, thereby preventing device damage over a wide temperature range regardless of the Si wafer material, and expanding the safe operating temperature range.

[0098] Figure 9 It means Figure 2The reverse recovery charge Q of the diode in fast mode shown RR (×10 -6 C / cm 2 A graph showing the relationship between temperature (°C) and operating temperature (°C). Figure 9 In the diagram, the vertical axis represents the power supply voltage V. CC 1000V, forward current density J F 33.7 A / cm 2 (×0.1J A ), dj / dt is 1200A / cm 2 μs, dV / dt is 13000V / μs, stray inductance L S Reverse recovery charge Q at a value of 2.0 μH RR (×10 -6 C / cm 2 The horizontal axis represents the operating temperature (°C). Additionally, the type of Si wafer, whether or not annealing was performed, and... Figure 4 same.

[0099] exist Figure 2 The diode shown has a reverse recovery charge Q in fast mode. RR A pattern of rapid increase leading to breakage. For this breakage pattern, according to... Figure 9 It is evident that without 400℃ annealing, the Si wafer exhibits significant material dependence, resulting in device destruction at operating temperatures ranging from -60℃ to -40℃. However, with 400℃ annealing, although Si wafer material dependence still exists, the… Figure 5 As shown, the increased well density of the recombination defect VOH promotes carrier recombination, resulting in an increase in the reverse recovery charge Q. RR Reducing the temperature can increase the fracture resistance. Thus, by performing annealing at 400°C, the material dependence of the Si wafer disappears, allowing for cutting even at a low operating temperature of -60°C. The mechanism of this increased fracture resistance also explains... Figure 8 The safe operating temperature range shown has been expanded.

[0100] Figure 10 It means Figure 2 The diode shown is capable of cutting off the current density J during recovery operation in high current mode. A A graph showing the relationship between (break) and the dose during electron beam irradiation, i.e., electron beam density. Figure 10 In the diagram, the vertical axis represents the power supply voltage V. CC The voltage is 800V, and the dj / dt is 1200A / cm. 2 μs, stray inductance L S= 200 nH, current density J at operating temperature 175 °C A (A / cm 2 ), and the horizontal axis indicates the normalized electron beam density (arb. unit). Further, the type of Si wafer, and the implementation of annealing or not were the same as in Figure 4 .

[0101] As is clear from Figure 10 , in the case where the annealing at 400 °C was not implemented, the current density J A (break) at which the diode was able to be turned off was affected by the electron beam density, but by implementing the annealing at 400 °C, as shown in Figure 5 , the trap density of the recombination defects VOH increased, the increased traps promoted the recombination of carriers, as a result, the reverse recovery charge Q RR decreased, and the safe operating area (SOA) at the time of recovery operation was enlarged, regardless of the electron beam density.

[0102] As explained above using Figure 8-10 , in the diode of the present embodiment 1 in which the annealing at 400 °C was implemented to increase the trap density of the recombination defects VOH, the off ability at the time of cutoff operation was improved, and the improvement of the dynamic withstand voltage and the enlargement of the safe operating temperature range were able to be achieved.

[0103] Figure 11 is a graph showing the reliability evaluation results of the diodes shown in Figure 2 and Figure 3 . In Figure 11 , the evaluation results of the reliability obtained by performing the HTRB (High Temperature Reverse Bias) test, the CBS (Cold Bias Stability) test, and the energization test on four samples obtained by the combination of the type of Si wafer and the implementation of annealing or not are shown. Further, the conditions in the case where the annealing was implemented were 120 minutes at 400 °C in a nitrogen (N2) environment.

[0104] In the HTRB test, the reverse bias voltage V R was set to 1020 V, and the operating temperature was set to 150 °C. In the CBS test, the reverse bias voltage V R was set to 1020 V, and the operating temperature was set to 25 °C. In the energization test, the current density J A was set to 337 A / cm 2 , and the operating temperature was set to 150 °C by air cooling.

[0105] In the HTRB test and the CBS test, in any of the samples, the peak repetitive reverse current IRRM and the on voltage V F did not change from the initial value, and in the two samples in which the annealing at 400°C was not performed, although the peak repetitive reverse current I RRM did not change from the initial value, but the on voltage V F changed by 5% from the initial value, and a tendency toward saturation was found after 250 hours. In addition, in the two samples in which the annealing at 400°C was performed, although the peak repetitive reverse current I RRM did not change from the initial value, but the on voltage V F changed by 5% from the initial value, and a tendency toward saturation was found after 500 hours.

[0106] As described above, it was found that in the diode of Embodiment 1 shown in Figs. 1 and 2, even if the annealing at 400°C was performed to increase the trap density of the recombination defect VOH, the reliability was substantially the same as that in the case where the annealing at 400°C was not performed, and thus the reliability was obtained in terms of thermal stability and long-term operation. Figure 2 Figure 3 As described above, it was found that in the diode of Embodiment 1 shown in Figs. 1 and 2, even if the annealing at 400°C was performed to increase the trap density of the recombination defect VOH, the reliability was substantially the same as that in the case where the annealing at 400°C was not performed, and thus the reliability was obtained in terms of thermal stability and long-term operation.

[0107] <Manufacturing Method>

[0108] Next, a manufacturing method of the semiconductor device having the diode of Embodiment 1 shown in Figs. 1 and 2 will be described with reference to a flowchart shown in Fig. 10. Figure 12-20 Figure 2 Figure 3 Next, a manufacturing method of the semiconductor device having the diode of Embodiment 1 shown in Figs. 1 and 2 will be described with reference to a flowchart shown in Fig. 10.

[0109] In Fig. 9, the active cell region R1, the intermediate region R2, and the edge termination region R3 are shown. First, a semiconductor substrate having only an N - drift layer 14 is prepared. Then, an insulating film 25 of an oxide film is formed on the semiconductor substrate and is patterned, ion implantation is performed using the insulating film 25 as a mask, and then, an annealing process is performed on the semiconductor substrate, whereby the N - drift layer 14 is formed in the surface layer portion of the N Figure 12

[0110] Figure 13 - drift layer 14 of the active cell region R1 is formed by ion implantation, and an annealing process is performed. Further, since the annealing conditions differ when the diffusion layer is formed, the diffusion layer depths of the P anode layer 10, the guard ring 22, and the field limiting ring 23 differ.

[0111] ​​​​​​Next, the insulating film 25 of the edge termination region R3 is selectively removed, and the N at the outer end of the edge termination region R3 is... - Ion implantation is performed on the surface of the drift layer 14 to form a channel cut-off layer 24, which is then annealed.

[0112] Afterwards, an interlayer insulating film 26 of TEOS film is formed on the upper surface of the semiconductor substrate, and then a process is performed to expose the lower surface of the semiconductor substrate.

[0113] Next, as Figure 14 As shown, with N exposed on the lower surface of the semiconductor substrate. - A polysilicon layer 122 doped with impurities is formed by contacting the drift layer 14. At this time, a polysilicon layer 123 is also formed on the upper surface of the semiconductor substrate.

[0114] Next, as Figure 15 As shown, the semiconductor substrate is heated to cause impurities in the polysilicon layer 122 to migrate towards the N-phase. - Diffusion on the lower surface of drift layer 14, in N - The lower surface of the drift layer 14 is formed by a high concentration of N + A getter layer 124 is formed by layer 124a and a high crystal defect density layer 124b. Subsequently, an annealing process is performed to capture N by the getter layer 124. - Metallic impurities, contaminating atoms, and damage in drift layer 14.

[0115] Then, as Figure 16 As shown, a liquid of hydrofluoric acid or a mixed acid (e.g., a mixture of hydrofluoric acid, nitric acid, and acetic acid) is used to selectively remove the polycrystalline silicon layer 123 on the upper surface of the semiconductor substrate.

[0116] Next, as Figure 17 As shown, contact holes are formed on the insulating film 25 and the interlayer insulating film 26 to reach each of the P-anode layer 10, the guard ring 22, the field limiting ring 23, and the channel cutoff layer 24. Then, an aluminum film with approximately 1% to 3% Si is formed on the upper surface of the semiconductor substrate by sputtering to create a pattern, thereby forming the anode electrode 5, the FLR electrode 27, and the channel cutoff electrode 28.

[0117] Next, as Figure 18 As shown, protective films, namely passivation films 29 and 30, are formed on the upper surface of the semiconductor substrate.

[0118] After that, as Figure 19 As shown, the getter layer 124 and polysilicon layer 122 on the lower surface of the semiconductor substrate are removed by grinding or etching. Furthermore, this removal process removes the semiconductor substrate (N... - The thickness of the drift layer 14) is set to correspond to the voltage rating of the semiconductor device.

[0119] Then, as Figure 20 As shown, in N - An N-buffer layer 15 is formed on the lower surface of the drift layer 14. Then, a P-cathode layer 18 is formed on the lower surface of the N-buffer layer 15. Next, an N-buffer layer 18 is formed in a portion of the P-cathode layer 18 within the active cell region R1. + Cathode layer 17. N buffer layer 15, N + The cathode layer 17 and the P-cathode layer 18 are diffusion layers formed by ion implantation and annealing. Finally, a cathode electrode 19 is formed on the lower surface of the semiconductor substrate.

[0120] The substrate concentration (C) of the Si wafer used in the diode of this embodiment 1 n- The voltage rating (C) is determined according to the voltage rating of the semiconductor device to be manufactured. For example, C n- Greater than or equal to 1.0 × 10 12 cm -3 And less than or equal to 5.0 × 10 14 cm -3 Si wafers are fabricated using either the FZ or MCZ process. Then, in... Figure 19 In the wafer fabrication process shown, the thickness of the device is precisely adjusted according to its voltage rating. Figure 20 The vertical structure 35 is constructed in the wafer process shown.

[0121] Next, as described in Japanese Patent Nos. 6065067 and 6558462, in forming N of this embodiment 1 - In the case of drift layer 14, similarly, in a manner that satisfies a carrier lifetime value calculated by the mathematical formula (1) shown below, N is made in the wafer process... - The process of restoring the carrier lifetime of drift layer 14 ( Figure 14 , Figure 15 (The process involves forming a high concentration, for example, a surface concentration greater than or equal to 1.0 × 10⁻⁶, on the back side of the wafer.) 20 cm -3 And less than or equal to 1.0 × 10 22 cm -3 N with a depth greater than or equal to 1.0 μm and less than or equal to 10 μm + The getter layer 124 is composed of layer 124a and high crystal defect density layer 124b. However, in this embodiment 1, when forming N buffer layer 15, N... + Before cathode layer 17, P cathode layer 18, etc., in the grinding process and the subsequent wet etching process ( Figure 19 In the process of removing the getter layer 124, the getter layer 124 is removed.

[0122] τ t=1.5×10 -5 exp(5.4×10 3 t N- (1)

[0123] In mathematical formula (1), t N- For N - The thickness (m) of the drift layer 14 is related to Figure 2 The t shown N- Comparable device parameters. Additionally, τ t N is the N that makes the effect of carrier lifetime on the diode's turn-on voltage disappear. - Carrier lifetime (sec) in drift layer 14.

[0124] Mathematical formula (1) is derived from the following viewpoint: that is, the on-state voltage of FWD is relative to N. - The carrier lifetime of drift layer 14 almost disappears from its dependence on a certain value. If the relationship between turn-on voltage and carrier lifetime can be controlled, the influence of carrier lifetime on switching losses can also be controlled. In addition, switching losses are also affected by carrier lifetime. As long as the carrier lifetime can be set in a way that makes the influence of carrier lifetime on turn-on voltage disappear, it will be effective for reducing switching losses and suppressing thermal runaway.

[0125] To achieve mathematical formula (1), the getter layer 124 used in the manufacturing method of this embodiment 1 is formed through the following process. First, with the aim of exposing the Si surface on the back side of the semiconductor substrate (wafer), the back side of the wafer is selectively etched only. Figure 13 At this time, the etching technique used is a liquid of hydrofluoric acid or mixed acid (e.g., a mixture of hydrofluoric acid / nitric acid / acetic acid).

[0126] Next, as a result of the formation of high concentrations of N + The material sources for layer 124a and high crystal defect density layer 124b are used to form polycrystalline silicon layer 122 via LPCVD (low pressure chemical vapor deposition). Figure 14 The polycrystalline silicon layer 122 is doped to form N. + The atoms of the layer, hereinafter referred to as the "d-polysilicon layer" for this polysilicon layer 122.

[0127] As the formation of N + Atoms in the layer, for example, selected from phosphorus, arsenic, and antimony, can diffuse in Si to form N. + The atoms of the layer. The d-polycrystalline silicon layer 122 is doped with atoms greater than or equal to 1 × 10⁻⁶. 19 cm -3high concentration of impurities and the film thickness is greater than or equal to 500 nm. The reason for requiring the high concentration of impurities is that the high concentration of impurities diffuses to the Si surface of the wafer back surface by subsequent annealing at the time of formation of the N + layer 124a. At this time, the d-poly-Si layer 122 is in direct contact with the Si surface exposed on the wafer back surface.

[0128] After deposition of the d-poly-Si, heat annealing in a nitrogen atmosphere at 900°C to 1000°C is performed, and the temperature is decreased from 900°C to 1000°C to 600°C to 700°C at an arbitrary rate. When annealing is performed at 600°C to 700°C, the heavy metals and contaminant atoms that have entered the wafer during wafer processing diffuse and move in the crystal lattice toward the gettering sites.

[0129] By the effect of the present technology, the N - carrier lifetime of the drift layer is recovered, and thus the N - carrier lifetime of the drift layer is recovered, and thus the N - carrier lifetime of the drift layer is recovered, and thus the N

[0130] In addition to the method using the d-poly-Si layer 122, the same effect is obtained by a method of forming the high crystal defect density layer 124b on the wafer back surface by using a laser annealing technique, such as a rapid heating / cooling and local annealing technique using a laser having a wavelength of 500 nm to 1000 nm. In this case, by setting the power density of the laser annealing to be greater than or equal to 4 J / cm 2 , laser annealing and the above-described annealing technique, that is, heat annealing in a nitrogen atmosphere at 900°C to 1000°C and annealing in a nitrogen atmosphere at 500°C to 700°C are used, and thus the high crystal defect density layer 124a is formed. By forming this high crystal defect density layer 124b, the effect of increasing the carrier lifetime is obtained and is stabilized.

[0131] In the diode manufacturing of Embodiment 1, as described using Figure 19 the drawing, it is important to control the trap density of the recombination defects VOH in the N - drift layer 14 after the gettering layer 124 and the poly-Si layer 122 on the lower surface side of the semiconductor substrate are removed. Hereinafter, the drawing is used. Figure 21The flowchart shown explains the procedure.

[0132] Here, when the N buffer layer 15, the N + cathode layer 17 and the P cathode layer 18 are formed, the aluminum wiring and the passivation film are present. As a result, when the N buffer layer 15, the N + cathode layer 17 and the P cathode layer 18 are formed, there is a temperature gradient in the depth direction of the semiconductor substrate so that the surface on which the vertical structure is not formed becomes a temperature lower than the melting point of the metal used for the aluminum wiring, that is, the melting point of aluminum, that is, 660°C. Also, an annealing technique using a laser of a wavelength at which heat is not conducted to the surface on which the vertical structure is not formed (laser annealing) or an annealing technique using an electric furnace at a low temperature of 320°C to 450°C, which is lower than or equal to the melting point of the metal, is used.

[0133] In Figure 19 the procedure shown, when the gettering layer 124 and the polysilicon layer 122 on the lower surface side of the semiconductor substrate are removed by etching or by polishing, the N - drift layer 14 is polished or etched so that the thickness t Figure 2 required for the device shown is obtained with high precision. device , for example, 40 μm to 700 μm. This is Figure 21 the procedure of Step S1 and Step S2 shown.

[0134] After that, a first impurity introduction procedure, that is, an ion implantation procedure for forming the N buffer layer 15 (Step S3) is performed, and a first annealing procedure (Step S4) is performed.

[0135] After that, a second annealing procedure (Step S5) is performed in order to control the trap density of the complex defects VOH in the N - drift layer 14. In this second annealing procedure, the N - drift layer 14 is annealed in a nitrogen (N2) atmosphere at a temperature of 450°C to 650°C for 120 minutes.

[0136] Figure 22 is a graph showing the relationship between the lifetime (Lifetime) in the N - drift layer 14 and the annealing temperature in the second annealing procedure in Figure 21 . Here, the second annealing procedure is performed in a nitrogen (N2) atmosphere, and the annealing time is 120 minutes. In Figure 22 , the vertical axis represents the lifetime (sec), and the horizontal axis represents the annealing temperature (°C).

[0137] The N -The lifetime in the drift layer 14 was measured by a microwave photo conductivity decay (μ-PCD) method. The μ-PCD method is an analysis method of irradiating a laser to an evaluation sample, detecting a change in the carrier over time caused by generation and recombination of the carrier based on reflectivity of the microwave, and evaluating the lifetime of the carrier. The N - The thickness t of the drift layer 14 N- That is, 350 μm, as required for the diode of Embodiment 1 calculated by mathematical expression (1) - The lifetime value of the drift layer 14 is greater than or equal to 1 x 10 -6 sec. Therefore, the lifetime of the evaluation sample was set to be greater than or equal to 1 x 10 -6 According to Figure 22 It was found that, in order to secure the lifetime greater than or equal to 1 x 10 -6 sec without affecting the lifetime, it was necessary to set the annealing temperature of the second annealing process to 370°C to 425°C. The second annealing process accurately controls the temperature by annealing using an electric furnace.

[0138] After the second annealing process, an ion implantation process (step S6) for forming the N + cathode layer 17 and the P cathode layer 18, that is, the second impurity introduction process was performed. Thereafter, a third annealing process (step S7) was performed. Here, the second annealing process (step S5) can be performed not after the first annealing process (step S4) but after the third annealing process (step S7) to obtain the same effect of controlling the N - The trap density of the recombination defect VOH in the drift layer 14 was controlled.

[0139] After the diffusion layer was formed, the performance control and the N - The trap generation process of the recombination defect VOH in the drift layer 14 was performed by irradiating a charged particle, here, an electron beam (step S8), and performing a room temperature (25°C) standing (step S9) and a fourth annealing process (step S10). The electron beam irradiation was performed from the front side of the semiconductor substrate in the state of the diffusion layer. Figure 20 In addition, as the charged particle, not limited to the electron, a proton or helium can be used. The room temperature standing time is a process which does not need to be limited in time.

[0140] The fourth annealing process suppresses the influence of the lifetime in the drift layer 14 and the impurity defect, that is, the recombination defect C - in the drift layer 14 caused by the charged particle. i OS (G-centre), C i O i Controlling the C-centre is a crucial factor. In particular, by controlling impurity defects (recombination defects) caused by charged particles within the region where the C-centre is dominant, it is possible to improve the performance controllability of power semiconductor devices, reduce fluctuations, enhance stabilization, and ensure thermal stability.

[0141] Figure 23 This indicates that N is produced by photoluminescence (PL) method. - The graph shows the relationship between the PL intensity during analysis of the G-centre and C-centre in drift layer 14 and the annealing temperature in the fourth annealing process. Here, the fourth annealing process is carried out in a nitrogen (N2) environment for 30 minutes. The PL method is an analytical method that observes the light emitted when electron-hole pairs recombine via defect energy levels by irradiating a semiconductor. Figure 23 In the figure, the vertical axis represents the normalized PL intensity, which is determined by the edge strength, in arbitrary units (arb.unit), and the horizontal axis represents the annealing temperature.

[0142] Figure 23 The laser intensity was 4.5 mW when irradiated onto the sample surface using a He-Ne laser with a wavelength of 633 nm at a sample temperature of 30 K. The laser diameter was 1.3 μm, and the laser intensity on the sample surface was 0.339 MW / cm². 2 The measurement results were obtained by the PL method. Figure 24 It represents N - A graph showing the relationship between the PL strength of the G-centre and C-centre in drift layer 14 and the annealing time in the fourth annealing process. Here, the fourth annealing process is carried out in a nitrogen (N2) environment at an annealing temperature of 350°C.

[0143] according to Figure 23 and Figure 24 It can be seen that by introducing charged particles into N - The impurity defects (composite defects) in drift layer 14 are dominated by annealing temperatures and annealing times greater than or equal to 300°C and greater than or equal to 6 minutes, respectively. However, if the annealing temperature is not less than or equal to the maximum annealing temperature of the second annealing process, then for N... - The lifespan of the drift layer 14 is affected, so the maximum temperature is set to 425°C. Therefore, the fourth annealing process is carried out at 300°C to 425°C for more than or equal to 6 minutes.

[0144] Further, the annealing process of forming the second buffer layer 15-2 which makes the crystal defect donor of the embodiment 6 described later to improve the device performance is the second annealing process. That is, the fourth annealing process is not for the purpose of donorization, but is an annealing for recovering the crystal defects (lattice defects) caused by the injection of charged particles, and thus is set to a temperature lower than that of the second annealing process.

[0145] Here, returning to the explanation of the flowchart of Figure 21 , after the fourth annealing process, as shown in Figure 21 , the lower surface of the semiconductor substrate is micro-etched to remove the N - The natural oxide film on the surface of the drift layer 14 is removed (step Sll), and then a metal layer for forming the cathode electrode 19 is formed by a sputtering method or an evaporation method (step S12). Here, in order to form an alloy of the Si layer and the metal layer, heat treatment can be performed, but from the viewpoint of suppressing the influence on the well in the drift layer 14, low-temperature heat treatment is performed within the allowable annealing temperature range of the fourth annealing process. - The natural oxide film on the surface of the drift layer 14 is removed (step Sll), and then a metal layer for forming the cathode electrode 19 is formed by a sputtering method or an evaporation method (step S12). Here, in order to form an alloy of the Si layer and the metal layer, heat treatment can be performed, but from the viewpoint of suppressing the influence on the well in the drift layer 14, low-temperature heat treatment is performed within the allowable annealing temperature range of the fourth annealing process.

[0146] The manufacturing method of the semiconductor device of the embodiment 1 described above controls the thickness of the longitudinal structure required for the voltage resistance level at the final stage in the wafer process while effectively utilizing the FZ wafer and the MCZ wafer. Therefore, in a manner capable of processing various wafer thicknesses which are problematic as wafer processes accompanying the large-diametering of Si wafers, for example, 40 μm to 700 μm thick wafers, the process equipment of the wafer process process is modified as much as possible to the minimum, and wafer processes compatible with Si wafers of a large diameter of 200 mm or more are realized.

[0147] Further, Figure 2 , and Figure 3 the N - The drift layer 14 is formed by annealing at 400°C for 120 minutes in the second annealing process and annealing at 350°C for 30 minutes in the fourth annealing process.

[0148] <Embodiment 2>

[0149] Figure 25 is a cross-sectional view of a semiconductor element constituting a semiconductor device, i.e., a PiN diode, to which the embodiment 2 is directed, and corresponds to a cross section along the A1-A2 line of Figure 1 . In addition, Figure 26 is a cross-sectional view showing an example of the configuration of the outer periphery of a semiconductor device having the PiN diode to which the embodiment 2 is directed, Figure 26 and corresponds to a cross section along the A3-A4 line of Figure 1 .Figure 25 and Figure 26 The structure is as shown in Embodiment 1. Figure 2 and Figure 3 The structure removes the P-cathode layer 18, leaving only the N-cathode layer. + The structure of cathode layer 17.

[0150] like Figure 26 As shown, there exists a region spanning the active cell region R1, the intermediate region R2, and the edge termination region R3 that will divide N - Drift layer 14, N buffer layer 15 and N + The cathode layer 17 is stacked to form a structure that is the vertical structure 35 of a PiN diode.

[0151] In the PiN diode according to Embodiment 2, the parameters of each diffusion layer are set as follows. - Drift layer 14 is composed of impurity concentration (C) n- ) greater than or equal to 1.0 × 10 12 cm -3 And less than or equal to 5.0 × 10 15 cm -3 The Si wafer (FZ wafer) is formed using the FZ process. The final device thickness (t) device The surface impurity concentration of the P anode layer 10 is set to be greater than or equal to 40 μm and less than or equal to 700 μm. 16 cm -3 The peak impurity concentration is greater than or equal to 2.0 × 10⁻⁶. 16 cm -3 And less than or equal to 1.0 × 10 18 cm -3 The depth is greater than or equal to 2.0 μm and less than or equal to 10.0 μm. The N buffer layer 15 is set to have a peak impurity concentration greater than or equal to 1.0 × 10⁻⁶. 16 cm -3 And less than or equal to 5.0 × 10 16 cm -3 The depth is greater than or equal to 1.2 μm and less than or equal to 5.0 μm. N + The cathode layer 17 is configured with a surface impurity concentration greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 And less than or equal to 1.0 × 10 21 cm -3 The depth is greater than or equal to 0.3 μm and less than or equal to 0.8 μm.

[0152] Furthermore, the manufacturing method and use of the PiN diode involved in Embodiment 2 Figure 12-20The manufacturing method of the semiconductor device of Embodiment 1 is the same, and the same effects as the semiconductor device of Embodiment 1 can be achieved.

[0153] <Embodiment 3>

[0154] Figure 27 is a cross-sectional view of a semiconductor element constituting a semiconductor device, namely, a trench gate type IGBT, which Embodiment 3 is directed to, and corresponds to a cross section along the A1-A2 line of Figure 1 . In addition, Figure 28 is a cross-sectional view showing an example of the configuration of the outer peripheral portion of a semiconductor device having the IGBT which Embodiment 3 is directed to, Figure 28 and corresponds to a cross section along the A3-A4 line of Figure 1 .

[0155] First, with reference to Figure 27 , the configuration of the IGBT formed in the active cell region R1 will be described. In the semiconductor substrate constituting the IGBT, an N - drift layer 14 of an N type (first conductive type) is formed. Below the N - drift layer 14 of the semiconductor substrate, an N buffer layer 15 of an N type having a higher peak impurity concentration than the N - drift layer 14 is formed.

[0156] Below the N buffer layer 15 of the semiconductor substrate, a P collector layer 16 (third impurity diffusion layer) of a P type (second conductive type) is formed. The P collector layer 16 is formed in a surface layer portion of the back surface side (second main surface side) of the semiconductor substrate, and a collector electrode 20 is formed on the back surface of the semiconductor device in a manner to contact the P collector layer 16.

[0157] Above the N - drift layer 14 of the semiconductor substrate, an N layer 11 (second impurity diffusion layer) having a higher peak impurity concentration than the N - drift layer 14 is formed, and above the N layer 11, a P base layer 9 (first impurity diffusion layer) of a P type is formed. The P base layer 9 is formed in a surface layer portion of the upper surface side (first main surface side) of the semiconductor substrate. In the surface layer portion of the P base layer 9, an N + emitter layer 7 (impurity diffusion region) of an N type, and a P + layer 8 (fourth impurity diffusion layer) of a P type having a higher peak impurity concentration than the P base layer 9 are selectively formed. In the IGBT, the junction of the P base layer 9 and the N layer 11 is a main junction.

[0158] On the upper surface of the semiconductor substrate, an N -The trench of the drift layer 14. The gate insulating film 12 is formed on the inner wall of the trench, and the gate electrode 13 is formed on the gate insulating film 12 in a manner to fill the trench. The gate electrode 13 is insulated from the N - The drift layer 14, the N layer 11, the P base layer 9, and the N + The emitter layer 7 is opposed to. The gate electrode 13, the N + The emitter layer 7, the P base layer 9, and the N layer 11 constitute a transistor structure (MOS transistor structure) of the insulated gate type in the IGBT.

[0159] The interlayer insulating film 6 is formed on the upper surface of the semiconductor substrate in a manner to cover the gate electrode 13, and the emitter electrode 4 is formed on the interlayer insulating film 6. The emitter electrode 4 is electrically connected to the N + The emitter layer 7 and the P + layer 8 via the contact hole. Further, the gate electrode 13 formed on the outer peripheral portion of the active cell region Rl, the N Figure 27 The right side of the two gate electrodes 13 shown at the active cell region Rl in FIG. 1 does not function as the original gate electrode, but is set as a dummy electrode of the same potential as the emitter electrode 4. The purpose and effect of the dummy electrode are described in Japanese Patent No. 4205128, Japanese Patent No. 4785334, and Japanese Patent No. 5634318, and are the suppression of the saturation current density of the IGBT, the suppression of the oscillation in the no-load short-circuit state caused by the control of the capacitance characteristics, the improvement of the short-circuit resistance due thereto, the low on-voltage due to the improvement of the carrier concentration on the emitter side, and the like.

[0160] Next, the configuration of the IGBT will be described with reference to Figure 28 to the active cell region Rl, the intermediate region R2, and the edge termination region R3. The active cell region Rl is a region where the IGBT is actually used, and the edge termination region R3 is a region where the edge termination is performed.

[0161] The N - The drift layer 14 is formed across the active cell region Rl, the intermediate region R2, and the edge termination region R3. The N - A P-type guard ring 22 is formed in the surface layer portion of the drift layer 14 deeper than the P base layer 9. The guard ring 22 extends to the active cell region Rl side and is connected to the P base layer 9, and encloses the dummy electrode, i.e., the gate electrode 13 inside, i.e., the guard ring 22 is formed deeper than the dummy electrode, i.e., the gate electrode 13. Further, the N - A P-type field limiting ring 23 is selectively formed in the surface layer portion of the drift layer 14.

[0162] Furthermore, the field limiting ring 23 at the edge termination region R3 has a structure identical to that of the active cell region R1, consisting of an N layer 11, a gate insulating film 12, and a gate electrode 13. N-type ... + The trench cut-off layer 24 is of the type. The trench cut-off layer 24 is designed to allow the protection ring 22 and the field limiting ring 23 to connect with the N-type. - The extension of the depletion layer extending from the junction of drift layer 14 is set up for the purpose of stopping the extension of the depletion layer.

[0163] An insulating film 25 is formed on the upper surface of the semiconductor substrate in the intermediate region R2 and the edge termination region R3. A surface gate electrode 13a connected to the gate electrode 13 is formed on the insulating film 25 in the intermediate region R2, and an interlayer insulating film 6 is formed on the insulating film 25 and the surface gate electrode 13a.

[0164] An FLR electrode 27, which passes through a contact hole and is connected to the field limiting ring 23, a channel cutoff electrode 28, which passes through a contact hole and is connected to the channel cutoff layer 24, and a surface gate electrode 31, which passes through a contact hole and is connected to the surface gate electrode 13a, are formed on the interlayer insulating film 6. Furthermore, the FLR electrode 27, the channel cutoff electrode 28, and the surface gate electrode 31 can be formed simultaneously with the emitter electrode 4 of the active cell region R1.

[0165] In addition, a protective film, namely a passivation film 29, is formed across the middle region R2 and the edge termination region R3, covering the FLR electrode 27, the channel cutoff electrode 28 and the surface gate electrode 31, and a passivation film 30 is formed on the passivation film 29.

[0166] like Figure 28 As shown, there exists a region spanning the active cell region R1, the intermediate region R2, and the edge termination region R3 that will divide N - The structure is formed by stacking a drift layer 14, an N-buffer layer 15, and a P-collector layer 16, which is the vertical structure 35 of the IGBT.

[0167] In addition, Figure 28 The diagram shows a structure in which a P-collector layer 16 is also formed in the intermediate region R2 and the edge termination region R3, but as... Figure 29 As shown, the P-collector layer 16 may not be formed in the intermediate region R2 and the edge termination region R3. That is, the longitudinal structure 35 of the intermediate region R2 and the edge termination region R3 may only be N. - Drift layer 14 and N buffer layer 15. Figure 29 IGBT and Figure 28 Compared to conventional IGBTs, this technology can suppress the effects of on-state voltage, on-state losses, and SOA under short-circuit conditions, and can significantly improve SOA during off-state operation. Details of this technology are described in Japanese Patent No. 6165271.

[0168] In the IGBT according to Embodiment 3, the parameters of each diffusion layer and trench are set as follows. N - Drift layer 14 is composed of impurity concentration (C) n- ) greater than or equal to 1.0 × 10 12 cm -3 And less than or equal to 5.0 × 10 14 cm -3 The Si wafer (FZ wafer) is formed using the FZ and MCZ methods. The final device thickness (t) device ) Greater than or equal to 40 μm and less than or equal to 700 μm.

[0169] The P-base layer 9 is set to have a peak impurity concentration greater than or equal to 1.0 × 10⁻⁶. 16 cm -3 Up to 1.0×10 18 cm -3 Depth than N + Emitter layer 7 is deeper than N layer 11. N layer 11 is set to have a peak impurity concentration greater than or equal to 1.0 × 10⁻⁶. 15 cm -3 And less than or equal to 1.0 × 10 17 cm -3 The depth is 0.5 μm to 1.0 μm deeper than the P-based electrode layer 9. N + Emitter layer 7 was set to have a peak impurity concentration greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 And less than or equal to 1.0 × 10 21 cm -3 The depth is greater than or equal to 0.2 μm and less than or equal to 1.0 μm. P + Layer 8 is set to have a surface impurity concentration greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 And less than or equal to 1.0 × 10 21 cm -3 Depth and N + The emitter layer 7 is the same as or deeper than it. The N buffer layer 15 is set to have a peak impurity concentration greater than or equal to 1.0 × 10⁻⁶. 16 cm -3 And less than or equal to 5.0 × 10 16 cm -3 The depth is greater than or equal to 1.2 μm and less than or equal to 5.0 μm. The P-collector layer 16 is set to have a surface impurity concentration greater than or equal to 1.0 × 10⁻⁶. 16 cm -3 And less than or equal to 1.0 × 10 20 cm -3The depth of the trench into which the gate electrode 13 is buried is greater than or equal to 0.3 μm and less than or equal to 0.8 μm. trench The depth is set to be greater than or equal to 2.0 μm and to at least N layers 11.

[0170] Furthermore, in the trench gate IGBT according to Embodiment 3, by applying... Figure 21 The flowchart illustrates the N - The process of controlling the well density of recombination defects VOH in the drift layer 14 can achieve the same effect as the semiconductor device of Embodiment 1.

[0171] <Implementation Method 4>

[0172] Figure 30 This is a cross-sectional view of the semiconductor element constituting the semiconductor device according to Embodiment 4, namely the trench gate RC (Reverse Conductivity)-IGBT, and along... Figure 1 The cross-sections of lines A1-A2 are equivalent. For example... Figure 30 As shown, RC-IGBT and Figure 27 The trench-gate IGBT shown similarly has: an IGBT region (transistor region), which consists of a P-collector layer 16, an N-buffer layer 15, and an N-buffer layer 16. - Drift layer 14, N layer 11, P base layer 9 and N + The emitter layer 7, gate electrode 13, and dumb electrode 131 constitute the diode region, which is composed of N... + Cathode layer 17, N buffer layer 15, N - Drift layer 14, N layer 11, P base layer 9, P + Layer 8 and dummy electrode 132 are used. Furthermore, in the active unit region R1 ( Figure 1 The IGBT region and the diode region are set alternately.

[0173] The dumb electrode 131 in the IGBT region and the dumb electrode 132 in the diode region are formed in the same manner as the gate electrode 13 by filling a trench. Similar to the dumb electrodes in the IGBT of Embodiment 3, they are surrounded by a gate insulating film. This trench extends vertically through the P-base layer 9 and the N-layer 11 to reach the underlying N-layer. - It is formed by means of drift layer 14. In addition, the upper part of the dumb electrode 131 in the IGBT region is covered by interlayer insulating film 6, but the upper part of the dumb electrode 132 in the diode region is not covered by interlayer insulating film 6.

[0174] In the IGBT region, an interlayer insulating film 6 is formed to cover the gate electrode 13 and the dumb electrode 131, and an emitter electrode 4 is formed on the interlayer insulating film 6. The emitter electrode 4 is connected to the N-type ... +Emitter layer 7 is electrically connected. Furthermore, in the diode region, emitter electrode 4 is connected to P... + Layer 8 is electrically connected, but in the diode region, the emitter electrode 4 functions as the anode electrode 5. P + Layer 8 acts as a contact layer, reducing the contact resistance with the emitter electrode 4.

[0175] Additionally, on the back side of the semiconductor device, the collector electrode 20 is connected to the P collector layer 16 and the N collector layer. + The cathode layer 17 is formed in a contact manner. As for the collector electrode 20, in the diode region, the collector electrode 20 functions as the cathode electrode 19.

[0176] In the RC-IGBT according to Embodiment 4, the parameters of each diffusion layer and trench are set as follows. - Drift layer 14 is composed of impurity concentration (C) n- ) greater than or equal to 1.0 × 10 12 cm -3 And less than or equal to 5.0 × 10 14 cm -3 The Si wafer (FZ wafer) is formed using the FZ and MCZ methods. The final device thickness (t) device ) Greater than or equal to 40 μm and less than or equal to 700 μm.

[0177] The P-base layer 9 is set to have a peak impurity concentration greater than or equal to 1.0 × 10⁻⁶. 16 cm -3 Up to 1.0×10 18 cm -3 Depth than N + Emitter layer 7 is deeper than N layer 11. N layer 11 is set to have a peak impurity concentration greater than or equal to 1.0 × 10⁻⁶. 15 cm -3 And less than or equal to 1.0 × 10 17 cm -3 The depth is 0.5 μm to 1.0 μm deeper than the P-based electrode layer 9. N + Emitter layer 7 was set to have a peak impurity concentration greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 And less than or equal to 1.0 × 10 21 cm -3 The depth is greater than or equal to 0.2 μm and less than or equal to 1.0 μm. P + Layer 8 is set to have a surface impurity concentration greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 And less than or equal to 1.0 × 10 21 cm -3 Depth and N+ The emitter layer 7 is the same as or deeper than it. The N buffer layer 15 is set to have a peak impurity concentration greater than or equal to 1.0 × 10⁻⁶. 16 cm -3 And less than or equal to 5.0 × 10 16 cm -3 The depth is greater than or equal to 1.2 μm and less than or equal to 5.0 μm. The P-collector layer 16 is set to have a surface impurity concentration greater than or equal to 1.0 × 10⁻⁶. 16 cm -3 And less than or equal to 1.0 × 10 20 cm -3 The depth of the trench into which the gate electrode 13 is buried is greater than or equal to 0.3 μm and less than or equal to 0.8 μm. trench The depth is set to be greater than or equal to 2.0 μm and to at least N layers. + The cathode layer 17 is configured with a surface impurity concentration greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 And less than or equal to 1.0 × 10 21 cm -3 The depth is greater than or equal to 0.3 μm and less than or equal to 0.8 μm.

[0178] Furthermore, in the trench gate type RC-IGBT according to Embodiment 4, by applying... Figure 21 The flowchart illustrates the N - The process of controlling the well density of recombination defects VOH in the drift layer 14 can achieve the same effect as the semiconductor device of Embodiment 1.

[0179] In addition, Figure 30 The diode region is designated as a PiN diode, but it can also be designated as... Figure 2 The RFC diode shown. Additionally, in Figure 30 In this embodiment, a structure is provided in the IGBT region where a dumb electrode 131 is provided in addition to the gate electrode 13, but it can also be provided in a structure where only the gate electrode 13 is provided. Regardless of the structure used, the same effect as the semiconductor device of Embodiment 1 can be achieved.

[0180] <Implementation Method 5>

[0181] Figure 31 This is a cross-sectional view of the semiconductor element constituting the semiconductor device, namely the trench gate RC-IGBT, according to Embodiment 5, and along... Figure 1 The cross-sections of lines A1-A2 are quite similar. Figure 31 The RC-IGBT shown is relative to Figure 30 The RC-IGBT shown has its P region of the diode removed.+ The structure is layer 8. In addition, regarding... Figure 30 The RC-IGBTs shown are labeled with the same reference numerals, and repeated descriptions of parameters for each diffusion layer and trench are omitted. By not setting P... + Layer 8 simplifies the manufacturing process.

[0182] Furthermore, in the trench gate type RC-IGBT according to Embodiment 5, by applying... Figure 21 The flowchart illustrates the N - The process of controlling the well density of the composite defect VOH in the drift layer 14 can achieve the same effect as the semiconductor device of Embodiment 1.

[0183] In addition, Figure 31 The diode region is designated as a PiN diode, but it can also be designated as... Figure 2 The RFC diode shown can achieve the same effect as the semiconductor device in Embodiment 1 in this case.

[0184] <Implementation Method 6>

[0185] Figure 32 This is a cross-sectional view of the semiconductor element constituting the semiconductor device, namely the RFC diode, according to Embodiment 6, and along... Figure 1 The cross-sections of lines A1-A2 are quite similar. Furthermore, regarding... Figure 32 Regarding the RFC diode shown, relative to Figure 2 The RFC diode shown has an N-buffer layer 15 with a two-layer structure consisting of a lower first buffer layer 15-1 and an upper second buffer layer 15-2. That is, the second buffer layer 15-2 is disposed between the first buffer layer 15-1 and the N-buffer layer 15-2. - Between drift layers 14. In addition, regarding... Figure 2 The RFC diodes shown have the same structure and are labeled with the same reference numerals. Repeated descriptions of the parameters of each diffusion layer and trench are omitted.

[0186] Figure 33 It is a substitute Figure 32 A cross-sectional view of a case where a PiN diode is used instead of an RFC diode. Figure 33 In terms of structure, compared to implementation method 2 Figure 25 The PiN diode shown has an N-buffer layer 15 with a two-layer structure consisting of a lower first buffer layer 15-1 and an upper second buffer layer 15-2.

[0187] Figure 34 It is a substitute Figure 32 A cross-sectional view of a case where a trench-gate IGBT is used instead of an RFC diode. Figure 34 In terms of structure, compared to implementation method 3Figure 27 The trench gate type IGBT shown has an N buffer layer 15 with a two-layer structure consisting of a lower first buffer layer 15-1 and an upper second buffer layer 15-2.

[0188] exist Figure 32-34 In the power semiconductors shown, such as FWD and IGBT, the following can be achieved:

[0189] (a) Reduce the leakage current when reverse bias is applied to the main junction to achieve a longitudinal structure with low disconnection loss and high temperature operation.

[0190] (b) A longitudinal structure that slows the extension of the depletion layer to the back side when a reverse bias is applied to the main junction through the second buffer layer 15-2, thereby suppressing the step phenomenon during cutoff operation and the oscillation phenomenon caused by the step phenomenon; and

[0191] (c) The two wells in the second buffer layer 15-2 control the carrier injection efficiency on the back side of the IGBT through carrier recombination, control the carrier injection efficiency in the RFC diode, and help suppress the operation of the built-in PNP transistor, thus improving the vertical structure of dynamic damage resistance.

[0192] Next, use Figure 32 Details of the N-buffer layer 15 of the semiconductor device according to Embodiment 6 will be described. As described above, the N-buffer layer 15 of the semiconductor device according to Embodiment 6 is composed of a lower first buffer layer 15-1 and an upper second buffer layer 15-2.

[0193] The first buffer layer 15-1 contains N-type impurities such as phosphorus and arsenic, with a peak impurity concentration (C). nb1，p ) greater than or equal to 1.0 × 10 16 cm -3 And less than or equal to 5.0 × 10 16 cm -3 Depth (X) from the back side of the semiconductor substrate j，nb1 The region that is greater than or equal to 1.2 μm and less than or equal to 5.0 μm.

[0194] The second buffer layer 15-2 contains selenium, sulfur, phosphorus, and protons (H). + And N-type impurities such as helium, with the maximum peak impurity concentration ((C) nb2，p ) max ) compared to the impurity concentration (C) of the semiconductor substrate n- : Greater than or equal to 1.0 × 10 12 cm -3 And less than or equal to 5.0 × 10 14 cm -3 (High, and less than or equal to 1.0 × 10)15 cm -3 , the depth (X j，nb2 ) from the back surface of the semiconductor substrate is greater than or equal to 4.0 and less than or equal to 50 μm.

[0195] According to the above relationship, the respective roles of the first buffer layer 15-1 and the second buffer layer 15-2 constituting the N buffer layer 15 are as described below.

[0196] The first buffer layer 15-1 assumes a role of stopping the depletion layer extending from the main junction in the static state, and exhibits a stable withstand voltage characteristic, and an effect of low switching loss due to low leakage current at the time of switching off.

[0197] As for the second buffer layer 15-2, in the on state, i.e., in a state in which a rated main current is flowing, the impurity concentration is increased by a carrier plasma layer generated by the carrier modulation phenomenon, as compared with the doping distribution at the time of forming the second buffer layer 15-2 in the wafer process. Therefore, the second buffer layer 15-2 has a role of widening the base width of the PNP transistor, and exhibits a reduced current amplification rate (α pnp ), and an effect of low switching loss due to low leakage current at the time of switching off. This carrier plasma layer functions as a residual carrier plasma layer in the dynamic state. In addition, the second buffer layer 15-2 makes the extension speed of the depletion layer extending from the main junction in the static and dynamic states slower than the N - drift layer 14, and, due to the presence of the residual carrier plasma layer from the on state, assumes a role of controlling the electric field intensity distribution, and exhibits an effect of suppressing the step phenomenon at the end of the cutoff operation and the oscillation phenomenon caused by the step phenomenon, and an improvement in controllability with respect to the on-off operation and an improvement in the breakdown tolerance in the dynamic state.

[0198] In the RFC diode according to Embodiment 6, the parameters of the diffusion layer other than the N buffer layer 15 are the same as those of the RFC diode according to Embodiment 1.

[0199] Figure 35 is a result of spectral analysis by the PL method for the first buffer layer 15-1 and the second buffer layer 15-2 constituting the two-layer-structured N buffer layer 15 according to Embodiment 6.

[0200] Figure 35 is a measurement result obtained by the PL method using a He-Ne laser having a wavelength of 633 nm, with a laser intensity of 4.5 mW and a laser diameter of 1.3 μm being irradiated to the sample surface at a sample temperature of 30 K, and the laser intensity on the sample surface being 0.339 MW / cm 2 .

[0201] In Figure 35In the diagram, the vertical axis represents the normalized PL intensity, which is determined by the intensity of the banded area, in arbitrary units (arb.unit), while the horizontal axis represents the photon energy.

[0202] The vertical axis represents the PL intensity, indicating the defect density. A stronger PL intensity indicates a higher density of defects that are the source of that intensity. According to... Figure 35 Nothing was detected in the first buffer layer 15-1, while a PL spectrum with two characteristic peaks originating from lattice defects was obtained in the second buffer layer 15-2. These two characteristic peaks are energy levels determined by the W-centre (photon energy: 1.0182 eV) and X-centre (photon energy: 1.0398 eV) present in the second buffer layer 15-2.

[0203] Thus, the N-buffer layer 15 is composed of a first buffer layer 15-1 without lattice defects and a second buffer layer 15-2 with lattice defects. That is, the N-buffer layer 15 is composed of multiple N-layers with different carrier lifetimes, and the carrier lifetime of the first buffer layer 15-1 is longer than that of the second buffer layer 15-2.

[0204] Figure 32 The manufacturing method and use of the RFC diode involved in Embodiment 6 shown Figure 12-20 The manufacturing method of the RFC diode described in Embodiment 1 is basically the same, but the manufacturing process of the two-layer N-buffer layer 15 is different from that of the single-layer N-buffer layer 15. Therefore, the following describes the process. Figure 36 The flowchart shown illustrates this process.

[0205] exist Figure 19 In the process shown, when the getter layer 124 and polysilicon layer 122 on the lower surface of the semiconductor substrate are removed by etching or by polishing, the N... - The drift layer 14 is ground and etched to achieve high precision. Figure 32 The required thickness t of the device shown device .This is Figure 36 The steps S21 and S22 shown are the procedures.

[0206] After that, a first impurity introduction process, i.e., an ion implantation process for forming the first buffer layer 15-1 is performed (step S23), and a first annealing process is performed (step S24). In the first annealing process, laser annealing is used, and for a second annealing process for forming the second buffer layer 15-2, high-temperature annealing at a higher temperature is performed. In addition, in order to avoid affecting the distribution of the activated impurities in the second buffer layer 15-2 and the types of lattice defects introduced into the second buffer layer 15-2, and in order to avoid affecting the carriers, i.e., electrons or holes, in the on state of the device, the formation of the second buffer layer 15-2 is performed after the first annealing process of the first buffer layer 15-1.

[0207] Next, a second impurity introduction process, i.e., an ion implantation process for forming the second buffer layer 15-2 is performed (step S25), and a second annealing process is performed (step S26).

[0208] Here, the first buffer layer 15-1 and the second buffer layer 15-2 are formed in a manner satisfying the following relationship. The peak position of the second buffer layer 15-2 is set to be located on the upper side (the junction X j，nb1 side) of the junction (X j，nb2 ) of the first buffer layer 15-1 and the second buffer layer 15-2. Thus, the first buffer layer 15-1 does not interfere with the second buffer layer 15-2, and the second buffer layer 15-2 can be formed with high accuracy.

[0209] As the ion species for forming the first buffer layer 15-1 and the second buffer layer 15-2, phosphorus and arsenic are used for the first buffer layer 15-1, and for the second buffer layer 15-2, selenium, sulfur, phosphorus, protons (H + ), and helium are introduced into Si at a high acceleration energy. In the case of using protons (H + ) and helium, a diffusion layer formation process technology for forming an N layer by a donorization phenomenon achieved by the annealing conditions described later is used. In addition to ion implantation, protons (H + ) and helium can also be introduced into Si by irradiation technology using a cyclotron. If protons (H + ) are introduced into Si, the following are formed:

[0210] (a) a complex defect formed by diffusion of the vacancies (V) generated after the introduction, and a reaction with impurities (hydrogen atoms (H), oxygen atoms (O), and carbon atoms (C)), and a replacement reaction of carbon atoms with lattice defects;

[0211] (b) diffusion and self-aggregation of the lattice defects generated at the time of introduction, and a complex defect formed by a reaction with oxygen atoms by annealing;

[0212] (c) The aggregates of the lattice defects (W-centre) generated at the time of the implantation are diffused by annealing, and the lattice defects formed by re-aggregation of the diffused W-centre are the X-centre.

[0213] In the present application, since the complex defects formed by the reaction of the holes and the impurities contain hydrogen, they become electron donors (donors), and the donor concentration increases due to the increase in the density of the complex defects caused by the annealing, and the mechanism of the increase in the donor concentration due to the thermal donor phenomenon caused by the ion implantation. As a result, the N - The layer after the donorization of the high impurity concentration drift layer 14, as the second buffer layer 15-2, contributes to the operation of the device. The present technology effectively utilizes the complex defects formed in the second buffer layer 15-2, and realizes the improvement in the device performance.

[0214] On the other hand, since there are also defects that become a lifetime suppressing factor that reduces the lifetime of the carriers in the complex defects formed in the second buffer layer 15-2, the impurity dose at the time of the formation of the second buffer layer 15-2, and the process flow at the time of the formation of the second buffer layer 15-2, that is, as described above, the formation of the second buffer layer 15-2 in the ion implantation process and the second annealing process after the formation of the first buffer layer 15-1, and the annealing conditions for the donorization of the second buffer layer 15-2 (the second annealing process) are important.

[0215] In the case of the second annealing process, from the viewpoint of the balance control of the lattice defects W-centre and X-centre in the second buffer layer 15-2 and the influence on the lifetime of the drift layer 14, the annealing temperature, time, and the like are important conditions. - From the viewpoint of the influence on the lifetime of the drift layer 14, the annealing temperature, time, and the like are important conditions. Figure 22 As a result shown in FIG. 6, the temperature is accurately controlled by the annealing using the electric furnace.

[0216] Figure 37 is a graph showing the relationship between the PL intensity at the time of the analysis of the lattice defects W-centre and X-centre in the second buffer layer 15-2 by the PL method and the annealing time. Here, the second annealing process is performed in a nitrogen (N2) environment, and the annealing temperature is 400°C. In the graph, the vertical axis shows the PL intensity normalized by the intensity of the band edge (Normalized PL Intensity) in arbitrary units (arb. unit), and the horizontal axis shows the annealing time (Aneealing Time). Figure 37 In the graph, the vertical axis shows the PL intensity normalized by the intensity of the band edge (Normalized PL Intensity) in arbitrary units (arb. unit), and the horizontal axis shows the annealing time (Aneealing Time).

[0217] From the viewpoint of the device performance of the power semiconductor, it is preferable to set the defect density of the lattice defects W-centre and X-centre to be low. According to the results shown in FIG. 6, the defect density of the lattice defects W-centre and X-centre is low when the annealing time is 10 minutes or more. Figure 37It is understood that the reason for the decrease in the annealing time dependence of the PL intensity indicating the defect density of the lattice defects W-centre and X-centre is the annealing of greater than or equal to 90 minutes. According to the results of Figure 22 and Figure 37 , in the second annealing step of Embodiment 6, the annealing temperature is preferably 370°C to 425°C and the annealing time is greater than or equal to 90 minutes in consideration of the influence on the lifetime of the N - drift layer 14, the balance control of the lattice defects W-centre and X-centre in the second buffer layer 15-2. Here, even if the second annealing step (step S26) is not performed after the ion implantation step (step S25) for forming the second buffer layer 15-2, but is performed after the third annealing step (step S23), the effect on the lifetime of the N - drift layer 14, the balance control of the lattice defects W-centre and X-centre in the second buffer layer 15-2 can be obtained.

[0218] Here, returning to the explanation of the flowchart of Figure 36 , after the second annealing step, the ion implantation step (step S27) for forming the N + cathode layer 17 and the P cathode layer 18, that is, the third impurity introduction step is performed. Thereafter, the third annealing step (step S28) is performed.

[0219] After the formation of the above-described diffusion layer, as the performance control of the diode of Embodiment 6 and the well generation step of the recombination defects VOH in the N - drift layer 14, a charged particle, here, an electron beam, is irradiated (step S29), and standing at room temperature (25°C) (step S30) and the fourth annealing step (step S31) are performed. The electron beam irradiation is performed from the front side of the semiconductor substrate in the state of Figure 20 . Further, as the charged particle, it is not limited to an electron, and a proton or helium can be used. The standing time at room temperature is a step in which the time is not limited. The effect obtained by irradiating the diode with a charged particle such as an electron beam is the same as that of Embodiment 1.

[0220] After the fourth annealing step, as shown in Figure 36 , the natural oxide film on the surface of the N - drift layer 14 is removed by micro-etching the lower surface of the semiconductor substrate (step S32), and thereafter, a metal layer for forming the cathode electrode 19 is formed by a sputtering method or an evaporation method (step S33).

[0221] <Embodiment 7>

[0222] Figure 38is a sectional view of a trench gate type RC-IGBT, which is a semiconductor element constituting a semiconductor device according to Embodiment 7, and corresponds to a cross section along the A1-A2 line of Figure 1 . As shown in Figure 38 , the RC-IGBT differs from the trench gate type RC-IGBT according to Embodiment 4 shown in Figure 30 in that the N buffer layer 15 has a two-layer structure of a first buffer layer 15-1 on the lower side and a second buffer layer 15-2 on the upper side. Except for this, the same components as those of the trench gate type RC-IGBT according to Embodiment 4 shown in Figure 30 are designated by the same reference numerals, and repeated description is omitted.

[0223] Further, in the trench gate type RC-IGBT according to Embodiment 7, the same effects as those of the semiconductor device according to Embodiment 6 can be achieved by the buffer layer having the two-layer structure of the first buffer layer 15-1 and the second buffer layer 15-2.

[0224] Further, in Figure 38 , the diode region is provided as a PiN diode, but can be provided as an RFC diode shown in Figure 2 . In this case, the same effects as those of the semiconductor device according to Embodiment 6 can be achieved.

[0225] <Embodiment 8>

[0226] Figure 39 is a sectional view of a trench gate type RC-IGBT, which is a semiconductor element constituting a semiconductor device according to Embodiment 8, and corresponds to a cross section along the A1-A2 line of Figure 1 . The RC-IGBT shown in Figure 39 is a structure in which the P Figure 38 layer 8 of the diode region is deleted from the RC-IGBT shown in + . Except for this, the same components as those of the RC-IGBT shown in Figure 38 are designated by the same reference numerals, and repeated description is omitted.

[0227] Further, in the trench gate type RC-IGBT according to Embodiment 8, the same effects as those of the semiconductor device according to Embodiment 6 can be achieved by the buffer layer having the two-layer structure of the first buffer layer 15-1 and the second buffer layer 15-2.

[0228] Further, in Figure 39 , the diode region is provided as a PiN diode, but can be provided as an RFC diode shown in Figure 2 . In this case, the same effects as those of the semiconductor device according to Embodiment 6 can be achieved.

[0229] The following can be achieved in the semiconductor element of Embodiments 6 to 8 described above:

[0230] (a) a vertical structure that reduces the leakage current when a reverse bias is applied to the main junction, achieves low off-loss, and operates at high temperature;

[0231] (b) a vertical structure that slows down the extension of the depletion layer toward the back side when a reverse bias is applied to the main junction by the second buffer layer 15-2, suppresses the step phenomenon at the time of the off operation of the IGBT, PIN diode, RFC diode, and RC-IGBT, and the oscillation phenomenon caused by the step phenomenon; and

[0232] (c) a vertical structure that controls the carrier injection efficiency toward the back side in the IGBT region of the IGBT and RC-IGBT by the recombination of carriers in the two wells of the second buffer layer 15-2, controls the carrier injection efficiency in the diode region of the diode and RC-IGBT, and helps to suppress the operation of the built-in PNP transistor, and improves the dynamic breakdown resistance.

[0233] Furthermore, the present application can freely combine each embodiment within the scope of the application, and appropriately modify, omit each embodiment.

[0234] Explanation of Reference Signs

[0235] 6 interlayer insulating film, 7 N + emitter layer, 8 P + layer, 9 P base layer, 10 P anode layer, 11 N layer, 14 N - drift layer, 15 N buffer layer, 15-1 first buffer layer, 15-2 second buffer layer, 16 P collector layer, 17 N + cathode layer, 18 P cathode layer.

Claims

1. A semiconductor device comprising: A semiconductor substrate having a first main surface and a second main surface; A drift layer of the first conductivity type is formed on the semiconductor substrate; A first impurity diffusion layer of the second conductivity type is formed on the first main surface side of the drift layer; as well as A buffer layer of the first conductivity type, formed on the second main surface side of the drift layer, has a higher peak impurity concentration compared to the drift layer. The drift layer has: The first well has an energy level that is 0.234 eV lower than the energy at the bottom of the conduction band; The second well has an energy level that is 0.349 eV lower than the energy at the bottom of the conduction band; as well as The third well has an energy level 0.470 eV lower than the bottom of the conduction band. The well density of the second well is greater than or equal to 2.0 × 10⁻⁶. 11 cm -3 .

2. The semiconductor device according to claim 1, wherein, The buffer layer includes: A second buffer layer, which contacts the drift layer; and The first buffer layer, compared to the second buffer layer, is formed on the second main surface side. The first buffer layer has impurities of the first conductivity type. The second buffer layer contains selenium, sulfur, phosphorus, protons and helium as impurities.

3. The semiconductor device according to claim 1 or 2, wherein, The drift layer comprises: Concentration less than or equal to 3.0 × 10 15 cm -3 Or the concentration is less than or equal to 7.0 × 10⁻⁶. 17 cm -3 oxygen; and Concentration greater than or equal to 1.0 × 10 14 cm -3 And less than or equal to 5.0 × 10 15 cm -3 Carbon.

4. The semiconductor device according to claim 1 or 2, wherein, Regarding the drift layer, the C-centre density in the composite defects caused by charged particles, as detected by photoluminescence, is higher than that of the G-centre.

5. The semiconductor device according to claim 1 or 2, wherein, The first impurity diffusion layer functions as the anode of the diode. On the second main surface side of the buffer layer, a cathode layer of the first conductivity type is formed, which functions as the cathode of the diode.

6. The semiconductor device according to claim 1 or 2, wherein, The first impurity diffusion layer functions as the anode of the diode. On the second main surface side of the buffer layer, a first cathode layer of a first conductivity type and a second cathode layer of a second conductivity type are formed, which function as the cathode of the diode.

7. The semiconductor device according to claim 1 or 2, wherein, The first impurity diffusion layer functions as the base layer of the transistor. The semiconductor device also features: A second impurity diffusion layer of the first conductivity type is formed between the first impurity diffusion layer and the drift layer; A third impurity diffusion layer of the second conductivity type is formed on the second main surface side of the buffer layer; The impurity diffusion region of the first conductivity type is selectively formed on the surface portion of the first impurity diffusion layer; and A trench gate that penetrates the impurity diffusion region, the first impurity diffusion layer, and the second impurity diffusion layer to reach the drift layer.

8. The semiconductor device according to claim 1 or 2, wherein, The semiconductor substrate has diode regions and transistor regions. In the diode region, The first impurity diffusion layer functions as the anode of the diode. On the second main surface side of the buffer layer, a cathode layer of a first conductivity type is formed, which functions as the cathode of the diode. In the transistor region The first impurity diffusion layer functions as the base layer of the transistor. The semiconductor device also features: A second impurity diffusion layer of the first conductivity type is formed between the first impurity diffusion layer and the drift layer; A third impurity diffusion layer of the second conductivity type is formed on the second main surface side of the buffer layer; The impurity diffusion region of the first conductivity type is selectively formed on the surface portion of the first impurity diffusion layer; and A trench gate that penetrates the impurity diffusion region, the first impurity diffusion layer, and the second impurity diffusion layer to reach the drift layer.

9. The semiconductor device according to claim 1 or 2, wherein, The semiconductor substrate has diode regions and transistor regions. In the diode region, The first impurity diffusion layer functions as the anode of the diode. On the second main surface side of the buffer layer, a first cathode layer of a first conductivity type and a second cathode layer of a second conductivity type are formed, which function as the cathode of the diode. In the transistor region The first impurity diffusion layer functions as the base layer of the transistor. The semiconductor device also features: A second impurity diffusion layer of the first conductivity type is formed between the first impurity diffusion layer and the drift layer; A third impurity diffusion layer of the second conductivity type is formed on the second main surface side of the buffer layer; The impurity diffusion region of the first conductivity type is selectively formed on the surface portion of the first impurity diffusion layer; and A trench gate that penetrates the impurity diffusion region, the first impurity diffusion layer, and the second impurity diffusion layer to reach the drift layer.

10. The semiconductor device according to claim 8, wherein, In the diode region, The surface portion of the first impurity diffusion layer also has a fourth impurity diffusion layer of the second conductivity type, which has a higher impurity concentration than the first impurity diffusion layer.

11. The semiconductor device according to claim 9, wherein, In the diode region, The surface portion of the first impurity diffusion layer also has a fourth impurity diffusion layer of the second conductivity type, which has a higher impurity concentration than the first impurity diffusion layer.

12. The semiconductor device according to claim 8, wherein, In the diode region, The surface portion of the first impurity diffusion layer becomes the first main surface of the semiconductor substrate.

13. The semiconductor device according to claim 9, wherein, In the diode region, The surface portion of the first impurity diffusion layer becomes the first main surface of the semiconductor substrate.

14. A method for manufacturing a semiconductor device, comprising: Step (a) involves forming a predetermined device structure on a semiconductor substrate having a first main surface and a second main surface and having a drift layer formed thereon; Step (b) involves grinding or etching the second main surface of the semiconductor substrate to a predetermined thickness; (c) First impurity introduction process, in which impurities are introduced from the second main surface into the semiconductor substrate; (d) The first annealing process involves forming a buffer layer by laser annealing the semiconductor substrate; (e) Second annealing process, in which the semiconductor substrate is annealed in an electric furnace to control the trap density of composite defects; (f) Second impurity introduction process, in which impurities are introduced from the second main surface into the semiconductor substrate; as well as (g) The third annealing process involves forming at least one impurity diffusion layer by laser annealing the semiconductor substrate.

15. The method of manufacturing a semiconductor device according to claim 14, wherein, After step (g), the following steps are performed sequentially: Step (h) involves introducing charged particles from the first main surface into the drift layer; Step (i): The semiconductor substrate is placed at room temperature; as well as (j) The fourth annealing process involves annealing the semiconductor substrate in an electric furnace at a temperature lower than that of the second annealing process.

16. The method of manufacturing a semiconductor device according to claim 15, wherein, The step (h) includes the process of introducing any one of electrons, protons, and helium as the charged particles.

17. The method of manufacturing a semiconductor device according to claim 14, wherein, In step (e), the annealing temperature of the second annealing step is set to be greater than or equal to 370°C and less than or equal to 425°C.

18. The method of manufacturing a semiconductor device according to claim 15, wherein, In step (j), the annealing temperature of the fourth annealing step is set to be greater than or equal to 300°C and less than or equal to 425°C.

19. The method of manufacturing a semiconductor device according to claim 14, wherein, The process (e) is performed after the process (g).

20. A method for manufacturing a semiconductor device, comprising: Step (a) involves forming a predetermined device structure on a semiconductor substrate having a first main surface and a second main surface and having a drift layer formed thereon; Step (b) involves grinding or etching the second main surface of the semiconductor substrate to a predetermined thickness; Step (c) forms a buffer layer comprising a first buffer layer and a second buffer layer, wherein the first buffer layer is disposed on the second main surface side of the drift layer and the second buffer layer is disposed between the first buffer layer and the drift layer; (d) The third impurity introduction process, wherein impurities are introduced from the second main surface into the semiconductor substrate; and (e) The third annealing process involves forming at least one impurity diffusion layer by laser annealing the semiconductor substrate. The process (c) includes: (c-1) First impurity introduction process: After step (b), impurities for the first buffer layer are introduced into the semiconductor substrate from the second main surface; (c-2) First annealing process: After the process (c-1), the first buffer layer is formed by laser annealing the semiconductor substrate; (c-3) Second impurity introduction process: After step (c-2), impurities for the second buffer layer are introduced into the semiconductor substrate from the second main surface; and (c-4) The second annealing process involves annealing the semiconductor substrate in an electric furnace to control the trap density of composite defects and form the second buffer layer.

21. The method of manufacturing a semiconductor device according to claim 20, wherein, After step (e), the following steps are performed sequentially: Step (f) involves introducing charged particles from the first main surface into the drift layer; Step (g): Placing the semiconductor substrate at room temperature; and (h) Fourth annealing process, in which the semiconductor substrate is annealed in an electric furnace at a temperature lower than that of the second annealing process.

22. The method of manufacturing a semiconductor device according to claim 21, wherein, The step (f) includes the step of introducing any one of electrons, protons and helium as the charged particles.

23. The method of manufacturing a semiconductor device according to claim 20, wherein, In step (c-4), the annealing temperature of the second annealing step is set to be greater than or equal to 370°C and less than or equal to 425°C.

24. The method of manufacturing a semiconductor device according to claim 21, wherein, In step (h), the annealing temperature of the fourth annealing step is set to be greater than or equal to 300°C and less than or equal to 425°C.

25. The method of manufacturing a semiconductor device according to claim 20, wherein, The process (c-4) is performed after the process (e).

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