Stacked amplifier, radio frequency transceiver circuit, device and switching control method

Abstract

A stacked amplifier, radio frequency transceiver circuit, device and switching control method, the stacked amplifier comprising a first transistor (41), a second transistor (42) and a bias circuit (43); the bias end of the first transistor (41) is connected to ground, and the output end is connected to the input end of the second transistor (42); the bias end of the second transistor (42) receives a bias voltage through the bias circuit (43), and the bias circuit (43) comprises a bias resistor and a variable impedance device. High impedance in the off state can be achieved, and the bidirectional loss of the circuit is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the electronic technology field, and in particular to a stacked amplifier, a radio frequency transceiver circuit, a device and a switching control method. BACKGROUND

[0002] In electronic control applications, in order to facilitate subsequent signal transmission or processing, an amplifier is usually required to be set to amplify the signal.

[0003] In order to ensure the signal amplification effect, a stacked amplifier with multiple amplifiers can be used to amplify the signal. The transistors in the current stacked amplifier are usually fixed impedance, so that the OFF impedance cannot meet the requirements, which makes the circuit where the stacked amplifier is located need to be additionally configured with a switching device to switch the state.

[0004] However, setting an additional switching device to switch the state will make the circuit loss larger, and also greatly reduce the performance of the circuit for high frequency signals. SUMMARY

[0005] Embodiments of the present application provide a stacked amplifier, a radio frequency transceiver circuit, a device and a switching control method to reduce the loss of the circuit and improve the performance of the circuit for high frequency signals.

[0006] In a first aspect, embodiments of the present application provide a stacked amplifier, comprising: a first transistor, a second transistor and a bias circuit.

[0007] The bias end of the first transistor is connected to ground, the input end of the first transistor is used to receive an input signal, and the output end of the first transistor is connected to the input end of the second transistor.

[0008] The bias end of the second transistor is connected to the control output end of an external circuit through the bias circuit to receive a bias voltage output by the external circuit through the control output end, the output end of the second transistor is used to output an amplified signal, and the bias circuit is used to make the second transistor have different impedances under the action of different bias voltages, and the OFF impedance of the second transistor is greater than a preset impedance, wherein the OFF impedance is the impedance of the second transistor under the action of an OFF bias voltage.

[0009] In a possible implementation, the bias circuit comprises: a bias resistor and a variable impedance device; the bias resistor and the variable impedance device are connected in series between the control output end and the ground, and the bias end of the second transistor is connected between the bias resistor and the variable impedance device.

[0010] In a second aspect, the embodiments of the present application further provide a stacked amplifier, comprising: a first transistor, a second transistor, and a bias circuit.

[0011] The bias end of the first transistor is grounded, the input end of the first transistor is configured to receive an input signal, and the output end of the first transistor is connected to the input end of the second transistor.

[0012] The bias end of the second transistor is connected to a control output end of an external circuit through the bias circuit, so as to receive a bias voltage output by the external circuit through the control output end, and the output end of the second transistor is configured to output an amplified signal; wherein the bias circuit comprises: a bias resistor and a variable impedance device, the bias resistor and the variable impedance device are connected in series between the control output end and the ground, and the bias end of the second transistor is connected between the bias resistor and the variable impedance device.

[0013] In a possible implementation of the first aspect or the second aspect, the variable impedance device is a variable capacitive device.

[0014] The stacked amplifier provided by the scheme can make the off-state impedance of the second transistor greater than a preset impedance through the variable capacitive device in the bias circuit, so as to improve the impedance of the second transistor in the off state, realize high impedance of the second transistor in the off state, and thus realize high impedance of the stacked amplifier in the off state. Through the variable capacitive device, the impedance of the second transistor in the off state is improved, the structure of the circuit is simpler, the loss cost of the circuit is smaller, and the circuit is easier to realize.

[0015] In another possible implementation, the variable impedance device can also be a variable inductive device.

[0016] In yet another possible implementation, the variable capacitive device is a metal oxide semiconductor (MOS) capacitor.

[0017] In still another possible implementation, the MOS capacitor can be an N-type MOS capacitor.

[0018] In still another possible implementation, the gate of the N-type MOS capacitor is connected to the bias resistor, and the source, the drain, and the substrate of the N-type MOS capacitor are all grounded.

[0019] In still another possible implementation, the gate of the N-type MOS capacitor is connected to the bias resistor, the source and the drain of the N-type MOS capacitor are both grounded, and the substrate of the N-type MOS capacitor is grounded through a preset resistor.

[0020] In still another possible implementation, the gate of the N-type MOS capacitor is connected to the bias resistor, the drain and the substrate of the N-type MOS capacitor are grounded, and the source of the N-type MOS capacitor is grounded through a preset resistor.

[0021] In still another possible implementation, the variable capacitance device shown above can also be a varactor or a switched capacitor.

[0022] In still another possible implementation, the stacked amplifier is a differential amplifier, and the differential amplifier includes two single-ended amplifiers, each of which includes the first transistor, the second transistor, and the bias circuit.

[0023] The differential input of the differential amplifier is the input of the first transistor in the two single-ended amplifiers, and the differential output of the differential amplifier is the output of the second transistor in the two single-ended amplifiers.

[0024] The stacked amplifier can be applied in a differential structure, which can be a differential amplifier. On the basis of realizing differential amplification, high impedance of each stacked amplifier in an off state is realized, thus, without involving additional switching switches, switching between on and off is realized, circuit loss is reduced, and thus, performance advantages of the circuit for high-frequency signals are ensured.

[0025] In still another possible implementation, the stacked amplifier includes multiple stages of the second transistor and multiple bias circuits. In the multiple stages of the second transistor, the input of the first stage of the second transistor is connected to the output of the first transistor, and the input of the later stage of the second transistor is connected to the output of the former stage of the second transistor.

[0026] The bias end of each stage of the second transistor is connected to the control output through one bias circuit.

[0027] In the multiple stages of stacked amplifiers, multiple amplifications are performed through the multiple stages of the second transistor, and thus, the amplification gain of the signal is ensured. In this embodiment, the stacked amplifier is applied in multiple stages of stacking, and in the case of realizing multiple amplifications through multiple stages of stacking, high impedance in an off state is realized, without involving additional switching switches, switching between on and off is realized, circuit loss is reduced, and thus, performance advantages of the circuit for high-frequency signals are ensured.

[0028] In still another possible implementation, the stacked amplifier is a common-source common-gate amplifier, the first transistor is a common-source transistor, the input of the first transistor is the gate of the common-source transistor, the output of the first transistor is the drain of the common-source transistor, and the bias end of the first transistor is the source of the common-source transistor.

[0029] The second transistor is a common-gate transistor, an input terminal of the second transistor is a source of the common-gate transistor, an output terminal of the second transistor is a drain of the common-gate transistor, and a bias terminal of the second transistor is a gate of the common-gate transistor.

[0030] In another possible implementation, an input terminal of the first transistor is a base of a common-shoot transistor, an output terminal of the first transistor is a collector of the common-shoot transistor, and a bias terminal of the first transistor is an emitter of the common-shoot transistor.

[0031] An input terminal of the second transistor is an emitter of a common-base transistor, an output terminal of the second transistor is a collector of the common-base transistor, and a bias terminal of the second transistor is a base of the common-base transistor.

[0032] In another possible implementation, the stacked amplifier further includes a transformer, a primary coil of the transformer is connected to the output terminal of the second transistor, and the transformer is configured to perform transformation processing on the amplified signal and output the signal through a secondary coil.

[0033] In a third aspect, an embodiment of the present application can also provide a radio frequency transceiver circuit, including an antenna, a radio frequency circuit, and the stacked amplifier of any one of the first aspect or the second aspect, the stacked amplifier being connected between the antenna and the radio frequency circuit.

[0034] In a possible implementation, the stacked amplifier includes a first stacked amplifier, an input terminal of a first transistor in the first stacked amplifier being connected to the radio frequency circuit, and an output terminal of a second transistor in the first stacked amplifier being connected to the antenna.

[0035] In another possible implementation, the stacked amplifier further includes a second stacked amplifier, an input terminal of a first transistor in the second stacked amplifier being connected to the antenna, and an output terminal of a second transistor in the second stacked amplifier being connected to the radio frequency circuit.

[0036] In a fourth aspect, an embodiment of the present application can also provide a communication device, including a baseband circuit and the radio frequency transceiver circuit of any one of the third aspect, the baseband circuit being connected to the radio frequency circuit in the radio frequency transceiver circuit.

[0037] In a fifth aspect, an embodiment of the present application can also provide a switching control method, including:

[0038] generating a bias voltage;

[0039] The bias end of the second transistor in the stacked amplifier of any one of the first aspect or the second aspect outputs a bias voltage, so that the second transistor has different impedances under the action of different bias voltages, and the off-state impedance of the second transistor is greater than a preset impedance.

[0040] The stacked amplifier, the radio frequency transceiver circuit, the device, and the switching control method provided by the embodiments of the present application, wherein the stacked amplifier can include: a first transistor, a second transistor, and a bias circuit; the bias end of the first transistor is grounded, the input end of the first transistor is used to receive an input signal, the output end of the first transistor is connected to the input end of the second transistor, the bias end of the second transistor is connected to the control output end of an external circuit through the bias circuit to receive a bias voltage output by the external circuit through the control output end, and the output end of the second transistor is used to output an amplified signal, wherein the bias circuit includes a bias resistor and a variable impedance device, the bias resistor and the variable impedance device are connected in series between the control output end and the ground, and the bias end of the second transistor is connected between the bias resistor and the variable impedance device. In the present application, the bias circuit connected to the bias end of the second transistor in the stacked amplifier is improved, the variable impedance device is included in the bias circuit of the second transistor, the second transistor has different impedances under the action of different bias voltages through the bias circuit including the variable impedance device, the impedance in the off state is greater than a preset impedance, the high impedance in the off state of the second transistor is realized, and the high impedance in the off state of the stacked amplifier is realized, so that the switching between the on state and the off state of the stacked amplifier can be realized without additional switching switches, the bidirectional loss of the circuit is reduced, and the bidirectional performance of the circuit is improved. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1A A schematic diagram of an application example one of the stacked amplifier provided by the embodiments of the present application;

[0042] Figure 1B A schematic diagram of an application example two of the stacked amplifier provided by the embodiments of the present application;

[0043] Figure 1C A schematic diagram of an application example three of the stacked amplifier provided by the embodiments of the present application;

[0044] Figure 1D A signal flow and a state diagram of a high impedance state of the stacked amplifier provided by the embodiments of the present application in the application example three;

[0045] Figure 1E Another state diagram of a signal flow and a high impedance state of the stacked amplifier provided by the embodiments of the present application in the application example three;

[0046] Figure 1F An application diagram of a stacked amplifier in a radio frequency field is provided for an embodiment of the present application;

[0047] Figure 2 An application diagram of a stacked amplifier in a radio frequency transceiver circuit is provided for an embodiment of the present application;

[0048] Figure 3 A structure diagram of a communication device is provided for an embodiment of the present application;

[0049] Figure 4 A circuit structure diagram of a stacked amplifier is provided for an embodiment of the present application;

[0050] Figure 5 A circuit structure diagram of another stacked amplifier is provided for an embodiment of the present application;

[0051] Figure 5A A diagram of a stacked amplifier with a variable capacitive device of an N-type MOS capacitor is provided for an embodiment of the present application;

[0052] Figure 5B Another diagram of a stacked amplifier with a variable capacitive device of an N-type MOS capacitor is provided for an embodiment of the present application;

[0053] Figure 5C Still another diagram of a stacked amplifier with a variable capacitive device of an N-type MOS capacitor is provided for an embodiment of the present application;

[0054] Figure 6 A diagram of a stacked amplifier of a differential structure is provided for an embodiment of the present application;

[0055] Figure 7 A diagram of a stacked amplifier of a multi-stage is provided for an embodiment of the present application;

[0056] Figure 8 A diagram of a stacked amplifier of an N-type MOS transistor is provided for an embodiment of the present application;

[0057] Figure 9 A diagram of a stacked amplifier of an NPN transistor is provided for an embodiment of the present application;

[0058] Figure 10 Another diagram of a stacked amplifier of a differential structure is provided for an embodiment of the present application;

[0059] Figure 11 An equivalent circuit diagram of another stacked amplifier of a differential structure in an off state is provided for an embodiment of the present application;

[0060] Figure 12A graph showing the variation of AC ground capacitance and bias voltage for another differential stacked amplifier provided in an embodiment of this application;

[0061] Figure 13 A graph showing the change in AC ground capacitance of the second MOS transistor versus signal frequency in another differential stacked amplifier provided in an embodiment of this application;

[0062] Figure 14 A graph showing the impedance versus signal frequency of the second MOS transistor in a stacked amplifier with a different differential structure provided in this application embodiment;

[0063] Figure 15 This is a flowchart illustrating a switching control method provided in an embodiment of this application. Detailed Implementation

[0064] The stacked amplifiers provided in the following embodiments of this application can be applied to any type of signal processing circuit, which can be a standalone processing chip or a circuit module on other chips. These stacked amplifiers can be used to amplify and output input signals.

[0065] This stacked amplifier can be applied to bidirectional transceiver scenarios. The following examples illustrate some implementation methods in bidirectional transceiver scenarios with reference to the attached diagram. Figure 1A This is a schematic diagram illustrating an application example of the stacked amplifier provided in this application embodiment. Figure 1B This is a schematic diagram illustrating a second application example of the stacked amplifier provided in this application. For example... Figure 1A As shown in the example of a bidirectional transceiver link, the first stacked amplifier 1 and the second stacked amplifier 2 each have a bidirectional external interface on one side, which may include an antenna interface, and a unidirectional external interface on the other side. Specifically, the bidirectional external interface connected to the input of the first stacked amplifier 1 can be the antenna interface. The first stacked amplifier 1 connects to an antenna through the antenna interface to receive and amplify the signal received by the antenna. Similarly, the external interface connected to the output of the second stacked amplifier 2 can also be an antenna interface. The second stacked amplifier 2 connects to an antenna through the antenna interface to send the amplified signal to the antenna.

[0066] like Figure 1BAs shown in another application example of the transceiving link in the bidirectional transceiving scenario, the first stacked amplifier 1 and the second stacked amplifier 2 have a side connectable to a bidirectional external interface, which can include: an intermediate frequency interface, and the other side connectable to a unidirectional external interface. The external interface connected to the output side of the first stacked amplifier 1 can be an intermediate frequency interface, and the first stacked amplifier 1 can connect to a radio frequency circuit through the intermediate frequency interface to transmit the amplified signal to the radio frequency circuit. The external interface connected to the input side of the second stacked amplifier 2 can be an intermediate frequency interface, and the second stacked amplifier 2 can connect to the radio frequency circuit through the intermediate frequency interface to receive the intermediate frequency signal from the radio frequency circuit to amplify the intermediate frequency signal.

[0067] Figure 1C A schematic diagram of an application example three of the stacked amplifier provided by the embodiment of the present application is shown in FIG. 6. Figure 1C As shown in another application example of the transceiving link in the bidirectional transceiving scenario, the first stacked amplifier 1 and the second stacked amplifier 2 have a side connectable to a bidirectional external interface, which can include: an intermediate frequency interface, and the other side connectable to a unidirectional external interface. The external interface connected to the output side of the first stacked amplifier 1 can be an intermediate frequency interface, and the first stacked amplifier 1 can connect to a radio frequency circuit through the intermediate frequency interface to transmit the amplified signal to the radio frequency circuit. The external interface connected to the input side of the second stacked amplifier 2 can be an intermediate frequency interface, and the second stacked amplifier 2 can connect to the radio frequency circuit through the intermediate frequency interface to receive the intermediate frequency signal from the radio frequency circuit to amplify the intermediate frequency signal. Figure 1C The first stacked amplifier 1 in FIG. 6 can input the signal from the bidirectional external interface connected to the input side, amplify the signal through the first stacked amplifier 1, and output the signal through the bidirectional external interface connected to the output side. The second stacked amplifier 2 can input the signal from the bidirectional external interface connected to the input side, amplify the signal through the second stacked amplifier 2, and output the signal through the bidirectional external interface connected to the output side.

[0068] The signal flow and the switching between the two states of the high impedance in the application example of the stacked amplifier with the bidirectional external interface connected to both sides are described as follows. Figure 1D A schematic diagram of the signal flow and one state of the high impedance of the stacked amplifier in the application example three provided by the embodiment of the present application is shown in FIG. 7. Figure 1E A schematic diagram of the signal flow and another state of the high impedance of the stacked amplifier in the application example three provided by the embodiment of the present application is shown in FIG. 8. Figure 1D and Figure 1E As shown in the application example of the transceiving link in the bidirectional transceiving scenario, the first stacked amplifier 1 and the second stacked amplifier 2 have a side connectable to a bidirectional external interface, which can include: an intermediate frequency interface, and the other side connectable to a unidirectional external interface. The external interface connected to the output side of the first stacked amplifier 1 can be an intermediate frequency interface, and the first stacked amplifier 1 can connect to a radio frequency circuit through the intermediate frequency interface to transmit the amplified signal to the radio frequency circuit. The external interface connected to the input side of the second stacked amplifier 2 can be an intermediate frequency interface, and the second stacked amplifier 2 can connect to the radio frequency circuit through the intermediate frequency interface to receive the intermediate frequency signal from the radio frequency circuit to amplify the intermediate frequency signal.

[0069] The stack amplifiers provided by the embodiments of the present application can be applied to the above-mentioned application examples, so that when one stack amplifier is in an operating state, the other stack amplifier is in a high-impedance state instead of a low-impedance state, and the signal flow of the stack amplifier in the operating state can be prevented from entering the branch in which the other stack amplifier is located, thereby reducing the loss.

[0070] The stack amplifiers mentioned in the present application can be used in the field of radio frequency to amplify radio frequency signals, that is, the bidirectional transceiving scenario in the above-mentioned application examples can be a radio frequency transceiving scenario in the field of radio frequency. Of course, the stack amplifiers provided by the embodiments of the present application can not only amplify radio frequency signals, but also amplify other signals with a preset frequency, and the embodiments of the present application do not limit this.

[0071] It should be understood that the technical solutions of the present application can be specifically applied to support any one of the following communication systems to amplify radio frequency signals of the corresponding frequency bands in each communication system. The communication system to which the technical solutions of the present application are applied may, for example, be a Global System for Mobile Communications (GSM), a Code Division Multiple Access (CDMA), a Wideband Code Division Multiple Access (WCDMA), a Time Division-Synchronous Code Division Multiple Access (TD-SCDMA), a Time Division Duplexing (TDD) system, a Universal Mobile Telecommunications System (UMTS), a Long Term Evolution (LTE) system, and the like. With the continuous development of communication technology, the technical solutions of the present application can also be used in future networks, such as a Fifth Generation Mobile Communication Technology (5G) system, also known as a New Radio (NR) system, a device to device (D2D) system, a machine to machine (M2M) system, and the like.

[0072] The following describes the application examples of the stack amplifiers in the field of radio frequency. Figure 1F An application schematic diagram of the stack amplifiers in the field of radio frequency provided by the embodiments of the present application is shown in FIG. 1. As shown in FIG. 1, the stack amplifiers in the field of radio frequency provided by the embodiments of the present application can be applied to a radio frequency transceiving system.Figure 1F As shown, the radio frequency transceiver circuit 10 to which the stacked amplifier provided by the embodiments of the present application is applied can include an antenna 11, a stacked amplifier 12 and a radio frequency circuit 13. The stacked amplifier 12 is connected between the antenna 11 and the radio frequency circuit 13, and can be used to amplify the radio frequency signal transmitted between the antenna 11 and the radio frequency circuit 13 and then transmit the radio frequency signal to the opposite end.

[0073] The signal transmission between the antenna 11 and the radio frequency circuit 13 is generally bidirectional, that is, the radio frequency transceiver circuit 10 generally has a transmitting path and a receiving path, and the radio frequency circuit 13 is integrated with a transmitting end and a receiving end. The transmitting path, also referred to as a transmitting path, refers to a transmission path from the transmitting end on the radio frequency circuit 13 to the antenna 11; the receiving path refers to a transmission path from the antenna 11 to the receiving end on the radio frequency circuit 13.

[0074] In the radio frequency transceiver circuit 10 provided by the embodiments, the transmitting path and the receiving path share the same antenna 11, so that when the transmitting path is in a working state, the receiving end of the receiving path is in a high resistance state, and vice versa, when the receiving path is in a working state, the transmitter of the transmitting path is in a high resistance state.

[0075] The present application Figure 1F At least one of the transmitting path and the receiving path of the radio frequency transceiver circuit 10 can be provided with the stacked amplifier provided by the embodiments described below, so that the stacked amplifier has high impedance in the off state by means of different impedances of the stacked amplifier in different states, so as to realize high impedance of the stacked amplifier in the path, so that the antenna is in a working state in another path of the radio frequency transceiver circuit 10. That is, the stacked amplifier 12 can be applied to the transmitting path of the radio frequency transceiver circuit 10, can be applied to the receiving path of the radio frequency transceiver circuit 10, and can also be applied to both the transmitting path and the receiving path of the radio frequency transceiver circuit 10.

[0076] If applied to the transmitting path, the stacked amplifier can also be referred to as a radio frequency amplifier or a radio frequency amplification circuit, or a power amplifier (PA). In this transmitting path, the input end of the stacked amplifier 12 can be connected to the transmitting port of the radio frequency circuit 13, and the output end of the stacked amplifier 12 is connected to the antenna 11.

[0077] If applied to the receiving path, the stacked amplifier can also be referred to as a low noise amplifier (LNA). In this receiving path, the input end of the stacked amplifier 12 can be connected to the antenna 11, and the output end of the stacked amplifier 12 is connected to the receiving port of the radio frequency circuit 13.

[0078] The following describes an example of the application of the stacked amplifier 12 in the transmit path of the RF transceiver circuit 10. In this transmit path, the stacked amplifier amplifies the RF signal generated by the RF circuit. Figure 2 This diagram illustrates an application example of a stacked amplifier in a radio frequency transceiver circuit, as provided in an embodiment of this application. Figure 2 As shown, the RF circuit 13 may have a transmit port TX and a receive port RX. The input of the stacked amplifier 12 can be connected to the transmit port TX of the RF circuit 13 to obtain the RF input generated by the RF circuit 13 from the transmit port TX. in The output of the stacked amplifier 12 can be connected to the antenna 11 to amplify the RF input signal and output the RF signal. out The signal is transmitted through antenna 11.

[0079] In this embodiment, for the transmission path of the radio frequency transceiver circuit 10, different impedances in the ON and OFF states can be achieved through the stacked amplifier 12 used in the following embodiments of this application, so that the impedance of the stacked amplifier 12 in the OFF state is greater than a preset impedance, thereby achieving high impedance in the OFF state. The preset impedance can be greater than or equal to the impedance of the stacked amplifier in the ON state.

[0080] In the receiving path of the RF transceiver circuit 10, the antenna 11 can be connected to the receiving port RX of the RF circuit 13 through the inductor L. The receiving port RX is also connected to a receive switch (SW RX). That is to say, a switch can be used to achieve high impedance in the off state in the receiving path.

[0081] It should be noted that the above Figure 1F or Figure 2 In the radio frequency transceiver circuit 10 shown, other circuit devices may also be connected between the radio frequency circuit 13 and the antenna 11, but this application does not limit this.

[0082] The stacked amplifier and RF transceiver circuit provided in this application can be applied to any communication device with wireless communication function, which can be a wireless network device such as a base station, or a wireless terminal device.

[0083] The wireless terminal device involved in the present application can refer to a device providing voice and / or data connectivity to a user, a handheld device with wireless connection function, or other processing device connected to a wireless modem, which can communicate with one or more core networks through a radio access network (RAN). For example, the wireless terminal device can be a wireless mobile terminal, such as a mobile phone (cellular phone) and a computer with a mobile terminal, and can also be a portable, pocket, handheld, built-in computer or vehicle-mounted wireless mobile device, wireless Internet of Things device, etc., such as a Personal Communication Service (PCS) phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), etc., which exchanges language and / or data with a wireless access network. Alternatively, the terminal can also be referred to as User Equipment (UE), Mobile Station (MS), mobile terminal, Subscriber Unit (SU), Subscriber Station (SS), Mobile Station (MB), Remote Station (RS), Access Point (AP), Remote Terminal (RT), Access Terminal (AT), User Terminal (UT), User Agent (UA), terminal device (UD), or User Equipment (UE), etc., which is not limited in the present application.

[0084] The base station involved in the present application can refer to a device in an access network that communicates with a terminal through one or more sectors over an air interface, which can coordinate the management of properties of the air interface. For example, the wireless access network device can be a base station in GSM or CDMA, such as a base transceiver station (BTS), a base station in WCDMA, such as a NodeB, an evolved base station in LTE, such as an eNB or e-NodeB (evolutional NodeB), a base station in a 5G system, such as a transmission reception point (TRP) or g-NodeB (gNB), or a base station in a future network, etc., which is not limited in the present application. Optionally, the base station can also be a relay device or other network element device with base station functions.

[0085] The communication device provided by the present application is described by an example as follows. Figure 3 A structural schematic diagram of a communication device provided by an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, in the technical solution of the present application, the communication device is based on the radio frequency transceiver circuit 10 shown in FIG. 1. Figure 3 Figure 1F Figure 2 As shown in FIG. 1, the communication device provided by the present application can further include a baseband circuit 20, which can be connected to the radio frequency circuit 13 in the radio frequency transceiver circuit 10. The radio frequency circuit 13 can convert the baseband signal output by the baseband circuit 20 into a radio frequency input signal and output to the stacked amplifier 12, so that the stacked amplifier 12 amplifies and processes to obtain a radio frequency output signal, and transmits the radio frequency output signal through the antenna 11.

[0086] Optionally, the radio frequency circuit 13 can also transmit the generated bias voltage to the stacked amplifier 12, so that the stacked amplifier 12 has different impedances under the action of the bias voltage, so that the impedance of the stacked amplifier 12 in the off state is greater than the preset impedance, thereby realizing the high impedance of the stacked amplifier 12 in the off state, and realizing the switching control of the conduction and the off of the stacked amplifier 12.

[0087] The stacked amplifier, the radio frequency transceiver circuit and the communication device involved in the present application can improve the bias circuit in the stacked amplifier, so that the stacked amplifier has different impedances under the action of different bias voltages under the action of the bias voltage, so that the impedance in the off state is greater than the preset impedance, thereby realizing the high impedance in the off state without the need of switching the switch, reducing the bidirectional loss of the circuit and improving the bidirectional performance of the circuit.

[0088] ​​The stacked amplifier and implementation principles provided by the embodiments of the present application are explained below in combination with multiple examples. The stacked amplifier, also known as a stacked tube amplifier, is formed by stacking multiple transistors, where the stacking of the transistors means that the output end of a previous layer of transistors is connected to the input end of a next layer of transistors, so that the signal amplified by the previous layer of transistors is input to the input end of the next layer of transistors, and the signal is amplified in the next layer of transistors, so that the voltage division of the amplified signal output by the stacked amplifier is on the multiple layers of the amplifier.

[0089] Figure 4 The circuit structure diagram of a stacked amplifier provided by the embodiments of the present application is shown in FIG. 1. As shown in the figure, the stacked amplifier can include a first transistor 41, a second transistor 42, and a bias circuit 43. Figure 4

[0090] The bias end of the first transistor 41 is connected to ground, the input end of the first transistor 41 is used to receive an input signal, and the output end of the first transistor 41 is connected to the input end of the second transistor 42.

[0091] The bias end of the second transistor 42 is connected to the control output end of an external circuit through the bias circuit 43, so as to receive a bias voltage output by the external circuit through the control output end, and the output end of the second transistor 42 is used to output an amplified signal. The bias circuit 43 is used to make the second transistor 42 have different impedances under the action of different bias voltages, and the off-state impedance of the second transistor 42 is greater than a preset impedance, where the off-state impedance is the impedance of the second transistor 42 under the action of an off-state bias voltage. The preset impedance can be greater than or equal to the on-state impedance, which can be the impedance of the second transistor 42 under the action of an on-state bias voltage. The external circuit can be, for example, a radio frequency circuit in the field of radio frequency or other control circuits.

[0092] In a specific implementation, the first transistor 41 can be the first layer of transistors of the stacked amplifier, and the input end of the first transistor 41 is the input end of the stacked amplifier, which can be connected to a first external signal end for receiving an input signal from the first external signal end. The bias end of the first transistor 41 is connected to ground, so that the first transistor 41 amplifies the input signal.

[0093] The input end of the second transistor 42 is connected to the output end of the first transistor 41, so as to obtain the signal amplified by the first transistor 41. The output end of the second transistor 42 is the output end of the stacked amplifier, which can be connected to a second external signal end for outputting the output signal amplified by the second transistor 42 to the second external signal end. The bias end of the second transistor 42 is connected to the bias circuit 43, and the bias circuit 43 can obtain a bias voltage from the control output end of the external circuit. The bias voltage can be an on-state bias voltage (Von), and the off-state bias voltage (Voff) can be 0 V.​ON ), or, the off bias voltage (V OFF ) is obtained. When the bias voltage obtained by the bias circuit 43 is the on bias voltage, the bias circuit 43 can make the second transistor 42 realize the amplification function under the action of the on bias voltage, and the amplified signal of the first transistor 41 is amplified again.

[0094] For the stacked amplifier, the amplified signal voltage can be the sum of the voltage amplified by the first transistor 42 and the voltage amplified by the second transistor 42.

[0095] In a possible application example, if the stacked amplifier is applied to the transmission path of the radio frequency transceiver circuit, the input end of the first transistor 41 can be connected to the radio frequency circuit in the radio frequency transceiver circuit. The radio frequency circuit can have a transmission port and a receiving port. In the implementation manner of the example, the input end of the first transistor 41 can be connected to the transmission port of the radio frequency circuit to obtain the radio frequency input signal generated by the radio frequency circuit, and the output end of the second transistor 41 can be connected to the antenna to output the radio frequency output signal amplified by the second transistor 42 to the second external signal end. That is, in the embodiment, the first external signal end connected to the input end of the first transistor 41 can be the transmission port of the radio frequency circuit, and the second external signal end connected to the output end of the second transistor 42 can be the antenna.

[0096] In another possible application example, if the stacked transistor is applied to the receiving path of the radio frequency transceiver circuit, the input end of the first transistor 41 can be connected to the antenna in the radio frequency transceiver circuit. In the implementation manner of the example, the input end of the first transistor 41 can be connected to the antenna to obtain the radio frequency input signal received by the antenna. That is, in the embodiment, the first external signal end connected to the input end of the first transistor 41 can be the antenna, and the second external signal end connected to the output end of the second transistor 42 can be the receiving port of the radio frequency circuit.

[0097] The stacked transistor provided by the embodiment can improve the bias circuit 43, so that the bias circuit 43 not only makes the second transistor 42 amplify the signal under the action of the on bias voltage, but also adjusts the impedance of the second transistor 42 based on the action of the off bias voltage when the bias voltage is from the on bias voltage to the off bias voltage, so that the second transistor 42 has different impedances in the on state and the off state. Due to the improvement of the bias circuit 43, the off impedance of the second transistor 42 is greater than the preset impedance, that is, the off impedance of the second transistor 42 is increased, and the high impedance of the second transistor 42 in the off state is realized, so that the stacked amplifier has high impedance in the off state. The preset impedance can be greater than the on impedance, and the on impedance can be the impedance of the second transistor 42 under the action of the on bias voltage.

[0098] In a possible implementation example, the biasing circuit 43 can include a biasing resistor and a variable impedance device, the biasing resistor and the variable impedance device can be connected in series between the control output end and the ground, and the biasing end of the second transistor 42 is connected between the biasing resistor and the variable impedance device.

[0099] In the cascode amplifier provided by the embodiments of the present application, each transistor can be a bipolar transistor (BJT) or a field effect transistor (FET). The bipolar transistor can also be referred to as a semiconductor triode or a crystal triode, and can be an NPN triode or a PNP triode. The field effect transistor can also be referred to as a unipolar transistor, and can be a junction field effect transistor (JFET) or a metal-oxide semiconductor field effect transistor (MOS-FET).

[0100] In a possible implementation, if the second transistor 42 is an N-type MOS tube or an NPN triode, the impedance of the variable impedance device is negatively correlated with the bias voltage, and the on bias voltage is greater than the off bias voltage. That is, the impedance of the variable impedance device increases as the bias voltage decreases, that is, the greater the bias voltage, the smaller the impedance of the variable impedance device, and the smaller the bias voltage, the greater the impedance of the variable impedance device.

[0101] In this implementation, the impedance adjustment of the second transistor 42 can be achieved by the variable impedance device in the biasing circuit 43. Since the impedance of the variable impedance device is negatively correlated with the bias voltage, the off impedance of the second transistor 42 under the action of the off bias voltage is greater than the preset impedance when the on bias voltage is greater than the off bias voltage, so that the impedance of the second transistor 42 in the off state is improved.

[0102] In another possible implementation, if the second transistor 42 is a P-type MOS tube or a PNP triode, the impedance of the variable impedance device is positively correlated with the bias voltage, and the on bias voltage is less than the off bias voltage. That is, the impedance of the variable impedance device increases as the bias voltage increases, that is, the greater the bias voltage, the greater the impedance of the variable impedance device, and the smaller the bias voltage, the smaller the impedance of the variable impedance device.

[0103] In the other implementation, the impedance adjustment of the second transistor 42 can also be realized by a variable impedance device in the bias circuit 43, and since the impedance of the variable impedance device is positively correlated with the bias voltage, the on-state bias voltage is less than the off-state bias voltage, so that the off-state impedance of the second transistor 42 under the action of the off-state bias voltage is greater than the preset impedance, and the high impedance of the second transistor 42 in the off state is realized.

[0104] The variable impedance device as shown in any of the above, for example, can be a variable capacitive device, and by adjusting the capacitance of the variable capacitive device, the capacitance of the variable capacitive device under the action of the off-state bias voltage is reduced, and the impedance of the second transistor 42 in the off state is increased.

[0105] The variable impedance device as shown in any of the above, for example, can also be a variable inductive device, and by adjusting the inductance of the variable inductive device, the inductance of the variable inductive device under the action of the off-state bias voltage is increased, and the impedance of the second transistor 42 in the off state is increased.

[0106] The preset impedance as mentioned above, for example, can be a fixed impedance device in the bias circuit 43, and the off-state impedance under the action of the off-state bias voltage is a preset fixed off-state impedance.

[0107] The stacked amplifier provided by the embodiment of the present application can receive an input signal through the input end of the first transistor, connect the output end of the first transistor to the input end of the second transistor, and ground the bias end of the first transistor, so that the first transistor can amplify the input signal. The bias end of the second transistor is connected to the control output end of the external circuit through the bias circuit to receive the bias voltage output by the external circuit through the control output end. Since the bias circuit includes a bias resistor and a variable impedance device, the second transistor can amplify the signal output by the first transistor under the action of the on-state bias voltage, and the impedance of the second transistor in the off state is greater than the preset impedance, and the high impedance of the second transistor in the off state is realized. Since the stacked amplifier can amplify the signal through the first transistor and the second transistor, and the impedance of the second transistor in the off state is greater than the preset impedance by the variable impedance device in the bias circuit of the second transistor, the high impedance of the second transistor in the off state is realized, so that the stacked amplifier can switch between the on and off states without additional switching switches, the circuit loss is reduced, and the bidirectional port performance of the circuit for high-frequency signals is ensured.

[0108] Meanwhile, the variable impedance device in the bias circuit of the second transistor in the stacked amplifier can realize high impedance of the stacked amplifier in the off state of high frequency signals, can avoid leakage current of the path where the stacked amplifier is located in the off state, reduces the loss of the circuit, and ensures the bidirectional port performance of the circuit to high frequency signals.

[0109] The stacked amplifier provided in the present application is explained and described by the following implementation example of improving the off state impedance of the second transistor 42 by using the variable impedance device as a variable capacitive device in the bias circuit 43. Figure 5 Another circuit structure diagram of a stacked amplifier provided in an embodiment of the present application is shown in FIG. 3. Figure 5 As shown in the figure, in the stacked amplifier, the bias circuit 43 can include: a bias resistor R1 and a variable capacitive device C1; the bias resistor R1 and the variable capacitive device C1 are connected in series between the control output end and the ground. The bias end of the second transistor 42 is connected between the bias resistor R1 and the variable capacitive device C1.

[0110] The control output end is the control output end of the external circuit mentioned above, which can be used to output the bias voltage V cas In an example, the variable capacitive device C1 can be realized by an analog method, which can be a varactor or a metal-oxide-semiconductor (MOS) capacitor. The variable capacitive device C1 can also be realized by a digital control method, such as a switched capacitor, i.e., a combination of a switching device and a fixed capacitor.

[0111] The bias voltage V cas can be the on voltage V ON , also known as the on bias voltage, or the off voltage V OFF , also known as the off bias voltage. The bias resistor R1 and the variable capacitive device C1 are connected in series between the control output end and the ground, so that under the action of the on bias voltage, the capacitance value of the variable capacitive device C1 can be the on capacitance C ON , so that the on impedance r ON of the second transistor 42 is in the amplification state to realize signal amplification. Under the action of the off bias voltage, the capacitance value of the variable capacitive device C1 can be the off capacitance C OFF , so that the off impedance r OFF of the second transistor 42 is in the off state.

[0112] If the second transistor 42 is an N-type MOS tube or an NPN-type transistor, the on bias voltage is greater than the off bias voltage, so that the on capacitance C ONgreater than the off capacitance C OFF , so that the on impedance r ON of the second transistor 42 is less than the off impedance r OFF , so that the on impedance of the second transistor 42 is improved.

[0113] In a specific implementation example, the MOS capacitor shown above can be an N-type MOS capacitor or a P-type MOS capacitor. The connection relationship of the variable capacitive device in the stacked amplifier provided by the embodiment of the present application is described below by taking the N-type MOS capacitor as an example. Figure 5A FIG. 1 is a schematic diagram of a stacked amplifier provided by the embodiment of the present application, in which the variable capacitive device is an N-type MOS capacitor. Figure 5A As shown in the figure, in the stacked amplifier provided by the embodiment of the present application, the variable capacitive device C1 can be an N-type MOS capacitor, the gate of the N-type MOS capacitor is connected between the bias resistor R1 and the bias end of the second transistor 42, and the source, the drain and the substrate of the N-type MOS capacitor are all grounded.

[0114] Figure 5B FIG. 2 is another schematic diagram of the stacked amplifier provided by the embodiment of the present application, in which the variable capacitive device is an N-type MOS capacitor. Figure 5B As shown in the figure, in the stacked amplifier provided by the embodiment of the present application, the variable capacitive device C1 can be an N-type MOS capacitor, the gate of the N-type MOS capacitor is connected between the bias resistor R1 and the bias end of the second transistor 42, the source and the drain of the N-type MOS capacitor are both grounded, and the substrate of the N-type MOS capacitor is grounded through a preset resistor.

[0115] Figure 5C FIG. 3 is still another schematic diagram of the stacked amplifier provided by the embodiment of the present application, in which the variable capacitive device is an N-type MOS capacitor. Figure 5C As shown in the figure, in the stacked amplifier provided by the embodiment of the present application, the variable capacitive device C1 can be an N-type MOS capacitor, the gate of the N-type MOS capacitor is connected between the bias resistor R1 and the bias end of the second transistor 42, the drain and the substrate of the N-type MOS capacitor are both grounded, and the source of the N-type MOS capacitor is grounded through a preset resistor.

[0116] It should be noted that the variable capacitive device in the stacked amplifier provided by the embodiment of the present application can also be a P-type MOS capacitor. In an implementation manner, the gate of the P-type MOS capacitor is grounded, the source, the drain and the substrate of the P-type MOS capacitor are all grounded and are connected between the bias resistor R1 and the bias end of the second transistor 42.

[0117] In another implementation, the gate of the P-type MOS capacitor is connected to ground, the source and the drain of the P-type MOS capacitor are both connected between the bias resistor R1 and the bias end of the second transistor 42, and the substrate of the P-type MOS capacitor is connected between the bias resistor R1 and the bias end of the second transistor 42 through a preset resistor.

[0118] In yet another implementation, the gate of the P-type MOS capacitor is connected to ground, the source and the substrate of the P-type MOS capacitor are both connected between the bias resistor R1 and the bias end of the second transistor 42, and the drain of the P-type MOS capacitor is connected between the bias resistor R1 and the bias end of the second transistor 42 through a preset resistor.

[0119] It should be noted that the connection mode of the N-type MOS capacitor or the P-type MOS capacitor in the stacked amplifier is not limited to the above examples, and other modes can also be used, which will not be described here.

[0120] The scheme of the embodiment achieves high impedance of the second transistor in the off state by the variable capacitive device in the bias circuit, so that the off impedance of the second transistor is greater than the on impedance of the second transistor, thereby achieving high impedance of the stacked amplifier in the off state. Therefore, without additional switching switches, the stacked amplifier can be switched between the on and off states. By the variable capacitive device, the impedance of the second transistor in the off state is improved, the structure of the circuit is simpler, the loss cost of the circuit is smaller, and the circuit is easier to implement.

[0121] The stacked amplifier shown in any of the above embodiments of the application can be applied to a single-ended structure or a differential structure, i.e., a double-ended structure. The stacked amplifier applied to the differential structure is exemplarily described as follows, which is also called a differential amplifier. Figure 6 A schematic diagram of a differential structure stacked amplifier provided by the embodiment of the application is shown in FIG. 4. Figure 6 As shown in FIG. 4, the differential structure stacked amplifier can include two single-ended amplifiers. Figure 4 Or Figure 5 Any of the above-mentioned stacked amplifiers can include a first transistor 41, a second transistor 42, and a bias circuit 43.

[0122] The differential input end of the differential structure stacked amplifier can be the input end of the first transistor 41 in the two single-ended amplifiers, which can receive the input signal. The bias end of the first transistor 42 in the two single-ended amplifiers is grounded, and the output end of the first transistor 41 in the two single-ended amplifiers is respectively connected to the input end of one second transistor 42.

[0123] The differential output of the differential-structure stacked amplifier can be the output of the second transistor 42 of the two single-ended amplifiers, which can output the amplified signal. The bias end of the second transistor 42 of the two single-ended amplifiers is connected to the control output of a bias circuit 43, respectively, to obtain the bias voltage output by the control output.

[0124] The differential-structure stacked amplifier provided by the embodiment includes two single-ended amplifiers. Each single-ended amplifier can be similar to any of the above-described stacked amplifiers, that is, including a first transistor 41, a second transistor 42, and a bias circuit 43. The connection relationship of the first transistor 41, the second transistor 42, and the bias circuit 43 in each single-ended amplifier can be similar to the above. Each bias circuit 43 is connected to the control output, that is, has the same bias voltage.

[0125] The stacked amplifier provided by the embodiment can be applied in a differential structure. On the basis of realizing differential amplification, the high impedance of each stacked amplifier in the off state is realized. Therefore, no additional switching switch is involved to realize the switching of the on and off states, the loss of the circuit is reduced, and the performance advantage of the circuit for high-frequency signals is ensured.

[0126] Any of the above-described stacked amplifiers can be integrated on a chip to be realized or can be realized as a discrete component. The stacked amplifier can also be applied to more levels of stacking, that is, any of the above-described stacked amplifiers can include multiple levels of second transistors 42 and multiple bias circuits 43. Figure 7 A schematic diagram of a multi-level stacked amplifier provided by the embodiment is shown in FIG. 6. Figure 7 As shown in the figure, the multi-level stacked amplifier includes a first transistor 41 and multiple levels of second transistors 42. The connection of the ports of the first transistor can be similar to the connection of the first transistor 41 in any of the above-described stacked amplifiers, which will not be described here. The input end of the first-level second transistor 42 is connected to the output end of the first transistor 41, and the input end of the second-level second transistor 42 is connected to the output end of the first-level second transistor 42. The bias end of each second transistor 42 is connected to the control output of a bias circuit 43. The bias circuits 43 of the multiple levels of second transistors 42 can share a bias voltage, that is, are connected to the control output of an external circuit to obtain the bias voltage. Each second transistor 42 can amplify the signal under the action of the on bias voltage.

[0127] The output end of the last-level second transistor 42 in the multiple levels of second transistors 42 can be the output end of the stacked amplifier, which is used to output the amplified signal.

[0128] The multi-stage stacked amplifier provided by the embodiment can be amplified by the multi-stage second transistor multiple times, so that the signal amplification gain can be ensured. In the embodiment, the stacked amplifier is applied to the multi-stage stack, so that the high impedance of the off state can be achieved without involving additional switching switches, the switching between the on and off states is realized, the loss of the circuit is reduced, and the bidirectional port performance of the circuit for high-frequency signals is ensured.

[0129] It should be noted that the stacked amplifier in any of the above Figures 3-7 may use bipolar transistors or field effect transistors.

[0130] The stacked amplifier provided by the embodiment of the present application will be explained and described as follows by using two types of transistors. In a possible implementation, field effect transistors can be used, that is, the first transistor 41 and the second transistor 42 in the stacked amplifier are field effect transistors. As an example, an N-type MOS transistor is used for description, Figure 8 a schematic diagram of an N-type MOS transistor stacked amplifier provided by the embodiment of the present application. In the embodiment, the stacked amplifier can be a cascode structure amplifier, in which the first transistor 41 can be a common source transistor, which can be, for example, the first MOS transistor M1 shown in Figure 8 The second transistor 42 can be a common gate transistor, which can be, for example, the second MOS transistor M2 shown in Figure 8 .

[0131] It should be noted that in the embodiment, the bias circuit 43 is explained and described by using the circuit structure similar to that in the above Figure 5 The bias circuit 43 provided by the embodiment of the present application can also have other circuit structures, for example, the structure shown in any of Figure 5A , Figure 5B or Figure 5C The present application does not limit this.

[0132] In the embodiment, the gate of the first MOS transistor M1 can be used as the input end of the first transistor 41 to receive the input signal, and the drain of the first MOS transistor M1 can be used as the output end of the first transistor 41 to output the amplified signal of the first transistor 41. The source of the first MOS transistor M1 can be used as the bias end of the first transistor 41 and grounded to provide bias for the first MOS transistor M1, so that the first MOS transistor M1 can be in the saturation region to realize reverse amplification of the signal.

[0133] The source of the second MOS transistor M2 can serve as the input terminal of the second transistor 42 to receive the signal output by the first transistor 41. The drain of the second MOS transistor M2 can serve as the output terminal of the second transistor 42 to output the amplified signal of the second transistor 42. The gate of the second MOS transistor M2 can serve as the bias terminal of the second transistor 42 and be connected to the bias circuit 43.

[0134] The bias resistor R1 and the variable capacitive device C1 can make the second MOS transistor M2 also be in the saturation region under the action of the conduction bias voltage, so as to realize the forward amplification of the signal. In this way, the amplified signal output by the stacked amplifier can be divided across the first MOS transistor M1 and the second MOS transistor M2.

[0135] Meanwhile, the capacitance of the variable capacitive device C1 in the bias circuit 43 under the action of the on-bias voltage is the on-capacitance C. ON The capacitance value under the action of the turn-off bias voltage is the turn-off capacitance C. OFF If the on-bias voltage is greater than the off-bias voltage, the off-capacitor C of the second MOS transistor M2 can be turned off. OFF Less than the on-capacitance C ON This increases the turn-off impedance of the second MOS transistor M2.

[0136] In another possible implementation, bipolar transistors can be used, meaning that both the first transistor 41 and the second transistor 42 in the stacked amplifier are bipolar transistors. The following explanation uses an NPN transistor as an example. Figure 9 This is a schematic diagram of a stacked amplifier using NPN transistors, provided as an embodiment of this application. In this embodiment, the first transistor 41 in the stacked amplifier can be a common-emitter transistor, for example, it can be... Figure 9 The first transistor Q1 and the second transistor 42 shown can be common-base transistors, for example, they can be... Figure 9 The second transistor Q2 is shown in the diagram.

[0137] It should be noted that, in this embodiment, the bias circuit 43 is based on the above-mentioned... Figure 5 The following description uses a similar circuit structure as an example. However, the bias circuit 43 provided in the embodiments of this application can also be other circuit structures, such as... Figure 5A , Figure 5B or Figure 5C This application does not limit the structure shown in any of the examples.

[0138] In this embodiment, the base of the first transistor Q1 can be used as the input terminal of the first transistor 41 to receive the input signal, and the collector of the first transistor Q1 can be used as the output terminal of the first transistor 41 to output the amplified signal of the first transistor 41. The emitter of the first transistor Q1 can be grounded as the bias terminal of the first transistor 41, so that the first transistor Q1 can be in the amplification zone to realize the reverse amplification of the signal.

[0139] The emitter of the second transistor Q2 can be used as the input terminal of the second transistor 42 to receive the signal output by the first transistor 41, and the collector of the second transistor Q2 can be used as the output terminal of the second transistor 42 to output the amplified signal of the second transistor 42. The base of the second transistor Q2 can be connected to the bias circuit 43 as the bias terminal of the second transistor 42.

[0140] The bias resistor R1 and the variable capacitive device C1 can make the second transistor Q2 also in the amplification zone under the action of the turned-on bias voltage, so as to realize the forward amplification of the signal, and thus the amplified signal output by the stacked amplifier can be divided on the first transistor Q1 and the second transistor Q2.

[0141] Meanwhile, the variable capacitive device C1 in the bias circuit 43 has a turned-on capacitance C ON under the action of the turned-on bias voltage, and a turned-off capacitance C OFF under the action of the turned-off bias voltage. If the turned-on bias voltage is greater than the turned-off bias voltage, the turned-off capacitance C OFF of the second transistor Q2 can be less than the turned-on capacitance C ON , so as to improve the turned-off impedance of the second transistor Q2.

[0142] As described above Figure 8 and Figure 9 are respectively possible implementation manners of two different types of transistors. In the stacked amplifier provided by the present application, the transistors can also be other transistors, which are not limited to the above, and the embodiments of the present application are not limited thereto.

[0143] In some other possible implementation manners, the stacked amplifier provided by the embodiments of the present application can further include a transformer, which can also be referred to as an output transformer, to output the amplified signal output by the stacked amplifier after transformation. The primary coil of the transformer is connected to the output terminal of the second transistor 42, and the transformer is used to output the amplified signal after transformation, through the output terminal of the secondary coil. The following is explained and described through a specific example, Figure 10 is a schematic diagram of another stacked amplifier with a differential structure provided by the embodiments of the present application. As Figure 10As shown, the differential structure stacked amplifier can include two first MOS transistors, two second MOS transistors, a transformer T1, a second capacitor C2 and a third capacitor C3, and two bias circuits.

[0144] The first a transistor M 1a and the first b transistor M 1b may be input transistors of the stacked transistors, and the gates thereof can receive a radio frequency input (RF in ) signal. The source of the first a transistor M 1a and the first b transistor M 1b are grounded, and the drain of the first a transistor M 1a is connected to the source of the second a transistor M 2a , and the drain of the first b transistor M 1b is connected to the source of the second b transistor M 2b .

[0145] The second a transistor M 2a and the second b transistor M 2b may be common-gate transistors in the stacked transistors. The two bias circuits are bias circuits of the two second MOS transistors, respectively. Among them, the first a bias resistor R 1a and the first a variable capacitive device C 1a constitute the bias circuit of the second a transistor M 2a , and the first b bias resistor R 1b and the first b variable capacitive device C 1b constitute the bias circuit of the second b transistor M 2b . The two bias circuits are connected between the control output end of the external circuit and the ground, wherein the gate of the second a transistor M 2a is connected between the first a bias resistor R 1a and the first a variable capacitive device C 1a ; and the gate of the second b transistor M 2b is connected between the first b bias resistor R 1b and the first b variable capacitive device C 1b . The first a variable capacitive device C 1a and the first b variable capacitive device C 1b are alternating current ground capacitors of the second a transistor M 2a and the second b transistor M 2b , respectively.

[0146] The transformer T1 is an output transformer of the stacked transistors, the second capacitor C2 is a coordination capacitor connected with the primary coil of the transformer T1, and the third capacitor C3 is a coordination capacitor connected with the secondary coil of the transformer T1. The output end of the secondary coil of the transformer T1 is the output end of the stacked amplifier, which is used to output a radio frequency output (RF out)Signal.

[0147] When the bias voltage output from the control output terminal is the off-end bias voltage V cas-OFF This causes the stacked amplifier to be in a turned-off state. Figure 11 The equivalent circuit diagram of another differential stacked amplifier in the off state provided in the embodiments of this application. Figure 11 The gate-drain capacitance C2' is as described above. Figure 10 Second capacitor C2, second a transistor M 2a Second b transistor M 2b Gate drain capacitance (C) gd The sum of ) and the gate-source capacitance C gs2 For the second a transistor M 2a Second b transistor M 2b Gate-source capacitance (C) gs The sum of these values, and the AC ground capacitance C1 is: Figure 10 The first variable capacitive device C 1a And the first b variable capacitive device C 1b The impedance ro is that of the second transistor M. 2a Second b transistor M 2b The real part of the output impedance.

[0148] The following explanation uses the curves showing the relationship between the capacitance of the AC ground capacitor and the bias voltage. Figure 12 A graph showing the AC ground capacitance versus bias voltage of another differential stacked amplifier provided in this application embodiment. In the stacked amplifier provided in this application, the first a variable capacitive device C... 1a And the first b variable capacitive device C 1b All are variable capacitive devices, making the bias voltage Vcas the conduction bias voltage, also known as the conduction voltage V. ON When the preset high voltage is applied, the stacked amplifier is in the conducting state, and the AC ground capacitor C1 exhibits the preset on-resistance value C. ON The bias voltage is the turn-off bias voltage, also known as the turn-off voltage V. OFF At the preset low voltage, the stacked amplifier is in the off state, and the AC ground capacitor C1 exhibits the preset turn-off capacitance C. OFF See also Figure 12 It can be seen that the change in bias voltage can be converted into a change in the capacitance of AC ground capacitor C1, which in turn leads to a change in impedance.

[0149] Figure 13 A graph showing the AC ground capacitance of the second MOS transistor versus signal frequency in another differential stacked amplifier provided in an embodiment of this application. Figure 13 It can be seen that as the signal frequency increases, the conduction capacitance C of the AC ground capacitor C1 increases. ON With turn-off capacitance COFF The gap is widening, reducing the capacitance of the AC ground capacitor C1 of the stacked amplifier in the off state for high-frequency signals.

[0150] The AC ground capacitor C1 exhibits different capacitance values ​​in the on and off states, resulting in different impedances ro, thus exhibiting a variable impedance. Due to the impedance transformation function of transformer T1, transformer T1 exhibits different impedances in the preset frequency band, thereby achieving high impedance of AC ground capacitor C1 in the off state under high frequency signals. Figure 14 This is a graph showing the impedance versus signal frequency of the second MOS transistor in a stacked amplifier with a different differential structure provided in an embodiment of this application. Figure 14 It can be seen that the conduction impedance r of impedance ro is... ON Less than the turn-off impedance r OFF Furthermore, as the signal frequency increases, the on-resistance r... ON With turn-off impedance r OFF The gap is widening. In other words, the stacked amplifier provided in this application is more effective at blocking high impedance for high-frequency signals than at blocking high impedance for low-frequency signals.

[0151] To complement the stacked amplifier, RF transceiver circuit, and communication equipment provided in the above embodiments of this application, and to achieve switching between conduction and shutdown, the embodiments of this application may also provide a switching control method. Figure 15 This is a flowchart illustrating a switching control method provided in an embodiment of this application. Figure 15 As shown, the method may include:

[0152] S1501 generates a bias voltage.

[0153] S1502 outputs a bias voltage to the bias terminal of the second transistor in the stacked amplifier.

[0154] The bias voltage can be used to make the second transistor have different impedances under different bias voltages, and the turn-off impedance of the second transistor is greater than a preset impedance. The turn-off impedance is the impedance of the second transistor under the turn-off bias voltage, and the preset impedance can be greater than the on-resistance, which can be the impedance of the second transistor under the on-resistance bias voltage. For example, the preset impedance can be a preset turn-off impedance, that is, the impedance of a device with a fixed impedance in the bias circuit of the second amplifier under the turn-off bias voltage.

[0155] The bias voltage is generated by an external circuit, and the bias voltage is output to the bias end of the second transistor in the stacked amplifier through a control output end of the external circuit. Based on the stacked amplifier, the bias circuit makes the second transistor have different impedances under different bias voltages, and the off impedance of the second transistor is greater than the preset impedance.

[0156] The switching control method can realize the state switching of the on and off of the stacked amplifier by generating the bias voltage and outputting the bias voltage to the stacked amplifier, so that the stacked amplifier has different impedances under different bias voltages, realizes the high impedance of the off state, and realizes the state switching of the on and off. Therefore, without additional switching switches, the state switching of the on and off of the stacked amplifier can be realized, the circuit loss is reduced, and the leakage current of the path where the stacked amplifier is located in the off state can also be avoided, further reducing the circuit loss and effectively ensuring the bidirectional port performance of the circuit to the high-frequency signal.

[0157] It should be noted that the "connection" involved in the embodiments of the present application as described above can be direct connection or indirect connection, wherein the direct connection can be, for example, direct contact connection, or connection through a wire, etc., and the indirect connection can be, for example, coupling connection, or connection through other elements. The embodiments of the present application do not limit the specific form of the connection.

[0158] The above is only a specific implementation manner of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application should be subject to the protection scope of the claims.

Claims

1. A stacked amplifier, characterized in that, include: The first transistor, the second transistor, and the bias circuit; The bias terminal of the first transistor is grounded, the input terminal of the first transistor is used to receive the input signal, and the output terminal of the first transistor is connected to the input terminal of the second transistor. The bias terminal of the second transistor is connected to the control output terminal of an external circuit through the bias circuit to receive the bias voltage output by the external circuit through the control output terminal, and the output terminal of the second transistor is used to output an amplified signal. The bias circuit includes a bias resistor and a variable impedance device. The bias resistor and the variable impedance device are connected in series between the control output terminal and ground. The bias terminal of the second transistor is connected between the bias resistor and the variable impedance device. The variable impedance device is used to make the second transistor have different impedances under different bias voltages, and the turn-off impedance of the second transistor is greater than a preset impedance. The turn-off impedance is the impedance of the second transistor under the turn-off bias voltage, and the preset impedance is greater than or equal to the on-resistance of the second transistor under the on-bias voltage.

2. The stacked amplifier according to claim 1, characterized in that, The variable impedance device includes a variable capacitive device.

3. The stacked amplifier according to claim 2, characterized in that, The variable capacitive device includes a metal oxide semiconductor (MOS) capacitor.

4. The stacked amplifier according to claim 3, characterized in that, The MOS capacitor is an N-type MOS capacitor.

5. The stacked amplifier according to claim 4, characterized in that, The gate of the N-type MOS capacitor is connected between the bias resistor and the bias terminal of the second transistor, and the source, drain and substrate of the N-type MOS capacitor are all grounded.

6. The stacked amplifier according to claim 4, characterized in that, The gate of the N-type MOS capacitor is connected between the bias resistor and the bias terminal of the second transistor. The source and drain of the N-type MOS capacitor are both grounded, and the substrate of the N-type MOS capacitor is grounded through a preset resistor.

7. The stacked amplifier according to claim 4, characterized in that, The gate of the N-type MOS capacitor is connected between the bias resistor and the bias terminal of the second transistor. The drain and substrate of the N-type MOS capacitor are both grounded, and the source of the N-type MOS capacitor is grounded through a preset resistor.

8. The stacked amplifier according to claim 2, characterized in that, The variable capacitive device includes a varactor diode.

9. The stacked amplifier according to claim 2, characterized in that, The variable capacitive device includes a switched capacitor.

10. The stacked amplifier according to claim 1, characterized in that, The variable impedance device includes a variable inductive device.

11. The stacked amplifier according to any one of claims 1-10, characterized in that, The stacked amplifier is a differential amplifier, which includes two single-ended amplifiers. Each single-ended amplifier includes: a first transistor, a second transistor, and the bias circuit. The differential input terminal of the differential amplifier is the input terminal of the first transistor in the two single-ended amplifiers, and the differential output terminal of the differential amplifier is the output terminal of the second transistor in the two single-ended amplifiers.

12. The stacked amplifier according to any one of claims 1-10, characterized in that, The stacked amplifier includes: multiple stages of second transistors, and multiple bias circuits; in the multiple stages of second transistors, the input terminal of the first stage second transistor is connected to the output terminal of the first transistor, and the input terminal of the subsequent stage second transistor is connected to the output terminal of the preceding stage second transistor; The bias terminal of the second transistor in each stage is connected to the control output terminal through one of the bias circuits.

13. The stacked amplifier according to any one of claims 1-10, characterized in that, The stacked amplifier is a common-source, common-gate amplifier, wherein the first transistor is a common-source transistor, the input terminal of the first transistor is the gate of the common-source transistor, the output terminal of the first transistor is the drain of the common-source transistor, and the bias terminal of the first transistor is the source of the common-source transistor. The second transistor is a common-gate transistor, with its input terminal being the source, its output terminal being the drain, and its bias terminal being the gate.

14. The stacked amplifier according to any one of claims 1-10, characterized in that, The input terminal of the first transistor is the base of the common-emitter transistor, the output terminal of the first transistor is the collector of the common-emitter transistor, and the bias terminal of the first transistor is the emitter of the common-emitter transistor. The input terminal of the second transistor is the emitter of the common-base transistor, the output terminal of the second transistor is the collector of the common-base transistor, and the bias terminal of the second transistor is the base of the common-base transistor.

15. The stacked amplifier according to any one of claims 1-10, characterized in that, The stacked amplifier further includes a transformer, the primary coil of which is connected to the output terminal of the second transistor. The transformer is used to transform the amplified signal and output it through the output terminal of the secondary coil.

16. A radio frequency transceiver circuit, characterized in that, include: The antenna, the radio frequency circuit, and the stacked amplifier as described in any one of claims 1-15, wherein the stacked amplifier is connected between the antenna and the radio frequency circuit.

17. The radio frequency transceiver circuit according to claim 16, characterized in that, The stacked amplifier includes: a first stacked amplifier, wherein the input terminal of a first transistor in the first stacked amplifier is connected to the radio frequency circuit, and the output terminal of a second transistor in the first stacked amplifier is connected to the antenna.

18. The radio frequency transceiver circuit according to claim 16 or 17, characterized in that, The stacked amplifier further includes a second stacked amplifier, wherein the input terminal of the first transistor in the second stacked amplifier is connected to the antenna, and the output terminal of the second transistor in the second stacked amplifier is connected to the radio frequency circuit.

19. A communication device, characterized in that, include: The baseband circuit and the radio frequency transceiver circuit according to any one of claims 16-18, wherein the baseband circuit is connected to the radio frequency circuit in the radio frequency transceiver circuit.

20. A switching control method, characterized in that, include: Generate a bias voltage; A bias voltage is output to the bias terminal of the second transistor in any of the stacked amplifiers described in claims 1-15, so that the second transistor has different impedances under different bias voltages, and the turn-off impedance of the second transistor is greater than a preset impedance, wherein the turn-off impedance is the impedance of the second transistor under the action of the turn-off bias voltage.

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