An electrocardio feature extraction acceleration circuit, electrocardio monitoring system and method

Abstract

The application discloses an electrocardio feature extraction acceleration circuit, an electrocardio monitoring system and method, and belongs to the field of parallel computation acceleration. The electrocardio feature extraction acceleration circuit comprises an electrocardio signal input module, a system-on-chip processor, a hardware calculation module, a storage module and a feature output module. The application constructs a multiplication array and an addition tree calculation unit based on hardware resources, performs parallel acceleration on multiplication operation of a Mallat algorithm feature matrix and an electrocardio signal numerical matrix, utilizes hardware resources, so that the multiplication operation can be completed in one clock cycle; meanwhile, a ping-pong buffer mechanism is introduced in a multiplication array operation result temporary storage unit, a plurality of storage subunits are formed, the multiplication array and the addition tree calculation unit two modules alternately perform data writing and reading operations, so that the effect of parallel computation is achieved, the system operation speed is significantly improved, and the real-time performance of system monitoring results is further improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a kind of electrocardio feature extraction acceleration circuit, electrocardio monitoring system and method, belong to parallel computing acceleration field. BACKGROUND

[0002] Cardiovascular disease has been one of the main threats to human health all the time. According to the data investigation of "China Cardiovascular Health and Disease Report 2020" released in 2021, at present, cardiovascular disease death accounts for the first place of total death causes of urban and rural residents, 46.66% in rural areas and 43.81% in cities. Cardiovascular disease brings increasing economic burden to residents and society.

[0003] The main reasons why cardiovascular disease is so threatening to human health are as follows. Firstly, cardiovascular disease is sudden and fast, and many times once cardiovascular disease occurs, it will soon threaten human life and health. Another reason is that the effective means for monitoring heart rhythm on the market is too limited. Although patients will have a phenomenon of accelerated heart rate before most cardiovascular diseases occur, the mainstream scheme for patients to monitor their heart rhythm is still limited to traditional medical personnel with medical equipment. This scheme has two disadvantages. One is that the number of medical personnel and medical equipment is limited, and the other disadvantage is that patients need to go to the local hospital for registration for a heart rhythm monitoring, and then medical personnel perform electrocardiogram detection, and finally doctors give the judgment result. The steps are complicated and real-time monitoring cannot be achieved.

[0004] Under the above two disadvantages, some patients with cardiovascular disease risk cannot get real-time heart rhythm monitoring, resulting in the result of missing the best treatment time. However, under the background of high-speed development of artificial intelligence and embedded technology in today's world, some heart rhythm condition intelligent monitoring devices based on embedded system and artificial intelligence algorithm have appeared on the market.

[0005] As shown in Figure 1, it is an intelligent ECG signal monitoring acceleration system based on programmable system on chip, wherein Figure 1(a) is a structural block diagram of the programmable system on chip, and Figure 1(b) is a data communication diagram of the ECG signal classification algorithm hardware acceleration module and the system on chip processor. The system architecture will cover the Mallat algorithm of complex matrix operation, the BP neural network algorithm is deployed on the hardware acceleration module, and the final result is placed in the storage module, and finally returned to the system on chip processor through the bus structure. The system on chip processor controls the execution of the specific algorithm in the whole system, and the hardware acceleration module executes the complex matrix operation. The embedded device of this type extracts appropriate ECG feature values and uses the neural network to intelligently judge. The Mallat algorithm responsible for ECG feature extraction will involve a large number of complex matrix operations, which will cause the system to consume time in the feature extraction step, further cause the delay of the system result, and finally cause the poor ECG monitoring effect and poor real-time performance.

[0006] The ECG signal intelligent monitoring acceleration system based on programmable system on chip shown in Figure 1 attempts to use hardware resources to accelerate the matrix operation involved in the ECG feature extraction part, but it does not give a specific effective acceleration scheme, and considering the limited hardware resources, the system architecture still needs to be further optimized. SUMMARY

[0007] In order to solve the problem of poor ECG monitoring effect and poor real-time performance caused by complex operation and long time consumption of the current ECG signal intelligent monitoring system, the application provides an ECG feature extraction acceleration circuit, an ECG monitoring system and a method.

[0008] The first object of the application is to provide an ECG feature extraction acceleration circuit, which comprises an ECG signal input module, a system on chip processor, a hardware calculation module, a storage module and a feature output module.

[0009] The system on chip processor uses the Mallat algorithm to extract features from the input ECG signal;

[0010] The hardware calculation module comprises a multiplication array based on a multiplier and an addition tree calculation unit based on an adder, and the multiplication array and the addition tree calculation unit are connected and used for hardware calculation of matrix calculation of the Mallat algorithm and the ECG signal;

[0011] The storage module is used for storing operation data and calculation result data in the feature extraction process;

[0012] The feature output module outputs the final extracted ECG signal feature value according to the calculation result of the hardware calculation module.

[0013] Optionally, the storage module includes: an electrocardiogram signal sequence storage unit, a Mallat feature matrix storage unit, and a temporary storage unit;

[0014] The ECG signal sequence storage unit is used to store the ECG signal numerical matrix S, the Mallat feature matrix storage unit is used to store the feature matrix M of the Mallat algorithm, and the temporary storage unit is used to store the calculation results of the multiplication array, while also allowing the addition tree calculation unit to read the calculation results of the multiplication array.

[0015] Optionally, the temporary storage unit includes a data caching mechanism.

[0016] Optionally, the hardware computing module's calculation process for the Mallat algorithm and the electrocardiogram signal includes:

[0017] The on-chip system processor deploys the feature matrix M of the Mallat algorithm and the electrocardiogram signal numerical matrix S onto the hardware computing module:

[0018] The feature matrix M of the Mallat algorithm is:

[0019]

[0020] The numerical matrix S of the electrocardiogram signal is:

[0021]

[0022] Wherein, each column of the electrocardiogram (ECG) signal numerical matrix S is a set of ECG signal sequences, and the calculation formulas for the feature matrix M and the ECG signal numerical matrix S of the Mallat algorithm are as follows:

[0023]

[0024] Where C is the result matrix, and each column is a combination of the approximate component cD and the detail component cA after the corresponding layer decomposition;

[0025] The specific hardware calculation process includes:

[0026] Step 1: The on-chip system processor stores the value of the Mallat algorithm feature matrix M in the Mallat feature matrix storage unit, stores the ECG signal value matrix S in the ECG signal sequence storage unit, retrieves the corresponding data from the Mallat feature matrix storage unit and the ECG signal sequence storage unit, and deploys them to the two-bit multipliers in the multiplication array to perform multiplication operations.

[0027] Step 2: The on-chip system processor writes the operation result of the multiplication array into the temporary storage unit;

[0028] Step 3: The on-chip system processor controls the addition tree calculation unit to read the result of the multiplication operation from the temporary storage unit and perform the addition operation to obtain the final result matrix C;

[0029] The temporary storage unit utilizes a data caching mechanism to enable the simultaneous and alternating execution of the write operation of the multiplication array operation result and the read operation of the addition tree calculation unit.

[0030] Optionally, the addition tree calculation unit sets up multiple levels of adder groups for the output result of the multiplication array. Each level of adder group calculates the calculation result of the previous level of adder group by adding each other in pairs.

[0031] Each adder group adjusts its calculation method based on the parity of the number of data to be added, including:

[0032] For an even number of data points to be added, simply add them pairwise.

[0033] For an odd number of data to be added, the last data is taken out separately and directly participates in the operation of the last-stage adder group, while the other data are added in pairs.

[0034] Optionally, the data caching mechanism is a ping-pong caching mechanism.

[0035] Optionally, the process of using the Mallat algorithm to decompose the ECG signal into multiple layers to obtain the result matrix C includes:

[0036] The filtering process of Mallat's algorithm using convolution operations is as follows:

[0037]

[0038]

[0039] Wherein, G1(n) is the output result of the input digital ECG signal sequence after passing through the first layer of digital low-pass filter, H1(n) is the output result of the digital ECG signal sequence after passing through the first layer of digital high-pass filter, S(n) is the digital ECG signal sequence, and g(n) and h(n) represent digital low-pass and high-pass filters, respectively.

[0040] Performing a matrix transformation on the above convolution formula, given that the length of the digital ECG signal sequence S(n) is N, and the lengths of the digital low-pass filter g(n) and the digital high-pass filter h(n) are both K, with N>K, the matrix form of the above formula becomes:

[0041]

[0042] The matrix formed by the digital high-pass filters h(n) in the first layer is called the high-pass filter characteristic matrix F. h1 Similarly, the matrix formed by the digital low-pass filter g(n) is called the low-pass filter characteristic matrix F. g1 The following rule transformation is applied to these two (K+N-1)×N matrices:

[0043] (1) Remove the first (K / 2)-1 rows and the last (K / 2)-1 rows from each matrix to form an (N+1)×N matrix;

[0044] (2) For the remaining N+1 rows, extract the even-numbered rows and perform sampling at intervals;

[0045] (3) Concatenate the two extracted matrices together to form an N×N matrix F1, where matrix F1 is the feature matrix and the decomposition layer number is 1.

[0046] The following is a set of electrocardiogram signal sequences, after which the detail component cD1 and approximate component cA1 are obtained after the first level decomposition of the Mallat feature matrix;

[0047]

[0048] For the second layer of decomposition, the input signal is now the approximate component cA1 obtained from the first layer decomposition, and the high-pass filter feature matrix F obtained during the first layer decomposition process. h1 and low-pass filter feature matrix F g1 Repeat steps (1), (2), and (3) above to obtain The characteristic matrix F2 is then multiplied with cA1 to obtain the detail component cD2 and the approximate component cA2 in the second decomposition.

[0049] The wavelet decomposition process can be expressed using matrices as follows:

[0050]

[0051]

[0052] Repeat steps (1), (2) and (3) to obtain the detail components and approximate components of the subsequent decomposition layer.

[0053] The second objective of this invention is to provide an electrocardiogram (ECG) monitoring system, the system comprising: an analog-to-digital conversion module, a signal classification module, an output display module, and the aforementioned ECG feature extraction acceleration circuit;

[0054] The analog-to-digital converter module is used to convert electrocardiogram signals into digital signals;

[0055] The ECG feature extraction acceleration circuit is connected to the analog-to-digital conversion module and is used to extract features from digital ECG signals.

[0056] The on-chip system processor is also used to read the digital electrocardiogram signal feature values, send them to the signal classification module to perform classification operations, classify the electrocardiogram data according to the electrocardiogram data feature values, and write the classification results into the storage module;

[0057] The output display module outputs the ECG signal classification result and the corresponding ECG signal waveform based on the classification result.

[0058] Optionally, the signal classification module uses a BP neural network to classify electrocardiogram signals.

[0059] A third objective of this invention is to provide an electrocardiogram (ECG) monitoring method, which uses the aforementioned ECG monitoring system to monitor ECG signals. The method includes:

[0060] Step 1: Use an analog-to-digital converter to acquire the raw ECG signal data and convert it into a digital ECG signal;

[0061] Step 2: The on-chip system processor executes the Mallat algorithm to extract features from the digital electrocardiogram signal;

[0062] Step 3: The on-chip system processor transmits the feature extraction operation data to the hardware computing module through the system bus. The on-chip system processor and the hardware computing module represent the decomposition process of the digital electrocardiogram signal using the Mallat feature matrix. Using hardware resources, a multiplication array is constructed based on multipliers, and an addition tree computing unit is constructed based on adders to accelerate the matrix operation process of the Mallat algorithm. Finally, the matrix C, which is the result of multiplying the Mallat algorithm feature matrix M and the electrocardiogram signal numerical matrix S, is obtained. Each column of C is a combination of the approximate component cD and the detail component cA after the corresponding layer decomposition.

[0063] Step 4: Based on the decomposition results of the Mallat algorithm and the frequency characteristics of each band, the differential thresholding method is used to locate each band on the corresponding decomposition layer, i.e., to determine the position of the peak point of each band; the digital ECG signal feature values ​​are calculated by the successive difference method, including: average P-wave interval, average Q-wave interval, average R-wave interval, average S-wave interval, average T-wave interval, and average QRS complex duration.

[0064] The main wavebands of an electrocardiogram (ECG) signal, namely the P wave, Q wave, R wave, S wave, and T wave, contain the main characteristics of an ECG. These wavebands also differ in frequency. Given that the Mallat algorithm has already decomposed the signal, the differential thresholding method can be used at the corresponding decomposition layer to locate each waveband based on its frequency characteristics, thus determining the position of the peak point of each waveband. Subsequently, the average intervals between P waves, Q waves, R waves, S waves, T waves, and the average duration of the QRS complex can be calculated using the successive difference method. These values ​​are then fed into a neural network to calculate the classification results.

[0065] Step 5: The on-chip system processor reads the digital electrocardiogram (ECG) signal feature values, sends them to the signal classification module to perform classification operations, classifies the ECG data according to the ECG data feature values, and finally writes the classification results into the storage module, waiting for further scheduling commands from the on-chip system processor;

[0066] Step 6: The on-chip system processor then outputs the classification results to the output display module;

[0067] Step 7: The output display module outputs the final judgment of heart rhythm status and the corresponding electrocardiogram signal waveform.

[0068] The beneficial effects of this invention are:

[0069] This invention fully utilizes the multipliers and adders in the hardware resources of a programmable on-chip system to construct a multiplication array and an addition tree computing unit to design a parallel acceleration circuit. Compared with an existing intelligent heart rhythm monitoring acceleration system based on a programmable on-chip system, which does not provide a specific and effective hardware acceleration solution under the constraint of limited hardware resources, this invention can effectively accelerate the ECG feature extraction process and improve the parallelism and real-time performance of the ECG monitoring system.

[0070] Furthermore, this invention utilizes registers in hardware resources as temporary storage units for the results of the multiplication array and introduces a ping-pong caching mechanism from the data caching mechanism, deploying multiple storage sub-units, each capable of storing the output results of a set of multiplication arrays. The write operations for the output results of the multiplication array and the read operations for the input data of the addition tree computation unit are performed simultaneously and alternately on different storage sub-units. Because the timing is the same but the operations are staggered, the multiplication array and the addition tree computation unit can avoid being idle or dormant due to shared data dependencies, thereby further improving the system's operating speed. Attached Figure Description

[0071] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0072] Figure 1(a) is a block diagram of an intelligent monitoring and acceleration system for electrocardiogram signals based on a programmable system-on-a-chip in the prior art.

[0073] Figure 1(b) shows a schematic diagram of data communication in a prior art intelligent monitoring and acceleration system for electrocardiogram signals based on a programmable system-on-a-chip.

[0074] Figure 2(a) shows a flowchart of the optimized electrocardiogram monitoring system of the present invention.

[0075] Figure 2(b) shows the flowchart of the optimized electrocardiogram monitoring system of the present invention.

[0076] Figure 3(a) shows a schematic diagram of the multiplication array in the acceleration circuit designed in this invention.

[0077] Figure 3(b) shows a schematic diagram of the addition tree calculation unit in the acceleration circuit designed in this invention.

[0078] Figure 4 The flowchart of wavelet decomposition using the Mallat algorithm is shown.

[0079] Figure 5 The diagram shows the ECG signal types corresponding to different decomposition layers in the 8-scale wavelet decomposition.

[0080] Figure 6 A standard example of an electrocardiogram (ECG) according to an embodiment of the present invention is shown.

[0081] Figure 7 The diagram illustrates the architecture of the ping-pong caching mechanism according to an embodiment of the present invention.

[0082] Figure 8 This is a hardware circuit diagram of the multiplication array according to an embodiment of the present invention.

[0083] Figure 9 This is a structural diagram of a temporary storage unit according to an embodiment of the present invention.

[0084] Figure 10 This is a flowchart of the calculation process of the addition tree calculation unit in this embodiment of the invention when dealing with an even number of data to be added.

[0085] Figure 11 This is a flowchart of the addition tree calculation unit in this embodiment of the invention for an odd number of data to be added. Detailed Implementation

[0086] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0087] First, some of the professional theoretical knowledge involved in this invention will be introduced:

[0088] Mallat algorithm:

[0089] The Mallat algorithm is a multi-resolution analysis method in wavelet analysis, such as... Figure 4 The diagram illustrates the Mallat algorithm's process of reducing the order of a signal, where S is the original ECG signal sequence, g is a low-pass filter, and G... i Let cDi be the value obtained after decomposing the original ECG signal sequence through the i-th low-pass filter, cDi be the approximate component obtained after decomposing the original ECG signal sequence through the i-th layer, h be the high-pass filter, and H be the value obtained after decomposing the original ECG signal sequence through the i-th layer. i cA is the value obtained after the original electrocardiogram signal sequence is decomposed by the i-th high-pass filter. i These are the detail components obtained after the original electrocardiogram signal sequence has been decomposed into its i-th layer. cDi and cA i Will be specifically for G i Data and H i The data is obtained by sampling at intervals.

[0090] The approximate component is the low-frequency part obtained by convolving the signal with a digital low-pass filter in wavelet decomposition and then sampling at intervals.

[0091] The detailed components are the high-frequency components obtained by convolving the signal with a digital high-pass filter in wavelet decomposition and then sampling at intervals.

[0092] Mallat performs convolution operations on the raw ECG signal with a digital low-pass filter and then samples at intervals to obtain the low-frequency approximation. It then performs convolution operations with a digital high-pass filter and samples at intervals to obtain the high-frequency detail components. This completes one layer of decomposition. The above operations are then repeated on the detail components to complete the next layer of decomposition.

[0093] By considering the characteristics of different bands of the electrocardiogram (ECG) signal, the differential thresholding method can be used on different decomposition layers of the Mallat algorithm to locate different bands of the ECG signal, such as P, Q, R, S, and T. Figure 6 It shows a standard example of an electrocardiogram, which vividly displays the characteristics of the P, Q, R, S, and T bands. Figure 5 The paper demonstrates the types of electrocardiogram signals corresponding to different decomposition layers in the 8-scale wavelet decomposition.

[0094] Differential thresholding method:

[0095] The differential thresholding method is a fast algorithm suitable for detecting QRS waves in real-time ECG signals. Its basic principle is as follows: Since the QRS wave represents the most dramatic change in the ECG waveform, its rising or falling slope differs significantly from other waveforms. Therefore, the location of the R wave can be detected by detecting the change in the slope of the ECG signal sequence's derivative with respect to time. Typically, the rising and falling edges of the R wave represent the regions with the greatest slope change in the ECG waveform. The zero-crossing points of the first derivative and the extreme points of the second derivative within this range are the locations of the R wave to be detected. The R wave is detected by performing first-order or second-order differential analysis on the filtered ECG signal and combining this with a determined threshold. Then, by finding the nearest nearest minimum point forward, the Q wave is identified; by finding the nearest nearest maximum point forward, the P wave is identified. Similarly, by finding the nearest nearest minimum point backward, the S wave is identified; and by finding the nearest nearest maximum point backward, the T wave is identified.

[0096] Example 1:

[0097] This embodiment provides an accelerated circuit for electrocardiogram (ECG) feature extraction, including an ECG signal input module, an on-chip system processor, a hardware computing module, a storage module, and a feature output module;

[0098] The on-chip system processor uses the Mallat algorithm to extract features from the input electrocardiogram signal;

[0099] The hardware computing module includes a multiplication array based on multipliers and an addition tree computing unit based on adders. The multiplication array is connected to the addition tree computing unit and is used to perform hardware computing on the matrix calculations of the Mallat algorithm and electrocardiogram signals.

[0100] The storage module is used to store the computational data and calculation results data during the feature extraction process;

[0101] The storage module includes: an ECG signal sequence storage unit, a Mallat feature matrix storage unit, and a temporary storage unit;

[0102] The ECG signal sequence storage unit is used to store the ECG signal numerical matrix S, the Mallat feature matrix storage unit is used to store the feature matrix M of the Mallat algorithm, and the temporary storage unit is used to store the calculation results of the multiplication array, while also allowing the addition tree calculation unit to read the calculation results of the multiplication array.

[0103] The feature output module outputs the final extracted ECG signal feature values ​​based on the calculation results of the hardware calculation module.

[0104] In this embodiment, the Mallat algorithm is used to extract features from digital electrocardiogram signals. The convolution operation process in the Mallat algorithm is described using a matrix method. For the matrix multiplication operation, hardware resources on the programmable on-chip system are called to construct a multiplication array based on multipliers and an addition tree computing unit based on adders to accelerate the matrix operation process in parallel.

[0105] The Mallat algorithm is a multi-resolution analysis method in wavelet analysis, such as... Figure 4 The diagram illustrates the Mallat algorithm's process of reducing the order of a signal, where S is the original ECG signal sequence, g is a low-pass filter, and G... i Let cDi be the value obtained after decomposing the original ECG signal sequence through the i-th low-pass filter, cDi be the approximate component obtained after decomposing the original ECG signal sequence through the i-th layer, h be the high-pass filter, and H be the value obtained after decomposing the original ECG signal sequence through the i-th layer. i cA is the value obtained after the original electrocardiogram signal sequence is decomposed by the i-th high-pass filter. i These are the detail components obtained after the original electrocardiogram signal sequence has been decomposed into its i-th layer. cDi and cA i Will be specifically for G i Data and H i The data is obtained by sampling at intervals.

[0106] The filtering process of Mallat's algorithm using convolution operations is as follows:

[0107]

[0108]

[0109] Where G1(n) is the output of the input signal sequence after passing through the first digital low-pass filter, and H1(n) is the output of the input signal sequence after passing through the first digital high-pass filter. S(n) is the original input signal sequence, and g(n) and h(n) represent the digital low-pass and high-pass filters, respectively.

[0110] Performing a matrix transformation on the above convolution formula, with the input signal S(n) having a length of N, and the digital low-pass filter g(n) and digital high-pass filter h(n) both having a length of K, and N>K, the matrix form of the above formula becomes:

[0111]

[0112] The matrix formed by h(n) in the first layer is called the high-pass filter feature matrix F. h1 Similarly, the matrix formed by the digital low-pass filter g(n) is called the low-pass filter characteristic matrix F. g1The following rule transformation is applied to these two (K+N-1)×N matrices:

[0113] (1) Remove the first (K / 2)-1 rows and the last (K / 2)-1 rows from each matrix to form an (N+1)×N matrix;

[0114] (2) For the remaining N+1 rows, extract the even-numbered rows and perform sampling at intervals;

[0115] (3) The two extracted matrices are concatenated together to form an N×N matrix F1, where matrix F1 is the feature matrix and the decomposition layer is 1.

[0116] The following is a set of electrocardiogram signal sequences, after which the approximate component cD1 and detail component cA1 are obtained after the first level decomposition of the Mallat feature matrix.

[0117]

[0118] For the second layer of decomposition, the input signal is the detail component cA1 obtained from the first layer decomposition, and the high-pass filter feature matrix F obtained during the first layer decomposition process. h1 and low-pass filter feature matrix F g1 Repeat steps (1), (2), and (3) above to obtain Given the characteristic matrix F2, perform matrix multiplication between F2 and cA1 to obtain the approximate component cD2 and the detail component cA2 on the second level of decomposition.

[0119] The wavelet decomposition process can be expressed using matrices as follows:

[0120]

[0121]

[0122] Subsequent decomposition layers follow the same steps as described above.

[0123] The wavelet decomposition process of the Mallat algorithm on the original ECG signal sequence involves a large number of matrix operations. Without accelerating these operations, the operating speed of the ECG monitoring system will be significantly reduced, increasing latency. Given the limited hardware resources of programmable on-chip systems, designing an acceleration circuit to achieve optimal operating speed has become a major limiting factor for ECG monitoring systems. This invention provides an acceleration circuit based on a multiplication array and an addition tree computation unit.

[0124] Multiple sets of electrocardiogram (ECG) signal sequences are combined column-wise to form an ECG signal numerical matrix S, and M represents the characteristic matrix of the Mallat algorithm. The multiplication process between M and S is described mathematically:

[0125] M·S=C

[0126]

[0127] First, multiply each row of matrix M by the first column of matrix S to obtain the first column of the resulting matrix C:

[0128]

[0129] The electrocardiogram (ECG) signal numerical matrix S is split column-wise into groups of ECG signal sequences and stored in fixed cells. The feature matrix of the Mallat algorithm is stored in another fixed cell. Simultaneously, data is read from the ECG signal sequence storage cell and the Mallat feature matrix storage cell and deployed to the multiplication array, allowing it to perform multiplication operations concurrently. The hardware circuit diagram is shown below. Figure 8 As shown:

[0130] The data obtained in each row of the multiplication array is the result of the dot product of each row of the Mallat algorithm feature matrix and each set of ECG signal sequences. All of the above operations can be completed simultaneously. Taking the first row of the multiplication array as an example, the result is:

[0131] M 11 ·S 11 M 12 ·S 21 M 13 ·S 31 M 1n ·S n1

[0132] Next, the results of each group will be stored in the temporary storage unit of the multiplication operation results in row order. See below. Figure 9 .

[0133] Once data storage is complete, the system issues a command, and each group of addition tree computation units retrieves the corresponding group of data from the temporary storage unit of the multiplication result and performs the addition operation. At the same time, the multiplication array reads the next group of ECG signal sequences from the ECG signal sequence storage unit, performs the multiplication operation in the multiplication array, and stores the data in the next storage sub-unit without waiting.

[0134] A ping-pong caching mechanism is introduced into the storage unit, where data write and read operations are performed alternately. This avoids the input data of the addition tree computation unit waiting for the multiplication array operation to finish and be successfully stored in the storage unit before performing a read operation. Alternatively, it avoids the output result of the multiplication array waiting for the addition tree computation unit to finish reading the data from the storage unit before performing a write operation.

[0135] This can avoid the idle state of each computing unit due to waiting for data, increase the parallelism of the system, effectively improve the system running speed, and reduce latency.

[0136] The addition tree calculation unit arranges two-bit adders in a tree structure and performs addition operations. After waiting for system instructions, each group of addition tree calculation units retrieves the corresponding data from the temporary storage subunit of the multiplication results and performs the addition operation. Depending on the pairwise addition selection, the addition tree calculation unit needs to adjust according to the parity of the input data.

[0137] For an even number of data points to be added, perform pairwise addition directly, see [link / reference]. Figure 10 .

[0138] For an odd number of data to be added, the last data is extracted separately and directly participates in the operation of the last-stage adder. See [link / reference]. Figure 11 .

[0139] This embodiment constructs a multiplication array based on multipliers and an addition tree computation unit based on adders to accelerate the multiplication process of the Mallat algorithm feature matrix M and the electrocardiogram signal numerical matrix S in parallel.

[0140] In this embodiment, the storage unit introduced between the multiplication array and the addition tree computation unit adopts a ping-pong caching mechanism. After the multiplication array completes the dot product of the Mallat algorithm feature matrix and the ECG signal sequence, the addition tree computation unit performs addition operations on the data. Therefore, there is a logical order between the output data of the multiplication array and the input data of the addition tree computation unit. This embodiment utilizes the ping-pong caching mechanism for data flow, which can effectively improve the system parallelism.

[0141] like Figure 7 As shown, the ping-pong caching mechanism is a data flow control processing technique. After the multiplication array completes the multiplication operation between data, it writes the output result sequentially into storage sub-units 1, 2, 3, and 4. That is, in the first time interval, the output result is written to storage sub-unit 1; in the second time interval, it is written to storage sub-unit 2; in the third time interval, it is written to storage sub-unit 3; in the fourth time interval, it is written to storage sub-unit 4; in the fifth time interval, the output result is rewritten to storage sub-unit 1, and so on.

[0142] While writing, the addition tree computing unit starts working. In the second time period, the addition tree computing unit will read the data in storage sub-unit 1. In the third time period, the addition tree computing unit will read the data in storage sub-unit 2, and so on, alternating with the write operation of the multiplication array.

[0143] Example 2:

[0144] This embodiment provides an electrocardiogram (ECG) monitoring system, including: an analog-to-digital conversion module, a signal classification module, an output display module, and an ECG feature extraction acceleration circuit described in Embodiment 1;

[0145] The analog-to-digital converter module is used to convert electrocardiogram (ECG) signals into digital signals;

[0146] The ECG feature extraction acceleration circuit is connected to the analog-to-digital conversion module and is used for feature extraction from digital ECG signals;

[0147] The on-chip system processor is also used to read the digital electrocardiogram signal feature values, send them to the signal classification module to perform classification operations, classify the electrocardiogram data according to the electrocardiogram data feature values, and write the classification results into the storage module;

[0148] In this embodiment, the signal classification module uses a BP neural network to classify electrocardiogram signals.

[0149] The output display module outputs the ECG signal classification result and the corresponding ECG signal waveform based on the classification result.

[0150] Example 3:

[0151] This embodiment provides a method for monitoring electrocardiogram (ECG) signals, using the ECG monitoring system described in Embodiment 2, and includes the following steps:

[0152] Step 1: Use an analog-to-digital converter to acquire the raw ECG signal data and convert it into a digital ECG signal;

[0153] Step 2: The on-chip system processor executes the Mallat algorithm to extract features from the digital electrocardiogram signal;

[0154] Step 3: The on-chip system processor transmits the feature extraction operation data to the hardware computing module through the system bus. The on-chip system processor and the hardware computing module represent the decomposition process of the digital ECG signal using the Mallat feature matrix. They also utilize hardware resources to construct a multiplication array based on multipliers and an addition tree computing unit based on adders to accelerate the matrix operation process of the Mallat algorithm. After completing the decomposition of the ECG signal, the feature values ​​of the digital ECG signal are obtained at the corresponding decomposition layer using the differential thresholding method based on the band characteristics of the feature values ​​contained in the ECG signal.

[0155] The Mallat algorithm is a multi-resolution analysis method in wavelet analysis, such as... Figure 4 The diagram illustrates the Mallat algorithm's process of reducing the order of a signal, where S is the original ECG signal sequence, g is a low-pass filter, and G... iLet cDi be the value obtained after decomposing the original ECG signal sequence through the i-th low-pass filter, cDi be the approximate component obtained after decomposing the original ECG signal sequence through the i-th layer, h be the high-pass filter, and H be the value obtained after decomposing the original ECG signal sequence through the i-th layer. i cA is the value obtained after the original electrocardiogram signal sequence is decomposed by the i-th high-pass filter. i These are the detail components obtained after the original electrocardiogram signal sequence has been decomposed into its i-th layer. cDi and cA i Will be specifically for G i Data and H i The data is obtained by sampling at intervals.

[0156] The filtering process of Mallat's algorithm using convolution operations is as follows:

[0157]

[0158]

[0159] Where G1(n) is the output of the input signal sequence after passing through the first digital low-pass filter, and H1(n) is the output of the input signal sequence after passing through the first digital high-pass filter. S(n) is the original input signal sequence, and g(n) and h(n) represent the digital low-pass and high-pass filters, respectively.

[0160] Performing a matrix transformation on the above convolution formula, with the input signal S(n) having a length of N, and the digital low-pass filter g(n) and digital high-pass filter h(n) both having a length of K, and N>K, the matrix form of the above formula becomes:

[0161]

[0162] The matrix formed by h(n) in the first layer is called the high-pass filter feature matrix F. h1 Similarly, the matrix formed by the digital low-pass filter g(n) is called the low-pass filter characteristic matrix F. g1 The following rule transformation is applied to these two (K+N-1)×N matrices:

[0163] (1) Remove the first (K / 2)-1 rows and the last (K / 2)-1 rows from each matrix to form an (N+1)×N matrix;

[0164] (2) For the remaining N+1 rows, extract the even-numbered rows and perform sampling at intervals;

[0165] (3) The two extracted matrices are concatenated together to form an N×N matrix F1, where matrix F1 is the feature matrix and the decomposition layer is 1.

[0166] The following is a set of electrocardiogram signal sequences, after which the approximate component cD1 and detail component cA1 are obtained after the first level decomposition of the Mallat feature matrix.

[0167]

[0168] For the second layer of decomposition, the input signal is the detail component cA1 obtained from the first layer decomposition, and the high-pass filter feature matrix F obtained during the first layer decomposition process. h1 and low-pass filter feature matrix F g1 Repeat steps (1), (2), and (3) above to obtain Given the characteristic matrix F2, perform matrix multiplication between F2 and cA1 to obtain the approximate component cD2 and the detail component cA2 on the second level of decomposition.

[0169] The wavelet decomposition process can be expressed using matrices as follows:

[0170]

[0171]

[0172] Subsequent decomposition layers follow the same steps as described above.

[0173] The Mallat algorithm involves a large number of matrix operations in the wavelet decomposition process of the original electrocardiogram signal sequence. By making efficient use of hardware resources, the matrix operations can be accelerated.

[0174] This embodiment constructs a multiplication array based on the multipliers in the hardware resources and constructs an addition tree computing unit based on the adders in the hardware resources to accelerate the matrix multiplication operation in parallel, which can effectively reduce the system's computation time and reduce system latency.

[0175] The design method for the ECG feature extraction acceleration circuit based on multiplication array and addition tree computing units is as follows:

[0176] Consider a feature matrix M, which is the algebraic expression of the feature matrix of the Mallat algorithm.

[0177]

[0178] Consider a numerical matrix S, where each column represents a sequence of electrocardiogram (ECG) signals.

[0179]

[0180] Next, the feature matrix M and the electrocardiogram signal numerical matrix S are processed in parallel using a multiplication array and an addition tree computation unit. The steps are as follows:

[0181] Step 1: Express the calculation process of the feature matrix M and the electrocardiogram signal numerical matrix S using mathematical formulas:

[0182]

[0183] Each column of the electrocardiogram (ECG) signal matrix S represents a set of ECG signal sequences. The study will focus on the first column:

[0184]

[0185] Step Two: Deploy the above system of equations onto hardware, configuring multipliers for the multiplication operations, with the multipliers forming a multiplication array. First, store the value of the Mallat algorithm feature matrix M in the Mallat feature matrix storage unit, and store the ECG signal sequence in the ECG signal sequence storage unit. Simultaneously, according to the operation order of the above system of equations, retrieve the corresponding data from the two storage units and deploy them onto the two-bit multipliers respectively:

[0186] Step 3: The result of the multiplication operation is stored in the temporary storage unit of the multiplication array operation result;

[0187] A ping-pong caching mechanism is introduced into the aforementioned storage unit, allowing the writing operation of the multiplication array operation result and the reading operation of the input data of the addition tree calculation unit to be executed simultaneously in an alternating manner.

[0188] In this embodiment, the storage unit introduced in the multiplication array and addition tree computation unit adopts a ping-pong caching mechanism. After the multiplication array completes the dot product of the Mallat algorithm feature matrix and the ECG signal sequence, the addition tree computation unit performs addition operations on the data. Therefore, there is a logical order between the output data of the multiplication array and the input data of the addition tree computation unit. This embodiment utilizes the ping-pong caching mechanism for data flow, which can effectively improve the system parallelism.

[0189] like Figure 7 As shown, the ping-pong caching mechanism is a data flow control processing technique. After the multiplication array completes the multiplication operation between data, it writes the output result sequentially into storage sub-units 1, 2, 3, and 4. That is, in the first time interval, the output result is written to storage sub-unit 1; in the second time interval, it is written to storage sub-unit 2; in the third time interval, it is written to storage sub-unit 3; in the fourth time interval, it is written to storage sub-unit 4; in the fifth time interval, the output result is rewritten to storage sub-unit 1, and so on.

[0190] While writing, the addition tree computing unit starts working. In the second time period, the addition tree computing unit will read the data in storage sub-unit 1. In the third time period, the addition tree computing unit will read the data in storage sub-unit 2, and so on, alternating with the write operation of the multiplication array.

[0191] Step 4: After waiting for system instructions, the addition tree calculation unit starts working, reading data from the multiplication result storage unit above according to the ping-pong caching mechanism to perform the addition operation.

[0192] Based on the choice of adding data pairwise, the addition tree calculation unit needs to be adjusted according to the parity of the input data.

[0193] For an even number of data points to be added, simply add them pairwise:

[0194] For an odd number of data to be added, the last data is extracted separately and directly participates in the operation of the last-stage adder:

[0195] After completing the above steps, the multiplication operation between the Mallat algorithm feature matrix and a set of electrocardiogram signal sequences can be accelerated.

[0196] Step 4: Repeat the above steps for the following set of ECG signal sequences to finally obtain matrix C, which is the result of multiplying the feature matrix M of the Mallat algorithm with the ECG signal numerical matrix S. Each column of C is a combination of the approximate component cD and the detail component cA after the corresponding layer decomposition.

[0197] Step 5: Based on the decomposition results of the Mallat algorithm and the frequency characteristics of each band, the differential thresholding method is used to locate each band on the corresponding decomposition layer, i.e., to determine the position of the peak point of each band; the digital ECG signal feature values ​​are calculated by the successive difference method, including: average P-wave interval, average Q-wave interval, average R-wave interval, average S-wave interval, average T-wave interval, and average QRS complex duration.

[0198] The main wavebands of an electrocardiogram (ECG) signal, namely the P wave, Q wave, R wave, S wave, and T wave, contain the main characteristics of an ECG. These wavebands also differ in frequency. Given that the Mallat algorithm has already decomposed the signal, the differential thresholding method can be used at the corresponding decomposition layer to locate each waveband based on its frequency characteristics, thus determining the position of the peak point of each waveband. Subsequently, the average intervals between P waves, Q waves, R waves, S waves, T waves, and the average duration of the QRS complex can be calculated using the successive difference method. These values ​​are then fed into a neural network to calculate the classification results.

[0199] The differential thresholding method is a fast algorithm suitable for detecting QRS waves in real-time ECG signals. Its basic principle is as follows: Since the QRS wave represents the most dramatic change in the ECG waveform, its rising or falling slope differs significantly from other waveforms. Therefore, the location of the R wave can be detected by detecting the change in the slope of the ECG signal sequence's derivative with respect to time. Typically, the rising and falling edges of the R wave represent the regions with the greatest slope change in the ECG waveform. The zero-crossing points of the first derivative and the extreme points of the second derivative within this range are the locations of the R wave to be detected. The R wave is detected by performing first-order or second-order difference on the filtered ECG signal and combining this with a determined threshold. Then, by finding the nearest minimum point forward, the Q wave is identified; by finding the nearest maximum point forward, the P wave is identified. Similarly, by finding the nearest minimum point backward, the S wave is identified; and by finding the nearest maximum point backward, the T wave is identified.

[0200] Step 6: The on-chip system processor reads the feature values ​​of the digital electrocardiogram (ECG) signal, sends them to the BP neural network to perform classification operations, classifies the ECG data according to the ECG data feature values, and finally stores the output of the neural network in the storage module, waiting for further scheduling commands from the on-chip system processor.

[0201] Step 7: The on-chip system processor then outputs the classification results to the output display module;

[0202] Step 8: The output display module outputs the final judgment of the heart rhythm status and the corresponding electrocardiogram signal waveform.

[0203] This embodiment utilizes hardware resources to design an accelerated circuit for ECG feature extraction. A multiplication array is constructed based on the multipliers in the hardware resources, and an addition tree computation unit is constructed based on the adders in the hardware resources. This allows for parallel computation and acceleration of the multiplication of the Mallat feature matrix and the ECG signal numerical matrix in the ECG feature extraction part. Operations that originally required multiple clock cycles can now be completed in a single clock cycle using hardware resources. This effectively increases the parallelism of the system's operations, improves the system's processing speed, and reduces system latency.

[0204] Furthermore, this embodiment introduces a ping-pong caching mechanism, constructing multiple storage sub-units in the temporary storage unit for multiplication results. This allows the multiplication array and the addition tree calculation unit to alternately perform write and read operations, achieving the effect of parallel computing. This avoids one side being idle or dormant due to sequential dependence on shared data, further improving system computing speed, reducing monitoring latency, and enhancing the real-time performance of ECG signals.

[0205] Some steps in the embodiments of the present invention can be implemented using software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0206] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An accelerated circuit for electrocardiogram feature extraction, characterized in that, The circuit includes: an electrocardiogram signal input module, an on-chip system processor, a hardware computing module, a storage module, and a feature output module; The on-chip system processor uses the Mallat algorithm to extract features from the input electrocardiogram signal; The hardware computing module includes a multiplication array based on multipliers and an addition tree computing unit based on adders. The multiplication array is connected to the addition tree computing unit and is used to perform hardware computing on the matrix calculations of the Mallat algorithm and electrocardiogram signals. The specific hardware calculation process includes: Step 1: The on-chip system processor stores the value of the Mallat algorithm feature matrix M in the Mallat feature matrix storage unit, stores the ECG signal value matrix S in the ECG signal sequence storage unit, retrieves the corresponding data from the Mallat feature matrix storage unit and the ECG signal sequence storage unit, and deploys them to the two-bit multipliers in the multiplication array to perform multiplication operations. Step 2: The on-chip system processor writes the operation result of the multiplication array into a temporary storage unit; Step 3: The on-chip system processor controls the addition tree calculation unit to read the result of the multiplication operation from the temporary storage unit and perform the addition operation to obtain the final result matrix C; The process of using the Mallat algorithm to decompose the ECG signal into multiple layers and obtain the result matrix C includes: The filtering process of Mallat's algorithm using convolution operations is as follows: Wherein, G1(n) is the output result of the input digital ECG signal sequence after passing through the first layer of digital low-pass filter, H1(n) is the output result of the digital ECG signal sequence after passing through the first layer of digital high-pass filter, S(n) is the digital ECG signal sequence, and g(n) and h(n) represent digital low-pass and high-pass filters, respectively. Performing a matrix transformation on the above convolution formula, given that the length of the digital ECG signal sequence S(n) is N, and the lengths of the digital low-pass filter g(n) and the digital high-pass filter h(n) are both K, with N>K, the matrix form of the above formula becomes: The matrix formed by the digital high-pass filters h(n) in the first layer is called the high-pass filter characteristic matrix F. h1 Similarly, the matrix formed by the digital low-pass filter g(n) is called the low-pass filter characteristic matrix F. g1 The following rule transformation is applied to these two (K+N-1)×N matrices: (1) Remove the first (K / 2)-1 rows and the last (K / 2)-1 rows from each matrix to form an (N+1)×N matrix; (2) For the remaining N+1 rows, extract the even-numbered rows and perform sampling at intervals; (3) Concatenate the two extracted matrices together to form an N×N matrix F1, where matrix F1 is the feature matrix and the decomposition layer number is 1. The following is a set of electrocardiogram signal sequences, after which the detail component cD1 and approximate component cA1 are obtained after the first level decomposition of the Mallat feature matrix; For the second layer of decomposition, the input signal is now the approximate component cA1 obtained from the first layer decomposition, and the high-pass filter feature matrix F obtained during the first layer decomposition process. h1 and low-pass filter feature matrix F g1 Repeat steps (1), (2), and (3) above to obtain The characteristic matrix F2 is then multiplied with cA1 to obtain the detail component cD2 and the approximate component cA2 in the second decomposition. The wavelet decomposition process can be expressed using matrices as follows: Repeat steps (1), (2) and (3) to obtain the detail components and approximate components of the subsequent decomposition layer; The temporary storage unit utilizes a data caching mechanism to enable the simultaneous and alternating execution of the write operation of the multiplication array operation result and the read operation of the addition tree calculation unit. The storage module is used to store the computational data and calculation results data during the feature extraction process; The feature output module outputs the final extracted ECG signal feature values ​​based on the calculation results of the hardware calculation module.

2. The ECG feature extraction acceleration circuit according to claim 1, characterized in that, The storage module includes: an electrocardiogram signal sequence storage unit, a Mallat feature matrix storage unit, and a temporary storage unit; The ECG signal sequence storage unit is used to store the ECG signal numerical matrix S, the Mallat feature matrix storage unit is used to store the feature matrix M of the Mallat algorithm, and the temporary storage unit is used to store the calculation results of the multiplication array, while also allowing the addition tree calculation unit to read the calculation results of the multiplication array.

3. The ECG feature extraction acceleration circuit according to claim 2, characterized in that, The temporary storage unit includes a data caching mechanism.

4. The ECG feature extraction acceleration circuit according to claim 3, characterized in that, The hardware computing module's calculation process for the Mallat algorithm and the electrocardiogram signal includes: The on-chip system processor deploys the feature matrix M of the Mallat algorithm and the electrocardiogram signal numerical matrix S onto the hardware computing module: The feature matrix M of the Mallat algorithm is: The numerical matrix S of the electrocardiogram signal is: Wherein, each column of the electrocardiogram (ECG) signal numerical matrix S is a set of ECG signal sequences, and the calculation formulas for the feature matrix M and the ECG signal numerical matrix S of the Mallat algorithm are as follows: Where C is the result matrix, and each column is a combination of the approximate component cD and the detail component cA after the corresponding layer decomposition.

5. The ECG feature extraction acceleration circuit according to claim 4, characterized in that, The addition tree calculation unit sets up multiple levels of adder groups for the output results of the multiplication array. Each level of adder group calculates the calculation results of the previous level of adder group by adding them in pairs. Each adder group adjusts its calculation method based on the parity of the number of data to be added, including: For an even number of data points to be added, simply add them pairwise. For an odd number of data to be added, the last data is taken out separately and directly participates in the operation of the last-stage adder group, while the other data are added in pairs.

6. The ECG feature extraction acceleration circuit according to claim 4, characterized in that, The data caching mechanism is a ping-pong caching mechanism.

7. An electrocardiogram (ECG) monitoring system, characterized in that, The system includes: an analog-to-digital conversion module, a signal classification module, an output display module, and an electrocardiogram feature extraction acceleration circuit as described in any one of claims 1-6; The analog-to-digital converter module is used to convert electrocardiogram signals into digital signals; The ECG feature extraction acceleration circuit is connected to the analog-to-digital conversion module and is used to extract and accelerate the features of digital ECG signals. The on-chip system processor is also used to read the feature values ​​of the digital electrocardiogram signal, send them to the signal classification module to perform classification operations, classify the electrocardiogram data according to the feature values ​​of the electrocardiogram data, and write the classification results into the storage module; The output display module outputs the ECG signal classification result and the corresponding ECG signal waveform based on the classification result.

8. The electrocardiogram monitoring system according to claim 7, characterized in that, The signal classification module uses a BP neural network to classify electrocardiogram signals.

9. A method for monitoring electrocardiogram (ECG), characterized in that, The method for monitoring electrocardiogram (ECG) signals using the ECG monitoring system as described in any one of claims 7 or 8 includes: Step 1: Use an analog-to-digital converter to acquire the raw ECG signal data and convert it into a digital ECG signal; Step 2: The on-chip system processor executes the Mallat algorithm to extract features from the digital electrocardiogram signal; Step 3: The on-chip system processor transmits the feature extraction operation data to the hardware computing module through the system bus. The on-chip system processor and the hardware computing module represent the decomposition process of the digital electrocardiogram signal using the Mallat feature matrix. Using hardware resources, a multiplication array is constructed based on multipliers, and an addition tree computing unit is constructed based on adders to accelerate the matrix operation process of the Mallat algorithm. Finally, the result matrix C is obtained by multiplying the Mallat algorithm feature matrix M and the electrocardiogram signal numerical matrix S, where each column of C is a combination of the approximate component cD and the detail component cA after the corresponding layer decomposition. Step 4: Based on the decomposition results of the Mallat algorithm and the frequency characteristics of each band, the differential thresholding method is used to locate each band on the corresponding decomposition layer, i.e., to determine the position of the peak point of each band; the digital ECG signal feature values ​​are calculated by the successive difference method, including: average P-wave interval, average Q-wave interval, average R-wave interval, average S-wave interval, average T-wave interval, and average QRS complex duration. Step 5: The on-chip system processor reads the digital electrocardiogram (ECG) signal feature values, sends them to the signal classification module to perform classification operations, classifies the ECG data according to the ECG data feature values, and finally writes the classification results into the storage module, waiting for further scheduling commands from the on-chip system processor; Step 6: The on-chip system processor then outputs the classification results to the output display module; Step 7: The output display module outputs the final judgment of heart rhythm status and the corresponding electrocardiogram signal waveform.

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