A test system and test method for the bus interface of an information processing microsystem
By designing test equipment and information processing microsystems, the problem of bus interface testing of information processing microsystems is solved, efficient and accurate bus interface testing is achieved, production costs are reduced, and bus function testing is suitable for multiple microsystems.
Patent Information
- Application Number
- CN202210472219.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-04-29
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2042-04-29
AI Technical Summary
The prior art cannot effectively test the various types and multiple bus interfaces of information processing microsystems, and lacks special equipment to meet the correctness testing requirements of the system call bus interface function.
A test system is designed, including testing equipment, test board and test cable. It uses a bus interface test unit, test master control unit, power control unit, data storage unit and timing synchronization unit to communicate with the micro system master control unit through the data address bus, provide clock supply and timing synchronization, and realize bus interface testing.
It improves the efficiency and accuracy of information processing microsystem bus interface testing, reduces production costs, and can be widely used in bus function testing of various types of microsystems.
Smart Images
Figure CN114966366B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the test of a bus interface, in particular to a test system and a test method for the bus interface of an information processing micro-system, and belongs to the field of integrated circuit testing. Background Art
[0002] With the increasing demands for miniaturization, low power consumption, and high reliability of weaponry, space systems, and aircraft, the architecture of using discrete circuits for separate packaging and then performing board-level interconnection cannot meet the requirements of the new generation of aerospace systems in terms of small volume, high precision, high density, and high reliability. As the architecture complexity of information processing micro-systems increases, the number and types of bus interfaces integrated within the system have increased significantly. Information processing micro-systems with multiple types and large quantities of bus interfaces have become the development trend in this field.
[0003] Due to system integration, the bus interfaces of information processing micro-systems cannot be tested using the functional testing or structural testing methods employed for single chips. At the same time, the test requirements for the bus interfaces of information processing micro-systems have newly added the correctness testing of the system when the system calls the functions of the bus interfaces. Therefore, the test of the bus interfaces of information processing micro-systems must achieve test control and data processing of the bus interfaces through system functions. Due to the large number of types of bus interfaces to be tested and the complex system architecture of information processing micro-systems, there is no dedicated test equipment that can simultaneously meet multiple test requirements, and large ATE equipment also cannot meet the requirements in aspects such as program loading, timing control, and reset mechanisms for complex system architectures. Summary of the Invention
[0004] The technical problem to be solved by the present invention is: to overcome the deficiencies of the prior art and provide a test system and a test method for the bus interface of an information processing micro-system. By the joint cooperation of a test device and an information processing micro-system, it overcomes the drawback that the single-chip bus interface test method cannot be used to test the bus interface of an information processing micro-system, and can simultaneously meet multiple test requirements.
[0005] The technical solution of the present invention is:
[0006] A test system for the bus interface of an information processing micro-system, comprising a test device, a test board, and test cables;
[0007] The test device includes a bus interface test unit, a test main control unit, a power control unit, a data storage unit, a communication unit, and a timing synchronization unit; the test board carries an information processing micro-system and a timing module;
[0008] The information processing microsystem includes a microsystem main control unit, a test program storage unit, a reconfigurable data processing unit, and each bus interface unit. The microsystem main control unit, the test program storage unit, and the reconfigurable data processing unit communicate with each other through the data address bus. The bus interface test unit on the test equipment is connected to the bus interface unit of the information processing microsystem through a test cable. The communication unit on the test equipment is connected to the microsystem main control unit on the information processing microsystem through a communication bus. The timing synchronization unit on the test equipment is connected to the timing module on the test board through a timing cable to provide clock supply and timing synchronization for the test.
[0009] The timing module on the test board provides the system clock and synchronization clock required during the test for the information processing microsystem through the clock trace on the test board.
[0010] Preferably, a bus interface peripheral circuit is also mounted on the test board.
[0011] For the bus interface unit that cannot be directly tested by the bus interface test unit on the test equipment, the test connection method is as follows:
[0012] The bus interface test unit on the test equipment is connected to the bus interface peripheral circuit on the test board through a test cable, and the bus interface peripheral circuit on the test board is connected to the bus interface unit inside the information processing microsystem through the bus interface trace on the test board.
[0013] Preferably, the bus interface peripheral circuit on the test board provides the coupling matching, level conversion, or protocol driving functions required for the test of the bus interface unit in the information processing microsystem.
[0014] Preferably, the bus interface test unit includes dedicated test equipment or boards for various bus interfaces.
[0015] The test main control unit is a controller with an operating system, which is used to execute the test of the bus interface of the information processing microsystem and send the test data and test results to the data storage unit.
[0016] The power control unit is a multi-channel programmable power supply that supplies power to the information processing microsystem.
[0017] The timing synchronization unit is a multi-channel clock source that provides clock supply and timing synchronization for the information processing microsystem.
[0018] The data storage unit realizes the storage of test data and test results.
[0019] The communication unit realizes the communication between the test equipment and the information processing microsystem.
[0020] A test method for the bus interface of an information processing microsystem includes the following steps:
[0021] 1) The test master unit on the test device issues an initialization instruction. After receiving the initialization instruction, the micro-system master unit starts to perform a status self-check, and the self-check result is fed back to the test master unit. If the test master unit determines that the self-check result passes, it jumps to step 2); if it determines that the self-check result fails, it jumps to step 8).
[0022] 2) The test master unit establishes the test sequence of the information processing micro-system bus interface, and sends the start instruction of the i-th bus interface test to the micro-system master unit according to the communication protocol between the test device and the information processing micro-system. The information processing micro-system enters step 3), and the test device enters step 6); the initial value of i is 0.
[0023] 3) After receiving the start instruction of the i-th bus interface test, the micro-system master unit runs the i-th bus interface micro-system end test program stored in the test program storage unit. The generated initial test data is sent to the bus interface test unit through the bus interface unit; the reconfigurable data processing unit performs data processing and analysis on the feedback data of the bus interface test unit, and the processed result is fed back to the micro-system master unit; the micro-system master unit judges the fed-back processing and analysis result. If the result meets the requirements, it jumps to step 5); if the result does not meet the requirements, it jumps to step 4); the reconfigurable data processing unit is loaded with a data processing and analysis program.
[0024] 4) The micro-system master unit feeds back the test error item of the i-th bus interface to the test master unit according to the communication protocol between the test device and the information processing micro-system, and enters step 7).
[0025] 5) The micro-system master unit feeds back the test passed item of the i-th bus interface to the test master unit according to the communication protocol between the test device and the information processing micro-system, and enters step 7).
[0026] 6) The test master unit executes the test program of the i-th bus interface test device end, calls the dedicated test board corresponding to the i-th bus interface in the bus interface test unit to receive the initial test data sent by the bus interface unit and perform processing and analysis on it, judges whether the communication rate, data length, and check format during bus interface communication meet the requirements, generates feedback data according to the judgment result and sends it to the bus interface unit, and feeds back the processing and analysis result to the test master unit, and enters step 7).
[0027] 7) The test master unit records the test result fed back by the micro-system master unit and the processing and analysis result fed back by the bus interface test unit; the value of i is incremented by 1, and it is judged whether i is greater than N. If it is greater, all bus interfaces have completed the test and jump to step 9); otherwise, jump to step 2); N is the total number of test items of the bus interface.
[0028] 8) The test master unit displays that the initialization fails and stops the test;
[0029] 9) The test master unit displays all bus test results and the test is completed.
[0030] Preferably, steps 3) to 5) are carried out simultaneously with step 6) and cooperate with each other.
[0031] A test method for a bus interface of an information processing microsystem, comprising the following steps:
[0032] 1) The test master unit on the test device issues an initialization instruction. After receiving the initialization instruction, the microsystem master unit starts to perform a status self-check, and the self-check result is fed back to the test master unit. If the test master unit determines that the self-check result passes, it jumps to step 2); if it determines that the self-check result fails, it jumps to step 8);
[0033] 2) The test master unit establishes the test sequence of the bus interface of the information processing microsystem, and sends the start instruction of the i-th bus interface test to the microsystem master unit according to the communication protocol between the test device and the information processing microsystem. The information processing microsystem enters step 3), and the test device enters step 6); the initial value of i is 0;
[0034] 3) After receiving the start instruction of the i-th bus interface test, the microsystem master unit runs the i-th bus interface microsystem-side test program stored in the test program storage unit. At the same time, the bus interface unit receives the initial test data sent by the bus interface test unit, and the reconfigurable data processing unit performs data processing and analysis on the initial test data. The result after processing and analysis is fed back to the microsystem master unit, and the feedback data is sent to the bus interface test unit through the bus interface unit; the microsystem master unit judges the feedback result of processing and analysis. If the result meets the requirements, it jumps to step 5); if the result does not meet the requirements, it jumps to step 4); The reconfigurable data processing unit is loaded with a data processing and analysis program;
[0035] 4) The microsystem master unit feeds back the test error item of the i-th bus interface to the test master unit according to the communication protocol between the test device and the information processing microsystem, and enters step 7);
[0036] 5) The microsystem master unit feeds back the test pass item of the i-th bus interface to the test master unit according to the communication protocol between the test device and the information processing microsystem, and enters step 7);
[0037] 6) The test master unit executes the test program for the device side of the i-th bus interface test, and calls the dedicated test board corresponding to the i-th bus interface in the bus interface test unit to send initial test data to the bus interface unit; the bus interface test unit receives the feedback data sent by the bus interface unit and processes and analyzes it, determines whether the communication rate, data length, and check format during bus interface communication meet the requirements, and feeds back the determination result to the test master unit, and enters step 7);
[0038] 7) The test master unit records the test results fed back to the micro-system master unit and the processing and analysis results fed back by the bus interface test unit; the value of i is incremented by 1, and it is determined whether i is greater than N. If it is greater, all bus interfaces have completed the test and jump to step 9); otherwise, jump to step 2); N is the total number of test items for the bus interface;
[0039] 8) The test master unit displays that the initialization fails and stops the test;
[0040] 9) The test master unit displays all bus test results and the test is completed.
[0041] Preferably, the communication protocol between the test device and the information processing micro-system stipulates the test start instruction and test end instruction for each bus interface test; among them, the test start instruction includes the bus interface type and bus interface number, and the test end instruction includes the test end flag, the test correct or specific test failure flag, and the test data to be recorded;
[0042] Preferably, the communication protocol between the test device and the information processing micro-system also stipulates the communication rate, data length, and check format during the communication of each bus interface test, and the data takes the form of pseudo-random numbers or fixed values.
[0043] Preferably, the test results in step 9) include whether all test items pass and the specific faults of the test failures.
[0044] The beneficial effects of the present invention compared with the prior art are:
[0045] (1) The present invention utilizes the large-capacity logic storage unit, programmable unit, and high-performance computing unit integrated inside the information processing micro-system to complete the bus interface control and test data processing within the information processing micro-system during the bus interface test process, and solves the problem that it is difficult to carry out tests on the bus interfaces within the information processing micro-system.
[0046] (2) In the present invention, the test data processing and analysis during the bus interface test process can be completed inside the information processing micro-system. Compared with caching first and then uploading to the host computer software for processing in the past, it reduces the overhead of additional data transmission and the interference between signals, and this test system enhances the accuracy and reliability of the test data.
[0047] (3) The test equipment built in the present invention has universality. According to the dedicated test equipment or board containing the bus interface in the test equipment, it can be widely applied to the bus function test of various types of microsystems.
[0048] (4) The test system for the bus interface of the information processing microsystem in the present invention, through the joint cooperation of the test equipment and the information processing microsystem, overcomes the shortcoming that the single-chip bus interface test method cannot perform the bus interface test of the information processing microsystem, can meet multiple test requirements at the same time, effectively improves the test efficiency of the bus interface function of the information processing microsystem, can be used for the mass production test of the information processing microsystem, and reduces the production cost. Description of the Drawings
[0049] Figure 1 is the structural schematic diagram of the test system of the present invention;
[0050] Figure 2 is the first step diagram of the test method of the present invention.
[0051] Figure 3 is the second step diagram of the test method of the present invention. Detailed Embodiments
[0052] As Figure 1 shown, the test system for the bus interface of the information processing microsystem of the present invention includes a test equipment 15, a test board 4 and a test cable 13.
[0053] The information processing microsystem 5 includes a microsystem main control unit (high-performance computing unit) 6, a test program storage unit (non-volatile large-capacity logic storage unit) 7, a reconfigurable data processing unit (large-scale field programmable logic unit and its configuration storage unit) 9, and each bus interface 10. The microsystem main control unit 6, the test program storage unit 7, and the reconfigurable data processing unit 9 communicate with each other through a data address bus 8.
[0054] The test equipment 15 includes a bus interface test unit (dedicated test equipment or board for each bus interface) 14, a test main control unit 16, a power control unit 17, a data storage unit 18, a communication unit 19, and a timing synchronization unit 21. Different bus interfaces correspond to different test units. Figure 1 In fact, the test equipment 15 in it includes 4 test units.
[0055] The test board 4 is equipped with the information processing microsystem 5, and is also equipped with a timing module 2 and a bus interface peripheral circuit 12.
[0056] The bus interface test unit 14 on the test equipment 15 is connected to the bus interface peripheral circuit 12 on the test board 4 through the test cable 13.
[0057] The communication unit 19 on the test device 15 is connected to the micro-system master control unit 6 on the information processing micro-system 5 through the communication bus 1 to realize communication between the test device 15 and the information processing micro-system 5.
[0058] The timing synchronization unit 21 on the test device 15 is connected to the timing module 2 on the test board 4 through the timing cable (usually a radio frequency signal line) 20 to provide clock supply and timing synchronization for the test.
[0059] The timing module 2 on the test board 4 provides the system clock and synchronization clock required during the test for the information processing micro-system 5 through the clock trace 3 on the test board 4.
[0060] The bus interface peripheral circuit 12 on the test board 4 is connected to the bus interface unit 10 inside the information processing micro-system 5 through the bus interface trace 11 on the test board 4. The bus interface peripheral circuit 12 on the test board 4 provides functions such as coupling matching, level conversion, or protocol driving required for the test of the bus interface unit 10 in the information processing micro-system 5. It usually includes capacitors, resistors with specific values, level conversion chips, PHY chips, etc.
[0061] The test device 15 includes 1) a bus interface test unit 14, which consists of function and protocol-specific test devices or boards for various bus interfaces to meet the test requirements of the information processing micro-system 5; 2) a test master control unit 16, usually a controller equipped with an operating system, to meet the operation requirements of the information processing micro-system 5; 3) a power control unit 17, usually a multi-channel programmable power supply, to meet the power supply requirements of the information processing micro-system 5; 4) a timing synchronization unit 21, usually a multi-channel clock source, to meet the clock supply and timing synchronization requirements of the information processing micro-system 5; 5) a data storage unit 18, usually a large-capacity storage module, to realize the storage of test data and test results; 6) a communication unit 19, usually a serial interface, an Ethernet port, etc., to realize communication between the test device and the information processing micro-system;
[0062] There is test software on the test master control unit 16 to realize functions such as test development, test operation, data analysis, and auxiliary management.
[0063] In the test system, the test fixture refers to the hardware that realizes the connection between the test device 15 and the information processing micro-system 5, including 1) the test board 4 carrying the information processing micro-system, which cooperates with the test device to meet the requirements of power supply, clock 2, system reset, bus interface peripheral circuit 12, etc. of the information processing micro-system; 2) the test cable 13 that realizes the connection between each interface on the test board and the information processing micro-system, meeting the requirements of each bus interface protocol.
[0064] The unit circuits for cooperation testing within the information processing microsystem 5 include: 1) the microsystem main control unit 6, usually a high-performance computing unit such as a high-performance CPU, high-performance DSP, etc.; 2) the test program storage unit 7, usually a non-volatile large-capacity logic storage unit; 3) the reconfigurable data processing unit 9, usually a large-scale field programmable logic unit and its configuration storage unit; and 4) the bus interface to be tested.
[0065] The microsystem-side test program running on the information processing microsystem 5 for controlling the information processing microsystem 5 to cooperate with the test equipment 15 for testing is burned into the test program storage unit 7 within the information processing microsystem 5 through the dedicated development software platform of the information processing microsystem.
[0066] Based on Figure 1 the test system with the shown interface, the first form of the bus interface test steps for the information processing microsystem is as Figure 2 . The following steps are included:
[0067] 1) The test main control unit issues an initialization instruction. After receiving the initialization instruction, the microsystem main control unit starts to perform a self-check on the status of the information processing microsystem, and the self-check result is fed back to the test main control unit. If the self-check result is passed, jump to step 2); if the self-check result is not passed, jump to step 5).
[0068] 2) The test main control unit sequentially performs bus interface tests according to the established bus interface test sequence of the information processing microsystem. During the test process, the test main control unit sends a certain bus interface test start instruction to the information processing microsystem according to the communication protocol. The information processing microsystem enters step 3.1), and the test equipment enters step 3.4).
[0069] 3.1) After receiving the test start instruction, the information processing microsystem runs the corresponding test program on the microsystem side stored in the test program storage unit within the information processing microsystem according to the communication protocol. The bus interface unit sends the initial test data to the bus interface test unit; the reconfigurable data processing unit performs data processing and analysis on the feedback data of the bus interface test unit, and the processed and analyzed result is fed back to the microsystem main control unit; the microsystem main control unit judges the fed-back processed and analyzed result. If the result meets the requirements, jump to step 3.3); if the result does not meet the requirements, jump to step 3.2); a data processing and analysis program is loaded in the reconfigurable data processing unit.
[0070] The data processing and analysis program in the reconfigurable data processing unit is written in advance and is loaded into the reconfigurable data processing unit in different cases after the test starts.
[0071] Possible situation 1: There are a total of n tests corresponding to m programs. During the i-th test, it is the j-th program (0 ≤ i ≤ n - 1, 0 ≤ j ≤ m - 1, 1 < m ≤ n).
[0072] Possible situation 2: There are a total of n tests corresponding to 1 program. During the i-th test, it is the 1st program.
[0073] The loading process is controlled by the test master unit on the test device. The program can be stored on the test device or in the information processing micro-system.
[0074] 3.2) The master unit of the information processing micro-system feeds back the specific test error items of this bus interface test to the test master unit according to the communication protocol, and proceeds to step 4);
[0075] 3.3) The master unit of the information processing micro-system feeds back the passed items of this bus interface test to the test master unit according to the communication protocol, and proceeds to step 4)
[0076] 3.4) The test master unit executes the test program for the corresponding bus interface test item on the test device side, calls the dedicated test board for the corresponding bus interface, receives the test data sent by the bus interface, processes and analyzes the data, generates feedback data according to the processing and analysis results, sends it to the bus interface, and feeds back the processing and analysis results to the test master unit. The test master unit proceeds to step 4);
[0077] 4) The test master unit receives the test results fed back by the master unit of the micro-system and the test unit, records the test results. If there are still bus interfaces to be tested, it jumps to 2). If all bus interfaces have been tested, it jumps to step 6)
[0078] 5) The test master unit displays that the initialization fails and stops the test;
[0079] 6) The test master unit displays all bus test results and stops the test.
[0080] Steps 3.1) to 3.3) and the said step 3.4) are carried out simultaneously.
[0081] In step 3.1), the communication protocol stipulates the test start instruction and test end instruction for each bus interface test. The test start instruction includes the bus interface type and bus interface number. The test end instruction includes the test end flag, the test correct or specific test failure flag, and the test data to be recorded.
[0082] In step 3.1), the communication protocol also stipulates the communication rate, data length, and check format during the communication of this bus interface for each bus interface test. The data can be in the form of pseudo-random numbers or fixed values.
[0083] The test results in step 6) include whether all test items pass and the specific faults of the test failures;
[0084] Based on Figure 1 The test system of the interface shown, the second form of the bus interface test steps of the information processing micro-system is as Figure 3 . It includes the following steps:
[0085] 1) The test master unit issues an initialization instruction. After receiving the initialization instruction, the micro-system master unit starts the self-check of the information processing micro-system state, and the self-check result is fed back to the test master unit. If the self-check result is passed, it jumps to step 2); if the self-check result is not passed, it jumps to step 5);
[0086] 2) The test master unit sequentially performs bus interface tests according to the established bus interface test sequence of the information processing micro-system. During the test, the test master unit sends a start instruction for a certain bus interface test to the information processing micro-system according to the communication protocol. The information processing micro-system enters step 3.1), and the test device enters step 3.4);
[0087] 3.1) After receiving the start instruction for this test, the information processing micro-system runs the corresponding test program at the micro-system end stored in the test program storage unit in the information processing micro-system according to the communication protocol. The bus interface unit receives the initial test data sent by the bus interface test unit; the reconfigurable data processing unit performs data processing and analysis on the initial test data, and the processed and analyzed result is fed back to the micro-system master unit, and the feedback data is sent to the bus interface test unit through the bus interface unit; the micro-system master unit judges the processed and analyzed result fed back. If the result meets the requirements, it jumps to step 3.3); if the result does not meet the requirements, it jumps to step 3.2); The data processing and analysis program is loaded into the reconfigurable data processing unit;
[0088] The data processing and analysis program in the reconfigurable data processing unit is written in advance and is loaded into the reconfigurable data processing unit in different cases after the test starts.
[0089] Possible case 1: There are a total of n tests corresponding to m programs. In the i-th test, it is the j-th program (0 ≤ i ≤ n - 1, 0 ≤ j ≤ m - 1, 1 < m ≤ n).
[0090] Possible case 2: There are a total of n tests corresponding to 1 program. In the i-th test, it is the 1st program.
[0091] The loading process is controlled by the test master unit on the test device. The program can be stored on the test device or in the information processing micro-system.
[0092] 3.2) The main control unit of the information processing microsystem feeds back the specific test error items of this bus interface test to the test main control unit according to the communication protocol, and proceeds to step 4);
[0093] 3.3) The main control unit of the information processing microsystem feeds back the passed items of this bus interface test to the test main control unit according to the communication protocol, and proceeds to step 4)
[0094] 3.4) The test main control unit executes the test program for the corresponding bus interface test item on the test equipment side, calls the dedicated test board for the corresponding bus interface, sends the initial test data, the bus interface test unit receives the feedback data sent by the bus interface and processes and analyzes it, and feeds back the processing and analysis results to the test main control unit, and the test main control unit proceeds to step 4);
[0095] 5) The test main control unit displays that the initialization fails and stops the test;
[0096] 6) The test main control unit displays all the bus test results and stops the test.
[0097] Steps 3.1) to 3.3) are carried out simultaneously with step 3.4).
[0098] In step 3.1), the communication protocol stipulates the test start instruction and test end instruction for each bus interface test. The test start instruction includes the bus interface type and bus interface number, and the test end instruction includes the test end flag, test correct or specific test failure flag, and test data to be recorded.
[0099] In step 3.1), the communication protocol also stipulates the communication rate, data length, and check format during the communication of this bus interface for each bus interface test. The data can be in the form of pseudo-random numbers or fixed values.
[0100] In step 6), the test results include whether all test items pass and the specific failures of the test failures.
[0101] In the present invention, the microsystem-side test program includes a microsystem-side main control program and N bus interface microsystem-side test programs. The i-th bus interface microsystem-side test program includes the i-th bus interface microsystem-side data processing and analysis program, the i-th bus interface microsystem-side sending test program, and the i-th bus interface microsystem-side receiving test program.
[0102] The test equipment-side test program includes a test equipment-side main control program and N bus interface test equipment-side test programs. The i-th bus interface test equipment-side test program includes the i-th bus interface test equipment-side data processing and analysis program, the i-th bus interface test equipment-side sending test program, and the i-th bus interface test equipment-side receiving test program.
[0103] The present invention overcomes the deficiencies of the prior art, fully combines the unit circuits within the information processing microsystem, and provides a test system for the bus interface of the information processing microsystem. Based on the large-capacity logic storage unit, programmable unit, and high-performance computing unit within the information processing microsystem, a bus interface test cooperation circuit is constructed, a bus interface test device with power supply and timing synchronization capabilities is built, a test master unit for developing control test equipment for test development, test operation, data analysis, and auxiliary management functions and a microsystem master unit for cooperating with the control information processing microsystem for testing are developed. By running the microsystem-side test program within the information processing microsystem and the test device-side test program within the test device, and connecting the test device to the bus interface to be tested on the information processing microsystem with test cables and test boards, the communication function test of the bus interface of the information processing microsystem is realized. The present invention effectively improves the test efficiency of the bus interface function of the information processing microsystem, can be used for mass production testing of the information processing microsystem, and reduces production costs. The test device developed by the present invention has a certain degree of generality and can be widely applied to the bus function testing of various types of microsystems.
[0104] The parts not described in detail in the present invention belong to the well-known technology in the art.
Claims
1. A test system for the bus interface of an information processing microsystem, characterized in that: It includes a test device (15), a test board (4) and test cables (13); The test device (15) includes a bus interface test unit (14), a test master control unit (16), a power control unit (17), a data storage unit (18), a communication unit (19) and a timing synchronization unit (21); An information processing micro-system (5) and a timing module (2) are mounted on the test board (4); The information processing micro-system (5) includes a micro-system master control unit (6), a test program storage unit (7), a reconfigurable data processing unit (9) and each bus interface unit (10). The micro-system master control unit (6), the test program storage unit (7) and the reconfigurable data processing unit (9) communicate with each other through a data address bus (8); The bus interface test unit (14) on the test device (15) is connected to the bus interface unit (10) of the information processing micro-system (5) through a test cable (13); The communication unit (19) on the test device (15) is connected to the micro-system master control unit (6) on the information processing micro-system (5) through a communication bus (1); The timing synchronization unit (21) on the test device (15) is connected to the timing module (2) on the test board (4) through a timing cable (20) to provide clock supply and timing synchronization for the test; The timing module (2) on the test board (4) provides the system clock and synchronization clock required during the test for the information processing micro-system (5) through the clock trace (3) on the test board (4); The bus interface test unit (14) includes dedicated test devices or boards for various bus interfaces; The test master control unit (16) is a controller equipped with an operating system, which is used to execute the test of the bus interface of the information processing micro-system and send the test data and test results to the data storage unit (18); The power control unit (17) is a multi-channel programmable power supply that powers the information processing micro-system; The timing synchronization unit (21) is a multi-channel clock source that provides clock supply and timing synchronization for the information processing micro-system; The data storage unit (18) realizes the storage of test data and test results; The communication unit (19) realizes the communication between the test device and the information processing micro-system; There is test software on the test master control unit (16) to realize test development, test operation, data analysis and auxiliary management functions.
2. The test system for the bus interface of the information processing microsystem according to claim 1, characterized in that: A bus interface peripheral circuit (12) is also mounted on the test board (4); For the bus interface unit (10) that cannot be directly tested by the bus interface test unit (14) on the test device (15), the test connection method is as follows: The bus interface test unit (14) on the test device (15) is connected to the bus interface peripheral circuit (12) on the test board (4) through a test cable (13), and the bus interface peripheral circuit (12) on the test board (4) is connected to the bus interface unit (10) inside the information processing micro-system (5) through the bus interface trace (11) on the test board (4).
3. The test system for the bus interface of the information processing microsystem according to claim 2, wherein: The bus interface peripheral circuit (12) on the test board (4) provides the coupling matching, level conversion or protocol driving functions required for testing for the bus interface unit (10) in the information processing micro-system (5).
4. A test method for the bus interface of an information processing microsystem, characterized in that The steps are as follows: 1) The test master unit on the test device issues an initialization instruction. After receiving the initialization instruction, the micro-system master unit starts to perform a status self-check, and the self-check result is fed back to the test master unit. If the test master unit determines that the self-check result passes, it jumps to step 2); if it determines that the self-check result fails, it jumps to step 8). 2) The test master unit establishes the test sequence for the bus interface of the information processing micro-system, and sends the start instruction for the i-th bus interface test to the micro-system master unit according to the communication protocol between the test device and the information processing micro-system. The information processing micro-system enters step 3), and the test device enters step 6); the initial value of i is 0. 3) After receiving the start instruction for the i-th bus interface test, the micro-system master unit runs the test program for the i-th bus interface at the micro-system end stored in the test program storage unit. The generated initial test data is sent to the bus interface test unit through the bus interface unit. The reconfigurable data processing unit performs data processing and analysis on the feedback data from the bus interface test unit, and the processed result is fed back to the micro-system master unit. The micro-system master unit judges the processed and analyzed result fed back. If the result meets the requirements, it jumps to step 5); if the result does not meet the requirements, it jumps to step 4). The reconfigurable data processing unit is loaded with a data processing and analysis program. 4) The micro-system master unit feeds back the test error item of the i-th bus interface to the test master unit according to the communication protocol between the test device and the information processing micro-system, and enters step 7). 5) The micro-system master unit feeds back the test passed item of the i-th bus interface to the test master unit according to the communication protocol between the test device and the information processing micro-system, and enters step 7). 6) The test master unit executes the test program for the i-th bus interface at the test device end, calls the dedicated test board card corresponding to the i-th bus interface in the bus interface test unit to receive the initial test data sent by the bus interface unit and perform processing and analysis on it, judges whether the communication rate, data length and check format during bus interface communication meet the requirements, generates feedback data according to the judgment result and sends it to the bus interface unit, and feeds back the processed and analyzed result to the test master unit, and enters step 7). 7) The test master unit records the test result fed back by the micro-system master unit and the processed and analyzed result fed back by the bus interface test unit. The value of i is incremented by 1. It is judged whether i is greater than N. If it is greater, all bus interfaces have completed the test and jump to step 9). Otherwise, it jumps to step 2); N is the total number of test items for the bus interface. 8) The test master unit displays that the initialization fails and stops the test. 9) The test master unit displays all bus test results, and the test is completed.
5. The test method for the bus interface of an information processing micro-system according to claim 4, characterized in that: Steps 3) to 5) are carried out simultaneously with step 6) and cooperate with each other.
6. A test method for the bus interface of an information processing micro-system, characterized in that The steps are as follows: 1) The test master unit on the test device issues an initialization instruction. After receiving the initialization instruction, the micro-system master unit starts to perform a status self-check, and the self-check result is fed back to the test master unit. If the test master unit determines that the self-check result passes, it jumps to step 2); if it determines that the self-check result fails, it jumps to step 8). 2) The test master unit establishes the test sequence for the information processing micro-system bus interface, and sends the start instruction for the i-th bus interface test to the micro-system master unit according to the communication protocol between the test device and the information processing micro-system. The information processing micro-system enters step 3), and the test device enters step 6); the initial value of i is 0. 3) After receiving the start instruction for the i-th bus interface test, the micro-system master unit runs the i-th bus interface micro-system end test program stored in the test program storage unit. At the same time, the bus interface unit receives the initial test data sent by the bus interface test unit, and the reconfigurable data processing unit performs data processing and analysis on the initial test data. The processed and analyzed result is fed back to the micro-system master unit, and the feedback data is sent to the bus interface test unit through the bus interface unit. The micro-system master unit judges the processed and analyzed result fed back. If the result meets the requirements, it jumps to step 5); if the result does not meet the requirements, it jumps to step 4); a data processing and analysis program is loaded in the reconfigurable data processing unit. 4) The micro-system master unit feeds back the test error items of the i-th bus interface to the test master unit according to the communication protocol between the test device and the information processing micro-system, and enters step 7). 5) The micro-system master unit feeds back the test passed items of the i-th bus interface to the test master unit according to the communication protocol between the test device and the information processing micro-system, and enters step 7). 6) The test master unit executes the test program for the i-th bus interface on the test device side, and calls the dedicated test board corresponding to the i-th bus interface in the bus interface test unit to send the initial test data to the bus interface unit. The bus interface test unit receives the feedback data sent by the bus interface unit and processes and analyzes it, judges whether the communication rate, data length, and check format during bus interface communication meet the requirements, and feeds back the judgment result to the test master unit, and enters step 7). 7) The test master unit records the test results fed back from the micro-system master unit and the processed and analyzed results fed back from the bus interface test unit; the value of i is incremented by 1, and it is judged whether i is greater than N. If it is greater, all bus interfaces have completed the test and jump to step 9). Otherwise, jump to step 2); N is the total number of test items for the bus interface. 8) The test master unit displays that the initialization fails and stops the test. 9) The test master unit displays all bus test results and the test is completed.
7. A test method for an information processing microsystem bus interface according to claim 4 or 6, characterized in that: The communication protocol between the test device and the information processing micro-system stipulates the start instruction and end instruction for each bus interface test; the start instruction includes the bus interface type and bus interface number, and the end instruction includes the test end flag, the test correct or specific test fault flag, and the test data to be recorded.
8. A test method for the bus interface of an information processing micro-system according to claim 7, characterized in that: The communication protocol of the test equipment and the information processing microsystem also stipulates the communication rate, data length, and verification format during the communication of each bus interface when performing the bus interface test, and the data takes the form of pseudo-random numbers or fixed values.
9. A test method for an information processing micro-system bus interface according to claim 4 or 6, characterized in that: The test results in step 9) include whether all test items pass and the specific faults of the test failures.
Citation Information
Patent Citations
1553B communication test method for digital signal processing micro system
CN112630631A