Display substrate, display device and manufacturing method

Abstract

The present invention discloses a display substrate, a display device and a manufacturing method, wherein the display substrate comprises: a substrate; a plurality of gate lines, which are located on the substrate and extend along a first direction and are arranged along a second direction; a plurality of data lines, which are located on the substrate and extend along the second direction and are arranged along the first direction, and the second direction intersects with the first direction; a plurality of sub-pixel regions are defined by the gate lines and the data lines; a plurality of sub-pixel electrodes, which are located in the plurality of sub-pixel regions on the substrate; a plurality of driving transistors, which are located on the substrate and are electrically connected to each data line, each gate line and each sub-pixel electrode; a grid structure, which is located on a side of a layer where the sub-pixel electrode is located away from the substrate, wherein the grid structure has an opening area for accommodating charged particles in each sub-pixel region, wherein the orthographic projection of the grid structure on the substrate at least partially covers the orthographic projection of the gate line and the data line on the substrate, and the ratio of the area of ​​the sub-pixel electrode to the area of ​​the sub-pixel region is greater than 70%.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate, a display device and a manufacturing method thereof. Background Art

[0002] At present, the electronic paper (EPD) on the market mainly adopts microcup / microcapsule type electronic paper film, and uses the electronic ink in the microcup / microcapsule to realize black, white and red display.

[0003] However, microcup / microcapsule electronic paper film has high technical barriers, forming a de facto technological monopoly, which makes the shipment volume and price of electronic paper seriously affected by microcup / microcapsule electronic paper film manufacturers, which is not conducive to the overall expansion of the electronic paper market. Summary of the invention

[0004] The embodiments of the present invention provide a display substrate, a display device and a manufacturing method thereof, so as to solve the above problems existing in the prior art.

[0005] In a first aspect, in order to solve the above technical problems, an embodiment of the present invention provides a display substrate, comprising:

[0006] substrate substrate;

[0007] A plurality of gate lines are located on the substrate and extend along a first direction and are arranged along a second direction;

[0008] A plurality of data lines are located on the substrate and extend along the second direction and are arranged along the first direction, wherein the second direction intersects the first direction; the gate lines and the data lines define a plurality of sub-pixel areas;

[0009] A plurality of sub-pixel electrodes are located in a plurality of the sub-pixel regions on the substrate;

[0010] A plurality of driving transistors, located on the base substrate and electrically connected to each of the data lines, each of the gate lines and each of the sub-pixel electrodes;

[0011] A grid structure is located on a side of the layer where the sub-pixel electrode is located away from the base substrate. The grid structure has an opening area for accommodating charged particles in each sub-pixel area. The orthographic projection of the grid structure on the base substrate at least partially covers the orthographic projection of the gate line and the data line on the base substrate. The ratio of the area of ​​the sub-pixel electrode to the area of ​​the sub-pixel area is greater than 70%.

[0012] In a possible implementation manner, the grid structure includes: first barrier bars extending along the first direction and arranged along the second direction, and second barrier bars extending along the second direction and arranged along the first direction;

[0013] The orthographic projection of the first barrier bar on the base substrate at least partially covers the gate line, and the orthographic projection of the second barrier bar on the base substrate at least partially covers the data line and has an overlapping area with the sub-pixel electrode.

[0014] In a possible implementation manner, a shape of a cross section of the first barrier strip along the second direction and a shape of a cross section of the second barrier strip along the first direction are both trapezoidal.

[0015] In a possible implementation manner, the ratio of the top side to the bottom side of the trapezoid is in the range of 0.5 to 0.8.

[0016] In a possible implementation manner, the display substrate further includes: a first block electrode and a second block electrode stacked in a plurality of the sub-pixel regions on the base substrate;

[0017] The first block electrode, the gate of the driving transistor and the gate line are all located in the gate metal layer, and the second block electrode and the source and drain of the driving transistor are all located in the source and drain metal layer;

[0018] The source-drain metal layer is located between the gate metal layer and the layer where the sub-pixel electrode is located;

[0019] A first storage capacitor is formed between the sub-pixel electrode and the second block electrode, and a second storage capacitor is formed between the second block electrode and the first block electrode.

[0020] In a possible implementation manner, in the opening region of the grid structure, the sub-pixel electrode is electrically connected to the first block electrode through a first via hole, and the sub-pixel electrode is electrically connected to the source of the driving transistor through a second via hole.

[0021] In a possible implementation manner, each of the second block electrodes is electrically connected via a common electrode line that is consistent with the extending direction of the data line;

[0022] The orthographic projection of the grid structure on the base substrate at least partially covers the common electrode line or is adjacent to the common electrode line.

[0023] In a possible implementation manner, the display substrate further includes: an inorganic insulating layer located between the layer where the driving transistor is located and the layer where the sub-pixel electrode is located;

[0024] The orthographic projection of the sub-pixel electrode on the base substrate covers the orthographic projection of the driving transistor, an organic insulating layer is provided between the inorganic insulating layer and the layer where the sub-pixel electrode is located, and the thickness of the organic insulating layer is greater than the thickness of the inorganic insulating layer.

[0025] In a possible implementation manner, the orthographic projections of the driving transistor and the sub-pixel electrode on the base substrate do not overlap each other, the orthographic projection of the driving transistor on the base substrate overlaps the gate line, and is located between the two data lines;

[0026] The line width of the gate line in a region overlapping the driving transistor is greater than the line width in other regions.

[0027] In a possible implementation manner, the display substrate further includes: a semiconductor layer between the source / drain metal layer and the gate metal layer;

[0028] The semiconductor layer is adjacent to the source-drain metal layer, and the semiconductor layer includes an active layer of the driving transistor and a third block electrode having a pattern consistent with the second block electrode.

[0029] In a possible implementation manner, materials of the organic insulating layer and the grid structure are both resin.

[0030] In a second aspect, an embodiment of the present invention provides a method for manufacturing a display substrate, comprising:

[0031] Providing a substrate;

[0032] A plurality of gate lines extending along a first direction and arranged along a second direction, and a plurality of data lines extending along the second direction and arranged along the first direction are sequentially formed on a surface of one side of the base substrate; the second direction intersects with the first direction, and the gate lines and the data lines define a plurality of sub-pixel areas;

[0033] While forming the gate line and the data line, forming the driving transistor;

[0034] After forming the driving transistor, an inorganic insulating layer and a sub-pixel electrode are sequentially formed; the ratio of the area of ​​the sub-pixel electrode to the area of ​​the sub-pixel region is greater than 70%;

[0035] A grid structure is formed around each of the sub-pixel regions, wherein the grid structure has an opening area for accommodating charged particles in each of the sub-pixel regions, and the orthographic projection of the grid structure on the base substrate at least partially covers the orthographic projection of the gate line and the data line on the base substrate.

[0036] In a possible implementation manner, when the orthographic projection of the sub-pixel electrode on the base substrate covers the orthographic projection of the driving transistor on the base substrate, the manufacturing method further includes:

[0037] After forming the inorganic insulating layer and before forming the sub-pixel electrode, an organic insulating layer having a thickness greater than that of the inorganic insulating layer is formed.

[0038] In a possible implementation manner, when the orthographic projection of the sub-pixel electrode on the base substrate and the orthographic projection of the driving transistor on the base substrate do not overlap each other, forming the gate line includes:

[0039] In a region where the gate line overlaps the driving transistor, a width of the gate line is formed to be greater than a width of other regions.

[0040] In a third aspect, an embodiment of the present invention provides a display device, including:

[0041] The display substrate as described in the first aspect, the counter substrate arranged opposite to the display substrate, the plasma layer filled in each opening area of ​​the grid structure, and the common electrode layer located on the side of the counter substrate facing the display substrate; wherein the plasma layer contains charged particles of at least two colors.

[0042] In a fourth aspect, an embodiment of the present invention provides a method for manufacturing a display device, comprising:

[0043] Providing the display substrate as described in the first aspect;

[0044] Filling a plasma layer in the grid structure of the display substrate;

[0045] Filling charged particles of at least two colors in a grid structure having a plasma layer;

[0046] An opposite substrate opposite to the display substrate is formed on the grid structure filled with single-color charged particles, and a common electrode is provided on a side of the opposite substrate close to the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a structural schematic diagram of an electronic paper product in the related art;

[0048] Figure 2 A schematic diagram of the structure of a partial area of ​​a display substrate provided by an embodiment of the present invention;

[0049] Figure 3 The embodiment of the present invention provides Figure 2 , showing a cross-sectional view of the substrate in the AA' direction;

[0050] Figure 4 A top view of a portion of a grid structure in a display substrate provided by an embodiment of the present invention;

[0051] Figure 5 The second barrier strip provided in the embodiment of the present invention is Figure 2 Cross-sectional view along the BB' direction;

[0052] Figure 6 The embodiment of the present invention provides Figure 3 A display principle diagram of a display device formed by a display substrate;

[0053] Figure 7 A top view of a sub-pixel region in a display substrate provided by an embodiment of the present invention;

[0054] Figure 8 The embodiment of the present invention provides Figure 7 Cross-section along CC' direction;

[0055] Fig. 9 A top view of a portion of sub-pixel regions in another display substrate provided by an embodiment of the present invention;

[0056] Fig.10 The embodiment of the present invention provides Fig. 9 Cross-section along the DD' direction;

[0057] Fig.11 A top view of a part of a sub-pixel region of another display substrate provided by an embodiment of the present invention;

[0058] Fig.12 The embodiment of the present invention provides Fig.11 Cross-sectional view along the F1F1' direction;

[0059] Fig.13 A schematic diagram of a second block electrode connected to a common electrode line provided by an embodiment of the present invention;

[0060] Fig.14 A top view of a part of a sub-pixel region of another display substrate provided by an embodiment of the present invention;

[0061] Fig.15 The embodiment of the present invention provides Fig.14 Cross-sectional view along the F2F2' direction;

[0062] Fig.16 The embodiment of the present invention provides Fig.14 Cross-sectional view along the F3F3' direction;

[0063] Fig.17 A schematic diagram of another embodiment of the present invention providing a connection between a second block electrode and a common electrode line;

[0064] Fig.18 A manufacturing flow chart of a display substrate provided by an embodiment of the present invention;

[0065] Fig.19 A schematic diagram of manufacturing a display substrate provided by an embodiment of the present invention;

[0066] Fig. 20 A schematic diagram of the structure of a display device provided by an embodiment of the present invention;

[0067] Fig.21 A manufacturing flow chart of a display device provided by an embodiment of the present invention;

[0068] Fig. 22 A schematic diagram of manufacturing a display device provided by an embodiment of the present invention.

[0069] Reference numerals:

[0070] First direction X, second direction Y, sub-pixel area ara;

[0071] Base substrate 1, gate line 2, data line 3, sub-pixel electrode 4, driving transistor 5, grid structure 6, first barrier rib 61, second barrier rib 62, inorganic insulating layer 7, organic insulating layer 8, first block electrode 9, second block electrode 10, common electrode line 11, third block electrode 12. DETAILED DESCRIPTION

[0072] Embodiments of the present invention provide a display substrate, a display device and a manufacturing method to solve the above problems.

[0073] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the present invention will be further described below with reference to the accompanying drawings and examples. However, the exemplary embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concepts of the exemplary embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. The words expressing position and direction described in the present invention are all explained using the accompanying drawings as examples, but changes can be made as needed, and the changes made are all included in the scope of protection of the present invention. The drawings of the present invention are only used to illustrate the relative position relationship and do not represent the true proportions.

[0074] It should be noted that specific details are described in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The subsequent description of the specification is a preferred embodiment of the present application, but the description is for the purpose of illustrating the general principles of the present application and is not intended to limit the scope of the present application. The scope of protection of the present application shall be determined by the definition of the attached claims.

[0075] See also Figure 1Schematic diagram of the structure of an electronic paper product in the related art. The electronic paper product includes an array substrate 100 and an opposing substrate 200 arranged opposite to the array substrate 100. A microcapsule layer 300 is arranged between the array substrate 100 and the opposing substrate 200. The microcapsule layer 300 includes a plurality of microcapsules 301. Each microcapsule 301 is filled with a transparent electrophoretic liquid a, white charged particles b, and black charged particles c. Usually, the charged particles of these two colors have opposite electrical properties. Each microcapsule 301 in the microcapsule layer 300 corresponds to a pixel. A pixel electrode 400 corresponding to each pixel is arranged on the surface of one side of the array substrate 100 close to the microcapsule layer 300. The driving transistor ( Figure 1 The counter substrate 200 is electrically connected to the pixel electrode 400 one by one (not shown in the figure), and a bonding glue 500 is further provided on the side of the pixel electrode 400 close to the microcapsule layer 300. The bonding glue 500 is used to fix the microcapsule 301. A common electrode layer 600 is provided on the surface of the counter substrate 200 close to the microcapsule layer 300. A protective film 700 is provided on the surface of the counter substrate 200 away from the microcapsule layer 300 for protecting the target substrate 300. The counter substrate 300 can be a polyethylene terephthalate (PET) film.

[0076] In the related art, there are high technical barriers to manufacturing the above-mentioned microcapsules 301 and realizing commercialization.

[0077] See also Figure 2 and Figure 3 , Figure 2 A schematic diagram of a structure of a partial area of ​​a display substrate provided by an embodiment of the present invention, Figure 3 The embodiment of the present invention provides Figure 2 The cross-sectional view of the display substrate in the AA' direction is shown in FIG. 1 . The present invention further provides a display substrate, the preparation method and process of which are simpler and have excellent display effects. The display substrate of this case includes:

[0078] Base substrate 1;

[0079] A plurality of gate lines 2 are located on the base substrate 1 and extend along a first direction X and are arranged along a second direction Y;

[0080] A plurality of data lines 3 are located on the base substrate 1 and extend along a second direction Y and are arranged along a first direction X, wherein the second direction Y intersects the first direction X; the gate lines 2 and the data lines 3 define a plurality of sub-pixel areas ara;

[0081] Since the gate line 2 and the data line 3 usually have a certain width in the display substrate, the sub-pixel region ara defined by the gate line 2 and the data line 3 can be a pattern defined by the center line of the gate line 2 (extending along the first direction X) and the center line of the data line 3 (extending along the second direction Y) (such as Figure 2 Figure surrounded by white dotted lines).

[0082] A plurality of sub-pixel electrodes 4 are located in a plurality of sub-pixel areas ara on the base substrate 1;

[0083] A plurality of driving transistors 5 are located on the substrate 1 and are electrically connected to each data line 3, each gate line 2 and each sub-pixel electrode 4; optionally, the driving transistor 5 is a transistor with a dual-gate structure, i.e., it is composed of two parallel transistors. By using the driving transistor 5 with a dual-gate structure, the driving capability of the driving transistor 5 can be improved, or optionally, the driving transistor 5 can also be a transistor with a single-gate structure, which is not limited here. Figure 2 and Figure 3 The driving transistor 5 shown in the figure is a bottom-gate transistor. In practical applications, the driving transistor 5 may also be a top-gate transistor.

[0084] It should be noted that Figure 3 The structure of a portion of the film layer that is in the same layer as the driving transistor 5 and located on the right side of the driving transistor 5 (the blank area between the base substrate 1 and the sub-pixel electrode 4) is not shown, and it should not be understood that this portion of the film layer is one film layer.

[0085] The grid structure 6 is located on the side of the layer where the sub-pixel electrode 4 is located away from the base substrate 1. The grid structure 6 has an opening area for accommodating charged particles in each sub-pixel area ara. The orthographic projection of the grid structure 6 on the base substrate 1 at least partially covers the orthographic projection of the gate line 2 and the data line 3 on the base substrate 1. The ratio of the area of ​​the sub-pixel electrode 4 to the area of ​​the sub-pixel area ara is greater than 70%. The grid structure 6 can cover part of the sub-pixel electrode 4 or have no overlap with the sub-pixel electrode 4.

[0086] like Figure 2 As shown, an opening area in the grid structure 6 corresponds to a sub-pixel electrode 4, and the area of ​​the opening area of ​​the grid structure 6 is smaller than the area of ​​the sub-pixel electrode 4. The area of ​​the sub-pixel electrode 4 is the orthographic projection area of ​​the sub-pixel electrode 4 in the corresponding sub-pixel area ara on the base substrate 1. The ratio of the area of ​​the sub-pixel electrode 4 to the area of ​​the sub-pixel area ara can be set to 75%, 80%, 85%, 88%, 90%, etc., and the size of the sub-pixel electrode 4 can be adjusted according to the set ratio.

[0087] In the embodiment provided by the present invention, a grid structure 6 is provided on a side of the layer where the sub-pixel electrode 4 is located away from the base substrate 1, and the orthographic projection of the grid structure 6 on the base substrate 1 at least partially covers the orthographic projection of the gate line 2 and the data line 3 on the base substrate 1, so that the opening area of ​​the grid structure 6 for accommodating charged particles corresponds to each sub-pixel area ara, so that the opening area of ​​the above-mentioned grid structure 6 can be used to replace the microcapsule or microcup for accommodating charged particles in the related art, and the overall expansion of the electronic paper market is no longer limited by factors such as the shipment volume and price of a single manufacturer. Moreover, since the grid structure 6 at least partially covers the gate line 2 and the data line 3, the opening area of ​​the grid structure 6 matches the size of the sub-pixel area ara, and compared with the solution using microcapsule / microcup paper film in the related art, it has the advantages of higher resolution, contrast, and lower driving voltage. Optionally, the grid structure 6 completely covers the gate line 2 and the data line 3. Optionally, the grid structure 6 completely covers the gate line 2 and the data line 3 and exceeds the gate line and the data line part, which is not limited here. At the same time, by setting the ratio of the area of ​​the sub-pixel electrode 4 to the area of ​​the sub-pixel area ara to be greater than 70%, after the plasma is filled in the opening area of ​​the grid structure 6 later, the plasma in each area of ​​the opening area of ​​the grid structure 6 can be fully driven, so that the charged particles filled in the opening area of ​​the grid structure 6 can be evenly driven.

[0088] See also Figure 4 A top view of a portion of a grid structure in a display substrate provided in an embodiment of the present invention. The grid structure 6 includes:

[0089] A first barrier rib 61 extending along the first direction X and arranged along the second direction Y, and a second barrier rib 62 extending along the second direction Y and arranged along the first direction X; the first barrier rib 61 and the second barrier rib 62 are arranged in the same layer, and two adjacent columns or two adjacent rows of sub-pixel areas ara share the same first barrier rib 61 or second barrier rib 62.

[0090] The orthographic projection of the first barrier strip 61 on the base substrate 1 at least partially covers the gate line 2, and the orthographic projection of the second barrier strip 62 on the base substrate 1 at least partially covers the data line 3 and has an overlapping area with the sub-pixel electrode 4. The orthographic projection of the first barrier strip 61 on the base substrate 1 may also fully cover the gate line 2, and the orthographic projection of the second barrier strip 62 on the base substrate 1 may also fully cover the data line 3.

[0091] See also Figure 5 The second barrier strip provided in the embodiment of the present invention is Figure 2 Cross-sectional view along the BB' direction.

[0092] The cross-sectional shape of the first blocking bar 61 along the second direction Y and the cross-sectional shape of the second blocking bar 62 along the first direction X are both trapezoidal, and optionally, they can be isosceles trapezoidal in this case, which is not limited here. The cross-sectional shape of the first blocking bar 61 along the second direction Y and the cross-sectional shape of the second blocking bar 62 along the first direction X are the same in size, and optionally, they can be isosceles trapezoidal, such as Figure 5 As shown. The length of the top side of the isosceles trapezoid is w1, the value range of w1 is 6 to 16um, the length of the bottom side is w2, the value range of w2 is 11 to 21um, and the height is h, the value range of h is 4 to 10um. For example, the length of the top side of the isosceles trapezoid can be set to 11um, the length of the bottom side of the isosceles trapezoid can be set to 16um, and the height of the isosceles trapezoid can be set to 5um.

[0093] The ratio range of the top side to the bottom side of the isosceles trapezoid can be set to 0.5 to 0.8. After determining the length of the top side or the length of the bottom side of the isosceles trapezoid, the length of the other side can be quickly determined according to this ratio range.

[0094] Please continue to see Figure 5 The gap between two adjacent sub-pixel electrodes 4 is w3, w3≤10um. By setting the gap between two adjacent sub-pixel electrodes 4 to be less than or equal to 10um, the area of ​​the sub-pixel electrode 4 can be as large as possible, thereby improving the coverage of the vertical electric field in the sub-pixel area ara.

[0095] It should be understood that the gap between the two adjacent sub-pixel electrodes 4 does not include a gap in which the driving transistor 5 is disposed.

[0096] In the embodiment provided by the present invention, by setting the pattern of the cross section of the first barrier rib 61 along the second direction Y and the pattern of the cross section of the second barrier rib 62 along the first direction X to be a trapezoid, the formed first barrier rib 61 and the second barrier rib 62 can be made more stable, and the size and shape of each opening area in the grid structure 6 can be kept consistent, so as to better match the sub-pixel area ara. The pattern of the cross section of the first barrier rib 61 along the second direction Y and the pattern of the cross section of the second barrier rib 62 along the first direction X are both set to be an isosceles trapezoid, and the ratio range of the top side to the bottom side of the isosceles trapezoid is set to 0.5 to 0.8, and the height is set to 4 to 6 um, so that each opening area of ​​the grid structure 6 can be filled with enough plasma without causing the plasma filled in the adjacent opening areas to crosstalk with each other, thereby effectively improving the display effect of the display device including the above-mentioned display substrate.

[0097] See also Figure 6 The embodiment of the present invention provides Figure 3 A display principle diagram of a display device formed by a display substrate is shown in FIG.

[0098] Figure 6 In the embodiment, a counter substrate 2000 is disposed opposite to the display substrate, and a common electrode 4000 is disposed on a surface of the counter substrate 2000 close to the display substrate. When a voltage is applied to the common electrode 4000 and the sub-pixel electrode 4 to form a vertical electric field, Figure 6 The electric field direction of the vertical electric field shown above is the direction from the display substrate 1000 to the opposing substrate 2000. At this time, the black charged particles (assuming they carry a "+" charge) are moved to the surface of the display device (i.e., the side close to the opposing substrate) under the action of the vertical electric field. The light is reflected by the surface of the display device, and the area covered by the vertical electric field normally reflects black (i.e., the user sees a black picture). In the area not covered by the vertical electric field (the area where the driving transistor 5 is projected onto the opposing substrate), even if it is affected by the edge electric field of the vertical electric field, the black display in this area is impure due to the weak edge electric field, thereby affecting the display effect.

[0099] When the vertical electric field is reversed and the electric field direction of the vertical electric field is changed to the direction from the opposing substrate 2000 to the display substrate 1000, the white charged particles (assuming they carry a "-" charge) move to the surface of the display device under the action of the vertical electric field, and the light is reflected by the surface of the display device. The area covered by the vertical electric field normally reflects white, and the user sees a white picture; while in the area where the driving transistor 5 is projected onto the opposing substrate 2000, the white charged particles have not yet crossed the black charged particles to reach the surface of the display device due to the weak fringe electric field, so that black remains in this area, and the user sees a black afterimage in this area, which affects the display effect.

[0100] In order to improve the display effect, the embodiment of the present invention provides the following two solutions to increase the area of ​​the sub-pixel electrode 4, so that the ratio of the area of ​​the sub-pixel electrode 4 to the area of ​​the sub-pixel region ara is greater than 88%, so that the charged particles in each grid structure can be fully driven regardless of where they are located:

[0101] Optionally, in the display substrate provided by the embodiment of the present invention, the sub-pixel electrode 4 covers the driving transistor 5, and optionally at least partially covers the driving transistor 5, for example, covers a partial area greater than 50% of the driving transistor 5, or may fully cover the area of ​​the driving transistor 5, which is not limited here.

[0102] See also Figure 7 and Figure 8 , Figure 7 A top view of a sub-pixel region in a display substrate provided by an embodiment of the present invention, Figure 8 The embodiment of the present invention provides Figure 7 The display substrate also includes:

[0103] An inorganic insulating layer 7 located between the layer where the driving transistor 5 is located and the layer where the sub-pixel electrode 4 is located;

[0104] The orthographic projection of the sub-pixel electrode 4 on the base substrate 1 covers the orthographic projection of the driving transistor 5 . An organic insulating layer 8 is provided between the inorganic insulating layer 7 and the layer where the sub-pixel electrode 4 is located. The thickness of the organic insulating layer 8 is greater than that of the inorganic insulating layer 7 .

[0105] The inorganic insulating layer 7 may be made of silicon nitride, and the organic insulating layer 8 and the grid structure 6 may be made of the same material, such as resin. The thickness of the organic insulating layer 8 may be more than 2.5 times the thickness of the inorganic insulating layer 7. For example, the thickness of the organic insulating layer 8 may be in the range of The thickness of the inorganic insulating layer 7 can range from

[0106] In the embodiment provided by the present invention, by adding an organic insulating layer 8 with a thickness greater than that of the inorganic insulating layer 7 between the inorganic insulating layer 7 and the layer where the sub-pixel electrode 4 is located, the organic insulating layer 8 and the inorganic insulating layer 7 can be used to isolate the sub-pixel electrode 4 covering the driving transistor 5 from the source, drain and active layer in the driving transistor 5, thereby avoiding the situation where the sub-pixel electrode 4 covers the driving transistor 5 when the organic insulating layer 8 with the above thickness is not added, causing the sub-pixel electrode 4, the inorganic insulating layer 7, the source, drain and active layer in the driving transistor 5 to form a top gate structure, thereby causing the characteristics of the driving transistor 5 to shift, thereby achieving an increase in the area of ​​the sub-pixel electrode 4 (i.e., increasing the ratio of the area of ​​the sub-pixel electrode 4 to the area of ​​the sub-pixel area ara) while maintaining the characteristics of the driving transistor 5 stable.

[0107] In addition, the organic insulating layer 8 may not be provided, and the thickness of the inorganic insulating layer 7 may be increased to Figure 8 The total thickness of the inorganic insulating layer 7 and the organic insulating layer 8 can also prevent the sub-pixel electrode 4 from covering the driving transistor 5, causing the sub-pixel electrode 4, the inorganic insulating layer 7, the source and drain electrodes in the driving transistor 5 and the active layer to form a top gate structure, thereby causing the characteristics of the driving transistor 5 to shift.

[0108] Please refer to Table 1, which shows the on / off current when the driving transistor 5 is set in the opening area and covered and not covered by the sub-pixel electrode 4 under the 4Mask process (i.e., the above-mentioned organic insulating layer 8 is not set between the inorganic insulating layer 7 and the sub-pixel electrode 4).

[0109] Table 1

[0110]

[0111] It can be seen from Table 1 that when the sub-pixel electrode 4 is directly covered with the driving transistor 5 based on the relevant technology, the turn-off current of the driving transistor 5 will increase significantly. This is because the aforementioned received sub-pixel electrode 4 and the inorganic insulating layer 7, source and drain, and active layer of the driving transistor 5 form a top gate structure, which is caused by the deviation of the characteristics of the driving transistor 5.

[0112] As shown in Table 2, the turn-on current and turn-off current of the driving transistor 5 are measured by adopting the solution of setting the organic insulating layer 8 in this case (that is, the sub-pixel electrode 4 covers the driving transistor 5, and an organic insulating layer 8 is added between the inorganic insulating layer 7 and the sub-pixel electrode 4).

[0113] Table 2

[0114]

[0115] It can be seen from Table 2 that in the solution with the organic insulating layer 8 , both the on-current and the off-current of the driving transistor 5 are relatively small, and this solution will not form the above-mentioned top gate structure to affect the characteristics of the driving transistor 5 .

[0116] In the solution where the organic insulating layer 8 is provided, the grid structure 6 does not cover the driving transistor 5 .

[0117] In another display substrate provided in the present case, the sub-pixel electrode 4 does not cover the driving transistor 5 , and the gate of the driving transistor 5 reuses the gate line 2 .

[0118] See also Fig. 9 A top view of a portion of sub-pixel regions in another display substrate provided by an embodiment of the present invention, Fig.10 The embodiment of the present invention provides Fig. 9 Cross-sectional view along the DD' direction.

[0119] The driving transistor 5 and the sub-pixel electrode 4 in the display substrate ( Fig. 9 and Fig.10 The orthographic projections of the driving transistor 5 on the substrate 1 do not overlap each other, and the orthographic projection of the driving transistor 5 on the substrate 1 overlaps with the gate line 2 and is located between the two data lines 3;

[0120] The line width of the gate line 2 in the region overlapping the driving transistor 5 is greater than the line width in other regions.

[0121] like Fig.10 Shown Fig. 9 The cross-sectional view along the DD' direction shows a portion of the region where the driving transistor 5 overlaps with the gate line 2. In this overlapping region, the width of the gate line 2 is greater than the width of the remaining region (combined with Fig. 9(see), so that the wider part of the gate line 2 is used as a component of the gate line 2 and as the gate of the driving transistor 5, so that the gate of the driving transistor 5 reuses the gate line 2, thereby reducing the positive projection area of ​​the driving transistor 5 on the base substrate 1, so that the area of ​​the sub-pixel electrode 4 can be increased when it does not cover the driving transistor 5, thereby increasing the ratio of the sub-pixel electrode 4 to the sub-pixel area ara, so that it can be greater than 88%. In addition, since this solution does not need to add an organic insulating layer 8 between the inorganic insulating layer 7 and the sub-pixel electrode 4 as in the solution with an organic insulating layer 8, on the one hand, it can reduce the thickness of the display substrate, and on the other hand, there is no need to add processes related to the organic insulating layer 8 during production, that is, it can be completed using the existing 4-mask process, thereby effectively saving processes, time and cost, and improving production capacity.

[0122] In the scheme of the gate line 2 of the driving transistor 5, the gap between two adjacent sub-pixel electrodes 4 can also be set to be less than or equal to 10um. Compared with the process of using 14um for the gap between adjacent sub-pixel electrodes 4 in the related art, the area of ​​the sub-pixel electrode 4 can be further increased, so that the area ratio of the sub-pixel electrode 4 to the sub-pixel area ara is further improved. In the same display substrate, the gap between the sub-pixel electrodes 4 arranged along the first direction X can be the same as or different from the gap between the sub-pixel electrodes 4 arranged along the second direction Y. For example, when the gate line 2 of the driving transistor 5 is reused, the gap between the sub-pixel electrodes 4 arranged along the second direction Y can be greater than the gap between the sub-pixel electrodes 4 arranged along the first direction X.

[0123] The gap between the adjacent sub-pixel electrodes 4 can be set according to the area ratio of the sub-pixel electrode 4 to the sub-pixel area ara and the precision of the equipment actually used. Of course, under the requirement of meeting the area ratio of the sub-pixel electrode 4 to the sub-pixel area ara, the gap between the adjacent sub-pixel electrodes 4 can be as large as possible, so as to prevent the adjacent sub-pixel electrodes 4 from short-circuiting.

[0124] See also Figure 11-12 , Fig.11 A top view of a part of a sub-pixel region of another display substrate provided by an embodiment of the present invention, Fig.12 The embodiment of the present invention provides Fig.11 The display substrate also includes:

[0125] A first block electrode 9 and a second block electrode 10 are stacked in a plurality of sub-pixel regions ara on a base substrate 1;

[0126] The first block electrode 9, the gate electrode of the driving transistor 5 and the gate line 2 are all located in the gate metal layer, and the second block electrode 10 and the source and drain electrodes of the driving transistor 5 are all located in the source and drain metal layer;

[0127] The source-drain metal layer is located between the gate metal layer and the layer where the sub-pixel electrode 4 is located;

[0128] A first storage capacitor C1 is formed between the sub-pixel electrode 4 and the second block electrode 10 , and a second storage capacitor C2 is formed between the second block electrode 10 and the first block electrode 9 .

[0129] In the opening area of ​​the grid structure 6 , the sub-pixel electrode 4 is electrically connected to the first block electrode 9 through the first via hole H1 , and the sub-pixel electrode 4 is electrically connected to the source of the driving transistor 5 through the second via hole H2 ; the first via hole H1 and the second via hole H2 are arranged adjacent to the gate line 2 .

[0130] Fig.11 Corresponding to the scheme in which the inorganic insulating layer 8 is set, a first block electrode 9 is set in the gate metal layer and a second block electrode 10 is set in the source and drain metal layer, so that a first storage capacitor C1 is formed between the sub-pixel electrode 4 and the second block electrode 10, and a second storage capacitor C2 is formed between the second block electrode 10 and the first block electrode 9, so that the first block electrode 9, the second block electrode 10, and the sub-pixel electrode 4 can be used to form a dual storage capacitor, so that the pixel voltage of the sub-pixel area ara will not lose power quickly, thereby fully driving the plasma and charged particles contained in the opening area of ​​the grid structure 6. Fig.12 yes Fig.11 The cross-sectional view along the F1F1' direction, Fig.11 The two vias in the same column are electrically connected to the same film layer, such as Fig.11 The first via holes H1 in the right column are all electrically connected to the sub-pixel electrode 4 and the first block electrode 9, and the second via holes H2 in the left column are all electrically connected to the sub-pixel electrode 4 and the source of the driving transistor 5. The first block electrode 9 is electrically connected to the sub-pixel electrode 4 through the first via hole to load the pixel voltage, and the second block electrode 10 is electrically connected to the common voltage signal line through the conductive via hole around the display area of ​​the display substrate to load the common voltage, and is electrically connected to the common electrode on the opposite substrate through the conductive metal ball in the frame sealant provided between the display substrate and the opposite substrate in the display device.

[0131] See also Fig.13 A schematic diagram of a second block electrode connected to a common electrode line provided by an embodiment of the present invention. Each second block electrode 10 is electrically connected via a common electrode line 11 extending in the same direction as the data line 3; the orthographic projection of the grid structure 6 on the base substrate 1 at least partially covers the common electrode line 11 or is adjacent to the common electrode line 11.

[0132] The common electrode line 11 and the second block electrode 10 are arranged in the same layer and made of the same material. The second block electrode 10 in the extending direction of the data line 3 is electrically connected through the common electrode line 11 in the same extending direction as the data line 3, and the grid structure 6 at least covers part of the common electrode line 11 or is adjacent to the common electrode line 11. The common electrode line 11 extends along the extending direction of the data line 3 to the non-display area to receive the common signal, such as Fig.13 The non-display area between the lower boundary of the display substrate, a sub-pixel area ara, and the fan-shaped area includes a boundary area A, an electrostatic dissipation area B, a common signal area C, and a fan-shaped area D in sequence. The boundary area A is provided with a boundary line surrounding the display area of ​​the display substrate. Its electric field is different from the electric field in the sub-pixel area ara, and is used to display a frame when the display device including the above-mentioned display substrate displays. An electrostatic line is provided in the electrostatic dissipation area B, and the data line 3 is electrically connected to the electrostatic line through a via. Optionally, an electrostatic release circuit can also be provided, and one end of the electrostatic release circuit is connected to the data line, and the other end is connected to the electrostatic line. The optional electrostatic line can be connected to the common electrode line of the non-display area, which is not limited here. The common signal area C is provided with a common signal line, and each column of the second block electrode 10 is electrically connected to the common signal line through the corresponding common electrode line 11, and then the conductive metal ball ( Fig.13 The common signal line (not shown) is electrically connected to the common electrode on the opposite substrate so that the second block electrode 10 and the common electrode are loaded with the same common voltage.

[0133] See also Figure 14 to Figure 16 , Fig.14 A top view of a part of a sub-pixel region of another display substrate provided by an embodiment of the present invention, Fig.15 The embodiment of the present invention provides Fig.14 The cross-sectional view along the F2F2' direction, Fig.16 The embodiment of the present invention provides Fig.14 Cross-sectional view along the F3F3' direction.

[0134] Fig.14 The corresponding sub-pixel electrode 4 does not cover the driving transistor 5, and the gate of the driving transistor 5 reuses the gate line 2. A first block electrode 9 is set in the gate metal layer, and a second block electrode 10 is set in the source and drain metal layer. In this way, a first storage capacitor C1 is formed between the sub-pixel electrode 4 and the second block electrode 10, and a second storage capacitor C2 is formed between the second block electrode 10 and the first block electrode 9. Therefore, the first block electrode 9, the second block electrode 10, and the sub-pixel electrode 4 can be used to form a dual storage capacitor, so that the pixel voltage of the sub-pixel area ara will not lose power quickly, thereby fully driving the plasma and charged particles contained in the opening area of ​​the grid structure 6. Fig.15 , Fig.16 They are Fig.14In the cross-sectional view in the directions of F2F2' and F3F3', the first block electrode 9 is electrically connected to the sub-pixel electrode 4 through the first via hole to load the pixel voltage, and the second block electrode 10 is electrically connected to the common voltage signal line through the conductive via hole around the display area of ​​the display substrate to load the common voltage, and is electrically connected to the common electrode on the opposite substrate through the conductive metal ball in the frame sealant arranged between the display substrate and the opposite substrate in the display device.

[0135] See also Fig.17 A schematic diagram of another second block electrode and common electrode line connection provided by an embodiment of the present invention. Each second block electrode 10 is electrically connected via a common electrode line 11 extending in the same direction as the data line 3; the orthographic projection of the grid structure 6 on the base substrate 1 at least partially covers the common electrode line 11 or is adjacent to the common electrode line 11.

[0136] The common electrode line 11 and the second block electrode 10 are arranged in the same layer and made of the same material. The second block electrode 10 in the extending direction of the data line 3 is electrically connected through the common electrode line 11 in the same extending direction as the data line 3, and the grid structure 6 at least covers part of the common electrode line 11 or is adjacent to the common electrode line 11. The common electrode line 11 extends along the extending direction of the data line 3 to the non-display area to receive the common signal, such as Fig.17 The non-display area between the lower boundary of the display substrate, a sub-pixel area ara, and the fan-shaped area includes a boundary area A, an electrostatic dissipation area B, a common signal area C, and a fan-shaped area D in sequence. The boundary area A is provided with a boundary line surrounding the display area of ​​the display substrate, and its electric field is different from the electric field in the sub-pixel area ara, which is used to display a frame when the display device including the above-mentioned display substrate displays. An electrostatic line is provided in the electrostatic dissipation area B, and the data line 3 is electrically connected to the electrostatic line through a via hole. Optionally, an electrostatic release circuit can also be provided, and one end of the electrostatic release circuit is connected to the data line, and the other end is connected to the electrostatic line. The optional electrostatic line can be connected to the common electrode line of the non-display area, which is not limited here. The common signal area C is provided with a common signal line, and each column of the second block electrode 10 is electrically connected to the common signal line through the corresponding common electrode line 11, and then the conductive metal ball ( Fig.17 The common signal line (not shown) is electrically connected to the common electrode on the opposite substrate so that the second block electrode 10 and the common electrode are loaded with the same common voltage.

[0137] It is important to understand that due to Fig.14 and Fig.17 The first block electrode 9 and the second block electrode 10 are almost overlapped, so it is difficult to distinguish the two. Fig.15 or Fig.16 ,and Fig.11 , Fig.14 , Fig.17 In order to make it easier to see that the first block electrode 9, the second block electrode 10, and the sub-pixel electrode 4 are overlapped, the layers of the second block electrode 10 and the sub-pixel electrode 4 are set to a semi-transparent state, so it should not be understood that the above-mentioned multiple layers are superimposed to form a certain layer.

[0138] Please continue to see Fig.15 and Fig.16 , the display substrate further includes a semiconductor layer between the source-drain metal layer and the gate metal layer;

[0139] The semiconductor layer is adjacent to the source-drain metal layer, and the semiconductor layer includes the active layer of the driving transistor 5 and the third block electrode 12 having the same pattern as the second block electrode 10. Here, the third block electrode 12 and the semiconductor layer of the driving transistor 5 are arranged in the same layer and the same material. During the manufacturing process, the semiconductor layer can be deposited first, and then the source-drain metal layer can be deposited, and finally etching can be performed, so that the semiconductor layer and the source-drain metal layer can share a mask, thereby reducing the mask and achieving the purpose of saving the process.

[0140] Based on the same inventive concept, an embodiment of the present invention provides a method for manufacturing a display substrate, see Fig.18 , the preparation method comprises:

[0141] Step S11: providing a substrate;

[0142] Step S12: forming a plurality of gate lines extending along the first direction and arranged along the second direction, and forming a plurality of data lines extending along the second direction and arranged along the first direction on a surface of one side of the substrate; the second direction intersects with the first direction, and the gate lines and the data lines define a plurality of sub-pixel areas;

[0143] Step S13: forming a driving transistor while forming the gate line and the data line;

[0144] Step S14: after forming the driving transistor, an inorganic insulating layer and a sub-pixel electrode are sequentially formed; the ratio of the area of ​​the sub-pixel electrode to the area of ​​the sub-pixel region is greater than 70%;

[0145] Step S15: forming a grid structure surrounding each sub-pixel region, wherein the grid structure has an opening area for accommodating charged particles in each sub-pixel region, and the orthographic projection of the grid structure on the base substrate at least partially covers the orthographic projection of the gate line and the data line on the base substrate.

[0146] See also Fig.19 A schematic diagram of manufacturing a display substrate provided by an embodiment of the present invention, Fig.19 Is produced Fig.14 Taking the display substrate of as an example, the specific production process is as follows:

[0147] Step S21: forming gate lines and first block electrodes.

[0148] A gate metal layer is deposited on the base substrate 1, and the gate metal layer is etched to form a gate line 2 and a first block electrode 9. For a display substrate in which the sub-pixel electrode 4 does not cover the driving transistor 5 and the gate of the driving transistor 5 reuses the gate line 2, when forming the gate line 2, for the portion reused as the gate of the driving transistor 5, the corresponding portion of the gate line 2 needs to have its width increased during patterning, that is, in the area where the gate line 2 overlaps with the driving transistor 5, the width of the formed gate line 2 is greater than that of other areas.

[0149] Step S22: forming a driving transistor, a data line, and a second block electrode.

[0150] A gate insulating layer, a semiconductor layer and a source-drain metal layer are sequentially deposited on the etched gate metal layer; thereafter, the source-drain metal layer and the semiconductor layer are further etched to form a data line 3 and an active layer and a source-drain electrode of a driving transistor 5, as well as a second block electrode 10 and a third block electrode 12. Thus, a data line 3, a driving transistor 5, a second block electrode 10 and a third block electrode 12 are formed.

[0151] Step S23: forming a sub-pixel electrode.

[0152] An inorganic insulating layer and a sub-pixel electrode layer are deposited on the etched source-drain metal layer, and the sub-pixel electrode layer is etched to form each sub-pixel electrode 4 .

[0153] Step S24: forming a grid structure.

[0154] A resin layer is deposited on the etched sub-pixel electrode layer, and the resin layer is etched to form a grid structure 6 .

[0155] If a display substrate with an organic insulating layer 8 is produced, there is no need to widen part of the gate lines during the process of forming the gate lines in the above step S1, and after depositing the inorganic insulating layer in step S3, it is necessary to first deposit a thicker organic insulating layer (such as resin) and then deposit the sub-pixel electrode layer.

[0156] Based on the same inventive concept, an embodiment of the present invention provides a display device, see Fig. 20 , the display device comprises:

[0157] The display substrate 1000 as described above, the counter substrate 2000 arranged opposite to the display substrate 1000, the plasma layer 3000 filled in each opening area of ​​the grid structure, and the common electrode layer 4000 located on the side of the counter substrate 2000 facing the display substrate 1000; wherein the plasma layer 3000 contains charged particles M of at least two colors.

[0158] The polarities of the charges carried by the two colors of charged particles M are opposite. For example, one of the charged particles M is a white particle with a negative charge, and the other charged particle M is a black particle with a positive charge.

[0159] Based on the same inventive concept, an embodiment of the present invention provides a method for manufacturing a display device, see Fig.21 , the preparation method comprises:

[0160] Step S31: providing the display substrate as above;

[0161] Step S32: filling a plasma layer in the grid structure of the display substrate;

[0162] Step S33: filling charged particles of at least two colors in the grid structure having the plasma layer;

[0163] Step S34: forming an opposite substrate opposite to the display substrate on the grid structure filled with single-color charged particles, wherein a side of the opposite substrate close to the display substrate has a common electrode.

[0164] See also Fig. 22 A schematic diagram of manufacturing a display device provided by an embodiment of the present invention.

[0165] A plasma layer and charged particles of at least two colors are filled in the display substrate with a grid structure provided by the present invention, and then an opposing substrate with a common electrode is arranged opposite to the display substrate, so that a display device can be formed.

[0166] The display device may be an electronic paper product, such as an electronic ink screen, an electronic sign, an electronic price tag, an electronic work badge, etc.

[0167] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0168] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A display substrate, characterized in that: include: substrate substrate; A plurality of gate lines are located on the substrate and extend along a first direction and are arranged along a second direction; A plurality of data lines are located on the substrate and extend along the second direction and are arranged along the first direction, wherein the second direction intersects the first direction; the gate lines and the data lines define a plurality of sub-pixel areas; A plurality of sub-pixel electrodes are located in a plurality of the sub-pixel regions on the substrate; A plurality of driving transistors are located on the base substrate and are electrically connected to each of the data lines, each of the gate lines and each of the sub-pixel electrodes; the orthographic projections of the driving transistor and the sub-pixel electrode on the base substrate do not overlap each other, the orthographic projection of the driving transistor on the base substrate overlaps with the gate line and is located between two of the data lines; the line width of the gate line in the area overlapping with the driving transistor is greater than the line width in other areas; A grid structure is located on a side of the layer where the sub-pixel electrode is located away from the base substrate. The grid structure has an opening area for accommodating charged particles in each sub-pixel area. The orthographic projection of the grid structure on the base substrate at least partially covers the orthographic projection of the gate line and the data line on the base substrate. The ratio of the area of ​​the sub-pixel electrode to the area of ​​the sub-pixel area is greater than 88%.

2. The display substrate according to claim 1, wherein: The grid structure comprises: first barrier bars extending along the first direction and arranged along the second direction, and second barrier bars extending along the second direction and arranged along the first direction; The orthographic projection of the first barrier bar on the base substrate at least partially covers the gate line, and the orthographic projection of the second barrier bar on the base substrate at least partially covers the data line and has an overlapping area with the sub-pixel electrode.

3. The display substrate according to claim 2, wherein: A cross-sectional shape of the first barrier strip along the second direction and a cross-sectional shape of the second barrier strip along the first direction are both trapezoidal.

4. The display substrate according to claim 3, wherein: The ratio of the top side to the bottom side of the trapezoid is in the range of 0.5 to 0.

8.

5. The display substrate according to claim 1, wherein: Also includes: A first block electrode and a second block electrode stacked in a plurality of the sub-pixel regions on the base substrate; The first block electrode, the gate of the driving transistor and the gate line are all located in the gate metal layer, and the second block electrode and the source and drain of the driving transistor are all located in the source and drain metal layer; The source-drain metal layer is located between the gate metal layer and the layer where the sub-pixel electrode is located; A first storage capacitor is formed between the sub-pixel electrode and the second block electrode, and a second storage capacitor is formed between the second block electrode and the first block electrode.

6. The display substrate according to claim 5, wherein: In the opening area of ​​the grid structure, the sub-pixel electrode is electrically connected to the first block electrode through a first via hole, and the sub-pixel electrode is electrically connected to the source electrode of the driving transistor through a second via hole.

7. The display substrate according to claim 5, wherein: Each of the second block electrodes is electrically connected via a common electrode line that is consistent with the extending direction of the data line; The orthographic projection of the grid structure on the base substrate at least partially covers the common electrode line or is adjacent to the common electrode line.

8. The display substrate according to claim 5, wherein: Also includes: A semiconductor layer between the source-drain metal layer and the gate metal layer; The semiconductor layer is adjacent to the source-drain metal layer, and the semiconductor layer includes an active layer of the driving transistor and a third block electrode having a pattern consistent with the second block electrode.

9. A method for manufacturing a display substrate, characterized in that: include: Providing a substrate; A plurality of gate lines extending along a first direction and arranged along a second direction, and a plurality of data lines extending along the second direction and arranged along the first direction are sequentially formed on a surface of one side of the base substrate; the second direction intersects with the first direction, and the gate lines and the data lines define a plurality of sub-pixel areas; While forming the gate line and the data line, forming a driving transistor; After forming the driving transistor, an inorganic insulating layer and a sub-pixel electrode are sequentially formed; the orthographic projections of the driving transistor and the sub-pixel electrode on the substrate do not overlap each other, the orthographic projection of the driving transistor on the substrate overlaps with the gate line and is located between the two data lines; the line width of the gate line in the area overlapping with the driving transistor is greater than the line width of other areas; the ratio of the area of ​​the sub-pixel electrode to the area of ​​the sub-pixel region is greater than 88%; A grid structure is formed around each of the sub-pixel regions, wherein the grid structure has an opening area for accommodating charged particles in each of the sub-pixel regions, and the orthographic projection of the grid structure on the base substrate at least partially covers the orthographic projection of the gate line and the data line on the base substrate.

10. A display device, characterized in that: include: A display substrate as described in any one of claims 1 to 8, an opposing substrate arranged opposite to the display substrate, a plasma layer filled in each opening area of ​​the grid structure, and a common electrode layer located on the side of the opposing substrate facing the display substrate; wherein the plasma layer has charged particles of at least two colors.

11. A method for manufacturing a display device, characterized in that: include: Providing a display substrate as described in any one of claims 1 to 8; Filling a plasma layer in the grid structure of the display substrate; Filling charged particles of at least two colors in a grid structure having a plasma layer; An opposite substrate opposite to the display substrate is formed on the grid structure filled with single-color charged particles, and a common electrode is provided on a side of the opposite substrate close to the display substrate.

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