Detection circuit and detection method

Abstract

The present invention application discloses a detection circuit and a detection method. The detection circuit is applicable to a system on a chip, the system on a chip is coupled to the alarm pin of the fourth generation double data rate (DDR4) memory through a connection pad, and the detection circuit includes a control circuit coupled to the connection pad. When the DDR4 memory is refreshed or a specific event occurs, the control circuit outputs a test signal with a first voltage level to the connection pad, and determines whether the voltage level on the connection pad is bound to a second voltage level. When it is determined that the voltage level on the connection pad is bound to the second voltage level, the control circuit outputs an interrupt signal to the central processor of the system on a chip, and the interrupt signal indicates that the alarm pin of the DDR4 memory is not normally controlled by the DDR4 memory.

Description

Technical Field

[0001] The present invention application relates to a detection circuit and a detection method, and particularly to a circuit and a method capable of actively detecting whether the ALERT_n pin of a Double-Data-Rate Fourth Generation (DDR4) memory is normally controlled by the DDR4 memory. Background Art

[0002] When a Cyclic Redundancy Check (CRC) error or a Command / Address / Parity error occurs, the DDR4 memory will pull the voltage level of an alert pin, that is, the ALERT_n pin, from High to Low to notify the host that an error has occurred. In other words, the ALERT_n pin can be used to confirm whether commands and data are correctly written into the DDR4 memory. However, when the ALERT_n pin is inadvertently or maliciously, for example, forced to conduct to the operating voltage VDD by a hacker, the DDR4 memory will not be able to pull down the voltage level of the ALERT_n pin. At this time, the error detection function of the DDR4 memory fails, and the data content in the DDR4 memory may be deleted or modified. Therefore, how to provide a circuit and a method capable of actively detecting whether the ALERT_n pin is normally controlled by the DDR4 memory has become an important issue in this field. Summary of the Invention

[0003] In view of this, an embodiment of the present invention provides a detection circuit, which is applicable to a System-on-a-Chip (SoC). The system single chip is coupled to the alert pin of the DDR4 memory through a pad, and the detection circuit includes a control circuit coupled to the pad. When the DDR4 memory performs a Refresh program or a specific event occurs, the control circuit outputs a test signal with a first voltage level to the pad and determines whether the voltage level on the pad is tied to a second voltage level. When it is determined that the voltage level on the pad is tied to the second voltage level, the control circuit outputs an interrupt signal to the central processing unit of the system single chip, and the interrupt signal indicates that the alert pin of the DDR4 memory is not normally controlled by the DDR4 memory.

[0004] In addition, an embodiment of the present invention provides a detection method applicable to a system-on-chip. The system-on-chip is coupled to an alert pin of a DDR4 memory through a connection pad, and the detection method includes the following steps. When a refresh program is performed on the DDR4 memory or a specific event occurs, a test signal having a first voltage level is output to the connection pad by using a control circuit, and it is determined whether the voltage level on the connection pad is bound to a second voltage level. When it is determined that the voltage level on the connection pad is bound to the second voltage level, an interrupt signal is output to the central processing unit of the system-on-chip by using the control circuit, and the interrupt signal indicates that the alert pin of the DDR4 memory is not normally controlled by the DDR4 memory.

[0005] To enable a further understanding of the features and technical content of the present invention, please refer to the following detailed description of the present invention and the accompanying drawings. However, the accompanying drawings are only provided for reference and illustration, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of a detection circuit provided by an embodiment of the present invention.

[0007] Figure 2 is Figure 1 a schematic circuit diagram of the detection circuit.

[0008] Figure 3 is a flowchart of steps of a detection method provided by an embodiment of the present invention.

[0009] SYMBOL DESCRIPTION

[0010] 1: System-on-chip

[0011] 10: Detection circuit

[0012] 102: Control circuit

[0013] 104: Shielding circuit

[0014] TS: Test signal

[0015] 12: Connection pad

[0016] 122, 124: Input / output unit

[0017] 14: Memory controller

[0018] 16: Central processing unit

[0019] 2: DDR4 memory

[0020] 22: Alert_n pin

[0021] VDD: Operating voltage

[0022] OES: Output enable signal

[0023] 1022, 1024, 1042: D-type flip-flops

[0024] 1026: Exclusive-OR gate

[0025] 1044: Data multiplexer

[0026] IS: Interrupt signal

[0027] S310 - S360: Process steps Detailed implementation manners

[0028] The following are specific embodiments to illustrate the implementation manners of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content provided in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not drawn according to actual sizes. The following embodiments will further detail the related technical content of the present invention, but the content provided is not used to limit the protection scope of the present invention.

[0029] It should be understood that although terms such as "first", "second", "third", etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another, or one signal from another. In addition, the term "or" used herein should, depending on the actual situation, possibly include any one or a combination of more of the associated listed items.

[0030] Please refer to Figure 1 , Figure 1 which is a block diagram of the detection circuit provided by the embodiment of the present invention. As Figure 1 shown, when a hacker conducts the Alert_n pin 22 (i.e., the alarm pin) of the DDR4 memory 2 from an external circuit to the operating voltage VDD, the hacker can forge commands or addresses in an attempt to modify or damage the protected area (ProtectionRegion) of a specific address in the DDR4 memory 2, and at this time, the Alert_n pin 22 has lost the function of notifying the occurrence of an abnormality because it can no longer be pulled down in voltage level by the DDR4 memory 2.

[0031] Therefore, considering the above situation, it is desired that, without the need for additional modifications or hardware addition from an external circuit and without violating the DDR transmission protocol, in this embodiment, an internal circuit is required to actively detect whether the ALERT_n pin 22 is normally controlled by the DDR4 memory 2. Therefore, the detection circuit 10 is applicable to the system-on-chip 1, and the system-on-chip 1 is coupled to the ALERT_n pin 22 of the DDR4 memory 2 through the connection pad 12.

[0032] In this embodiment, the DDR4 memory 2 can be a DDR4 dynamic random access memory (DRAM), but the present invention is not limited thereto, and the present invention does not limit the specific implementation manner of the system-on-chip 1. In summary, the system-on-chip 1 may further have a memory controller 14 and a central processing unit 16, and the detection circuit 10 is coupled to the connection pad 12, the memory controller 14, and the central processing unit 16.

[0033] The detection circuit 10 includes a control circuit 102 and a shielding circuit 104. The control circuit 102 is coupled to the connection pad 12. When the DDR4 memory 2 performs a refresh program or a specific event occurs, a test signal TS with a first voltage level is output to the connection pad 12, and it is determined whether the voltage level on the connection pad 12 is bound to a second voltage level. In this embodiment, the first voltage level and the second voltage level are a low voltage level and a high voltage level respectively. However, in other embodiments, considering that the ALERT_n pin 22 is inadvertently or maliciously forced to be connected to the ground voltage, the first voltage level and the second voltage level can be changed to a high voltage level and a low voltage level respectively. In summary, the first voltage level and the second voltage level are opposite voltage levels, and in the following text, parentheses will be used to label L or H to indicate that it is a low voltage level or a high voltage level.

[0034] It should be noted that when the control circuit 102 outputs the test signal TS with the first voltage level (L) to the connection pad 12, if the Alert_n pin 22 is not forced to be connected to the operating voltage VDD from an external circuit, the test signal TS will be fed back to the internal circuit through the connection pad 12, so that the central processing unit 16 will misjudge this as a notification of a CRC error or a command / address / parity check error sent by the DDR4 memory 2 because it receives the test signal TS with the first voltage level (L). Therefore, the shielding circuit 104 is coupled to the connection pad 12, and during the period when the control circuit 102 outputs the test signal TS to the connection pad 12, the test signal TS fed back through the connection pad 12 is shielded, so that the central processing unit 16 will not be able to receive the test signal TS.

[0035] In this embodiment, when it is determined that the voltage level on the connection pad 12 is bound to the second voltage level (H), it means that the connection pad 12 and the Alert_n pin 22 may be forced by an external circuit to be connected to the operating voltage VDD. Therefore, the control circuit 102 outputs an interrupt signal IS( Figure 1 not shown yet, but please refer to Figure 2 ) to notify the central processing unit 16 that the Alert_n pin 22 is not normally controlled by the DDR4 memory 2. That is, the control circuit 102 outputs the interrupt signal IS to the central processing unit 16, and the interrupt signal IS indicates that the Alert_n pin 22 is not normally controlled by the DDR4 memory 2.

[0036] Specifically, the DDR4 memory 2 performs a refresh procedure according to a refresh command issued by the host( Figure 1 not shown). In addition, a specific event may be a situation where the DDR4 memory 2 has not been initialized or is in an idle state, but the present invention is not limited thereto. Although no refresh command is issued by the host when the above situation occurs, since no read / write operation is performed on the DDR4 memory 2 at this time, the control circuit 102 can also output a test signal TS with a first voltage level (L) to the connection pad 12 when a specific event occurs, and determine whether the voltage level on the connection pad 12 is bound to the second voltage level (H).

[0037] In other words, before the control circuit 102 outputs the test signal TS with a first voltage level (L) to the connection pad 12 and determines whether the voltage level on the connection pad 12 is bound to the second voltage level (H), the detection circuit 10 will wait for the host to issue a refresh command or a specific event to occur. In addition, although the connection pad 12 belongs to a bidirectional transmission interface, under normal operation, the connection pad 12 is only used to receive the Alert_n signal transmitted by the DDR4 memory 2. Therefore, before the control circuit 102 outputs the test signal TS to the connection pad 12, the control circuit 102 can first generate an Output Enable signal OES to the connection pad 12 to enable the output mode of the connection pad 12.

[0038] For the convenience of the following description, the connection pad 12 in this embodiment will use the input / output (I / O) units 122 and 124 to represent its output mode and input mode. As Figure 1As shown, in addition to an input terminal and an output terminal, the input / output unit 122 further includes an output enable terminal to receive an output enable signal OES generated by the control circuit 102. After the output mode of the connection pad 12 is enabled, the input terminal of the input / output unit 122 receives a test signal TS output by the control circuit 102, and outputs the test signal TS through its output terminal. In addition, the input terminal of the input / output unit 124 is coupled to the output terminal of the input / output unit 122 to feedback the test signal TS to the internal circuit.

[0039] On the contrary, in this embodiment, when it is determined that the voltage level on the connection pad 12 is not bound to the second voltage level (H), it means that the connection pad 12 and the Alert_n pin 22 are not forced to be connected to the operating voltage VDD from the external circuit. Therefore, the control circuit 102 can generate an output disable signal ( Figure 1 not shown) to turn off the output mode of the connection pad 12 to avoid bus conflicts, and the detection circuit 10 will return to the step of waiting for the host to issue a refresh command or a specific event to occur. In summary, under normal operation, the output mode of the connection pad 12 should be turned off so that the input terminal of the input / output unit 124 only receives the Alert_n signal transmitted by the DDR4 memory 2, and inputs the Alert_n signal to the internal circuit through its output terminal.

[0040] It should be understood that the input / output unit 122 is equivalent to a three-state logic buffer, and the output enable signal OES and the output disable signal can be implemented by a single digital signal. For example, a digital signal with a logic level of 1 can be used to represent the output enable signal OES, and a digital signal with a logic level of 0 can be used to represent the output disable signal, but the present invention is not limited thereto. In addition, please refer to Figure 2 , Figure 2 is Figure 1 a schematic circuit diagram of the detection circuit 10 of

[0041] As Figure 2 shown, the control circuit 102 may include D flip-flops 1022, 1024 and an exclusive-OR gate 1026. The D flip-flop 1022 is used to generate the output enable signal OES, the D flip-flop 1024 is used to output a test signal TS with a first voltage level (L), and two input terminals of the exclusive-OR gate 1026 respectively receive the test signal TS output by the D flip-flop 1024 and the test signal TS feedback through the input / output unit 124. In other words, the control circuit 102 can determine whether the voltage level on the connection pad 12 is bound to the second voltage level (H) by checking whether the output test signal TS with the first voltage level (L) is different from the test signal TS feedback through the connection pad 12 (for example, whether they have the same voltage level).

[0042] If the test signal TS with the first voltage level (L) output by the control circuit 102 is different from the test signal TS fed back through the connection pad 12, the control circuit 102 can determine that the voltage level on the connection pad 12 is bound to the second voltage level (H), and output an interrupt signal IS with a high logic level (1) through the exclusive-OR gate 1026 to notify the central processing unit 16 that the Alert_n pin 22 is not normally controlled by the DDR4 memory 2. In contrast, if the test signal TS with the first voltage level (L) output by the control circuit 102 is the same as the test signal TS fed back through the connection pad 12, the control circuit 102 can determine that the voltage level on the connection pad 12 is not bound to the second voltage level (H), and output an interrupt signal IS with a low logic level (0) (i.e., equivalent to no output of the interrupt signal IS) through the exclusive-OR gate 1026. However, the logic level of the interrupt signal IS of the present invention is not limited thereto.

[0043] In addition, the shielding circuit 104 may include a D flip-flop 1042 and a data multiplexer 1044. One input terminal of the data multiplexer 1044 is coupled to the output terminal of the input / output unit 124, another input terminal receives the operating voltage VDD, and the selection terminal is coupled to the data output terminal of the D flip-flop 1042. That is, during the period when the control circuit 102 outputs the test signal TS to the connection pad 12, the data multiplexer 1044 can select the operating voltage VDD as the output through the D flip-flop 1042, so that the central processing unit 16 cannot receive the test signal TS. In contrast, under normal operation, the data multiplexer 1044 selects the signal transmitted through the connection pad 12 as the output through the D flip-flop 1042.

[0044] Since the operating principles of the D flip-flop, the exclusive-OR gate, and the data multiplexer are already well-known to those of ordinary skill in the art, the details of the control circuit 102 and the shielding circuit 104 will not be elaborated herein. In summary, the use of the D flip-flops 1022, 1024 and the exclusive-OR gate 1026 in the control circuit 102, and the use of the D flip-flop 1042 and the data multiplexer 1044 in the shielding circuit 104 for implementation are only examples and are not intended to limit the present invention. Finally, please refer to Figure 3 , Figure 3 which is the step flowchart of the detection method provided by the embodiment of the present invention. Since the detailed step flow has been described as in the foregoing embodiments, only an overview is provided here and no more redundant description will be given.

[0045] As Figure 3As shown, in step S310, the detection circuit 10 of the system-on-chip 1 will wait for the host to issue a refresh command or a specific event to occur, and when a refresh program is performed on the DDR4 memory 2 (i.e., the host issues a refresh command) or a specific event occurs, the detection circuit 10 of the system-on-chip 1 will start to execute step S320. In step S320, the control circuit 102 is used to generate an output enable signal OES to turn on the output mode of the connection pad 12, and in step S330, the control circuit 102 outputs a test signal TS with a first voltage level (L) to the connection pad 12. Then, in step S340, the control circuit 102 is used to determine whether the voltage level on the connection pad 12 is bound to a second voltage level (H).

[0046] As mentioned above, although the first voltage level and the second voltage level in this embodiment are a low voltage level (L) and a high voltage level (H) respectively, in other embodiments considering that the ALERT_n pin 22 is inadvertently or maliciously forced to conduct to the ground voltage, the first voltage level and the second voltage level are changed to a high voltage level (H) and a low voltage level (L) respectively. In addition, in order to prevent the central processing unit 16 from receiving the test signal TS and making a misjudgment, during the period when the control circuit 102 outputs the test signal TS to the connection pad 12, the shielding circuit 104 is used to shield the test signal TS fed back through the connection pad 12, but Figure 3 the flowchart of this omits this step.

[0047] Then, when it is determined that the voltage level on the connection pad 12 is bound to the second voltage level (H), the detection circuit 10 of the system-on-chip 1 will execute step S350, and when it is determined that the voltage level on the connection pad 12 is not bound to the second voltage level (H), the detection circuit 10 of the system-on-chip 1 will execute step S360. In step S350, the control circuit 102 is used to output an interrupt signal IS to the central processing unit 16, and the interrupt signal IS indicates that the Alert_n pin 22 is not normally controlled by the DDR4 memory 2.

[0048] In addition, in step S360, the control circuit 102 is used to generate an output disable signal to turn off the output mode of the connection pad 12, and return to step S310. As mentioned above, since the connection pad 12 will not turn on the output mode during normal operation, after the detection circuit 10 executes step S350, the control circuit 102 can also generate an output disable signal to turn off the output mode of the connection pad 12, and return to step S310, but Figure 3 the flowchart of this omits this step.

[0049] In summary, since the memory needs to be refreshed periodically, the detection circuit and detection method of the present invention can actively detect whether the ALERT_n pin is normally controlled by the DDR4 memory at a fixed period or when a specific event occurs. In addition, the detection circuit and detection method of the present invention can be implemented without making additional modifications or adding hardware to the external circuit and without violating the DDR transmission protocol.

[0050] The content provided above is only the preferred and feasible embodiment of the present invention, and does not limit the protection scope of the claims of the present invention. Therefore, all equivalent technical changes made by using the content of the specification and drawings of the present invention are included in the scope of protection required by the present invention application.

Claims

1. A detection circuit, suitable for use in a system on a chip, characterized in that: The system single chip is coupled to an alarm pin of a fourth generation double data rate (DDR4) memory through a connection pad, and the detection circuit includes: a control circuit coupled to the connection pad, outputting a test signal having a first voltage level to the connection pad when the DDR4 memory is refreshed or a specific event occurs, and determining whether a voltage level on the connection pad is bound to a second voltage level; When it is determined that the voltage level on the connection pad is bound to the second voltage level, the control circuit outputs an interrupt signal to a central processor of the system single chip, and the interrupt signal indicates that the alarm pin of the DDR4 memory is not normally controlled by the DDR4 memory.

2. The detection circuit according to claim 1, characterized in that: The specific event is that the DDR4 memory has not been initialized or is in an idle state, and the detection circuit further includes: A shielding circuit is coupled to the connection pad, and shields the test signal fed back through the connection pad during the period when the control circuit outputs the test signal to the connection pad, so that the central processor of the system single chip cannot receive the test signal.

3. The detection circuit according to claim 1, characterized in that: Before the control circuit outputs the test signal to the connection pad, the control circuit also generates an output enable signal to turn on an output mode of the connection pad, and when it is determined that the voltage level on the connection pad is not bound to the second voltage level, the control circuit generates an output disable signal to turn off the output mode of the connection pad.

4. The detection circuit according to claim 1, characterized in that: The control circuit determines whether the voltage level on the connection pad is bound to the second voltage level by checking whether the output test signal having the first voltage level is different from the test signal fed back through the connection pad.

5. The detection circuit according to claim 4, characterized in that: If the test signal with the first voltage level output by the control circuit is different from the test signal fed back through the connection pad, the control circuit determines that the voltage level on the connection pad is bound to the second voltage level and outputs the interrupt signal with a high logic level to the central processing unit.

6. A detection method, applicable to a system on a chip, characterized in that: The system single chip is coupled to an alarm pin of the DDR4 memory via a connection pad, and the detection method includes: When the DDR4 memory is refreshed or a specific event occurs, a control circuit is used to output a test signal having a first voltage level to the connection pad, and determine whether the voltage level on the connection pad is bound to a second voltage level; and When it is determined that the voltage level on the connection pad is bound to the second voltage level, the control circuit is used to output an interrupt signal to a central processor of the system single chip, and the interrupt signal indicates that the alarm pin of the DDR4 memory is not normally controlled by the DDR4 memory.

7. The detection method according to claim 6, characterized in that The specific event is that the DDR4 memory has not been initialized or is in an idle state, and the detection method further includes: During the period when the control circuit outputs the test signal to the connection pad, a shielding circuit is used to shield the test signal fed back through the connection pad, so that the central processor of the system single chip cannot receive the test signal.

8. The detection method according to claim 6, characterized in that: Before using the control circuit to output the test signal to the connection pad and determining whether the voltage level on the connection pad is bound to the second voltage level, the detection method further includes: Waiting for a host to issue a refresh command or for the specific event to occur.

9. The detection method according to claim 8, characterized in that: Before the control circuit outputs the test signal to the connection pad, the detection method further includes: The control circuit is utilized to generate an output enable signal to start an output mode of the connection pad.

10. The detection method according to claim 9, characterized in that: The detection method further comprises: When it is determined that the voltage level on the connection pad is not bound to the second voltage level, the control circuit is used to generate an output disable signal to turn off the output mode of the connection pad, and return to the step of waiting for the host to issue the refresh command or the specific event to occur.

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