Data relocation operation techniques

Abstract

This application relates to data relocation operation techniques. A memory system can include a block of memory cells, such as within a non-volatile memory device of the memory system. The memory system can identify a command to perform a data relocation operation associated with a block of memory cells, and can select between a first procedure and a second procedure for performing the data relocation operation. The memory system can select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system can select the first procedure if the one or more parameters satisfy the threshold, and the memory system can select the second procedure if the one or more parameters do not satisfy the threshold. The memory system can perform the data relocation operation using the selected procedure.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 150,901, filed February 18, 2021, by Papa et al., entitled “Data Relocation Operation Techniques,” which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves data relocation operation technology. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even in the absence of an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a memory system; and a controller coupled to the memory system and operable such that the apparatus: recognizes a command to perform a data relocation operation associated with a memory cell block of the memory system; selects between a first program for performing the data relocation operation and a second program for performing the data relocation operation, at least in part based on whether one or more parameters associated with the data relocation operation satisfy a threshold; and performs the data relocation operation using either the first program or the second program, at least in part based on recognizing the command and selecting between the first program and the second program.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: identify a command to perform a data relocation operation associated with a memory cell block of a memory system; select between a first program and a second program for performing the data relocation operation, at least in part based on whether one or more parameters associated with the data relocation operation satisfy a threshold; and perform the data relocation operation using either the first program or the second program, at least in part based on identifying the command and selecting between the first program and the second program.

[0008] A method performed by a memory system is described. The method may include: identifying a command to perform a data relocation operation associated with a memory cell block of the memory system; selecting between a first program and a second program for performing the data relocation operation, based at least in part on whether one or more parameters associated with the data relocation operation satisfy a threshold; and performing the data relocation operation using either the first program or the second program, based at least in part on identifying the command and selecting between the first program and the second program. Attached Figure Description

[0009] Figure 1 This document describes examples of systems that support data relocation techniques, as illustrated in the examples disclosed herein.

[0010] Figure 2 This document describes examples of data schemes that support data relocation techniques, as illustrated in the examples disclosed herein.

[0011] Figure 3 This document provides an example of a process flow that supports data relocation techniques based on examples disclosed herein.

[0012] Figure 4A block diagram of a memory system that supports data relocation operation techniques based on examples disclosed herein is shown.

[0013] Figure 5 The flowchart illustrates one or more methods of supporting data relocation operation techniques based on examples disclosed herein. Detailed Implementation

[0014] A memory device in a memory system stores data at corresponding physical addresses, where the physical address identifies the physical location of the corresponding memory cell within the memory device. The physical location of data within the memory device may change over time due to the memory device accommodating additional data writes, maintenance operations performed by the memory device (e.g., garbage collection), or for any number of other reasons. A host system coupled to the memory system may reference data using logical addresses (e.g., logical block addresses (LBAs), virtual addresses, system addresses, or other logical addresses) (e.g., if a read, write, or other command associated with the data is issued), and the memory device can generate and maintain a mapping between the logical addresses associated with the data and the physical addresses of the memory cells storing the data. This allows the memory device to change physical addresses over time.

[0015] Memory systems can perform data relocation operations (e.g., garbage collection, dynamic wear leveling, reliability relocation, protocol-specific folding, refresh, reflow relocation, or some other data relocation operation) to free up, merge, or relocate memory space. In some instances, data relocation operations can be associated with blocks of memory cells in the memory system. For example, in response to a command to perform a data relocation operation, the memory system can locate the valid pages (i.e., pages containing valid data) of a memory cell block and write the valid pages to a new memory cell block. Additionally, the memory system can update the mapping between the logical addresses associated with the valid pages and the physical addresses of the memory cells in the new block storing the valid pages. However, in some cases, the memory cell block associated with a data relocation operation may contain a relatively large number of valid pages (e.g., approximately 80% of the pages in the memory cell block are valid, or some other percentage of the pages in the memory cell block are valid). Some procedures used for performing data relocation operations can increase memory system latency and power consumption due to locating a large number of valid pages and updating the mapping of each valid page written to a new memory cell block. Therefore, it may be necessary to improve the technology of the program used for data relocation operations.

[0016] This document describes techniques, systems, and apparatuses for improving the performance of data relocation operations by selecting different procedures for performing the data relocation operation based on or in response to one or more parameters associated with the data relocation operation. For example, a memory system may identify a command to perform a data relocation operation associated with a memory cell block; in response to identifying the command, the memory system may select between a sparse data relocation procedure and a dense data relocation procedure based on or in response to whether one or more parameters associated with the data relocation operation meet a threshold. For example, if one or more parameters meet the threshold (e.g., if a threshold percentage of pages in the memory cell block are valid pages), then the memory system may select a dense data procedure, and if one or more parameters do not meet the threshold, then the memory system may select a sparse data procedure. The memory system may perform the data relocation operation using the selected procedure. In some instances, the dense data procedure may include a process of writing valid and invalid pages of the memory cell block to a new memory cell block without updating the mapping indicating the relationship between logical addresses and physical addresses. This process can eliminate or reduce the latency associated with locating valid pages of the memory cell block and update the mapping, thereby reducing the latency for performing the data relocation operation. In some cases, as described in this article, intensive data procedures can reduce latency and power consumption, and improve the performance of memory systems associated with data relocation operations.

[0017] Firstly, in reference Figure 1 The features of this disclosure are described in the context of the system described. (See references...) Figure 2 and 3 The features of this disclosure are described in the context of the data scheme and process flow described herein. These and other features of this disclosure are provided by reference to [reference needed]. Figure 4 and 5 The device diagrams and flowcharts related to the data relocation operation techniques described herein are further illustrated and described with reference to the device diagrams and flowcharts.

[0018] Figure 1 This describes an example of a system 100 that supports data relocation operation techniques as disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0020] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing means.

[0021] System 100 may include a host system 105 that can be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an example of a control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled and communicate with the memory device 130 to perform operations at the memory device 130 that are generally referred to as access operations, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic for the operation of the memory system controller 115 herein. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or another memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or another memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, then data may be stored in local memory 120, and said data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0028] although Figure 1 The example of memory system 110 described herein includes memory system controller 115; however, in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described herein, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information. If configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0033] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, memory cells within different blocks 170 can be operated on in parallel, as long as the different blocks 170 are in different planes 165. In some cases, parallel operations in different planes 165 may be subject to one or more limitations, such as performing the same operation on memory cells within different pages 175, which have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0035] In some instances, a set of one or more blocks 170 may be referred to as a virtual block. Each block 170 in the set of blocks 170 of a virtual block may contain a certain number of pages 175. A page line of a virtual block may refer to a single line of pages 175 of the virtual block. For example, the page line corresponding to the first line of a virtual block may contain the first page 175 of each block 170 in the set of blocks 170. A dynamic block may refer to a subset of the page lines of a virtual block.

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit (e.g., a set of memory cells) of memory that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 can be the smallest unit (e.g., a set of memory cells) of memory that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Additionally, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0037] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages 175 of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise represent data held in the old block 170 as invalid or obsolete, and may update the logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 rather than the old invalid block 170. In some cases, this copying and remapping may be performed, rather than erasing and rewriting the entire old block 170, due to considerations such as latency or wear. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or planes 165) for use by local controller 135 or memory system controller 115 (e.g., for referencing and updating).

[0038] In some cases, an L2P mapping table can be maintained, and data can be marked as valid or invalid at the page granularity level. Page 175 may contain valid data, invalid data, or no data. Invalid data may be outdated data due to the latest or newer version of the data being stored in a different page 175 of memory device 130. Invalid data may have been previously programmed into an invalid page 175 but may no longer be associated with a valid logical address, such as the logical address referenced by host system 105. Valid data may be the latest version of such data stored on memory device 130. Page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0039] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called “garbage collection” may be invoked to allow block 170 to be erased and freed up for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting pages 175 in block 170 containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, allowing more blocks 170 to be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0040] The memory system controller 115 or local controller 135 can recognize commands to perform data relocation operations, which may be instances of one or more media management operations, wear leveling operations, garbage collection operations, folding operations, or any combination thereof, as described herein. In some instances, the data relocation operation may be associated with a virtual block. Some procedures for performing data relocation operations may include updating the mapping between the logical address associated with a valid page 175 of the virtual block and the physical address of the memory cell of the new virtual block storing the valid page 175. However, in some cases, the virtual block may contain a relatively large number of pages 175. Additionally, a relatively large percentage of pages 175 may be valid pages 175. Such procedures for performing data relocation operations can increase the latency and power consumption of system 100 due to updating the mapping of each valid page 175.

[0041] To reduce latency and power consumption associated with data relocation operations, the memory system controller 115 or local controller 135 may select a program from one or more programs for performing the data relocation operation based on or in response to one or more parameters associated with the data relocation operation. For example, the memory system controller 115 or local controller 135 may recognize a command to perform a data relocation operation associated with a dynamic block. In response to recognizing the command, the memory system controller 115 or local controller 135 may select between a sparse data relocation program and a dense data relocation program based on or in response to whether one or more parameters associated with the data relocation operation meet a threshold. For example, if one or more parameters meet a threshold (e.g., if a threshold percentage of pages in a memory cell block are valid pages), then the memory system controller 115 or local controller 135 may select a dense data program, and if one or more parameters do not meet a threshold, then the memory system controller 115 or local controller 135 may select a sparse data program. The memory system controller 115 or local controller 135 may use the selected program to perform the data relocation operation. In some instances, the intensive data relocation procedure may include writing valid and invalid pages of a memory cell block to a new memory cell block without updating the mapping, thereby eliminating or reducing the latency associated with updating the mapping. Additionally, by selecting between the intensive and sparse data relocation procedure at the dynamic block level, the memory system controller 115 and the local controller 135 can improve the performance of data relocation operations at the virtual block level.

[0042] System 100 may include any number of non-transitory computer-readable media that support data relocation operation techniques. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0043] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is an MNAND system.

[0044] Figure 2 This describes an example of a data scheme 200 that supports data relocation operation techniques, as disclosed in the examples herein. See references... Figure 1 The components of the described system 100 implement data scheme 200. For example, data scheme 200 may be implemented by a memory device of a memory system, such as memory device 130, and a controller of a memory system or memory device (or both), such as memory system controller 115 or local controller 135, as referenced. Figure 1 As described herein. In some instances, data scheme 200 may be a logical representation and organization of memory cells used by the controller to perform data relocation operations as described herein.

[0045] Data scheme 200 describes virtual block 205. Virtual block 205 can be a logical grouping of one or more blocks 210, wherein each block 210 can be as described in the reference. Figure 1 An example of block 170 is described. For instance, the controller may group blocks 210-a, 210-b, and 210-c, and this group may be referred to as virtual block 205. The controller may assign an index to virtual block 205, and the controller may use the index to locate virtual block 205 and access its memory locations. For illustrative purposes, Figure 2 Virtual block 205 is depicted as containing three blocks 210; however, the principles disclosed herein are adaptable and applicable to virtual block 205 to contain any number of blocks 210.

[0046] Each of blocks 210-a, 210-b, and 210-c may contain a number of pages 220, which may be as shown in the reference. Figure 1An example of page 175 is described. A page line of virtual block 205 may refer to a single row of page 220 of virtual block 205. For example, a page line corresponding to the top row of virtual block 205 may include the top pages 220 of blocks 210-a, 210-b, and 210-c. Dynamic block 215 may refer to a logical grouping of page lines of virtual block 205. For example, dynamic block 215-a may contain the first four page lines of virtual block 205; dynamic block 215-b may contain the next four page lines of virtual block 205; and dynamic block 215-c may contain the last four page lines of virtual block 205. In some instances, the number of page lines included in a given dynamic block 215 may be pre-configured. In other instances, the controller may configure the number of page lines included in a given dynamic block 215. The controller may assign an index to each dynamic block 215, and the controller may use the index to locate and access the memory cells of the given dynamic block 215.

[0047] The controller can generate, maintain, and store a first mapping that maps the index of dynamic block 215 to the corresponding virtual block 205. For example, an entry in the first mapping that maps dynamic block 215-a to virtual block 205 may contain a first index associated with dynamic block 215-a, a second index associated with virtual block 205, and an offset of dynamic block 215-a within virtual block 205. Therefore, by reading the entries in the first mapping, the controller can determine the virtual block 205 in which dynamic block 215-a resides and its position within virtual block 205. In some instances, the first mapping may be referred to as a dynamic block array table.

[0048] The controller may generate, maintain, and store a second mapping indicating the relationship between logical addresses and their corresponding physical addresses. For example, an entry in the second mapping may map the logical address of page 220 to its corresponding physical address. Therefore, by reading the entry in the second mapping, the controller can determine the physical address of page 220. In some instances, the second mapping may be an instance of a Physical Pointer Table (PPT) that maps logical addresses (e.g., LBAs) to their corresponding physical addresses in a non-volatile memory device coupled to the controller (e.g., memory device 130, a NAND device, or some other non-volatile memory device). In some cases, the second mapping may be an instance of an L2P mapping table. In some instances, in order to update the second mapping (e.g., if data contained in page 220 is written to a different page 220), the controller may load at least a portion of the entries in the second mapping that are to be updated to the memory system in a volatile memory device (e.g., local memory 120, memory device 130 containing volatile memory cells), update the entries, and unload said portion of the second mapping to the memory system in a non-volatile memory device 130 (e.g., memory device 130 containing non-volatile memory cells).

[0049] The controller can recognize commands to perform data relocation operations associated with dynamic block 215 and can select between a dense data relocation procedure and a sparse data relocation procedure for the data relocation operation. To perform a data relocation operation using a dense data relocation operation, the controller can read data stored at the associated dynamic block 215 and write the data to a second dynamic block 215 (e.g., a different virtual block 205). For example, if a data relocation operation is associated with dynamic block 215-a, the controller can read data stored in each of the pages 220 contained in dynamic block 215-a and write the data to the page 220 of the second dynamic block 215. In some instances, dynamic block 215-a may contain one or more pages 220 containing valid data and one or more pages 220 containing invalid data. Here, the controller can read both the page 220 containing valid data and the page 220 containing invalid data and write both the valid and invalid data to the second dynamic block 215. In some instances, the controller can write data read from dynamic block 215-a to the second dynamic block 215 in the same order as data is written to dynamic block 215-a. In other words, a data relocation operation using a dense data relocation procedure may involve copying dynamic block 215-a to the second dynamic block 215.

[0050] Additionally, to perform data relocation operations using a intensive data procedure, the controller can update the first mapping to indicate the updated location of the associated dynamic block 215 and can prevent updates to the second mapping. For example, the controller can update the entry of the first mapping associated with dynamic block 215-a. To update the entry of the first mapping, the controller can update the second index of the entry to indicate the virtual block 205 associated with the second dynamic block 215 and can update the offset to indicate the location of dynamic block 215-a within virtual block 205. Because the second dynamic block 215 is a copy of dynamic block 215-a (e.g., dynamic block 215-a has changed location), the controller can prevent updates to the second mapping. Alternatively, the controller can subsequently use the updated first mapping (e.g., combined with the unupdated second mapping) to determine the physical address of page 220 of the second dynamic block 215.

[0051] Alternatively, to perform data relocation operations using a sparse data relocation procedure, the controller can determine the page 220 of dynamic block 215 associated with the data relocation procedure containing valid data, and can write the page containing valid data to a second dynamic block 215 (e.g., a different virtual block 205). For example, if a data relocation operation is associated with dynamic block 215-b, the controller can determine which pages 220 contained in dynamic block 215-b contain valid data and can write the page 220 containing valid data to the second dynamic block 215. Additionally, the second mapping is updated to map the logical address of the page 220 written to the second dynamic block 215 to the corresponding physical address of the second dynamic block 215.

[0052] Compared to using a sparse data relocation procedure, a dense data relocation procedure can reduce the latency associated with performing a data relocation operation. For example, the initial latency associated with performing a data relocation operation using a dense data relocation procedure can be estimated (e.g., calculated) using the following equation:

[0053] L1 = C I *(t DL +t DF (1)

[0054] Where L1 is the first waiting time, C I The number of pages 220 copied to the second dynamic block 215 (e.g., the number of pages 220 contained in dynamic block 215-a), t DL The time it takes to load the data read from dynamic block 215 into the volatile memory device, and t DF The amount of time required to refresh data from the volatile memory device. Additionally, a second latency associated with the data relocation operation using a sparse data relocation procedure can be estimated (e.g., calculated) using the following equation:

[0055] L2=T*[t TL +M*(t TS +t DL )+t TU +t TF ]+C std *t DF (2)

[0056] Where L2 is the second waiting time, T is the number of portions of the second mapping to be loaded / unloaded from the volatile memory device, and t TL The time required to load a portion of the second mapping, M is the average number of logical addresses associated with a valid page for each portion of the second mapping, and t is the time required to load a portion of the second mapping. TS The time amount t is used to locate a portion of the second mapping. DLt is the amount of time it takes to load the data read from dynamic block 215 into the volatile memory device. TU The amount of time t is used to update a portion of the second mapping loaded into the volatile memory device. TF The amount of time required to unload a portion of the second mapping, C std The number of pages 220 copied to the second dynamic block 215 (e.g., the number of pages 220 contained in dynamic block 215-b containing valid data), and t DF The amount of time required to refresh data from a volatile memory device.

[0057] As the values ​​of T and M increase, the second latency associated with the sparse data relocation procedure increases relative to the first latency associated with the dense data relocation procedure. Additionally, C... std The value can usually be less than C. I The value of . However, with C std As the value of C increases, the second waiting time increases relative to the first waiting time because C I The value can remain relatively static. Therefore, as the number of pages containing valid data in dynamic block 215 increases, the dense data relocation procedure becomes increasingly faster than the sparse data relocation procedure. For example, defragmentation operations performed on a B16CNAND device using the dense data relocation procedure are approximately 2.5 times faster than those using the sparse data relocation procedure. Therefore, using the dense data relocation procedure reduces the latency associated with performing data relocation operations.

[0058] In some instances, data relocation operations may be associated with virtual block 205. Here, the controller may independently select a program to perform data relocation operations for each dynamic block 215 of virtual block 205. For example, the controller may select a dense data relocation program to perform data relocation operations for dynamic blocks 215-a and 215-c, and a sparse data relocation program to perform data relocation operations for dynamic block 215-b. The controller may select a corresponding program to perform data relocation operations for the corresponding dynamic block 215 based on or in response to whether one or more parameters associated with the data relocation operation for the corresponding dynamic block 215 meet one or more associated thresholds. In this way, the controller may implement a unified data relocation method that selects programs to perform data relocation operations on a per-dynamic-block basis.

[0059] Figure 3 This describes an example of a process flow 300 that supports data relocation operation techniques as disclosed herein. Process flow 300 may be provided by a memory system (e.g., reference...) Figure 1The process flow 300 may be performed by components of the memory system 110 described herein. For example, the process flow 300 may be performed by a controller of the memory system or memory device (or both) (e.g., as described in reference). Figure 1 The process flow 300 describes the selection of a program for performing a data relocation operation and the process of performing the data relocation operation using the selected program. This process can be implemented to reduce latency and power consumption, improve system performance, and provide other benefits. Aspects of the process flow 300 can be implemented by the controller and other components. Alternatively, aspects of the process flow 300 can be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to the memory system controller 115 or the local controller 135). For example, if executed by a controller (e.g., memory system controller 115, local controller 135), the instructions can cause the controller to perform the operation of process flow 300.

[0060] In the following description of process flow 300, operations may be performed in different orders or at different times. Some operations may also be omitted from process flow 300, or other operations may be added to process flow 300.

[0061] At point 305, a command to perform a data relocation operation can be identified. For example, the controller can identify a command to perform a data relocation operation, wherein the data relocation operation is associated with a dynamic block (e.g., dynamic block 215) of a memory device coupled to the controller (e.g., a non-volatile memory device containing non-volatile memory cells). In some instances, to identify the command, the controller may receive the command from a host system coupled to the controller. In other instances, to identify the command, the controller may initiate a data relocation operation.

[0062] At 310, one or more parameters associated with a data relocation operation can be evaluated regarding whether one or more parameters meet one or more associated thresholds. Instances of one or more parameters associated with a data relocation operation may include the percentage of pages containing valid data in a dynamic block, the latency associated with the data relocation operation, the type of data relocation operation, the state of the host system coupled to the controller, the number of pages containing valid data in a dynamic block, or any combination thereof.

[0063] The controller can determine whether one or more parameters meet one or more associated thresholds. For example, the controller can determine whether the percentage of pages containing valid data in a dynamic block meets the threshold valid page percentage (e.g., 80% of the pages in the dynamic block are valid pages, or some other threshold valid page percentage), whether the latency associated with a data relocation operation meets the threshold latency (e.g., whether the latency associated with a data relocation operation using a sparse data relocation procedure meets the threshold latency, whether the latency associated with a data relocation operation using a dense data relocation procedure meets the threshold latency), whether the type of data relocation is a specific type of data relocation operation (e.g., whether the type corresponds to a foreground operation, a background operation, or some other operation type), whether the host system is idle, whether the number of pages containing valid data in the dynamic block meets the threshold valid page number, or a combination thereof.

[0064] The controller can maintain a counter to determine whether the percentage of pages containing valid data in a dynamic block meets a threshold valid page percentage, or whether the number of pages containing valid data in the dynamic block meets a threshold valid page number, or both. For example, the controller can generate, maintain, and store a counter that tracks the number of pages containing valid data in a dynamic block. The controller can compare the number of pages containing valid data indicated by the counter to the total number of pages in the dynamic block to calculate the percentage of pages containing valid data in the dynamic block. The controller can then compare the calculated percentage to the threshold valid page percentage to determine whether the calculated percentage meets the threshold valid page percentage. Alternatively, the controller can compare the number of pages containing valid data in the dynamic block indicated by the counter to the threshold valid page number to determine whether the number of pages containing valid data in the dynamic block meets the threshold valid page number. In some instances, the counter may be called a dynamic valid page counter.

[0065] If at 310, the controller determines that one or more parameters satisfy one or more associated thresholds, then the controller may proceed as follows: 315 and 320. For example, if the controller determines that the percentage of pages containing valid data in a dynamic block is greater than (e.g., equal to) a threshold valid page percentage, that data relocation using a sparse data relocation procedure will not meet a wait time threshold, that the data relocation operation is associated with a foreground operation, that the host system is in a state other than idle, that the number of pages containing valid data in a dynamic block is greater than (e.g., equal to) a threshold valid page number, or a combination thereof, then the controller may proceed as follows: 315 and 320.

[0066] At point 315, a dense data relocation procedure can be selected. For example, the controller can select a dense data relocation procedure to perform a data relocation operation based on or in response to determining whether one or more parameters meet (e.g., determining that one or more parameters meet) one or more associated thresholds.

[0067] At position 320, a dense data relocation procedure can be used for data relocation, as shown in the reference. Figure 2 As described. For example, to perform a data relocation operation using a dense data relocation procedure, the controller can read data stored in a dynamic block associated with the data relocation operation and write the data read from the dynamic block to a second dynamic block. In some instances, the dynamic block can contain both valid pages and invalid pages. Here, the controller can write both valid data from valid pages and invalid data from invalid pages to the second dynamic block.

[0068] If at 310, the controller determines that one or more parameters do not meet one or more associated thresholds, then the controller may proceed as follows: 325 and 330. For example, if the controller determines that the percentage of pages containing valid data in a dynamic block is less than (e.g., equal to) a threshold valid page percentage, that data relocation using a sparse data relocation procedure will meet a wait time threshold, that the data relocation operation is associated with a background operation, that the host system is idle, that the number of pages containing valid data in a dynamic block is less than (e.g., equal to) a threshold valid page number, or a combination thereof, then the controller may proceed as follows: 325 and 330.

[0069] At point 325, a sparse data relocation procedure can be selected. For example, the controller can select a sparse data relocation procedure to perform a data relocation operation based on or in response to determining whether one or more parameters are not met (e.g., determining that one or more parameters are not met) associated with one or more thresholds.

[0070] At position 330, a sparse data relocation procedure can be used for data relocation, as shown in the reference. Figure 2 As described. For example, to perform data relocation operations using a sparse data relocation procedure, the controller may write pages containing valid data from a dynamic block to a second dynamic block. Here, the controller may prevent pages containing invalid data from a dynamic block from being written to the second dynamic block. Additionally, the controller may update the mapping indicating the relationship between logical addresses and physical addresses (e.g., a PPT, L2P table, or some other logical-to-physical mapping) to map the logical address associated with the page written to the second dynamic block to the corresponding physical address in the second dynamic block.

[0071] Figure 4A block diagram 400 illustrates a memory system 420 that supports data relocation operation techniques according to examples disclosed herein. The memory system 420 may be as described in the references... Figures 1 to 3 Examples of aspects of the described memory system. Memory system 420 or its various components may be examples of various components for performing data relocation operations as described herein. For example, memory system 420 may include command component 425, selection component 430, data relocation component 435, parameter component 440, mapping component 445, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0072] Command component 425 may be configured or otherwise supported to include means for identifying commands for performing data relocation operations associated with memory cell blocks of the memory system. Selection component 430 may be configured or otherwise supported to include means for selecting between a first procedure and a second procedure for performing a data relocation operation, based at least in part on whether one or more parameters associated with the data relocation operation meet thresholds. Data relocation component 435 may be configured or otherwise supported to include means for performing a data relocation operation using either the first or second procedure, based at least in part on the identified command and the selection between the first and second procedures.

[0073] In some instances, parameter component 440 may be configured or otherwise supported to support means for determining whether one or more parameters meet a threshold. In some instances, selection component 430 may be configured or otherwise supported to support means for selecting a first procedure at least in part based on determining that one or more parameters meet a threshold. In some instances, data relocation component 435 may be configured or otherwise supported to support means for performing a data relocation operation using a first procedure at least in part based on selecting a first procedure.

[0074] In some instances, to support data relocation operations using the first procedure, the data relocation component 435 may be configured or otherwise support a means for reading data stored at a memory cell block. In some instances, to support data relocation operations using the first procedure, the data relocation component 435 may be configured or otherwise support a means for writing data read from a memory cell block to a second memory cell block.

[0075] In some instances, a memory cell block may contain one or more pages associated with valid data and one or more pages associated with invalid data, and the data relocation component 435 may be configured or otherwise support means for writing one or more pages associated with valid data and one or more pages associated with invalid data to a second memory cell block, at least in part based on a data relocation operation performed using a first procedure.

[0076] In some instances, mapping component 445 may be configured or otherwise support a component for updating a first entry of a mapping that maps an index associated with a memory cell block to a group of memory cell blocks, based at least in part on a data relocation operation using a first procedure, wherein the updated first entry includes a first index associated with a second memory cell block, a second index associated with a first group of memory cell blocks containing the second memory cell block, and an offset of the second memory cell block within the first group of memory cell blocks.

[0077] In some instances, mapping component 445 may be configured or otherwise support a component for preventing updates to the mapping indicating the relationship between logical addresses and physical addresses, based at least in part on a data relocation operation performed using a first procedure.

[0078] In some instances, to support determining whether one or more parameters meet a threshold, parameter component 440 may be configured or otherwise support components for maintaining a counter associated with a memory cell block, the counter tracking the number of pages associated with valid data in the memory cell block. In some instances, to support determining whether one or more parameters meet a threshold, parameter component 440 may be configured or otherwise support components for determining whether the number of pages associated with valid data in the memory cell block meets a threshold number of pages associated with valid data.

[0079] In some instances, parameter component 440 may be configured or otherwise supported to support means for determining whether one or more parameters do not meet a threshold. In some instances, selection component 430 may be configured or otherwise supported to support means for selecting a second procedure at least in part based on the determination that one or more parameters do not meet a threshold. In some instances, data relocation component 435 may be configured or otherwise supported to support means for performing a data relocation operation using a second procedure at least in part based on the selection of a second procedure.

[0080] In some instances, to support data relocation operations using a second procedure, the data relocation component 435 may be configured or otherwise supported to support means for writing pages associated with valid data from one memory cell block to another memory cell block. In some instances, to support data relocation operations using a second procedure, the mapping component 445 may be configured or otherwise supported to support means for updating a mapping indicating the relationship between logical addresses and physical addresses to map the logical address associated with a page written to the second memory cell block to the corresponding physical address in the second memory cell block.

[0081] In some instances, command component 425 may be configured or otherwise support a component for receiving commands for performing data relocation operations from a host system coupled to the memory system, wherein identifying the commands for performing data relocation operations is at least in part based on commands for performing data relocation operations received from the host system.

[0082] In some instances, the data relocation component 435 may be configured or otherwise support a component for initiating a data relocation operation by the memory system, wherein the command for identifying the data relocation operation is at least partially based on the initiation data relocation operation.

[0083] In some instances, one or more parameters associated with a data relocation operation include the percentage of pages containing valid data in a memory cell block, the latency associated with the data relocation operation, the type of data relocation operation, the state of the host system coupled to the memory system, or any combination thereof.

[0084] In some instances, the non-volatile memory device of a memory system comprises blocks of memory cells.

[0085] Figure 5 The flowchart illustrates a method 500 that supports data relocation operation techniques according to examples disclosed herein. The operation of method 500 can be implemented by a memory system or its components as described herein. For example, the operation of method 500 can be implemented by a reference... Figures 1 to 4 The described memory system performs the functions described. In some instances, the memory system can execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0086] At point 505, the method may include identifying a command to perform a data relocation operation associated with a memory cell block of the memory system. The operation at point 505 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 4 The described command component 425 performs the operation of 505.

[0087] At 510, the method may include selecting between a first procedure and a second procedure for performing the data relocation operation, based at least in part on whether one or more parameters associated with the data relocation operation satisfy a threshold. The operation at 510 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 4 The described aspect of the selection component 430 performing the operation of 510.

[0088] At 515, the method may include performing a data relocation operation using either the first or second procedure, at least in part, based on an identification command and a selection between the first and second procedures. The operation at 515 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 4 The described data relocation component 435 performs the operation of 515.

[0089] In some instances, the device as described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: identifying a command to perform a data relocation operation associated with a memory cell block of a memory system; selecting between a first program and a second program for performing the data relocation operation, at least in part based on whether one or more parameters associated with the data relocation operation satisfy a threshold; and performing the data relocation operation using either the first or second program, at least in part based on the identified command and the selection between the first and second programs.

[0090] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: determining whether one or more parameters satisfy a threshold, wherein selecting between a first procedure and a second procedure includes selecting the first procedure at least in part based on determining that one or more parameters satisfy the threshold, and performing a data relocation operation using the first procedure or the second procedure includes performing the data relocation operation using the first procedure at least in part based on selecting the first procedure.

[0091] In some instances of the method 500 and apparatus described herein, the data relocation operation using a first procedure may include operations, features, circuitry, logic, components, or instructions for reading data stored in a memory cell block and writing data read from the memory cell block to a second memory cell block.

[0092] In some instances of the method 500 and apparatus described herein, the memory cell block may contain one or more pages associated with valid data and one or more pages associated with invalid data, and the method, apparatus, and non-transitory computer-readable medium may contain additional operations, features, circuitry, logic, components, or instructions for writing one or more pages associated with valid data and one or more pages associated with invalid data to a second memory cell block, at least in part based on a data relocation operation using a first program.

[0093] Some instances of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for updating a first entry of a mapping that maps an index associated with a memory cell block to a group of memory cell blocks, at least in part based on a data relocation operation using a first procedure, wherein the updated first entry includes a first index associated with a second memory cell block, a second index associated with a first group of memory cell blocks containing the second memory cell block, and an offset of the second memory cell block within the first group of memory cell blocks.

[0094] Some instances of the method 500 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for preventing updates to a mapping indicating the relationship between logical addresses and physical addresses, at least in part, based on a data relocation operation performed using a first procedure.

[0095] In some instances of the methods 500 and devices described herein, determining whether one or more parameters satisfy a threshold may include operations, features, circuit systems, logic, components, or instructions for maintaining a counter associated with a memory cell block that tracks the number of pages in the memory cell block that can be associated with valid data, and determining whether the number of pages in the memory cell block that can be associated with valid data satisfies a threshold number of pages associated with valid data.

[0096] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: determining whether one or more parameters do not meet a threshold, wherein selecting between a first procedure and a second procedure includes selecting the second procedure at least in part based on determining that one or more parameters do not meet a threshold, and performing a data relocation operation using the first procedure or the second procedure includes performing the data relocation operation using the second procedure at least in part based on selecting the second procedure.

[0097] In some instances of the method 500 and apparatus described herein, the data relocation operation using a second procedure may include operations, features, circuitry, logic, components, or instructions for: writing pages of a memory cell block that can be associated with valid data to a second memory cell block; and updating a mapping indicating the relationship between logical addresses and physical addresses to map the logical address associated with the page written to the second memory cell block to the corresponding physical address of the second memory cell block.

[0098] Some examples of the methods 500 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for receiving a command to perform a data relocation operation from a host system coupled to a memory system, wherein identifying the command to perform the data relocation operation may be based at least in part on the command to perform the data relocation operation received from the host system.

[0099] Some examples of the methods 500 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for initiating a data relocation operation from a memory system, wherein the command identifying the data relocation operation may be at least partially based on the initiating data relocation operation.

[0100] In some instances of the method 500 and apparatus described herein, one or more parameters associated with the data relocation operation include the percentage of pages containing valid data in a memory cell block, the latency associated with the data relocation operation, the type of data relocation operation, the state of the host system coupled to the memory system, or any combination thereof.

[0101] In some instances of the methods 500 and devices described herein, the non-volatile memory device of the memory system comprises blocks of memory cells.

[0102] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0103] Describe an apparatus. The apparatus may include: a memory system; and a controller coupled to the memory system and operable such that the apparatus: recognizes a command to perform a data relocation operation associated with a memory cell block of the memory system; selects between a first program and a second program for performing the data relocation operation, at least in part based on whether one or more parameters associated with the data relocation operation satisfy a threshold; and performs the data relocation operation using either the first program or the second program, at least in part based on recognizing the command and selecting between the first program and the second program.

[0104] In some instances of the device, the controller may be further configured such that the device determines whether the one or more parameters associated with the data relocation operation meet the threshold, wherein selecting between the first program and the second program includes selecting the first program at least in part based on determining that the one or more parameters meet the threshold; and performing the data relocation operation using the first program or the second program includes performing the data relocation operation using the first program at least in part based on selecting the first program.

[0105] In some instances of the device, in order to perform the data relocation operation using the first program, the controller may be further configured to cause the device to read data stored in the memory cell block and write the data read from the memory cell block to a second memory cell block.

[0106] In some instances of the device, the memory cell block contains one or more pages associated with valid data and one or more pages associated with invalid data, and the controller is further configured such that the device writes the one or more pages associated with valid data and the one or more pages associated with invalid data to the second memory cell block, at least in part, based on the data relocation operation performed using the first procedure.

[0107] In some instances of the device, the controller may be further configured such that the device updates a first entry of the mapping that maps an index associated with a memory cell block to a group of memory cells, at least in part, based on the data relocation operation performed using the first procedure. The updated first entry includes a first index associated with the second memory cell block, a second index associated with a first group of memory cells containing the second memory cell block, and an offset of the second memory cell block within the first group of memory cells.

[0108] In some instances of the device, the controller may be further configured such that the device, at least in part, prevents updates to the mapping indicating the relationship between logical addresses and physical addresses based on the data relocation operation performed using the first procedure.

[0109] In some instances of the device, in order to determine whether the one or more parameters meet the threshold, the controller may be further configured such that the device maintains a counter associated with the memory cell block, the counter tracking the number of pages of the memory cell block that can be associated with valid data, and determining whether the number of pages of the memory cell block that can be associated with valid data meets a threshold number of pages associated with valid data.

[0110] In some instances of the device, the controller may be further configured such that the device determines whether the one or more parameters do not meet the threshold, wherein selecting between the first program and the second program includes selecting the second program at least in part based on determining that the one or more parameters do not meet the threshold, and performing the data relocation operation using the first program or the second program includes performing the data relocation operation using the second program at least in part based on selecting the second program.

[0111] In some instances of the device, in order to perform the data relocation operation using the second procedure, the controller may be further configured to cause the device to write pages of the memory cell block that can be associated with valid data to a second memory cell block, and to update the mapping indicating the relationship between logical addresses and physical addresses to map the logical address associated with the page written to the second memory cell block to the corresponding physical address of the second memory cell block.

[0112] In some instances of the device, the controller may be further configured such that the device receives the command to perform the data relocation operation from a host system coupled to the memory system, wherein the command to perform the data relocation operation is identified as being at least partially based on the command to perform the data relocation operation received from the host system.

[0113] In some instances of the device, the controller may be further configured such that the device initiates the data relocation operation from the memory system, wherein the command identifying the data relocation operation may be at least partially based on initiating the data relocation operation.

[0114] In some instances of the device, the one or more parameters associated with the data relocation operation include the percentage of pages containing valid data in the memory cell block, the latency associated with the data relocation operation, the type of the data relocation operation, the state of the host system coupled to the memory system, or any combination thereof.

[0115] In some instances of the device, the non-volatile memory device of the memory system includes the memory cell block.

[0116] The information and signals described herein can be represented using any of a variety of techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some figures may illustrate signals as single signals; however, the signals may represent signal buses, which may have various bit widths.

[0117] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if there exists any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the flow of signals between connected components for a period of time.

[0118] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently not allowed to travel between the components via a conductive path, and in which a signal can travel between the components via the conductive path. If, for example, a component of a controller couples other components together, then the component initially allows a change in the flow of signals between the other components via conductive paths that were previously not permitted.

[0119] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, components separated by a switch located between two components are isolated from each other when the switch is open. If a controller isolates two components, then the controller achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0120] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0121] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0122] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action that is independent of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly in response to" such other condition or action.

[0123] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0124] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. These terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "turned on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "turned off" or "deactivated."

[0125] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatus are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0126] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0127] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distribution such that different parts of the functions are implemented in different physical locations.

[0128] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0129] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates a list containing endpoints, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0130] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or another remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used in this article, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0131] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein but is intended to embody the broadest scope conforming to the principles and novel features disclosed herein.

Claims

1. A memory system comprising: One or more memory devices; as well as A processing circuitry system coupled to and configured such that the memory system: Identify commands that perform data relocation operations associated with memory cell blocks of the memory system; The selection between a first program and a second program for performing the data relocation operation is based at least in part on whether one or more parameters associated with the data relocation operation meet a threshold. The data relocation operation is performed using either the first program or the second program, at least in part, based on recognizing the command and selecting between the first program and the second program. as well as The determination of whether to update the mapping indicating the relationship between logical addresses and physical addresses is based at least in part on whether the data relocation operation uses the first procedure or the second procedure.

2. The memory system of claim 1, wherein the processing circuitry is further configured such that the memory system: Determine whether one or more parameters associated with the data relocation operation satisfy the threshold, wherein: Choosing between the first procedure and the second procedure includes selecting the first procedure at least in part based on determining that one or more parameters satisfy the threshold; and Performing the data relocation operation using the first program or the second program includes performing the data relocation operation using the first program at least in part based on the selection of the first program.

3. The memory system of claim 2, wherein, in order to perform the data relocation operation using the first program, the processing circuitry is further configured such that the memory system: Read the data stored in the memory cell block; and The data read from the memory cell block is written to the second memory cell block.

4. The memory system according to claim 3, wherein: The memory cell block includes one or more pages associated with valid data and one or more pages associated with invalid data; and The processing circuitry is further configured such that the memory system writes the one or more pages associated with valid data and the one or more pages associated with invalid data to the second memory cell block, at least in part, based on the data relocation operation performed using the first program.

5. The memory system of claim 3, wherein the processing circuitry is further configured such that the memory system: The first entry of the second mapping that maps the index associated with the memory cell block to the group of memory cell blocks is updated at least in part based on the data relocation operation performed using the first procedure. The updated first entry includes a first index associated with the second memory cell block, a second index associated with the first group of memory cell blocks that includes the second memory cell block, and an offset of the second memory cell block within the first group of memory cell blocks.

6. The memory system of claim 2, wherein the processing circuitry is further configured such that the memory system: The mapping update is prevented at least in part based on the data relocation operation performed using the first procedure.

7. The memory system of claim 2, wherein, in order to determine whether the one or more parameters satisfy the threshold, the processing circuitry is further configured such that the memory system: Maintain a counter associated with the memory cell block, the counter tracking the number of pages in the memory cell block associated with valid data; and Determine whether the number of pages associated with valid data in the memory cell block meets the threshold number of pages associated with valid data.

8. The memory system of claim 1, wherein the processing circuitry is further configured such that the memory system: Determine whether one or more parameters do not meet the threshold, wherein: Choosing between the first procedure and the second procedure includes selecting the second procedure at least in part based on determining that one or more parameters do not meet the threshold; and Performing the data relocation operation using the first program or the second program includes performing the data relocation operation using the second program at least in part based on the selection of the second program.

9. The memory system of claim 8, wherein, in order to perform the data relocation operation using the second program, the processing circuitry is further configured such that the memory system: Write the page associated with valid data from the memory cell block to the second memory cell block; and The mapping is updated to map the logical address associated with the page written to the second memory cell block to the corresponding physical address of the second memory cell block.

10. The memory system of claim 1, wherein the processing circuitry is further configured such that the memory system: The command to perform the data relocation operation is received from a host system coupled to the memory system, wherein the command to perform the data relocation operation is identified as being at least in part based on the command to perform the data relocation operation received from the host system.

11. The memory system of claim 1, wherein the processing circuitry is further configured such that the memory system: The data relocation operation is initiated by the memory system, wherein the command identifying the data relocation operation is at least partially based on initiating the data relocation operation.

12. The memory system of claim 1, wherein the one or more parameters associated with the data relocation operation include the percentage of pages containing valid data in the memory cell block, the latency associated with the data relocation operation, the type of the data relocation operation, the state of the host system coupled to the memory system, or any combination thereof.

13. The memory system of claim 1, wherein the non-volatile memory device of the memory system comprises the memory cell block.

14. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by one or more processors of a memory system, cause the memory system to: Identify commands that perform data relocation operations associated with memory cell blocks of the memory system; The selection between a first program and a second program for performing the data relocation operation is based at least in part on whether one or more parameters associated with the data relocation operation meet a threshold. The data relocation operation is performed using either the first program or the second program, at least in part, based on recognizing the command and selecting between the first program and the second program. as well as The determination of whether to update the mapping indicating the relationship between logical addresses and physical addresses is based at least in part on whether the data relocation operation uses the first procedure or the second procedure.

15. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: Determine whether one or more parameters satisfy the threshold, wherein: Choosing between the first procedure and the second procedure includes selecting the first procedure at least in part based on determining that one or more parameters satisfy the threshold; and Performing the data relocation operation using the first program or the second program includes performing the data relocation operation using the first program at least in part based on the selection of the first program.

16. The non-transitory computer-readable medium of claim 15, wherein, in order to perform the data relocation operation using the first program, the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: Read the data stored in the memory cell block; and The data read from the memory cell block is written to the second memory cell block.

17. The non-transitory computer-readable medium according to claim 16, wherein: The memory cell block includes one or more pages associated with valid data and one or more pages associated with invalid data; and When executed by one or more processors of the memory system, the instructions further cause the memory system to write the one or more pages associated with valid data and the one or more pages associated with invalid data to the second memory cell block, at least in part, based on the data relocation operation performed using the first program.

18. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: The first entry of the second mapping that maps the index associated with the memory cell block to the group of memory cell blocks is updated at least in part based on the data relocation operation performed using the first procedure. The updated first entry includes a first index associated with the second memory cell block, a second index associated with the first group of memory cell blocks that includes the second memory cell block, and an offset of the second memory cell block within the first group of memory cell blocks.

19. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: The mapping update is prevented at least in part based on the data relocation operation performed using the first procedure.

20. A method performed by a memory system, comprising: Identify commands that perform data relocation operations associated with memory cell blocks of the memory system; The selection between a first program and a second program for performing the data relocation operation is based at least in part on whether one or more parameters associated with the data relocation operation meet a threshold. The data relocation operation is performed using either the first program or the second program, at least in part, based on recognizing the command and selecting between the first program and the second program. as well as The determination of whether to update the mapping indicating the relationship between logical addresses and physical addresses is based at least in part on whether the data relocation operation uses the first procedure or the second procedure.

21. The method of claim 20, further comprising: Determine whether one or more parameters satisfy the threshold, wherein: Choosing between the first procedure and the second procedure includes selecting the first procedure at least in part based on determining that one or more parameters satisfy the threshold; and Performing the data relocation operation using the first program or the second program includes performing the data relocation operation using the first program at least in part based on the selection of the first program.

22. The method of claim 21, wherein performing the data relocation operation using the first program comprises: Read the data stored in the memory cell block; as well as The data read from the memory cell block is written to the second memory cell block.

23. The method of claim 22, wherein the memory cell block comprises one or more pages associated with valid data and one or more pages associated with invalid data, the method comprising: The data relocation operation is performed using the first procedure, at least in part, to write the one or more pages associated with valid data and the one or more pages associated with invalid data to the second memory cell block.

24. The method of claim 22, further comprising: The first entry of the second mapping that maps the index associated with the memory cell block to the group of memory cell blocks is updated at least in part based on the data relocation operation performed using the first procedure. The updated first entry includes a first index associated with the second memory cell block, a second index associated with the first group of memory cell blocks that includes the second memory cell block, and an offset of the second memory cell block within the first group of memory cell blocks.

25. The method of claim 21, further comprising: The mapping update is prevented at least in part based on the data relocation operation performed using the first procedure.

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