A control method for a memory, a memory, and a storage system

Abstract

The present invention provides a control method for a memory, a memory, and a storage system. The control method includes: when writing data, applying for a mapping relationship between the logical address range and the physical address range stored in at least one dynamic mapping unit, and setting a group number for the dynamic mapping unit according to the application order of the dynamic mapping unit; judging, according to the group number, whether the mapping relationship stored in the dynamically mapped unit that was applied for first has been flushed to the storage area. If the mapping relationship stored first has not been flushed, then flushing the mapping relationship stored first; otherwise, judging whether there are enough blank dynamic mapping units; when there are enough blank dynamic mapping units, writing data; otherwise, flushing the mapping relationship stored in the dynamic mapping unit with the longest vertical length in the dynamic mapping table, and writing data. The control method for the memory proposed by the present invention can improve the writing performance of the memory.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and particularly relates to a control method for a memory, a memory, and a storage system. Background Art

[0002] Compared with traditional hard disks, solid state drives (SSDs) do not have the feature of "overwriting repeatedly". When performing a write operation, it is necessary to first perform an erase operation on the flash memory before writing data. For the data written by the host at a specified logical address, the position where the data is stored in the flash memory is not fixed. Therefore, it is necessary to set up a mapping table of logical addresses and physical addresses (L2PTable) to accurately find out which position in the flash memory the data corresponding to a certain logical address exists. For a memory with a DRAM-Less scheme, due to limited cache resources, a section of space in the cache is mostly designated to store the mapping relationship of the data just written, and then the mapping relationship of the written data is flushed down to the flash block dedicated to storing the data mapping relationship.

[0003] However, when using the position in the valid relationship mapping table to drive the flushing down of earlier mapping relationships, a cache mapping node can occupy multiple positions in the valid mapping relationship table, which easily leads to differences between the cache mapping node and the cache mapping table, thereby increasing the frequency of flushing the cache and reducing the write performance. Summary of the Invention

[0004] In view of the above defects of the prior art, the present invention proposes a control method for a memory, a memory, and a storage system to improve the read and write performance, for example, the random read and write performance can be improved.

[0005] To achieve the above object and other objects, the present invention proposes a control method for a memory, including:

[0006] Setting up a dynamic mapping table in the buffer area, and the dynamic mapping table includes a plurality of dynamic mapping units;

[0007] When writing data, applying for the mapping relationship between the logical address range and the physical address range for storing the data of at least one of the dynamic mapping units, and setting a group number for the dynamic mapping unit according to the order of application of the dynamic mapping unit;

[0008] According to the group number, determining whether the mapping relationship stored in the dynamically mapped unit applied for first has been flushed down to the storage area. If the mapping relationship stored in the dynamically mapped unit applied for first has not been flushed down, then flushing down the mapping relationship stored in the dynamically mapped unit applied for first; if the mapping relationship stored in the dynamically mapped unit applied for first has been flushed down, then determining whether there are sufficient blank dynamic mapping units; and

[0009] When there are sufficient blank dynamic mapping units, data writing is performed; when there are insufficient blank dynamic mapping units, the mapping relationships stored in the dynamic mapping units in the vertical linked list with the longest vertical length in the dynamic mapping table are flushed down, and data writing is performed.

[0010] Further, the dynamic mapping units with the same logical address segmentation are located in the same vertical linked list.

[0011] Further, the control method of the memory further includes: dividing the dynamic mapping units into multiple groups according to the number of the dynamic mapping units, and each group of dynamic mapping units includes an equal number of the dynamic mapping units, and the grouping numbers of the dynamic mapping units within the same group are the same.

[0012] Further, when applying for the dynamic mapping units, the control method of the memory further includes:

[0013] Determining the group to which the dynamic mapping unit belongs according to the order of applying for the dynamic mapping unit.

[0014] Further, when determining whether the mapping relationships stored in the previously applied dynamic mapping units are flushed down to the storage area, the control method of the memory includes the following steps:

[0015] Determining whether the current dynamic mapping unit is the first dynamic mapping unit in the group. If so, determining whether there are dynamic mapping units in the group with a grouping number differing from the current grouping number by a preset value. If so, setting the flag for flushing the cached mapping relationship to the first flag bit.

[0016] Further, after setting the grouping number for the dynamic mapping unit, the control method of the memory further includes: updating the number of the dynamic mapping units in the group.

[0017] Further, when there are insufficient blank dynamic mapping units, the control method of the memory further includes: setting the flag for flushing the cached mapping relationship to the second flag bit.

[0018] Further, when there are sufficient blank dynamic mapping units, the control method of the memory further includes: adding the current dynamic mapping unit to the dynamic mapping table.

[0019] Further, when the mapping relationships stored in the previously applied dynamic mapping units are not flushed down and the mapping relationships stored in the previously applied dynamic mapping units are flushed down, the control method of the memory includes: flushing down the mapping relationships between the logical address ranges and physical address ranges stored in all the dynamic mapping units in the vertical lists where all the dynamic mapping units with a grouping number differing from the current grouping number by a preset value are located.

[0020] The present invention further provides a memory, comprising:

[0021] A rewritable non-volatile memory module storing program instructions;

[0022] A memory controller electrically connected to the rewritable non-volatile memory module, the memory controller running the program instructions for the control method of the above-mentioned memory.

[0023] The present invention further provides a storage system, comprising:

[0024] A host;

[0025] A memory connected to the host, wherein the memory comprises:

[0026] A rewritable non-volatile memory module storing program instructions;

[0027] A memory controller electrically connected to the rewritable non-volatile memory module, the memory controller running the program instructions to implement the control method of the above-mentioned memory.

[0028] In summary, the present invention proposes a control method for a memory, a memory and a storage system. The present invention sets a first-level mapping table in the storage area. The first-level mapping table includes multiple logical address segments. The multiple logical address segments can be arranged by segment addresses, and each logical address segment can correspond to a storage space in the storage area. At the same time, a second-level mapping table and a dynamic mapping table are set in the buffer area. The second-level mapping table includes multiple static mapping units. One static mapping unit corresponds to one logical address segment. Each static mapping unit includes a flag bit and a physical address segment. The physical address segment corresponds to the logical address segment, and the flag bit has a first state and a second state. When performing a write data operation, the controller applies for at least one dynamic mapping unit, and at the same time stores the logical address range and physical address range of the data in the dynamic mapping unit, and sets a group number for the dynamic mapping unit according to the application order of the dynamic mapping unit to record the application order of the dynamic mapping unit. When writing data, first judge whether the mapping relationship stored in the first-applied dynamic mapping unit is flushed. After the mapping relationship stored in the first-applied dynamic mapping unit is flushed, judge whether the number of blank mapping units is sufficient. When the number of blank dynamic mapping units is sufficient, store the dynamic mapping unit storing the mapping relationship of the logical address range and physical address range of the data in the dynamic mapping table. Combining the flushing of the mapping relationship stored in the earlier-applied dynamic mapping unit with the flushing of the mapping relationship caused by insufficient blank mapping nodes can effectively reduce the frequency of flushing the mapping relationship during sequential writing and improve the sequential writing performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 : Schematic structural diagram of the storage system in the present invention.

[0030] Figure 2 : In the present invention Figure 1 Schematic structural diagram of the memory in

[0031] Figure 3 : In the present invention Figure 2 Schematic structural diagram of the memory controller in

[0032] Figure 4 : Schematic diagram of managing physical blocks in the present invention.

[0033] Figure 5 : Schematic structural diagram of a memory in the present invention.

[0034] Figure 6 : Mapping relationship diagram of the first-level mapping table and the second-level mapping in the present invention.

[0035] Figure 7 : Schematic structural diagram of the dynamic mapping table in the present invention.

[0036] Figure 8 : Schematic structural diagram of the dynamic mapping unit in the present invention.

[0037] Figure 9 : Flowchart of a control method for a memory in the present invention.

[0038] Figure 10 : Flowchart during data writing in the present invention.

[0039] Figure 11 : Flowchart for determining whether the previously applied dynamic mapping unit is flushed down in the present invention.

[0040] Figure 12 : Flowchart for determining whether there are sufficient blank dynamic mapping units in the present invention.

[0041] Figure 13 : Flowchart for flushing down the dynamic mapping unit in the present invention. Detailed implementation manners

[0042] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0044] The system described herein includes a novel architecture for controlling a mass storage module including flash memory chips. The overall system is shown in highly schematic form in Figure 1 . Like other boxes herein, Figure 1 the elements shown in Figure 1 are conceptual in nature, showing the nature of the interrelationships between these functional blocks and not intended to represent an actual physical circuit-level implementation.

[0045] Please refer to Figure 1 shown. This embodiment also presents a storage system, which may include a host 110 and a memory 200 to which the host 110 transfers commands and / or data. The storage system can be implemented as a personal computer (PC), a workstation, a data center, an Internet data center, a storage area network, a network-attached storage (NAS), or a mobile computing device, but the inventive concept is not limited to these examples.

[0046] Please refer to Figure 1 shown. The memory 200 can be a flash-based memory device, but is not limited thereto. The memory 200 can be implemented as an SSD, an embedded SSD (eSSD), a universal flash memory (UFS), an MMC, an embedded MMC (eMMC), or a managed NAND, but the inventive concept is not limited to these examples.

[0047] The memory includes a rewritable non-volatile memory module and a controller (control circuit). The memory can be used with a host so that the host can write data to the memory or read data from the memory.

[0048] Please refer to Figure 1 shown. Figure 1 is shown as a schematic diagram of the host and the memory. The host 100 includes a computer 110 and an input / output (I / O) device 120. The computer 110 includes a microprocessor 111, a random access memory (RAM) 112, a data transfer interface 113, and a system bus 114. The input / output device 120 can include a mouse, a keyboard, a display, and a printer.

[0049] Please refer to Figure 1As shown, in an embodiment of the present invention, the memory 200 is electrically connected to other components of the host 100 through the data transmission interface 113. Data can be written into the memory 200 or read from the memory 200 through the operation of the microprocessor 111, the random access memory 112, and the input / output device 120. For example, the memory 200 can be a rewritable non-volatile memory such as a USB flash drive, a memory card, or a solid state drive (SSD).

[0050] Please refer to Figure 1 As shown, in an embodiment of the present invention, the host 100 is any system that can substantially cooperate with the memory 200 to store data. Although in this exemplary embodiment, the host 100 is illustrated as a computer system, however, in some embodiments, the host 100 can be a system such as a digital camera, a video camera, a communication device, an audio player, or a video player. For example, when the host 100 is a digital camera, the rewritable non-volatile memory is an SD card, an MMC card, a memory stick, a CF card, or an embedded storage device used by it. The embedded storage device includes an embedded multimedia card, and the embedded multimedia card is directly electrically connected to the substrate of the host 100.

[0051] Please refer to Figure 2 As shown, Figure 2 Shown as Figure 1 a block diagram of the memory 200 in. The memory 200 includes a connector 201, a memory controller 202, and a rewritable non-volatile memory module 203.

[0052] Please refer to Figure 2As shown, in one embodiment of the present invention, the connector 201 is compatible with the Serial Advanced Technology Attachment standard. The connector 201 can also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) standard, the Peripheral Component Interconnect Express (PCI Express) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the Memory Stick (MS) interface standard, the Multi Media Card (MMC) interface standard, the Compact Flash (CF) interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards.

[0053] Please refer to Figure 2 As shown, in one embodiment of the present invention, the memory controller 202 is used to execute a plurality of logic gates or control instructions implemented in hardware form or firmware form, and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 203 according to the instructions of the host 100.

[0054] Please refer to Figure 2 As shown, in one embodiment of the present invention, the rewritable non-volatile memory module 203 is electrically connected to the memory controller 202 and is used to store the data written by the host 100. The rewritable non-volatile memory module 203 has physical blocks. The physical blocks can belong to the same memory die or different memory dies. Each physical block has a plurality of physical pages, and each physical page has at least one physical sector, where the physical pages belonging to the same physical block can be independently written and simultaneously erased. For example, each physical block is composed of 128 physical pages, and each physical page has 8 physical sectors. That is to say, in the example where each physical sector is 512 bytes, the capacity of each physical page is 4 Kilobytes (KB). However, in one embodiment, each physical block can be composed of 64 physical pages, 256 physical pages, or any other number of physical pages.

[0055] Please refer to Figure 2As shown, a physical block is the smallest unit to be erased. That is, each physical block contains the minimum number of storage units that are erased together. A physical page is the smallest programmable unit. That is, a physical page is the smallest unit for writing data. However, in some embodiments, the smallest unit for writing data may also be a physical sector or other sizes. Each physical page generally includes a data bit area and a redundant bit area. The data bit area is used to store user data, and the redundant bit area is used to store system data (e.g., error checking and correction codes).

[0056] Please refer to Figure 2 As shown, in an embodiment of the present invention, the rewritable non-volatile memory module 203 is a multi-level cell (MLC) NAND flash memory module. In other embodiments, the rewritable non-volatile memory module 203 may also be a single-level cell (SLC) NAND flash memory module, other flash memory modules, or other memory modules with the same characteristics.

[0057] Please refer to Figure 3 As shown, Figure 3 Shown as Figure 2 a block diagram of the memory controller in. The memory controller 202 includes a memory management circuit 2022, a host interface 2023, and a memory interface 2026.

[0058] Please refer to Figure 3 As shown, in an embodiment of the present invention, the memory management circuit 2022 is used to control the overall operation of the memory controller 202. Specifically, the memory management circuit 2022 has a plurality of control instructions, and when the memory 200 operates, these control instructions will be executed to perform operations such as data writing, reading, and erasing.

[0059] Please refer to Figure 3 As shown, in an embodiment of the present invention, the control instructions of the memory management circuit 2022 are implemented in the form of firmware. For example, the memory management circuit 2022 has a microprocessor unit and a read-only memory, and these control instructions are burned into this read-only memory. When the memory 200 operates, these control instructions will be executed by the microprocessor unit to perform operations such as data writing, reading, and erasing.

[0060] Please refer to Figure 3As shown, in some embodiments, the control instructions of the memory management circuit 2022 may also be stored in a specific area of the rewritable non-volatile memory module 203 in the form of program code (for example, the system area dedicated to storing system data in the memory module). In addition, the memory management circuit 2022 has a microprocessor unit, a read-only memory, and a random access memory. This read-only memory has drive code, and when the memory controller 202 is enabled, the microprocessor unit first executes this drive code segment to load the control instructions stored in the rewritable non-volatile memory module 203 into the random access memory of the memory management circuit 2022. After that, the microprocessor unit runs these control instructions to perform operations such as data writing, reading, and erasing. Of course, the control instructions of the memory management circuit 2022 may also be implemented in a hardware form.

[0061] Please refer to FIG. In an embodiment of the present invention, the host interface 2023 is electrically connected to the memory management circuit 2022 and is used to receive and identify the instructions and data transmitted by the host 100. That is, the instructions and data transmitted by the host 100 will be transmitted to the memory management circuit 2022 through the host interface 2023. In this embodiment, the host interface 2023 is compatible with the SATA standard. Of course, the host interface 2023 may also be compatible with the PATA standard, IEEE1394 standard, PCI Express standard, USB standard, SD standard, MS standard, MMC standard, CF standard, IDE standard, or other suitable data transmission standards.

[0062] Please refer to Figure 3 As shown, the memory interface 2026 is electrically connected to the memory management circuit 2022 and is used to access the rewritable non-volatile memory module 203. That is, the data to be written to the rewritable non-volatile memory module 106 will be converted into a format acceptable to the rewritable non-volatile memory module 203 through the memory interface 2206.

[0063] Please refer to Figure 3 As shown, the memory controller 202 further includes a buffer memory 2025, a power management circuit 2021, and an error checking and correction circuit 2024. The buffer memory 2025 is electrically connected to the memory management circuit 2022 and is used to temporarily store data and instructions from the host 100 or data from the rewritable non-volatile memory module 203. The power management circuit 2021 is electrically connected to the memory management circuit 2022 and is used to control the power supply of the memory controller 202.

[0064] Please refer to Figure 3As shown, in an embodiment of the present invention, the error checking and correcting circuit 2024 is electrically connected to the memory management circuit 2022 and is used to execute an error checking and correcting program to ensure the correctness of data. Specifically, when the memory management circuit 2022 receives a write instruction from the host 100, the error checking and correcting circuit 2024 generates a corresponding error checking and correcting code (ECC Code) for the data corresponding to this write instruction, and the memory management circuit 2022 writes the data corresponding to this write instruction and the corresponding error checking and correcting code into the rewritable non-volatile memory module 203. After that, when the memory management circuit 2022 reads data from the rewritable non-volatile memory module 203, it will simultaneously read the error checking and correcting code corresponding to this data, and the error checking and correcting circuit 2024 will execute an error checking and correcting program on the read data according to this error checking and correcting code

[0065] Please refer to Figure 4 As shown, in an embodiment of the present invention, the memory management circuit 2022 of the memory controller 202 logically groups physical blocks (0) to physical block (N) into a data area 204, a blank area 205, a system area 206, and a replacement area 207

[0066] Please refer to Figure 4 As shown, in an embodiment of the present invention, the physical blocks logically belonging to the data area 204 and the blank area 205 are used to store data from the host 100. Specifically, the physical blocks in the data area 204 are regarded as physical blocks storing data, and the physical blocks in the blank area 205 are used to replace the physical blocks in the data area 204. That is to say, when receiving a write instruction and the data to be written from the host 100, the memory management circuit 2022 extracts a physical block from the blank area 205 and writes the data into the extracted physical block to replace the physical block in the data area 204

[0067] Please refer to Figure 4 As shown, in an embodiment of the present invention, the physical blocks logically belonging to the system area 206 are used to record system data. For example, the system data includes the manufacturer and model of the rewritable non-volatile memory module, the number of physical blocks of the rewritable non-volatile memory module, the number of physical pages of each physical block, etc

[0068] Please refer to Figure 4As shown, in an embodiment of the present invention, the physical blocks logically belonging to the replacement area 207 are used for the bad physical block replacement program to replace the damaged physical blocks. Specifically, if there are still normal physical blocks in the replacement area 207 and the physical blocks in the data area 204 are damaged, the memory management circuit 2022 will extract the normal physical blocks from the replacement area 207 to replace the damaged physical blocks.

[0069] Please refer to Figure 5 As shown, in an embodiment of the present invention, the memory 200 includes a cache area 210 and a storage area 220, and the cache area 210 is connected to the storage area 220. The memory 200 can be a solid-state drive, for example, a solid-state drive without dynamic random access memory, that is, a DRAM-Less SSD.

[0070] Please refer to Figure 5 As shown, in this embodiment, the cache area 210 includes a secondary mapping table 211 and a dynamic mapping table 212. The secondary mapping table 211 can correspond to the primary mapping table 222 in the storage area 220. At the same time, a storage space 221 is also set in the storage area 220. The storage space 221 is, for example, a storage block (block) or a physical block. The memory 200 reads or writes based on a page, but the erase operation can only be based on a storage block. The erase operation means setting all bits of this block to "1". Before erasing, the flash memory controller needs to first copy the valid data in this storage block to a blank page in another block. The valid data in the storage block refers to the data saved in this block that has not been modified, and this part of the data may be read. The invalid data in the storage block refers to the data saved in this block that has been modified, and this part of the data cannot be read. The primary mapping table 222 contains the mapping relationship between all logical addresses and corresponding physical addresses, and manages the segmented writing and reading of logical addresses.

[0071] Please refer to Figures 5 - 6 As shown, in this embodiment, the primary mapping table 222 includes multiple logical address segments, for example Figure 6 shows logical address segment 0, logical address segment 1, logical address segment 2, logical address segment 3, and logical address segment 4. The logical lengths of logical address segments 0 to 4 are the same. For example, logical address segment 0 is, for example, from logical address 0 to logical address 9, logical address segment 1 is, for example, from logical address 10 to logical address 19, logical address segment 2 is, for example, from logical address 20 to logical address 29, logical address segment 3 is, for example, from logical address 30 to logical address 39, and logical address segment 4 is, for example, from logical address 40 to logical address 49. From Figure 6It can be seen that the logical address segment 0 corresponds to the physical address 3211 corresponding to the logical address (N) to the physical address 3212 corresponding to the logical address (N + the number of logical addresses within the segment - 1). The physical address 3211 corresponding to the logical address (N) to the physical address 3212 corresponding to the logical address (N + the number of logical addresses within the segment - 1) is also the storage space corresponding to the logical address segment 0. The storage space can be used to store data and storage mapping relationships. It should be noted that the number of logical addresses within the segment represents the number of logical addresses included in this logical address segment.

[0072] Please refer to Figures 5 - 6 As shown, in this embodiment, the secondary mapping table 211 includes a plurality of static mapping units, such as static mapping units 2111 to 2115. The static mapping units 2111 to 2115 all have a flag bit and a physical address segment, and the physical address segment is used to index the mapping relationship in the logical address segment. For example, the status of the flag bit in the static mapping unit 2111 is the first status, that is, the status of the flag bit is 0. At the same time, the static mapping unit 2111 also includes a physical address segment 0, and the physical address segment 0 corresponds to the logical address segment 0 in the primary mapping table 222. Similarly, the status of the flag bit in the static mapping unit 2112 is the first status, that is, the status of the flag bit is 0. At the same time, the static mapping unit 2112 also includes a physical address segment 1, and the physical address segment 1 corresponds to the logical address segment 1 in the primary mapping table 222. In this embodiment, since the secondary mapping table 211 is located in the buffer area 310, the buffer area 210 has a flash translation layer (FTL). The flash translation layer is used to store the correspondence between the logical address of the data and the actual address. Therefore, the flash translation layer is used to convert the logical address in the write data request or read data request sent by the system controller into the actual address of the data in the solid-state drive. Therefore, when the logical address is input, the physical address segment corresponding to the logical address can be found from the secondary mapping table 211, and then the logical address segment can be found in the primary mapping table 222, so as to write data into the storage space. In this embodiment, the first status means that the logical address segment index area is located in the primary mapping table.

[0073] Please refer to Figure 5 and Figure 7 As shown, in an embodiment of the present invention, a plurality of dynamic mapping units 2121 are also provided in the buffer area 210. The plurality of dynamic mapping units 2121 can form a dynamic mapping table 212. Among them, the dynamic mapping table 212 is, for example, a hash linked list, and each dynamic mapping unit 2121 is a mapping relationship node, such as Figure 7Each figure represents a mapping relation node. When performing a data writing operation, the controller applies for at least one dynamic mapping unit 2121 to temporarily store the mapping relation between the logical address range and the physical address range of the data. Multiple dynamic mapping units 2121 are connected together to form a hash linked list. And in each hash linked list, the dynamic mapping units 2121 with the same logical address segment are located in the same vertical linked list, as Figure 7 shown, the same figure represents the dynamic mapping units 2121 with the same logical address segment.

[0074] Due to limited cache resources, the size of the dynamic mapping table is limited. While writing data, it is necessary to timely flush the mapping relation stored in the dynamic mapping unit to ensure that the number of blank dynamic mapping units is sufficient.

[0075] Please refer to Figure 2 and Figure 9 shown, for the memory provided by the present invention, the rewritable non-volatile memory module may store program instructions, and the memory controller runs the program instructions to implement the above-mentioned control method of a memory. And the present invention provides a control method of a memory, including steps S1 - S7.

[0076] S1. Divide the dynamic mapping units into multiple groups according to the number of dynamic mapping units.

[0077] S2. When writing data, apply for a blank dynamic mapping unit to store the mapping relation between the logical address range and the physical address range of the data, and set a group number for the dynamic mapping unit.

[0078] S3. According to the group number, judge whether the mapping relation stored in the previously applied dynamic mapping unit has been flushed to the storage area. If the mapping relation stored in the previously applied dynamic mapping unit has not been flushed, then execute step S4. Flush the mapping relation stored in the previously applied dynamic mapping unit; if the mapping relation stored in the previously applied dynamic mapping unit has been flushed, then execute step S5.

[0079] S5. Judge whether the blank dynamic mapping units are sufficient. If the blank dynamic mapping units are sufficient, then execute step S7. Perform data writing; if the dynamic mapping units are not sufficient, then execute step S6. Flush the mapping relation stored in the dynamic mapping unit with the longest vertical length in the dynamic mapping table, and execute step S7. Perform data writing.

[0080] Please refer to Figure 7 and Figure 9As shown, in an embodiment of the present invention, in step S1, the dynamic mapping table 212 includes, for example, a plurality of dynamic mapping units 2121, and the dynamic mapping units 2121 are interconnected to form the dynamic mapping table 212. And the dynamic mapping units 2121 with the same logical address segmentation are located in the same vertical linked list, and a plurality of vertical linked lists are connected to form the dynamic mapping table 212. As Figure 7 shown, the dynamic mapping units 2121 with the same logical address segmentation are represented by the same graph. In this embodiment, in the buffer 210, the buffer size is limited, so the size of the dynamic mapping table 212 set in the buffer is also limited. In a specific embodiment of the present invention, the buffer includes, for example, M dynamic mapping units 2121, and the M dynamic mapping units 2121 are divided into A groups. In each group, the number of dynamic mapping units 2121 is equal, for example, B, then M = A × B. And within each group, the grouping numbers of the dynamic mapping units 2121 are the same, and the number of each grouping number is B. In this embodiment, the grouping number is, for example, i, and the value range of i is [1, A], and i is an integer. The number of each i is B.

[0081] Please refer to Figure 7 and Figure 8 As shown, in an embodiment of the present invention, each dynamic mapping unit 2121 stores the logical address range and physical address range of the written data, and a flag bit is set. In this embodiment, the flag bit is the grouping number of the dynamic mapping unit 2121. And the group number of each dynamic mapping unit 2121 is not fixed. When writing data, each dynamic mapping unit 2121 is numbered according to the order of data writing.

[0082] Please refer to Figure 9 and Figure 10 As shown, in an embodiment of the present invention, when executing step S2, it can be specifically executed according to steps S21 - S24.

[0083] S21. The host sends a write command and data.

[0084] S22. The memory stores the data in the buffer.

[0085] S23. Apply for at least one blank dynamic mapping unit to store the mapping relationship between the logical address range and physical address range of the data.

[0086] S24. Determine the group to which the dynamic mapping unit belongs according to the order of applying for the dynamic mapping unit.

[0087] Please refer to Figure 7 and Figure 10As shown, in an embodiment of the present invention, in step S23, when applying for storing the mapping relationship of at least one blank dynamic mapping unit for the logical address range and the physical address range, specifically, the logical address of the data may include a logical start address and a data length. The logical start address indicates the position of the logical address segment where the data is located, and the data length represents the size of the data. For example, when the logical start address is 22 and the data length is 6, then the logical start address is located in logical address segment 3, and the size of the data is the length from logical address 22 to logical address 28. The physical address of the data may include a physical start address and a data length. When the written data belongs to different logical address segments, multiple blank dynamic mapping units may be applied for storing the mapping relationship of the logical address range and the physical address range. This method of storing the mapping relationship of the logical address range and the physical address range can use one mapping relationship node to store consecutive logical addresses. This storage method has no impact on random writes, but for sequential writes, it can greatly reduce the occupation of mapping relationship nodes.

[0088] Please refer to Figure 7 and Figure 10 As shown, in an embodiment of the present invention, in step S24, when determining the group to which the dynamic mapping unit 2121 belongs, the grouping number of the current dynamic mapping unit 2121 can be determined according to the current application record, that is, the group to which the current dynamic mapping unit 2121 belongs. Specifically, when the grouping number is first set for the applied dynamic mapping unit 2121, the grouping number of the dynamic mapping unit 2121 is, for example, 1 and it belongs to the first group. In the subsequent process of continuously writing data, when the number of dynamic mapping units 2121 with a grouping number of 1 reaches B, when setting the grouping number for the applied dynamic mapping unit 2121 again, the grouping number of the dynamic mapping unit 2121 is set to 2 and it belongs to the second group. Until the grouping number of the applied dynamic mapping unit 2121 is A and the number of A reaches B, then the grouping number of the dynamic mapping unit 2121 is set to 1 again, forming a cycle.

[0089] Please refer to Figure 7 As shown, in an embodiment of the present invention, the dynamically mapped units 2121 marked as shaded parts of the graph, for example, have the same grouping number, that is, a plurality of sequentially applied dynamic mapping units 2121.

[0090] Please refer to Figure 9 and Figure 11 As shown, in an embodiment of the present invention, when performing step S3, the specific process of determining whether the mapping relationship stored in the previously applied dynamic mapping unit is flushed to the storage area can be executed according to steps S31 - S34.

[0091] S31. Determine whether the current dynamic mapping unit is the first dynamic mapping unit in the group. If so, execute step S32; otherwise, execute step S34.

[0092] S32. Determine whether all dynamic mapping units exist in the group whose group number differs from the current group number by a preset value. If so, execute step S33; otherwise, execute step S34.

[0093] S33. Set the flag bit of the downbrush cache mapping relationship to the first flag bit, and execute step S34 after setting.

[0094] S34. Set the group number for the current dynamic mapping unit and update the number of dynamic mapping units in the group.

[0095] Please refer to Figure 7 and Figure 11 As shown, in an embodiment of the present invention, in step S32, when determining whether there are dynamic mapping units in the group whose group number differs from the current group number by a preset value, the preset value can be set according to specific requirements. In an embodiment of the present invention, for example, the group number of the current dynamic mapping unit 2121 is 2, and when the preset value is 3, it is determined whether there is a dynamic mapping unit in the group with the group number 5. In another embodiment of the present invention, if the group number of the current dynamic mapping unit is, for example, A, and the preset value is 3, it is determined whether there is a dynamic mapping unit in the group with the group number 3. In step S34, after storing the mapping relationship of the data using the dynamic mapping unit 2121, the number of the current dynamic mapping unit 2121 is added to the number of the original dynamic mapping unit 2121 until the number of dynamic mapping units 2121 in the group reaches B, and then switch to the next group.

[0096] Please refer to Figure 9 and Figure 12 As shown, in an embodiment of the present invention, in step S5, the specific process of determining whether the blank dynamic mapping units are sufficient can be executed according to steps S51 - S53.

[0097] S51. Determine whether the current blank dynamic mapping units are sufficient. If so, execute step S53; if not, execute step S52.

[0098] S52. Set the flag bit of the downbrush cache mapping relationship to the second flag bit, and execute step S53.

[0099] S53. Add the current dynamic mapping unit to the dynamic mapping table.

[0100] Please refer to Figure 7 and Figure 12As shown, in an embodiment of the present invention, it is determined whether there are sufficient blank dynamic mapping units currently, that is, it is determined whether the number of blank dynamic mapping units is less than a preset number. This preset number can be flexibly set according to specific circumstances, as long as it can ensure that there are enough blank dynamic mapping units to store the mapping relationship between the logical address range and the physical address range each time data is written. After adding the dynamic mapping unit 2121 to the dynamic mapping table 212, the status of the static mapping unit in the secondary mapping table can be updated. When the logical address of the input data is 2 and the length of the data is 3, the logical address of the data is also the logical starting address of the data. Therefore, the logical address of the input data is located in the logical address segment 0. Thus, the controller applies for a blank dynamic mapping unit 0, and then stores the logical address and data length of the data in the dynamic mapping unit 2121. Since the logical address of the data is located in the logical address segment 0, and since the static mapping unit 2111 in the secondary mapping table corresponds to the logical address segment 0, the flag bit in the static mapping unit 2111 in the secondary mapping table is updated from the first state to the second state, that is, the status of the flag bit is updated from "0" to "1". In this embodiment, the second state means that the logical address segment index area is located in the dynamic mapping table 212. In this embodiment, the physical address of the data can represent the position where the data is stored in the storage space, and the content of the data can be read according to the physical address of the data. After completing the update of the dynamic mapping table 212, the normal data writing process can be carried out.

[0101] Please refer to Figure 9 and Figure 13 As shown, in an embodiment of the present invention, in steps S5 and S6, when it is necessary to flush the cache mapping relationship, the process of flushing the cache mapping relationship is triggered by setting the flag bit of the cache mapping relationship to be flushed. In this embodiment, the process of flushing the cache mapping relationship can be executed together with the data writing process, or can be executed after the data writing is completed according to the state of the memory controller. Specifically, the process of flushing the cache mapping relationship specifically includes steps S71 - S6.

[0102] S71. Detect whether the flag for flushing the cache mapping relationship is set.

[0103] S72. When the flag for flushing the cache mapping relationship is set, obtain the reason why the flag for flushing the cache mapping relationship is set. When the setting is caused by the mapping relationship stored in the previously applied dynamic mapping unit not being flushed, execute steps S73 - S74; when the setting is caused by insufficient blank dynamic mapping units, execute steps S75 - S76.

[0104] In the vertical list of all dynamic mapping units whose lower brush differs from the current group number by a preset value, the mapping relationship between the logical address range and the physical address range stored in all dynamic mapping units.

[0105] S74. Determine whether there are dynamic mapping units in the group whose difference from the current group number is the preset value. If so, return to step S73; otherwise, end the process.

[0106] S75. Lower brush the mapping relationship stored in the dynamic mapping unit with the longest vertical length in the dynamic mapping table.

[0107] S76. Determine whether there are sufficient current blank dynamic mapping units. If so, end the process; otherwise, return to step S75.

[0108] Please refer to Figure 13 As shown, in an embodiment of the present invention, when obtaining the reason for setting the flag of the lower brush memory mapping relationship, when the flag bit of the lower brush storage mapping tube relationship is the first flag bit, it indicates that the reason for setting the flag of the lower brush cache mapping relationship is that the mapping relationship stored in the previously applied dynamic mapping unit 2121 has not been lower brushed. When the flag bit of the lower brush storage mapping tube relationship is the second flag bit, it indicates that the reason for setting the flag of the lower brush cache mapping relationship is that there are insufficient blank dynamic mapping units.

[0109] In the present invention, the first flag bit and the second flag bit are flag bits set in program instructions when lower brushing dynamic mapping units for different reasons. They can be arbitrarily set and defined according to program instructions. The first flag bit is set to, for example, 1 to mark that the setting is caused by the mapping relationship stored in the previously applied dynamic mapping unit not being lower brushed. The second flag bit is set to, for example, 2 to mark that the setting is caused by insufficient blank dynamic mapping units.

[0110] Please refer to Figure 7 and Figure 13 As shown, in an embodiment of the present invention, in step S73, in the group whose difference from the current group number is the preset value, the preset value can be a difference set according to actual requirements. In a specific embodiment of the present invention, taking the preset value as, for example, 3, when the current group is 2, determine whether the mapping relationship between the logical address range and the physical address range stored in all dynamic mapping units in the fifth group in the previous round has been lower brushed. If not, lower brush the mapping relationship between the logical address range and the physical address range stored in all dynamic mapping units in the vertical list of all dynamic mapping units with the group number 5. As Figure 7As shown, when the dynamic mapping unit with a grouping number of 5 is, for example, the dynamic mapping unit marked by the shadow in the figure, then the mapping relationship between the logical address range and the physical address range stored in all the dynamic mapping units in the vertical list where the subordinate shadow-marked dynamic mapping unit is located. That is, the mapping relationship between the logical address range and the physical address range stored in all the dynamic mapping units in the first, second, fourth, and fifth column vertical lists is flushed. After the mapping relationship between the logical address range and the physical address range stored in the dynamic mapping unit, the dynamic mapping unit becomes a blank dynamic mapping unit, and the flag bit is cleared, that is, the grouping number of the dynamic mapping unit is cleared, and when waiting to be applied for use again, the grouping number is set again in accordance with the application order.

[0111] Please refer to Figure 7 and Figure 13 As shown, in an embodiment of the present invention, in step S75, when it is judged whether the current blank dynamic mapping units are sufficient, that is, whether the number of blank dynamic mapping units is less than a preset number. This preset number can be flexibly set according to specific circumstances, and it can be ensured that there are enough blank dynamic mapping units to store the mapping relationship between the logical address range and the physical address range each time data is written. Specifically, the preset number is, for example, any number such as 5, 10, 15, or 20. In this embodiment, to ensure that the number of blank dynamic mappings is sufficient, at least, for example, 2 groups of blank dynamic mapping units can be reserved by grouping, that is, the number of blank dynamic mapping units is greater than or equal to 2B. When the setting is caused by insufficient blank dynamic mapping units, the mapping relationship stored in the dynamic mapping unit with the longest vertical length in the dynamic mapping table is flushed. In a specific embodiment, if the dynamic mapping table enters Figure 7 As shown, then it is only necessary to flush the mapping relationship between the logical address range and the physical address range stored in all the dynamic mapping units in the first column vertical list. When the flushing of the mapping relationship is completed for the first time, it is then judged in step S76 whether the blank dynamic mapping units are sufficient. If the blank dynamic mapping units are still not sufficient, then in accordance with Figure 7 As shown, then the mapping relationship between the logical address range and the physical address range stored in all the dynamic mapping units in the fifth column vertical list is flushed. Steps S75 and S76 are repeatedly executed until the number of blank dynamic mapping units is approximately the preset value.

[0112] In summary, the present invention provides a control method for a memory, a memory, and a storage system. In the present invention, a first-level mapping table is set in the storage area. The first-level mapping table includes a plurality of logical address segments, which can be arranged according to numbers, and each logical address segment can correspond to a storage space in the storage area. At the same time, a second-level mapping table and a dynamic mapping table are set in the buffer area. The second-level mapping table includes a plurality of static mapping units, one static mapping unit corresponds to one logical address segment, each static mapping unit includes a flag bit and a physical address segment, the physical address segment corresponds to the logical address segment, and the flag bit has a first state and a second state. When a write data operation is performed, the controller applies for at least one dynamic mapping unit, and at the same time forms a dynamic mapping table with the logical addresses of the data in a plurality of dynamic mapping units in the same logical address segment, and updates the state of the flag bit in the second-level mapping table. And when writing data, first judge whether the mapping relationship stored in the first applied dynamic mapping unit has been flushed to the storage area. If the mapping relationship stored in the first applied dynamic mapping unit has not been flushed, then flush the mapping relationship stored in the first applied dynamic mapping unit; if the mapping relationship stored in the first applied dynamic mapping unit has been flushed, then judge whether the idle dynamic mapping units are sufficient. If the idle dynamic mapping units are sufficient, then perform data writing; when the dynamic mapping units are not sufficient, then flush the mapping relationship stored in the dynamic mapping unit with the longest vertical length in the dynamic mapping table, and perform data writing.

[0113] The above description is only a preferred embodiment of the present application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by the specific combination of the above technical features. At the same time, it should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, a technical solution formed by mutually replacing the above features with (but not limited to) technical features with similar functions disclosed in the present application.

[0114] Except for the technical features described in the specification, the remaining technical features are known to those skilled in the art. To highlight the innovative features of the present invention, the remaining technical features are not described herein again.

Claims

1. A control method for a memory, characterized in that, comprising: setting a dynamic mapping table in a buffer area, and the dynamic mapping table includes a plurality of dynamic mapping units; when writing data, applying for a mapping relationship between a logical address range and a physical address range for at least one of the dynamic mapping units to store data, and setting a group number for the dynamic mapping unit according to the order in which the dynamic mapping unit is applied; judging, according to the group number, whether the mapping relationship stored in the dynamically mapped unit applied first is flushed to the storage area. If the mapping relationship stored in the dynamically mapped unit applied first is not flushed, then flushing the mapping relationship stored in the dynamically mapped unit applied first; if the mapping relationship stored in the dynamically mapped unit applied first has been flushed, then judging whether there are sufficient blank dynamically mapped units; and when there are sufficient blank dynamically mapped units, performing data writing; when there are not enough blank dynamically mapped units, flushing the mapping relationship stored in the dynamically mapped unit in the vertical linked list with the longest vertical length in the dynamic mapping table, and performing data writing.

2. The control method for a memory according to claim 1, characterized in that, the dynamically mapped units with the same logical address segments are located in the same vertical linked list.

3. The control method for a memory according to claim 1, characterized in that, the control method for the memory further includes: dividing the dynamic mapping units into multiple groups according to the number of the dynamic mapping units, and each group of dynamic mapping units includes an equal number of the dynamic mapping units, and the group numbers of the dynamic mapping units within the same group are the same.

4. The control method for a memory according to claim 1, characterized in that, when applying for the dynamic mapping unit, the control method for the memory further includes: determining the group to which the dynamic mapping unit belongs according to the order of applying for the dynamic mapping unit.

5. The control method for a memory according to claim 4, characterized in that, when judging whether the mapping relationship stored in the dynamically mapped unit applied first is flushed to the storage area, the control method for the memory includes the following steps: judging whether the current dynamic mapping unit is the first dynamic mapping unit in the group. If so, judging whether there is a dynamic mapping unit in the group with a group number different from the current group number by a preset value. If so, setting the flag for flushing the cache mapping relationship to a first flag.

6. The control method for a memory according to claim 4, characterized in that, after setting the group number for the dynamic mapping unit, the control method for the memory further includes: updating the number of the dynamic mapping units in the group.

7. The control method for a memory according to claim 1, characterized in that, when there are not enough blank dynamically mapped units, the control method for the memory further includes: setting the flag for flushing the cache mapping relationship to a second flag.

8. The control method for a memory according to claim 1, characterized in that, When the available blank dynamic mapping units are sufficient, the control method of the memory further includes: adding the current dynamic mapping unit to the dynamic mapping table.

9. The control method of the memory according to claim 1, wherein, when the mapping relationship stored in the previously applied dynamic mapping unit is not flushed and the mapping relationship stored in the previously applied dynamic mapping unit is flushed, the control method of the memory includes: flushing the mapping relationships between the logical address ranges and the physical address ranges stored in all the dynamic mapping units in the vertical list where all the dynamic mapping units with a preset difference from the current group number are located.

10. A memory, wherein, comprising: a rewritable non-volatile memory module storing program instructions; a memory controller electrically connected to the rewritable non-volatile memory module, and the memory controller runs the program instructions to implement the control method of the memory according to claim 1.

11. A storage system, wherein, comprising: a host; a memory connected to the host, wherein the memory includes: a rewritable non-volatile memory module storing program instructions; a memory controller electrically connected to the rewritable non-volatile memory module, and the memory controller runs the program instructions to implement the control method of the memory according to claim 1.

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