Size of an extended memory unit

Abstract

Various embodiments described herein provide for expanding the size of memory cells of a memory device, such as the size of codewords of a page of the memory device, where the memory device can be included in a memory system. In particular, some embodiments implement expanding (e.g., increasing) the size of the memory cells (e.g., codewords) to store more data, such as more host data (e.g., user data) and protection data (e.g., parity data) within the memory cells, while using memory cell storage slots (e.g., codeword storage slots in a page) that are smaller than the expanded memory cells.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory devices, and more specifically, to extending the size of memory cells of a memory device, such as a page or a codeword of a page of a memory device. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can use a memory sub-system to store data at a memory device and to retrieve data from a memory device. SUMMARY

[0003] One embodiment of the present disclosure provides a system comprising: a memory device; and a processing device operatively coupled to the memory device, the processing device configured to perform operations comprising: receiving, from a host system, a first request to read stored data from a first memory address, the first memory address corresponding to a first memory location on the memory device; and in response to receiving the first request, processing the first request by: accessing a truncated version of a first memory cell from the first memory location, the truncated version of the first memory cell including a first portion of first protection data for a non-truncated version of the first memory cell and not including a second portion of the first protection data for the non-truncated version of the first memory cell; performing an error correction process on the truncated version of the first memory cell based on the first portion of the first protection data; determining whether the error correction process performed on the truncated version of the first memory cell would trigger an error correction failure; and in response to determining that the error correction process performed on the truncated version of the first memory cell would trigger the error correction failure: accessing the second portion of the first protection data from a different memory cell of the memory device; generating the non-truncated version of the first memory cell by combining the truncated version of the first memory cell accessed from the first memory location with the second portion of the first protection data accessed from the different memory cell; and performing the error correction process on the non-truncated version of the first memory cell based on the first portion of the first protection data and the second portion of the first protection data.

[0004] Another embodiment of the present disclosure provides a method comprising: receiving, at a memory system from a host system, a request to write host data to a memory address, the memory address corresponding to a memory location on a memory device of the memory system; and in response to receiving the request, processing the request by: generating a non-truncated version of a memory cell based on a selected portion of the host data, the non-truncated version of the memory cell including a truncated version of the memory cell, the truncated version including a first portion of protection data for the non-truncated version of the memory cell, the non-truncated version of the memory cell including a second portion of protection data for the non-truncated version of the memory cell; storing the truncated version of the memory cell from the non-truncated version of the memory cell to the memory location, the truncated version of the memory cell not including the second portion of protection data; and storing the second portion of protection data from the non-truncated version of the memory cell to a selected location in a different memory cell of the memory device.

[0005] Yet another embodiment of the present disclosure provides at least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processing device of a memory system, cause the processing device to perform operations comprising: processing a request from a host system to read stored data from a memory address, the memory address corresponding to a memory location on a memory device of the memory system, the processing the request comprising: performing an error correction process on a truncated version of a memory cell accessed from the memory location, the truncated version of the memory cell including a first portion of protection data for a non-truncated version of the memory cell and not including a second portion of protection data for the non-truncated version of the memory cell, the error correction process being performed on the truncated version of the memory cell based on the first portion of protection data; determining whether the error correction process performed on the truncated version of the memory cell would trigger an error correction failure; and in response to determining that the error correction process performed on the truncated version of the memory cell would trigger the error correction failure: accessing the second portion of protection data from a different memory cell of the memory device; generating the non-truncated version of the memory cell by combining the truncated version of the memory cell accessed from the memory location with the second portion of protection data accessed from the different memory cell; and performing the error correction process on the non-truncated version of the memory cell based on the first portion of protection data and the second portion of protection data. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description, taken in conjunction with the accompanying drawings, in which like reference numerals refer to like elements throughout. The drawings, however, are not intended to limit the present disclosure to the particular embodiment presented in the drawings.

[0007] Figure 1 is a block diagram illustrating an example computing system including a memory subsystem, in accordance with some embodiments of the present disclosure.

[0008] Figures 2 to 5 is a flowchart of an example method for performing operations on a memory cell having an extended size, in accordance with some embodiments of the present disclosure.

[0009] Figure 6 is a diagram illustrating an example of a memory cell having an extended size, in accordance with some embodiments of the present disclosure.

[0010] Figure 7 is a diagram illustrating an example of a truncated memory cell and associated protection data, and an example of performing an error correction process, in accordance with some embodiments of the present disclosure.

[0011] Figure 8A , 8B and 8C provide interaction diagrams illustrating interactions between components of a computing environment in the context of some embodiments, in which methods for processing requests to read stored data from a memory cell having an extended size, as described herein, are performed.

[0012] Figure 9 is a block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0013] Various aspects of this disclosure relate to the size of memory cells in an extended memory device, such as the codeword size of a page in the memory device, wherein the memory device may be contained within a memory system (e.g., a memory subsystem). Specifically, some embodiments implement an extension (e.g., an increase) in the size of the memory cells (e.g., codewords) to store more data, such as more host data (e.g., user data) and protection data (e.g., parity data), within the memory cells, while using memory cell storage slots (e.g., codeword storage slots in pages) smaller than the extended memory cells. Hereinafter, a memory cell with an extended size may be referred to as an extended memory cell. Some embodiments truncate the extended memory cell such that the protection data of the extended memory cell is broken (e.g., divided into at least two parts), but the resulting truncated memory cell (e.g., a truncated codeword containing a portion of the protection data) is suitable for placement within its designated memory cell storage slot. In addition, various embodiments implement support for extended (e.g., increased size) codewords while at least maintaining the encoding rate of the codewords (e.g., while continuing to provide a sufficient amount of parity data, such as low-density parity check (LDPC) data, within the codeword), which enables the memory device to meet or maintain target durability, retention, and reliability characteristics.

[0014] The memory subsystem can be a storage device, a memory module, or a combination of both. The following text combines... Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may use a memory subsystem that includes one or more components, such as a memory device for storing data (e.g., host data). The host system may send access requests to the memory subsystem to store data at the memory subsystem and to read data from the memory subsystem.

[0015] The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on memory devices at the memory subsystem, read data from memory devices at the memory subsystem, or write / read constructs (e.g., commit and complete queues) relative to memory devices at the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may contain logical address information (e.g., logical block address (LBA), namespace) of the host data, which is the location associated between the host system and the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., error correction code (ECC) codeword, parity check code), data version (e.g., the period used to distinguish the data being written), a validity bitmap (which LBAs or logical pass units contain valid data), and so on.

[0016] The memory subsystem can initiate media management operations, such as write operations, on host data stored on the memory device. For example, as part of a garbage collection management operation, the firmware of the memory subsystem can rewrite previously written host data from its location on the memory device to a new location. The rewritten data (e.g., as booted via firmware) is referred to below as "garbage collection data".

[0017] In the following text, "user data" broadly refers to host data and garbage collection data. "System data" refers to data generated and / or maintained by the memory subsystem for performing operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical-to-physical memory address mapping tables, also referred to herein as L2P tables), data from logging, high-speed scratchpad data, etc.

[0018] The memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. For some memory devices, a block is the smallest erasable area. Each block consists of a set of pages. Each page consists of a set of memory cells storing data bits. The memory device can be a raw memory device (e.g., NAND) that is managed externally, for example, by an external controller. The memory device can be a managed memory device (e.g., managed NAND) that is a raw memory device combined with a local embedded controller for memory management within the same memory device package.

[0019] Traditionally, the page size of NAND flash memory devices has been set based on industry-standard sector sizes. Generally, each page comprises a specific number of codewords, where each codeword includes a payload portion (or load) for storing a certain number of data sectors (or sectors), which include data from the host system (or host data), and where each codeword includes a non-payload portion that may contain protection data (e.g., parity data) for protecting (e.g., facilitating error correction) all data in the codeword. The non-payload portion may also contain protection information, cyclic redundancy check (CRC) data, and metadata (e.g., security metadata and firmware metadata), etc. In the past, the sector size used by the host system was set to 512 bytes, and therefore, NAND flash memory devices have been configured with 16-kilobyte pages comprising four 4096-byte codewords, where each codeword includes a payload, each storing eight 512-byte sectors and including parity data to facilitate error correction of the host data stored in the payload.

[0020] However, recent advancements in memory technology (e.g., for enterprise markets and applications) have led to an increase in sector size and payload size per codeword (e.g., increasing to 4588 bytes of payload per codeword to store eight 528-byte sectors), which typically reduces the space available in the codeword for storing protection data (e.g., LDPC data). For example, in cases where the protection data includes parity data, the reduced space may prevent the codeword from storing enough parity data to meet the target error correction capability (e.g., to meet error correction requirements). For instance, in cases where the parity data includes LDPC data, the reduced space available within the codeword for storing the LDPC data will result in a higher coding rate (CR) for the codeword. As used herein, the coding rate of a codeword is the ratio between the size of the codeword's payload and the total size of the codeword. For example, in the case of a 4588-byte codeword containing a 4224-byte payload, the coding rate of the codeword would be 0.929. The encoding rate of a codeword can be used as an indicator of the data protection (e.g., error protection) provided by the protection data (e.g., parity data) stored within the codeword for bit errors within the codeword. Generally, the lower the encoding rate of a codeword, the more data protection (e.g., error protection) is provided to the codeword through its protection data. Therefore, as LDPC data decreases within the codeword, the resulting encoding rate for the codeword will be higher, and the data protection (e.g., error correction) provided by the LDPC data for the data within the codeword will be lower. For some applications, such as enterprise applications, it is necessary to have an encoding rate of less than 0.929 for the codewords of pages in NAND flash memory devices, as this ensures that the NAND flash memory device meets specific reliability (e.g., adequately overcoming the bit error rate of the memory device), durability, and expected data retention. Disadvantageously, increasing the sector and payload size within the codeword without increasing the codeword size within the page or the page size itself can result in a higher encoding rate and reduced / weakened data protection.

[0021] The aspects of this disclosure address the above and other shortcomings by expanding the size of memory cells (e.g., pages or codewords within pages) of a memory device without increasing the size of the memory cell storage slots used to store the memory cells on the memory device. Memory cells whose size is expanded according to embodiments may be referred to as expanded memory cells. For example, some embodiments expand the size of the codewords in a page (to produce expanded codewords) while avoiding an increase in the size of the codeword storage slots within the page or an increase in the encoding rate of the codewords. The various embodiments described herein facilitate the size of expanded memory cells by truncating the expanded memory cells (e.g., expanded codewords) to produce truncated versions of the expanded memory cells (truncated memory cells), wherein the truncated memory cells are produced such that they can be placed in memory cell storage slots (e.g., codeword storage slots), and wherein the protection data (e.g., parity data) of the expanded memory cells is broken (e.g., divided) into a first portion and a second portion of the protection data, and the second portion of the protection data is stored separately from the truncated memory cells.

[0022] For example, embodiments may generate an extended codeword larger than a target codeword storage slot (of a page in the memory device), wherein the extended codeword will be stored. Embodiments may divide (e.g., split or deconstruct) the extended codeword into a first codeword portion and a second codeword portion, the first codeword portion including at least a payload for storing host data and a first portion of protection data for the extended codeword (e.g., a first portion of parity data), the second codeword portion including a second portion of protection data for the extended codeword (e.g., a second portion of parity data), wherein the first and second portions of protection data form the original protection data for the extended codeword. Embodiments may store the first codeword portion in the target codeword storage slot and may store the second codeword portion in another codeword storage slot (e.g., on the same page or a different page). In this manner, the extended codewords described herein can be truncated (e.g., shortened) to fit into their intended (target) codeword storage slot (e.g., a codeword storage slot with a size of 1 / 4 page), and the protective data resulting from the truncation (broken / divided) can be stored elsewhere (accessed when error correction operations are required on the extended codeword). As a result, various embodiments enable the codeword to be expanded in size to support larger payload or sector sizes (larger than would be possible with conventional techniques), while the extended codeword can use the existing size of the codeword storage slot (e.g., a 1 / 4 page-sized storage slot initially configured to fit a 1 / 4 page-sized codeword), and the target encoding rate for the extended codeword can still be achieved. Depending on the embodiment, the second codeword portion resulting from the truncation of the extended codeword (including the second portion of the protective data) can be stored in a different codeword storage slot within the same page as the first codeword portion resulting from the truncation, or in a codeword storage slot on a different page of the memory device. Additionally, a second codeword portion resulting from multiple truncated codewords (e.g., on the same page or on different pages) can be stored together in one or more codeword storage slots on different pages.

[0023] Various embodiments perform operations (e.g., read or write operations) on the extended memory cell based on storing a truncated version of the extended memory cell separately in a first memory cell storage slot at a memory location of the memory device and a portion of the protection data of the extended memory cell in a second memory cell storage slot (e.g., at the same or another memory location of the memory device). For example, after the extended codeword has been partitioned and a first codeword portion (including a first portion of host data and protection data) and a second codeword portion (including a second portion of protection data) have been stored separately on the memory device, the extended codeword can be read from the memory device by initially processing the first codeword portion using the first portion of protection data and not using the second codeword portion (e.g., not using the second portion containing protection data), using an error correction component (error correction engine, such as an LDPC engine). For example, where the error correction component is expected to receive and process the extended codeword, the error correction component may only have the first codeword portion and be instructed / configured to ignore the remaining portion of the extended codeword corresponding to the second codeword portion (e.g., to avoid error correction on the remaining portion of the extended codeword). When the error correction component does not detect a data error, various embodiments avoid the need to access and use the second codeword portion to correct the extended codeword. However, in response to the error correction component detecting a data error in the first codeword portion (e.g., detecting an LDPC trigger or LDPC failure) and failing to correct the data error using the first portion of the protection data, the second codeword portion (containing the second portion of the protection data) can be accessed from the memory device, and the first codeword portion can be processed by the error correction component, but together with the second codeword portion (e.g., the error correction component is instructed / configured to stop ignoring the remaining portion of the extended codeword corresponding to the second codeword portion). In doing so, the error correction component is able to perform error correction on the extended codeword using the second portion of the protection data (e.g., the second portion of parity data) from the second codeword portion accessed after the error correction component failed. While some embodiments relating to codewords are described herein, the various embodiments described herein can be applied to different types of memory cells used on memory devices.

[0024] By using certain embodiments, protection data (e.g., parity data) stored in memory cells (e.g., codewords within pages) of existing memory devices (e.g., NAND-type memory devices) can be expanded without reconfiguring the size of the memory cell storage slots (e.g., codeword storage slots) on the memory device used to store the expanded memory cells. In doing so, a strong coding rate for the codewords can be achieved (e.g., by using sufficient LDPC parity to make the CR less than 0.929) without increasing the size of the codeword storage slots within the pages of the memory device.

[0025] As used herein, a memory cell may include a page of a memory device or a codeword of a page. As used herein, a portion of a page may store multiple codewords. For example, a page may store four codewords (e.g., four 4KB codewords). As used herein, the encoding rate may include the ratio between the total host data stored within a codeword (e.g., the size of a host sector within the codeword) and the total size of the codeword. As used herein, protection data may include parity check data, such as LDPC data. As used herein, LDPC represents an instance of an error correction algorithm. Various embodiments may use other types of error correction algorithms, such as erasure coding algorithms. As used herein, an extended memory cell may refer to a memory cell (e.g., a codeword slot) having a size larger than a separate memory cell storage slot (e.g., a codeword storage slot) used to store individual memory cells (e.g., codewords) on a memory device. As used herein, an untruncated version of a memory cell (untruncated memory cell) may refer to all of its memory cells. An untruncated version of a memory cell may include: a truncated version of the memory cell containing a first portion of protective data; and a second portion of the protective data for the untruncated version of the memory cell. As used herein, a truncated version of the memory cell (truncated memory cell) may refer to a version of the memory cell containing a first portion of protective data but truncated to fit into a memory cell storage slot of a memory device.

[0026] This article discloses some examples of the size of memory cells in extended memory devices, as described herein.

[0027] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0028] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, secure digital cards (SD cards), embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0029] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0030] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0031] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 120 uses memory subsystem 110 to, for example, write data to and read data from memory subsystem 110.

[0032] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, SATA interfaces, peripheral component interconnect high-speed (PCIe) interfaces, universal serial bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), small computer system interface (SCSI), dual data rate (DDR) memory bus, dual in-line memory module (DIMM) interfaces (e.g., DIMM socket interfaces supporting dual data rate (DDR)), open NAND flash interface (ONFI), dual data rate (DDR), low power dual data rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further use an NVM high-speed (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0033] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0034] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory can perform bit storage based on changes in volume resistance in conjunction with stackable cross-grid data access arrays. Furthermore, crosspoint non-volatile memory allows for in-place write operations, unlike many flash-based memories, where non-volatile memory cells can be programmed without prior erasing. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0035] Each memory device 130 may include one or more arrays of memory cells. One type of memory cell, such as SLC, may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), TLC, four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0036] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0037] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0038] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0039] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although... Figure 1 The instance memory subsystem 110 is shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0040] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) associated with memory device 130 and physical memory addresses (e.g., physical block addresses). The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system 120 into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0041] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0042] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0043] The memory subsystem controller 115 includes an extended memory cell operator 113 that implements or facilitates operation of extended memory cells on memory devices of the memory subsystem 110, such as memory devices 130 and 140. In some embodiments, the memory subsystem controller 115 receives a request from the host system 120 to read stored data (e.g., stored host data) from a memory address, where the memory address corresponds to a memory location on the memory device (e.g., 130, 140). In response to the request, the memory subsystem controller 115 may process the request to read the stored data from the memory address. In some embodiments, the memory subsystem controller 115 processes the request to read stored data from the memory address by accessing a truncated version of a selected memory cell (truncated memory cell) from the memory location, wherein the truncated version of the selected memory cell is accessed from a selected location in the memory location (e.g., a selected memory cell storage slot). The truncated version of the selected memory cell may include a first portion of protective data for the untruncated version of the selected memory cell and may not include a second portion of the protective data for the untruncated version of the selected memory cell. Selected memory cell refers to an extended memory cell whose size is set to be larger than the size of the memory cell storage slot (memory location) intended to store the extended memory cell; as described herein, the extended memory cell may be truncated by the embodiments described herein to fit into the memory cell storage slot. The memory location may include pages of a memory device (e.g., 130, 140), and the memory location may include multiple memory cell storage slots (e.g., codeword storage slots), such as four codeword storage slots each comprising 1 / 4 of a page.

[0044] According to various embodiments, the memory subsystem controller 115 processes requests to read stored data from a memory address by: performing an error correction process on a truncated version of a selected memory cell (truncated memory cell) accessed from the memory location; and determining whether the error correction process performed on the truncated version will trigger an error correction failure. In some embodiments, the error correction process is performed on the truncated version of the selected memory cell based on a first portion of protection data (included in the truncated version). In some embodiments, the truncated version of the selected memory cell does not include a second portion of protection data for the untruncated version of the selected memory cell (untruncated memory cell). In some embodiments, the error correction process is performed on the truncated version of the selected memory cell such that the error correction process uses the first portion of protection data (from the truncated version) and ignores the second portion of protection data not included in the truncated version of the selected memory cell. For example, the error correction process may include LDPC processing (e.g., performed via the LDPC decoder of the memory system), and low-density parity checking processing may ignore the second portion of protection data not included in the truncated version of the selected memory cell by using erase zeros (e.g., phantom zeros). The protection data may include parity data for selecting an untruncated version of the memory cell. For example, the parity data may include LDPC data, and the error correction process may include LDPC processing. Error correction failure may include a failure of the error correction process to correct a truncated version of the selected memory cell based on a first portion of the protection data. For example, error correction failure may include an LDPC failure (e.g., a hard LDPC failure).

[0045] In some embodiments, in response to determining that an error correction process performed on a truncated version of the selected memory cell will not trigger an error correction failure, the memory subsystem controller 115 generates at least a partial response to the host system 120 for the request using the result of the error correction process performed on the truncated version of the selected memory cell. The result of the error correction process performed on the truncated version may include a truncated version of the selected memory cell to which one or more error corrections (e.g., an error-corrected version of the selected memory cell) are applied based on a first portion of the protection data. Therefore, the response to the host system 120 may include host data from the payload portion of the truncated version of the selected memory cell provided via the result of the error correction process (e.g., with error correction applied). Alternatively, according to some embodiments, in response to determining that an error correction process performed on a truncated version of the selected memory cell will trigger an error correction failure, the memory subsystem controller 115 accesses a second portion of the protection data from different memory cells of the memory device. Different memory cells may be stored in the same memory location (e.g., the same page) of the memory device (e.g., 130, 140) as the location where a truncated version of the selected memory cell is stored, or different memory cells may be stored in different memory locations (e.g., different pages) of the memory device. According to various embodiments, the memory subsystem controller 115 generates (e.g., reconstructs) an untruncated version of the selected memory cell (untruncated) by combining a truncated version of the selected memory cell accessed from the memory location with a second portion of protection data accessed from the different memory cells. Combining the truncated version of the selected memory cell with the second portion of the protection data may include attaching (e.g., reattaching) the protection data to the truncated version of the selected memory cell, thereby fully restoring or reconstructing the selected memory cell.

[0046] Subsequently, in some embodiments, the memory subsystem controller 115 performs an error correction process on an untruncated version of the selected memory cell based on a first portion and a second portion of the protection data. In some embodiments, the memory subsystem controller 115 determines whether the error correction process performed on the untruncated version of the selected memory cell will trigger an error correction failure. According to some embodiments, in response to determining that the error correction process performed on the untruncated version of the selected memory cell will not trigger an error correction failure, the memory subsystem controller 115 generates at least a partial response to the host system 120 for the request using the result of the error correction process performed on the untruncated version of the selected memory cell. The result of the error correction process performed on the untruncated version may include an untruncated version of the selected memory cell for which one or more error corrections (e.g., an error-corrected version of the selected memory cell) have been applied based on the first portion and the second portion of the protection data. Therefore, the response to the host system 120 may include host data from the payload portion of the untruncated version of the selected memory cell provided via the result of the error correction process (e.g., with error correction applied).

[0047] In some embodiments, the memory subsystem controller 115 receives a request from the host system 120 to write host data to a memory address, where the memory address corresponds to a memory location on a memory device (e.g., 130, 140). In response to the request, the memory subsystem controller 115 may process the request to write host data to the memory address. In some embodiments, the memory subsystem controller 115 processes the request to write host data to the memory address by generating an untruncated version of the selected memory cell based on a selected portion of the host data, wherein the untruncated version of the selected memory cell includes (e.g., partially represented) a truncated version of the selected memory cell containing a first portion of protective data, and includes (e.g., partially represented) a second portion of the protective data for the untruncated version of the selected memory cell. Based on the untruncated version of the selected memory cell, embodiments may divide the untruncated version of the selected memory cell into a truncated version of the selected memory cell and a second portion of the protective data for the untruncated version of the selected memory cell. As described herein, the size of the truncated version of the selected memory cell may be set such that it can be placed within a memory cell storage slot of a memory location of the memory device. Generating an untruncated version of a selected memory cell may include truncating (e.g., partitioning) the untruncated version of the selected memory cell. Based on the untruncated version of the selected memory cell, in some embodiments, the memory subsystem controller 115 stores a truncated version of the selected memory cell in a memory location, wherein the truncated version of the selected memory cell includes a first portion of protection data for the untruncated version of the selected memory cell, but does not include a second portion of the protection data for the untruncated version of the selected memory cell. According to various embodiments, the truncated version of the selected memory cell is stored in a memory cell storage slot of the memory location. For various embodiments, the size of the memory cell storage slot (for storing the truncated version of the selected memory cell) is too small to store the untruncated version of the selected memory cell, but the size of the truncated version of the selected memory cell is less than or equal to the size of the memory cell storage slot. Additionally, based on the untruncated version of the selected memory cell, in some embodiments, the memory subsystem controller 115 stores a second portion of the protection data in a selected location within a different memory cell of the memory device. In this way, the second portion of the protection data can be stored separately from the truncated version of the selected memory cell. In various embodiments, different memory cells are stored in a first memory cell storage slot that is different from a second memory cell storage slot used to store a truncated version of the selected memory cell. The first memory cell storage slot and the second memory cell storage slot may have the same memory location (e.g., the same page of memory device 130), or each may be part of a separate memory location (e.g., two different pages of memory device 130).Different memory cells (e.g., different codewords) used to store a second portion of protection data for selecting a non-truncated version of a memory cell can be used to store a second portion of protection data for multiple, different non-truncated memory cells (e.g., multiple non-truncated codewords), wherein the second portion of protection data for each non-truncated memory cell is stored at a different (e.g., specified) location within the different memory cells.

[0048] refer to Figure 6 Examples of untruncated versions of page memory cells (e.g., untruncated codewords) and memory cell storage slots (e.g., codeword storage slots) are shown and described. References Figure 7 An example is shown and described where the second part of the stored and protected data in the truncated memory cell (e.g., truncated codeword) is stored separately from the truncated memory cell.

[0049] Depending on the embodiment, selecting a memory cell may include a first codeword, and different memory cells may include a second (different) codeword. For example, selecting a memory cell may include a first codeword comprising a payload portion and a non-payload portion, wherein the payload portion is configured to store data provided by host system 120 (e.g., host data), and wherein the non-payload portion includes a first portion of protection data. The non-payload portion may also include at least one of, for example, protection information of the first codeword, cyclic redundancy check (CRC) data of the first codeword, and metadata of the first codeword. Different memory cells may include a second codeword, wherein the second codeword may be configured to store a second portion of protection data for a plurality of codewords in the memory device (e.g., 130, 140), and wherein the plurality of codewords include the first codeword. For example, the second codeword may include a payload portion and a non-payload portion, wherein the payload portion may be configured to store a second portion of protection data for a plurality of codewords, and wherein the non-payload portion may be configured to store non-host data (e.g., protection information, CRC data, metadata, etc.) for the second codeword.

[0050] Figures 2 to 5 This is a flowchart of an example method for performing operations on a memory cell having an extended size, according to some embodiments of the present disclosure. Methods 200, 300, 400, and 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, at least one of methods 200, 300, 400, and 500 is performed by… Figure 1The memory subsystem controller 115 is executed based on the extended memory cell operator 113. Alternatively or additionally, in some embodiments, at least one of methods 200, 300, 400, and 500 is at least partially performed by… Figure 1 The local media controller 135 of the memory device 130 executes the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are used in every embodiment. Other process flows are also possible.

[0051] Now for reference Figure 2 Method 200, in some embodiments, represents a method for processing a request from a host system (e.g., 120) to read stored data from a memory address, wherein the memory address corresponds to a memory location (e.g., a page) on a memory device (e.g., 130, 140) of a memory system (e.g., memory subsystem 110). At operation 220, a processing means (e.g., processor 117 of memory subsystem controller 115) performs an error correction process on a truncated version of the memory cell accessed from the memory location, wherein the truncated version of the memory cell includes a first portion of protection data for the untruncated version of the memory cell and does not include a second portion of protection data for the untruncated version of the memory cell. In some embodiments, the memory cell includes a first codeword, wherein the first codeword includes a payload portion and a non-payload portion, and wherein the payload portion is configured to store data provided by the host system, and the non-payload portion includes protection data. For example, the non-payload portion may include at least one of, for example, protection information of the first codeword, cyclic redundancy check (CRC) data of the first codeword, and metadata of the first codeword. Additionally, in some embodiments, the protection data may include parity data for an untruncated version of the memory cell. For example, the parity data may include low-density parity check (LDPC) data for an untruncated version of the memory cell, wherein the LDPC data may be used by LDPC processing to check and correct errors in the untruncated version of the memory cell.

[0052] Although not in Figure 2 As shown, but a truncated version of the memory cell can be accessed from the memory location before operation 220. At operation 222, the processing means (e.g., processor 117) determines whether the error correction process performed on the truncated version of the memory cell will trigger an error correction failure.

[0053] In some embodiments, operation 220 (performing an error correction process on a truncated version of the memory cell) includes performing an error correction process on a truncated version of the memory cell such that the error correction process uses a first portion of the protection data (from the truncated version) and ignores a second portion of the protection data not included in the truncated version of the memory cell. Operation 220 may, for example, cause (e.g., by instruction or configuration) the error correction process to use the first portion of the protection data and ignore the second portion of the protection data (that is, the truncated version of the memory cell does not include the second portion of the protection data). In various embodiments, the error correction process includes a low-density parity check (LDPC) process, and the LDPC process ignores the second portion of the protection data not included in the truncated version of the memory cell by using zero erasure (e.g., phantom zero).

[0054] In response to the determination (at operation 222) that the error correction process performed on the truncated version of the memory cell would trigger an error correction failure, at operation 224, the processing means (e.g., processor 117) accesses a second portion of the protection data (for the untruncated version of the memory cell) from different memory cells of the memory means (e.g., 130, 140). At operation 226, the processing means (e.g., processor 117) generates an untruncated version of the memory cell by combining the truncated version of the memory cell accessed from the memory location with the second portion of the protection data accessed from the different memory cells (accessed at operation 224). In some embodiments, the memory cell includes a first codeword, and the different memory cells include a second codeword. For example, the different codewords may be configured to store a second portion of the protection data for a plurality of codewords of the memory means (e.g., 130, 140), wherein the plurality of codewords includes the first codeword. Subsequently, at operation 228, the processing device (e.g., processor 117) performs an error correction process on the untruncated version of the memory cell generated at operation 226 based on the first portion and the second portion of the protection data. (See reference...) Figure 3 Further related additional operations are shown and described (based on operation 228).

[0055] Although not in Figure 2 As shown, in response to determining (at operation 222) that the error correction process performed on the truncated version of the memory cell will not trigger an error correction failure, the processing device (e.g., processor 117) generates at least a partial response using the result of the error correction process performed on the truncated version of the memory cell.

[0056] Now for reference Figure 3 Method 300, in some embodiments, is similar to Figure 2Method 200, wherein operations 320, 322, 324, 326, and 328 are similar to operations 220, 222, 224, 226, and 228 of method 200, respectively. At operation 302, a processing device (e.g., processor 117 of memory subsystem controller 115) receives a request from the host system to read stored data from a memory address, wherein the memory address corresponds to a memory location on a memory device (e.g., 130, 140). In response to receiving the request at operation 302, the processing device (e.g., processor 117) processes the request by performing operations 318 to 332 (at operation 304).

[0057] At operation 318, the processing device (e.g., processor 117) accesses a truncated version of a memory cell from a memory location, wherein the truncated version of the memory cell includes a first portion of protection data for the untruncated version of the memory cell and does not include a second portion of protection data for the untruncated version of the memory cell. Operations 320 to 328 are performed after operation 318, wherein operations 320, 322, 324, 326, and 328 are respectively similar to Figure 2 Method 200 includes operations 220, 222, 224, 226, and 228.

[0058] At operation 330, the processing device (e.g., processor 117) determines whether an error correction process performed on the untruncated version of the memory cell (at operation 328) will trigger an error correction failure. In response to determining (at operation 330) that the error correction process performed on the untruncated version of the memory cell will not trigger an error correction failure, the processing device (e.g., processor 117) may stop processing the request to read the stored data and may notify the host system (e.g., 120) of the request processing failure. Alternatively, in response to determining (at operation 330) that the error correction process performed on the untruncated version of the memory cell will not trigger an error correction failure, at operation 332, the processing device (e.g., processor 117) uses the result produced by the error correction process performed on the untruncated version of the memory cell (at operation 328) to generate at least a partial response to the host system (e.g., 120) for the request (received at operation 302). Finally, the resulting response may be provided (e.g., sent from) by the memory system (e.g., memory subsystem 110) to the host system (e.g., 120). The result of the error correction process performed on the untruncated version of the memory cell may include an untruncated version of the memory cell to which error correction has been applied (the error correction process applies a first portion of the protection data from the truncated version of the memory cell and a second portion of the protection data accessed from a different memory cell).

[0059] Similarly, Figure 3As shown, in response to determining (at operation 328) that the error correction process performed on the truncated version of the memory cell will not trigger an error correction failure, at operation 332, the processing device (e.g., processor 117) generates at least a partial response using the result produced by the error correction process performed on the truncated version of the memory cell (at operation 320). The result produced by the error correction process performed on the truncated version of the memory cell may include the truncated version of the memory cell to which error correction (the second part applied by the error correction process without using the protection data) has been applied.

[0060] Now for reference Figure 4 Method 400, in some embodiments, represents a method for processing a request from a host system (e.g., 120) to write host data to a memory address, wherein the memory address corresponds to a memory location (e.g., a page) on a memory device (e.g., 130, 140) of a memory system (e.g., memory subsystem 110). At operation 420, a processing means (e.g., processor 117 of memory subsystem controller 115) generates an untruncated version of the memory cell based on a selected portion of the host data provided by the host system (e.g., 120), wherein the untruncated version of the memory cell includes: a truncated version of the memory cell, which includes a first portion of protection data for the untruncated version of the memory cell; and a second portion of protection data for the untruncated version of the memory cell. In some embodiments, the memory cell includes a first codeword, wherein the first codeword includes a payload portion and a non-payload portion, and wherein the payload portion is configured to store a selected portion of the host data. In some embodiments, the non-payload portion includes at least one of the following: protection information of the first codeword, cyclic redundancy check (CRC) data of the first codeword, and metadata of the first codeword. In other embodiments, the non-payload portion does not include protection data.

[0061] At operation 422, the processing device (e.g., processor 117) stores a truncated version of the memory cell from the untruncated version of the memory cell (generated at operation 420) to a memory location, wherein the truncated version of the memory cell does not include the second portion of the protection data. Additionally, at operation 424, the processing device (e.g., processor 117) stores the second portion of the protection data from the untruncated version of the memory cell (generated at operation 420) to selected locations in different memory cells of the memory device. In some embodiments, the different memory cells include second (different) codewords, wherein the second codewords can be configured to store the second portion of the protection data for a plurality of codewords of the memory device, and wherein the plurality of codewords includes the first codeword.

[0062] Now for reference Figure 5Method 500, in some embodiments, is similar to Figure 4 Method 400, wherein operations 520, 522, and 524 are similar to operations 420, 422, and 424 of method 400, respectively. At operation 502, a processing device (e.g., processor 117 of memory subsystem controller 115) receives a request from the host system to write host data to a memory address, where the memory address corresponds to a memory location on a memory device (e.g., 130, 140). In response to receiving the request at operation 502, the processing device (e.g., processor 117) processes the request by performing operations 520 through 524 (at operation 504).

[0063] Figure 6 This is a diagram illustrating an example of a memory cell 600 with an extended size according to some embodiments of the present disclosure. Depending on the embodiment, the memory cell 600 may be expanded in size to accommodate more payload data (e.g., host data), more non-payload data (e.g., protection information or metadata), or both. Memory cell 600 represents a non-truncated version of memory cell 600 prior to storage according to the various embodiments described herein, and memory cell storage slot 610 represents a storage slot intended for storing a truncated version (e.g., a page) of memory cell 600. As shown, memory cell 600 has a size larger than memory cell storage slot 610 (e.g., having a 1 / 4 page size), and therefore, various embodiments may truncate memory cell 600 and break down (e.g., divide at 620) protection data (as described herein) to allow memory cell 600 to fit into memory cell storage slot 610. For example, in the case where the memory cell storage slot of a page has a size of 4588 bytes, memory cell 600 (its untruncated version) can have a size of 4652 bytes, wherein the truncated version of the memory cell can have a size of 4588 bytes, and 64 bytes not included in memory cell 600 (e.g., including protection data) can be stored in different memory cells as described herein. Figure 6In this embodiment, memory cell 600 includes a payload portion 602 for storing host data and a non-payload portion 604 for storing non-host data that may contain protection data. For example, as shown, non-payload portion 604 may store protection information (PI), cyclic redundancy check (CRC) data calculated across all data (specified as HCRC) of memory cell 600, metadata (MD) of memory cell 600, cyclic redundancy check (CRC) data calculated across payload portion 602, and parity data 606 of memory cell 600, wherein parity data 606 may represent protection data of memory cell 600. In some embodiments, memory cell 600 implements codewords with an extended size larger than the codeword storage slots to be used for storing codewords. According to the various embodiments described herein, parity data 606 is broken (e.g., divided) into a first portion and a second portion such that: a truncated version of memory cell 600, including the first portion of parity data 606 but excluding the second portion of parity data 606, can be placed in memory cell storage slot 610; and the second portion of parity data 606 can be stored in another memory cell storage slot (e.g., for possible future retrieval in the event that error correction of the truncated version of memory cell 600 using only the first portion of parity data 606 fails).

[0064] Figure 7 This is a diagram illustrating examples of truncating memory cells and associated protection data according to some embodiments of the present disclosure, as well as examples of performing an error correction process. Specifically, Figure 7 A superpage 702 is shown comprising sixteen pages (pages 0 to 15) including memory devices (e.g., 130, 140). As shown, each page in superpage 702 includes four memory cell storage slots for storing four memory cells (MUs). For example, page 0 of superpage 702 is shown storing memory cells 0 to 3 (MU0 to MU3), and page 15 of superpage 702 is shown storing memory cells 60 to 63 (MU60 to MU63). According to various embodiments, each of memory cells 0 to 62 (MU0 to MU62) may represent a truncated version of a memory cell (e.g., similar to 600) larger than the memory cell storage slots provided by the pages of superpage 702. For example, in Figure 7 In this context, each memory cell storage slot may have a size sufficient to store a truncated version of a memory cell with a size of 4588 bytes, which may not include the 64 bytes of data in the untruncated version of the memory cell. Additionally, according to various embodiments, such as... Figure 7As shown, a portion of the protected data not included in each of the memory cells 0 to 62 (MU0 to MU64) is stored in memory cell 63 (MU63) (e.g., stored in a corresponding location within memory cell 63).

[0065] Figure 7 Examples 700A and 700B illustrate the operation of processing a request to read (at least partially) data stored in memory cell 2 (MU2) of page 0 of superpage 702. Now refer to... Figure 7 In embodiment 700A, when processing the request, various embodiments access MU2, which is a truncated version of a storage memory cell (having 4588 bytes). Various embodiments then perform an error correction process on the accessed MU2 (which does not include a portion of the protection data) using an error correction component 720 of the memory system (e.g., an LDPC decoder). At 712, Figure 7 The diagram illustrates how a MU2 containing a first portion (714) of protected data and excluding a second portion (716) of protected data (64 bytes missing from MU2) can be fed as an erase or phantom zero into an error correction component 720, which allows the error correction component 720 (e.g., an LDPC decoder) to ignore error correction for the missing bytes of the second portion of protected data.

[0066] Now for reference Figure 7 In 700B, the error correction process performed on MU2 causes the error correction component 720 to trigger an error correction failure (as described herein), and various embodiments access a second portion (716) of the protection data (64 bytes) associated with (corresponding to) MU2 from memory cell 63 (MU63). Various embodiments then use the error correction component 720 of the memory system (e.g., an LDPC decoder) to perform an error correction process on the combination of the accessed MU2 (which does not include the second portion of the protection data) and the second portion of the protection data accessed from MU63. As described herein, the combination of the accessed MU2 and the second portion of the protection data (accessed from MU63) can represent a non-truncated version of the memory cell. At 718, Figure 8A This illustrates how the combination of the accessed MU2 and the second portion of the protection data accessed from MU63 is fed into the error correction component 720. If the error correction process performed on the combination of the accessed MU2 and the second portion of the protection data accessed from MU63 does not cause the error correction component 720 to trigger an error correction failure (as described herein), the result of the error correction component processing (e.g., the output of the error correction component 720) can be used to generate at least a partial response to a request to read the stored data.

[0067] When using MU2 codewords, performing error correction on a 4588-byte MU2 codeword without its second 64-byte protection data (at 712) results in a coding rate of 0.93, which may lead to a lower-than-expected rate of error correction failures (e.g., hard LDPC failures). In contrast, performing error correction on a 4588-byte MU2 codeword with its second 64-byte protection data (at 716) results in a coding rate of 0.92, representing a stronger correction capability than 0.93 and a reduced rate of error correction failures (e.g., hard LDPC failures).

[0068] Figures 8A to 8C , 8B 8C provides interaction diagrams illustrating interactions between components of a computing environment in the context of some embodiments, wherein methods as described herein for processing requests to read stored data from memory cells of extended size are performed. The operation of the methods may be performed by processing logic, which may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing means), or a combination thereof. In some embodiments, the methods are performed by a host system (e.g., 120), a memory subsystem controller (e.g., 115), a memory device (e.g., 130 or 140), or a combination thereof. Although operations are shown in a particular order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are used in every embodiment. Figure 8A In the context of the example shown, the host system may include host system 120, the memory subsystem controller may include memory subsystem controller 115, and the memory device may include memory device 140.

[0069] like Figure 8BAs shown, at operation 802, host system 120 sends a request to read stored data from a memory address to memory subsystem 110, where the memory address corresponds to a memory location of memory device 140. At operation 810, memory subsystem controller 115 receives the request from host system 120. In response to receiving the request, memory subsystem controller 115 can process the received request. Specifically, at operation 812, memory subsystem controller 115 accesses a truncated version of the memory cell from the memory location, wherein the truncated version of the memory cell includes a first portion of protection data for the untruncated version of the memory cell, and does not include a second portion of protection data for the untruncated version of the memory cell. At operation 840, memory device 140 grants memory subsystem controller 115 access to the truncated version of the memory cell.

[0070] At operation 814, the memory subsystem controller 115 performs an error correction procedure on a truncated version of the memory cell (accessed from the memory location) based on the first portion of the protection data. Subsequently, at operation 816, the memory subsystem controller 115 determines whether the error correction procedure performed on the truncated version of the memory cell (at operation 814) will trigger an error correction failure.

[0071] In response to the determination (at operation 816) that the error correction process performed on the truncated version of the memory cell would trigger an error correction failure, at operation 818, the memory subsystem controller 115 accesses a second portion of the protection data (for the untruncated version of the memory cell) from different memory cells of the memory device 140. At operation 842, the memory device 140 grants access rights to the different memory cells to the memory subsystem controller 115.

[0072] Now for reference Figure 8C At operation 820, the memory subsystem controller 115 generates an untruncated version of the memory cell by combining a truncated version of the memory cell accessed from a memory location (at operation 812) with a second portion of protection data accessed from a different memory cell (at operation 818). At operation 822, the memory subsystem controller 115 performs an error correction process on the untruncated version of the memory cell based on the first and second portions of the protection data. Subsequently, at operation 824, the memory subsystem controller 115 determines whether the error correction process performed on the untruncated version of the memory cell will trigger an error correction failure.

[0073] Now for reference Figure 9In response to determining (at operation 824) that the error correction process performed on the untruncated version of the memory cell will not trigger an error correction failure, at operation 826, the memory subsystem controller 115 generates at least a partial response to the host system 120 in response to the request received at operation 810. For various embodiments, the memory subsystem controller 115 generates at least a partial response using the result of the error correction process performed on the untruncated version of the memory cell at operation 822. For some embodiments, the response generated at operation 826 may include host data from the payload portion of the selected untruncated version of the memory cell, as provided via the result of the error correction process (e.g., in the case of applied error correction). Subsequently, the memory subsystem controller 115 provides the response (generated at operation 826) to the host system 120 at operation 828. At operation 804, the host system 120 receives a response to the request sent at operation 802.

[0074] Figure 1 An example machine in the form of a computer system 900 is shown, within which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system 900 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 may be used to perform the operations described herein. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0075] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, although a single machine is shown, it should also be understood that the term "machine" includes any set of machines that individually or jointly execute a set (or sets of sets) of instructions to perform any or more of the methods discussed herein.

[0076] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 918, which communicate with each other via a bus 930.

[0077] Processing device 902 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, processing device 902 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. Computer system 900 may further include a network interface device 908 for communication via network 920.

[0078] Data storage device 918 may include machine-readable storage medium 924 (also referred to as computer-readable medium) storing one or more sets of instructions or software 926 embodying any one or more of the methods or functions described herein. Instructions 926 may also reside wholly or at least partially within main memory 904 and / or processing device 902 during execution by computer system 900, which also constitute machine-readable storage medium. Machine-readable storage medium 924, data storage device 918, and / or main memory 904 may correspond to... Figure 1 The memory subsystem 110.

[0079] In one embodiment, instruction 926 includes instructions for implementing the same as those for memory cells having the extended size described herein (e.g., ​ The extended memory unit operator 113) executes instructions corresponding to the functions of the operation. Although the machine-readable storage medium 924 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0080] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. An algorithm here is generally considered to be a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0081] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0082] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, each coupled to a computer system bus, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions.

[0083] The algorithms and demonstrations presented herein are inherently independent of any particular computer or other device. Various general-purpose systems can be used with programs based on the teachings herein, or it may be convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0084] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0085] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A memory system comprising: Memory devices; as well as A processing device operatively coupled to the memory device, the processing device being configured to perform operations including: The host system receives a first request to read stored data from a first memory address, the first memory address corresponding to a first memory location on the memory device; as well as In response to receiving the first request, the first request is processed by the following operations: Access a truncated version of a first memory cell from the first memory location, the truncated version of the first memory cell including a first portion of first protection data for an untruncated version of the first memory cell, and excluding a second portion of the first protection data for the untruncated version of the first memory cell; An error correction process is performed on the truncated version of the first memory cell based on the first portion of the first protection data; Determine whether the error correction process performed on the truncated version of the first memory cell will trigger an error correction failure; as well as In response to determining that the error correction process performed on the truncated version of the first memory cell would trigger an error correction failure: Access the second portion of the first protected data from different memory cells of the memory device; The untruncated version of the first memory cell is generated by combining the truncated version of the first memory cell accessed from the first memory location with the second portion of the first protection data accessed from the different memory cells. as well as The error correction process is performed on the untruncated version of the first memory cell based on the first portion of the first protection data and the second portion of the first protection data.

2. The memory system of claim 1, wherein the operation includes: Determine whether the error correction process performed on the untruncated version of the first memory cell will trigger an error correction failure; as well as In response to determining that the error correction process performed on the untruncated version of the first memory cell will not trigger an error correction failure, at least a partial response to the host system is generated using the result of the error correction process performed on the untruncated version of the first memory cell for the first request.

3. The memory system of claim 2, wherein the result of the error correction process performed on the untruncated version of the first memory cell includes the untruncated version of the first memory cell to which error correction has been applied.

4. The memory system of claim 2, wherein the operation includes: In response to determining that the error correction process performed on the truncated version of the first memory cell will not trigger the error correction failure, the at least partial response is generated using the result of the error correction process performed on the truncated version of the first memory cell.

5. The memory system of claim 1, wherein the first protection data includes the untruncated version of parity data for the first memory cell.

6. The memory system of claim 5, wherein the parity data includes the untruncated version of low-density parity check (LDPC) data for the first memory cell.

7. The memory system of claim 1, wherein the first memory location comprises a page of the memory device.

8. The memory system of claim 1, wherein the first memory unit includes a first codeword, and the different memory units include different codewords.

9. The memory system of claim 1, wherein the first memory cell includes a first codeword, the first codeword including a payload portion and a non-payload portion, the payload portion being configured to store data provided by the host system.

10. The memory system of claim 9, wherein the non-payload portion comprises at least one of the following: protection information of the first codeword, cyclic redundancy check (CRC) data of the first codeword, and metadata of the first codeword.

11. The memory system of claim 1, wherein the different memory cells comprise different codewords, the different codewords being configured to store a second portion of protection data for a plurality of codewords of the memory device.

12. The memory system of claim 1, wherein the error correction process includes a low-density parity check (LDPC) process.

13. The memory system of claim 1, wherein performing the error correction process on the truncated version of the first memory cell comprises: The error correction process is performed on the truncated version of the first memory cell such that the error correction process uses the first portion of the first protection data and ignores the second portion of the first protection data that is not included in the truncated version of the first memory cell.

14. The memory system of claim 13, wherein the error correction process includes a low-density parity check (LDPC) process, and the LDPC process ignores the second portion of the first protection data not included in the truncated version of the first memory cell by erasing zeros.

15. The memory system of claim 1, wherein the operation includes: The host system receives a second request to write host data to a second memory address, the second memory address corresponding to a second memory location on the memory device; as well as In response to receiving the second request, the second request is processed by the following operations: A truncated version of the second memory cell is stored in the second memory location, the truncated version of the second memory cell including a selected portion of the host data, the truncated version of the second memory cell including a first portion of second protection data for the untruncated version of the second memory cell, and not including a second portion of the second protection data for the untruncated version of the second memory cell; as well as The second portion of the second protection data is stored in a selected location within the different memory cells, and the second portion of the first protection data is stored in a different location within the different memory cells.

16. The memory system of claim 15, wherein the second memory cell includes a first codeword, the first codeword including a payload portion and a non-payload portion, the payload portion being configured to store the selected portion of the host data.

17. The memory system of claim 16, wherein the non-payload portion comprises at least one of the following: protection information of the first codeword, cyclic redundancy check (CRC) data of the first codeword, and metadata of the first codeword.

18. The memory system of claim 15, wherein the operation includes: Before storing the truncated version of the second memory cell to the second memory location and storing the second portion of the second protection data to the selected location in the different memory cells, an untruncated version of the second memory cell is generated based on the selected portion of the host data. The untruncated version of the second memory cell includes the truncated version of the second memory cell and includes the second portion of the second protection data.

19. A method for performing memory operations, comprising: The memory system receives a request from the host system to write host data to a memory address, which corresponds to a memory location on the memory device of the memory system. as well as In response to receiving the request, the request is processed through the following operations: An untruncated version of the memory cell is generated based on a selected portion of the host data. The untruncated version of the memory cell includes a truncated version of the memory cell. The truncated version includes a first portion of protection data for the untruncated version of the memory cell. The untruncated version of the memory cell includes a second portion of protection data for the untruncated version of the memory cell. The truncated version of the memory cell is stored from the untruncated version of the memory cell to the memory location, wherein the truncated version of the memory cell does not include the second portion of the protection data; as well as The second portion of the protected data is stored from the untruncated version of the memory cell to a selected location in a different memory cell of the memory device.

20. At least one non-transitory machine-readable storage medium, comprising instructions that, when executed by a processing device of a memory system, cause the processing device to perform operations including: Processing a request from a host system to read stored data from a memory address corresponding to a memory location on a memory device of the memory system, the processing of the request includes: An error correction process is performed on a truncated version of a memory cell accessed from the memory location, the truncated version of the memory cell including a first portion of protection data for an untruncated version of the memory cell and excluding a second portion of protection data for an untruncated version of the memory cell, the error correction process being performed on the truncated version of the memory cell based on the first portion of the protection data; Determine whether the error correction process performed on the truncated version of the memory cell will trigger an error correction failure; as well as The error correction process performed in response to determining that the truncated version of the memory cell will trigger an error correction failure: Access the second portion of the protection data from different memory cells of the memory device; The untruncated version of the memory cell is generated by combining the truncated version of the memory cell accessed from the memory location with the second portion of the protection data accessed from the different memory cells. as well as The error correction process is performed on the untruncated version of the memory cell based on the first portion and the second portion of the protection data.

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