Analytical-Numerical Hybrid Design Method for Class E Power Amplifier

Abstract

The present invention discloses an analytical-numerical hybrid design method for class-E power amplifiers. First, the formulas of class-E power amplifiers under ideal conditions, as well as the ZVS and ZVDS conditions, are used to solve the initial values of the parallel capacitor C, the residual inductor L, the series inductor L0, and the capacitor C0 in the circuit. Then, the incremental error under non-ideal conditions is introduced, and the component parameters in the circuit are optimized through the relaxation iteration technique of equation solving. This method not only avoids the complicated derivations required for the correction of various existing ideal analytical methods, but also is simpler, faster in calculation than pure numerical methods such as optimization and full-circuit equation solving. The simulation and experimental results verify the accuracy and effectiveness of this method. The advantages of this method will be more prominent in the field of high-frequency or radio-frequency power amplifier design that requires more consideration of the parasitic effects of devices and circuits.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design, and relates to a design optimization method for an analog circuit, and in particular to an analytical-numerical hybrid design method for a class E power amplifier. Background Art

[0002] Class E power amplifiers are also called switching power amplifiers. The amplifier tube in the circuit works in a switching state. It has the advantages of high conversion efficiency, simple structure, and high cost performance. Since it was proposed, it has been widely used. Class E power amplifiers that meet the conditions of ZVS (Zero Voltage Switching) and ZVDS (Zero Voltage Derivative Switching) are considered to be the most efficient amplifiers. When the amplifier tube is regarded as an ideal switch, the drain voltage and the current flowing through the drain do not overlap at all, the switching loss is zero, and the theoretical conversion efficiency can reach 100%.

[0003] The traditional design method of Class E power amplifier is to use a set of analytical design equations derived based on a series of ideal assumptions. These assumptions include: the amplifier tube is equivalent to an ideal switch, the quality factor of the load resonant circuit and the choke inductance are large enough so that the current flowing through the load is a pure sine wave with a fundamental frequency, and the power supply current through the choke is DC. However, the actual circuit is obviously different from these ideal assumptions, so the circuit designed in this way cannot meet the ZVS and ZVDS conditions, and there are significant errors, causing the circuit to deviate from the optimal working state and affecting the conversion efficiency. For this reason, how to take into account the influence of various non-ideal factors in the design has long been a problem of concern in the design of Class E power amplifiers.

[0004] In response to the above problems, there are roughly two types of solutions in the prior art. The first is to modify the design equations under ideal conditions: early work mainly took into account the effects of switch on-resistance, finite load loop quality factor, and finite feed inductance in the derivation of ideal design equations. In recent years, the effects of MOS tube gate-drain linear capacitance and drain-source nonlinear parasitic capacitance have been further considered. Although this type of method can derive analytical design equations, it requires complicated derivations; and often one method can only consider the effects of non-ideal effects in one aspect. The second is to use numerical methods: usually using optimization technology to express the ZVS and ZVDS conditions as optimization objective functions or constraints. The advantage of using numerical methods is that various non-ideal parasitic effects can be considered without restriction, but the calculation is more complicated, and the purely numerical method also lacks physical meaning. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention proposes an analytical-numerical hybrid design method for a class E power amplifier, introduces errors into the traditional analytical method, and uses a relaxation iterative technique for solving equations to obtain optimized component parameters.

[0006] The analytical-numerical hybrid design method of the class E power amplifier specifically includes the following steps:

[0007] Step 1: Set the number of iterations k = 0, and determine the parallel capacitance C, the residual inductance L, and the series inductance L by deriving the formula of the class E power amplifier under ideal conditions. 0 and capacitor C 0 The initial value of .

[0008] Step 2: Perform SPICE simulation based on the design values ​​of the circuit components to obtain the fundamental frequency amplitude of the load current With phase φ k , the current i on the choke inductor RFC k (ωt), output current i R k (ωt) and drain current i d k (ωt).

[0009] Calculation of DC current based on ZVDS conditions have:

[0010]

[0011] In actual situations, since the choke inductance is a finite value, the current i on the choke inductance is RFC k (ωt) In addition to the DC component In addition, there is an increment Δi RFC k (ωt):

[0012]

[0013] Due to the quality factor Q of the load circuit L is a finite value, so the output current i R k (ωt) is not a pure fundamental sine wave. The sum of all harmonic components except the fundamental wave is Δi R k (ωt) is:

[0014]

[0015] Considering the numerous parasitic effects of the MOS tube, including on-resistance, nonlinear parasitic capacitance, etc., the voltage is not completely zero when it is turned on. Therefore, the current i flowing through the parallel capacitor C during the period of π≤ωt≤2π when the MOS tube is turned off is c k (ωt) is:

[0016]

[0017] in:

[0018] Δi C k (ωt)=Δi RFC k (ωt)-Δi R k (ωt)-i d k (ωt) (5)

[0019] Δq k (ωt) represents the increment of charge on the parallel capacitor C:

[0020]

[0021] The voltage between the drain and source of the MOS tube is v C k (ωt) is:

[0022]

[0023] in is the voltage across the switch under ideal conditions, v C k (π) and v C k (2π) are the voltage values ​​at the moments ωt=π and ωt=2π respectively obtained according to the simulation results.

[0024] According to the ZVS condition, we have:

[0025]

[0026] Therefore, the iteratively updated phase φ k+1 Need to meet:

[0027]

[0028] Among them, q k (π)=Cv C k (π), T is the period. That is, after iterative update, the fundamental frequency amplitude of the load current With phase φk+1 for:

[0029]

[0030]

[0031] Step 3: If under the simulation conditions of step 2, the difference δ between the simulation value and the ideal value of the switch voltage at t = 1us is k If it is less than the error control requirement ε, the iteration ends and the simulation parameters are output as the component parameters of the class E power amplifier; otherwise, go to step 4.

[0032] Preferably, the error control requirement is ε=0.1%.

[0033] Step 4: Update the base frequency amplitude of the load current according to step 2 With phase φ k+1 , update the parallel capacitor C, residual inductance L, series inductance L 0 and capacitor C 0 Parameters.

[0034] The voltage across the parallel capacitor C is v C k The DC component of (ωt) is still the power supply voltage V DD :

[0035]

[0036] in:

[0037]

[0038] According to formula (12), the updated parallel capacitance Ck is solved +1 .

[0039] Fundamental frequency voltage amplitude across the residual inductance L for:

[0040]

[0041] in:

[0042]

[0043] Therefore, the updated residual inductance L k+1 for:

[0044]

[0045] According to the quality factor and resonance condition, the updated series inductance L is obtained. 0 k+1 and C 0k+1 :

[0046]

[0047]

[0048] Step 5: Set k=k+1 and return to step 2.

[0049] The present invention has the following beneficial effects:

[0050] This method can obtain accurate design component parameters by compensating for the errors in traditional analytical methods and using the relaxation iteration technology of equation solving. This method not only avoids the complicated derivation required for various existing corrections based on ideal analytical methods, but also is simpler and faster than pure numerical methods such as optimization and solving full circuit equations. Simulation and experimental results verify the accuracy and effectiveness of this method. For high-frequency or RF power amplifiers, there are more parasitic effects of devices and circuits that need to be considered, such as finite switching time, choke loss, etc., and the advantages of this method will be more prominent. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 The design flow chart of this method;

[0052] Figure 2 This is the circuit schematic diagram of a class E power amplifier;

[0053] Figure 3 is the switching voltage waveform under the initial value condition in the embodiment;

[0054] Figure 4 is the switching voltage waveform after iterative convergence in the embodiment;

[0055] Figure 5 is the output voltage waveform after iterative convergence in the embodiment;

[0056] Figure 6 is the switching voltage waveform of the actual circuit made in the embodiment;

[0057] Figure 7 : is the output voltage waveform of the actual circuit made in the embodiment. DETAILED DESCRIPTION

[0058] The present invention is further explained below in conjunction with the accompanying drawings.

[0059] like Figure 1 As shown, the analytical-numerical hybrid design method of the class E power amplifier specifically includes the following steps:

[0060] Step 1: Class E power amplifier Figure 2As shown in the figure, when the MOS tube is in the best working state, the ZVS and ZVDS conditions met are:

[0061] ZVS:v C (ωt)| ωt＝2π =0 (1)

[0062]

[0063] In an ideal situation, the quality factor of the load circuit is close to infinity, so it can be assumed that the output current i R (ωt) is a pure sine wave, i R (ωt)=I m sin(ωt+φ); the value of the feed inductance is also very large, and the current flowing through can be considered to contain only the DC I DC , so when the switch is turned off, the current i flowing through the parallel capacitor C C (ωt) is:

[0064] i C (ωt)=I DC -I m sin(ωt+φ) (3)

[0065] According to the ZVDS condition described in formula (2), I DC =I m sinφ, therefore:

[0066] i C (ωt)=I m sinφ-I m sin(ωt+φ) (4)

[0067] When the duty cycle D = 0.5, the voltage across the switch v C (ωt) is:

[0068] According to the ZVS condition, the phase φ of the load current is:

[0069]

[0070] According to the circuit structure of the class E power amplifier, the voltage v across the switch is C The DC component of (ωt) and the power supply voltage V DD equal:

[0071]

[0072] Therefore, the initial value of the parallel capacitance C can be obtained by solving formula (7).

[0073] I DC ,I m With load resistance RL It can be determined by formula (9):

[0074]

[0075]

[0076] The initial value of the residual inductance L can be determined based on the fundamental voltage amplitude V L And ωL=V L / I m Sure:

[0077]

[0078] According to the quality factor Q L and resonant condition to determine the series inductance L 0 and capacitor C 0 Initial value of:

[0079]

[0080] The number of iterations k is set to 0, and based on the initial value of the circuit obtained by the above calculation, the subsequent iterative optimization step is entered.

[0081] Step 2: Perform SPICE simulation based on the design values ​​of the circuit components to obtain the fundamental frequency amplitude of the load current With phase φ k , the current i on the choke inductor RFC k (ωt), output current i R k (ωt) and drain current i d k (ωt).

[0082] Calculating DC Current

[0083]

[0084] In actual situations, since the choke inductance is a finite value, the current i on the choke inductance is RFC k (ωt) In addition to the DC component In addition, there is an increment Δi RFC k (ωt):

[0085]

[0086] Due to the quality factor Q of the load circuit L is a finite value, so the output current i R k(ωt) is not a pure fundamental sine wave. The sum of all harmonic components except the fundamental wave is Δi R k (ωt) is:

[0087]

[0088] Considering the numerous parasitic effects of the MOS tube, including on-resistance, nonlinear parasitic capacitance, etc., the voltage is not completely zero when it is turned on. Therefore, the current i flowing through the capacitor C during the period of π≤ωt≤2π when the MOS tube is turned off is c k (ωt) is:

[0089]

[0090] in:

[0091] Δi C k (ωt)=Δi RFC k (ωt)-Δi R k (ωt)-i d k (ωt) (16)

[0092] Δq k (ωt) represents the increment of charge on the parallel capacitor C:

[0093]

[0094] The voltage between the drain and source of the MOS tube is v C k (ωt) is:

[0095]

[0096] in is the voltage across the switch under ideal conditions, v C k (π) and v C k (2π) are the voltage values ​​at the moments ωt=π and ωt=2π respectively obtained according to the simulation results.

[0097] According to the ZVS condition, we have:

[0098]

[0099] Therefore, the iteratively updated phase φ k+1 Need to meet:

[0100]

[0101] Among them, q k (π)=Cv C k (π), T is the period. That is, after iterative update, the fundamental frequency amplitude of the load current With phase φ k+1 for:

[0102]

[0103]

[0104] Step 3: If under the simulation conditions of step 2, the difference δ between the simulation value and the ideal value of the switch voltage at t = 1us is k If it is less than 0.1%, the iteration ends and the simulation parameters are output as the component parameters of the class E power amplifier; otherwise, the process goes to step 4.

[0105] Step 4: Update the base frequency amplitude of the load current according to step 2 With phase φ k+1 , update the parallel capacitor C, residual inductance L, series inductance L 0 and capacitor C 0 Parameters.

[0106] The voltage across the parallel capacitor C is v C k The DC component of (ωt) is still the power supply voltage V DD :

[0107]

[0108] in:

[0109]

[0110] According to formula (12), the updated parallel capacitance C is solved k+1 .

[0111] Fundamental frequency voltage amplitude across the residual inductance L for:

[0112]

[0113] in:

[0114]

[0115] Therefore, the updated residual inductance L k+1 for:

[0116]

[0117] According to the quality factor and resonance condition, the updated series inductance L is obtained. 0 k+1 and C 0 k+1 :

[0118]

[0119]

[0120] Step 5: Set k=k+1 and return to step 2.

[0121] In this embodiment, the operating frequency f = 1MHz, the power supply voltage VDD = 5V, the load resistance R L =4Ω, the parameters of the class E power amplifier with an output power of 3W were optimized under simulation. The IRF530 tube was used as the switch tube, and the gate input was a sine wave with an amplitude of 5V. The main PSPICE model parameters of the switch tube are shown in Table 1:

[0122]

[0123] Table 1

[0124] First, the parameters are designed according to ideal conditions. The choke inductance L RFC =120μH, quality factor Q L =10, the design results are shown in the second row of Table 2. This circuit is simulated using the ideal switch and the actual MOS tube model, and the voltage waveforms at both ends of the MOS tube are shown in Figure 3 As shown. It can be seen that although the waveform in the ideal case can meet the ZVS and ZVDS conditions, the actual voltage is about 0.83V when ωt=2π. At the same time, there is also an obvious non-zero voltage between 0<ωt<π when the switch is closed. The switch current has a peak of about 631mA and overlaps with the switch voltage, resulting in additional power loss.

[0125] Then the design result obtained under the above ideal conditions is used as the initial value, and the iterative optimization is performed through this method. When ε = 0.1%, it converges after 3 iterations. The optimization results are shown in the third row of Table 2. SPICE simulation is performed on this circuit, and the voltage across the MOS tube and the output voltage waveform are obtained as follows Figure 4 and Figure 5 As shown, it can be seen that v CS (2π)=29μV, the waveform can meet the ZVS and ZVDS conditions with high accuracy. From the data in Table 2, after the optimization by this method, the key indicators of the circuit are obviously better than the two optimization methods introduced in the background technology.

[0126]

[0127] Table 2

[0128] In addition, according to the design results in Table 2, this embodiment also makes an actual power amplifier circuit, in which the MOSFET uses IRF530PBF from Vishay. The measured switching voltage and output voltage waveforms are shown in Figure 6 and Figure 7 As shown, the comparison between the parameters of the actual circuit and the simulation results is shown in Table 3:

[0129]

[0130] Table 3

[0131] According to the data comparison results in Table 3, the measured circuit results are consistent with the computer simulation results, which can prove that this method is effective and reliable.

Claims

1. Analytical-numerical hybrid design method for class E power amplifiers, Features: The specific steps include: Step 1: Set the number of iterations k = 0, and determine the parallel capacitance C, the residual inductance L, and the series inductance L by deriving the formula of the class E power amplifier under ideal conditions. 0 and capacitor C 0 The initial value of Step 2: Perform SPICE simulation based on the design values ​​of the circuit components to obtain the fundamental frequency amplitude of the load current With phase φ k , the current i on the choke inductor RFC k (ωt), output current i R k (ωt) and drain current i d k (ωt); Consider the current i flowing through the choke inductor RFC k The increment Δi of (ωt) RFC k (ωt): in For DC current: Considering the output current i R k The sum of all harmonic components except the fundamental wave on (ωt) Δi R k (ωt): After considering the parasitic effects of the MOS tube, the current i flowing through the parallel capacitor C during the cut-off period is c k (ωt) is: in: Δi C k (ωt)=Δi RFC k (ωt)-Δi R k (ωt)-i d k (ωt) (5) Δq k (ωt) represents the increment of charge on the parallel capacitor C: The voltage between the drain and source of the MOS tube is v C k (ωt) is: in is the voltage across the MOS switch under ideal conditions, v C k (π) and v C k (2π) are the voltage values ​​at the time of ωt=π and ωt=2π obtained according to the simulation results; According to the ZVS condition, we have: Therefore, the iteratively updated phase φ k+1 Need to meet: Among them, q k (π)=Cv C k (π), T is the period; therefore, the fundamental frequency amplitude of the updated load current is obtained With phase φ k+1 for: Step 3: If under the simulation conditions of step 2, the difference δ between the simulation value and the ideal value of the switch voltage at t = 1us is k If it is less than the error control requirement ε, the iteration ends and the simulation parameters are output as the component parameters of the class E power amplifier; otherwise, go to step 4; Step 4: Update the base frequency amplitude of the load current according to step 2 With phase φ k+1 , update the parallel capacitor C, residual inductance L, series inductance L 0 and capacitor C 0 Parameters; The voltage across the parallel capacitor C is v C k The DC component of (ωt) and the power supply voltage V DD equal: in: According to formula (12), the updated parallel capacitance C is solved k+1 ; Fundamental frequency voltage amplitude across the residual inductance L for: in: Therefore, the updated residual inductance L k+1 for: According to the quality factor and resonance condition, the updated series inductance L is obtained. 0 k+1 and C 0 k+1 : Step 5: Set k=k+1 and return to step 2.

2. The analytical-numerical hybrid design method for a class E power amplifier as claimed in claim 1, Features: The error control requirement is set to ε=0.1%.

3. The analytical-numerical hybrid design method for a class E power amplifier as claimed in claim 1, Features: When the MOS tube is in the best working state, the ZVS condition is met as follows: ZVS:v C (ωt)| ωt＝2π =0 (19)。 4. The analytical-numerical hybrid design method for a class E power amplifier as claimed in claim 1, Features: The ideal condition is that the quality factor of the load circuit is infinite and the output current i R (ωt) is a pure sine wave; the value of the feeding inductance is infinite and the current flowing through is DC.

5. The analytical-numerical hybrid design method for a class E power amplifier as claimed in claim 1, 3 or 4, Features: The derivation formula of the class E power amplifier under ideal conditions is: When the switch is turned off, the current i flowing through the parallel capacitor C C (ωt) is: i C (ωt)=I DC -I m sin(ωt+φ) (20) According to the ZVDS condition, I DC =I m sinφ, therefore: I C (ωt)=I m sinφ-I m sin(ωt+φ) (21) When the duty cycle D = 0.5, the voltage across the switch v C (ωt) is: According to the ZVS condition, the phase φ of the load current is obtained as: According to the circuit structure of the Class E power amplifier, the voltage v across the switch C The DC component of (ωt) and the power supply voltage V DD equal: The initial value of the parallel capacitance C is obtained by solving formula (7); I DC ,I m With load resistance R L for: The initial value of the residual inductance L is determined by the fundamental voltage amplitude V at both ends of the inductance L. L And ωL=V L / I m Sure: According to the quality factor Q L and resonant condition to determine the series inductance L 0 and capacitor C 0 Initial value of: ωL 0 =Q L R L -ω L 、 6. The analytical-numerical hybrid design method for a class E power amplifier as claimed in claim 5, Features: The ZVDS conditions are: ZVDS:

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