A multi-coding implementation method based on high-density flash memory
By setting up multiple sets of Gray code arbitration mechanisms in the flash controller, Gray code arbitration is carried out on data with different operations and access popularity, the problem of unbalanced read and write performance of high-density flash memory is solved, and the reading and write performance optimization is achieved.
Patent Information
- Application Number
- CN202210696864.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-20
- Publication Date
- 2025-08-08
- Estimated Expiration
- 2042-06-20
AI Technical Summary
There are contradictions in the read and write performance of existing high-density flashes, and the read performance cannot be guaranteed after the programming performance is improved.
Multiple sets of Gray code arbitration mechanisms are set up in the flash controller. Gray code arbitration is performed on data of different operations and data of access popularity. Gray codes are used to improve reading performance, Gray codes are good in programming performance to improve writing performance, and Gray codes are converted in combination with data access characteristics.
It realizes the optimization of read and write performance of high-density flash memory, improves read and write performance, and solves the contradiction between read and write performance.
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Figure CN114974373B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of flash memory performance, and in particular to a multi-coding implementation method based on high-density flash memory. Background Art
[0002] 3D NAND flash memory, with its high density, low cost, and lightweight design, has become a crucial storage medium in solid-state drives (SSDs). Over the past decade, its development has primarily focused on two key aspects: First, the number of stacked layers has increased significantly, from 24 in the early days to over 220 in the most advanced technologies. Second, the number of bits that can be stored in each memory cell has increased from 1 bit per cell to 4 bits per cell. Based on extensive research, achieving more layers per block and storing more bits per cell remains on the roadmap of flash memory vendors. For example, PLC flash memory with 5 bits per cell and HLC flash memory with 6 bits per cell have been announced. These approaches can significantly increase storage density and reduce production costs. However, these high-density, low-cost flash memories face two key challenges: reliability and performance degradation, which have hindered their further development.
[0003] Previous work proposed a two-step programming (TSP) algorithm to improve flash memory write performance. Compared to the earlier proposed single-step programming (OSP) algorithm, the TSP algorithm is more reliable. The TSP algorithm consists of coarse-grained programming in the first step and fine-grained programming in the second step. Taking QLC flash memory as an example, in the first step of programming, the memory cells in a word line are programmed to 16 intermediate states. After programming the adjacent word line to the intermediate state, the memory cells on the current word line are programmed to the final state. In this case, interference between word lines can be minimized. However, the basic TSP programming algorithm introduces a high programming delay. To improve programming efficiency, previous work proposed reducing the overall programming delay by accelerating the first step of programming and proposed several optimized TSP schemes. For example, different TSP algorithms are represented by TSP(N,M), where N and M are the number of programmed states in the first and second steps, respectively. These include TSP(16,16), TSP(8,16), and TSP(4,16). TSP(4,16) has the shortest programming time. However, different TSP schemes support different Gray codes, which are highly correlated with read performance. Different Gray codes are represented by GC(A,B,C,D), where A, B, C, and D are the reference voltages required to read four pages in QLC flash memory.
[0004] Table 1 below shows the Gray code voltage level distribution of QLC flash memory and the reference voltage numbers corresponding to the pages under different Gray codes:
[0005] Table 1 Gray code voltage level distribution of QLC flash memory
[0006]
[0007] Table 2 below compares the read and write performance of different Gray codes and the TSP algorithms they support:
[0008] Table 2 Comparison of different Gray codes
[0009]
[0010] Among all TSP algorithms, TSP(16,16) can support any Gray code, such as GC(3,4,4,4). TSP(8,16) supports GC(1,2,4,8), and TSP(4,16) supports GC(1,2,6,6). TSP(4,16) with GC(1,2,6,6) exhibits unbalanced read performance across the four pages, known as an unbalanced Gray code (UGC). TSP(16,16) with GC(3,4,4,4) exhibits comparable read performance across the four pages, known as a balanced Gray code (BGC). However, TSP(4,16), with its higher write performance, can only support UGC, which has poorer read performance, while BGC, with its higher read performance, can only use TSP(16,16), which has poorer write performance. Furthermore, some pages encoded with UGC will be more sensitive to reliability.
[0011] In summary, while programming performance in high-density flash memory improves, read performance is not guaranteed. Therefore, existing programming algorithms and the Gray codes they support cannot achieve dual benefits in read and write performance. This invention, from a coding perspective, uses different Gray codes for data with different access characteristics, effectively optimizing read and write performance. Summary of the Invention
[0012] The purpose of the present invention is to address the deficiencies of the existing technology and provide a multi-coding implementation method based on high-density flash memory. The method uses Gray code arbitration for data of different operations and data of different access popularity. For the first written data, Gray code with better read performance is used to improve read performance, while for updated data, Gray code with better programming performance is used to improve write performance. By performing Gray code arbitration on data of different operations and data of different access popularity, and combining the access characteristics of the data, the hot data is appropriately converted to Gray code to improve read and write performance, thereby optimizing the read and write performance of high-density flash memory.
[0013] The specific technical solution for achieving the purpose of the present invention is: a multi-encoding implementation method based on high-density flash memory, which is characterized in that an arbitration mechanism including an initial Gray code arbitration method for data and a Gray code arbitration method for hot read data is set in the flash memory controller, and Gray code arbitration is performed on data of different operations and data of different access heat. For the first written data, a single bit is added to the mapping table to mark the Gray code type, and Gray code with better read performance is used to improve the read performance; Gray code with better programming performance is used to improve the write performance; Gray code arbitration is further performed on hot data, and it is migrated to a page with better read performance, thereby optimizing the read and write performance of high-density flash memory.
[0014] The arbitration mechanism provided in the flash memory controller includes an initial Gray code arbitration method for data and a Gray code arbitration method for hot-read data. This mechanism implements the encoding and decoding of data under different Gray codes by adding two sets of hardware circuits, encoding and decoding, inside each plane in the flash memory array. The Gray code arbitration method arbitrates data in multiple encoding modes, using a balanced Gray code for hot-read data and an unbalanced Gray code for hot-write data. For each Gray code, the optimal supported programming algorithm is selected to optimize read and write performance.
[0015] The multi-coding refers to the balanced Gray code and unbalanced Gray code used in high-density flash memory; the balanced Gray code means that the number of reference voltages required when reading each page in a single word line is relatively balanced; the unbalanced Gray code means that the number of reference voltages required when reading each page in a single word line varies greatly, so that when writing or updating data, the corresponding Gray code is arbitrated for encoding.
[0016] The Gray code arbitration method ensures read performance by using balanced Gray code BGC with better overall reliability for hot read data; and ensures write performance by using unbalanced Gray code UGC supported by a programming algorithm with faster programming speed for hot write data; the data written for the first time is written using a programming algorithm supported by Gray code with better read performance, while the updated data is written using a programming algorithm with better programming performance to improve write performance.
[0017] The present invention analyzes the existing single Gray code and deeply explores the advantages and disadvantages of each Gray code. Experiments show that the Gray code supported by the algorithm that can achieve fast programming has poor and unstable reading performance, while the Gray code that can achieve better reading performance can only be supported by a programming algorithm with poor writing performance. To address this problem, first, multiple sets of control circuits are added to the flash memory controller to support different Gray codes. Secondly, a Gray code arbitration mechanism is added to the flash memory transmission layer, including an initial Gray code arbitration method for data and a Gray code arbitration method for hot read data. This method arbitrates the encoding method of the data and combines the local access characteristics of the data to achieve the optimization of read and write performance. The basic idea of the present invention is to use Gray code with better read performance for hot read data, and Gray code supported by the fast programming algorithm for hot write data. Based on the above ideas, the present invention balances read and write performance and optimizes flash memory read performance relative to the most advanced encoding method.
[0018] Compared with the existing technology, the present invention has higher read and write performance. By performing Gray code arbitration on data of different operations and data of different access heat, and combining the access characteristics of the data, the hot data is appropriately converted to Gray code to improve the read and write performance, thereby optimizing the read and write performance of high-density flash memory. Hot read data uses more reliable encoding to improve read performance, while hot write data uses encoding with higher programming performance to improve write performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 This is a diagram of the architecture of the present invention;
[0020] Figure 2 Enables various Gray code schemes in the flash controller. DETAILED DESCRIPTION
[0021] The present invention adds a Gray code arbitration mechanism to the flash memory controller, including an initial Gray code arbitration method for data and a Gray code arbitration method for hot read data. A single bit is added to the mapping table to identify the Gray code type, and a LRU linked list is used to identify hot read data.
[0022] The multi-coding used in the Gray code arbitration method refers to the balanced Gray code (BGC) and unbalanced Gray code (UGC) used in high-density flash memory. Balanced Gray code means that the number of reference voltages required when reading each page in a single word line is relatively balanced. Unbalanced Gray code means that the number of reference voltages required when reading each page in a single word line varies significantly. Taking QLC flash memory as an example, Gray code GC(3,4,4,4) is a balanced Gray code, while Gray code GC(1,2,4,8) and Gray code GC(1,2,6,6) are unbalanced Gray codes.
[0023] The Gray code arbitration method uses balanced Gray code (BGC) for hot read data, which offers better overall reliability, to ensure read performance. For hot write data, unbalanced Gray code (UGC), supported by a faster programming algorithm, is used to ensure write performance. Based on this basic concept, the initial write data is written using a programming algorithm supported by Gray code with better read performance, while updated data is written using a programming algorithm with better programming performance to improve write performance. This significantly improves read performance while ensuring write performance.
[0024] The key to the Gray code arbitration method lies in supporting multiple Gray code mechanisms within the controller. Flash memory controllers can support multiple Gray code types. To achieve this, two sets of encoding and decoding components are required. The encoding component, for example, determines the Gray code type and determines the threshold voltage value for the corresponding Gray code when writing data. For QLC flash memory, the four bits in a storage cell can be represented by 16 threshold voltage values. However, for the same bit value, different Gray codes use different threshold voltages. Therefore, the encoding component is primarily responsible for translating threshold voltages between different Gray codes. The decoding component, when reading data, uses the obtained Gray code type to provide a corresponding reference voltage sequence, enabling data page reads under the corresponding Gray code. This allows for encoding of the corresponding Gray code when writing or updating data. Furthermore, Gray code switching is required for hot read data. Overall, by adding two sets of hardware circuits within each plane of the flash memory array, primarily the encoding and decoding components, data encoding and decoding under different Gray codes is achieved.
[0025] The Gray code arbitration method uses balanced Gray code for hot-read data and unbalanced Gray code for hot-write data. This optimizes read and write performance. For each Gray code, the optimal programming algorithm that can be supported is selected. Extensive research and experiments have shown that among existing two-step programming (TSP) algorithms, those with better programming performance cannot support more reliable Gray codes; however, reliable Gray codes can only be achieved through suboptimal programming algorithms. To achieve dual guarantees for read and write performance, the present invention combines data access characteristics with Gray code types, optimizing read and write performance through Gray code arbitration. In the present invention, Gray code GC(1,2,6,6), supported by the currently fastest two-step programming algorithm TSP(4,16), and Gray code GC(3,4,4,4), which has the best overall read performance, and its corresponding two-step programming algorithm TSP(16,16), are used as the default unbalanced Gray code and balanced Gray code.
[0026] The hot read data uses balanced Gray code, while the hot write data uses unbalanced Gray code. The number of data accesses is recorded, so that the hot read data can be migrated to the low-latency page in the word line using unbalanced Gray code, thereby further improving the read performance.
[0027] Conventional encoding schemes program data based on a predefined mapping between encoding bit information and corresponding voltage states. During the programming process, a successful verify operation on a memory cell indicates that the cell has reached the desired voltage state and is excluded from subsequent programming steps. For example, for the two-step programming algorithm TSP(4,16) with Gray code GC(1,2,6,6), the data to be written is determined by the mapping between encoding bit information and voltage states based on the Gray code type. To enable this process, two encoding mapping tables should be maintained in the flash memory controller. These tables record the mapping between Gray code GC(1,2,6,6) and Gray code GC(3,4,4,4) and their corresponding voltage states. If data is programmed using TSP(4,16), the data is encoded using Gray code GC(1,2,6,6). The corresponding verify voltage is then applied to the bit line. Otherwise, Gray code GC(3,4,4,4) is used for encoding. Finally, the programming voltage Vpp is applied to the word line. The remaining programming steps are identical to those of conventional programming schemes. In addition to programming, read operations also differ from the single Gray code approach. The two Gray codes use different reference voltages to sense memory cells. Similar to the write process, two additional mapping tables for decoding should be maintained on the flash memory controller. These two tables are intended to record the mapping between Gray code GC(1,2,6,6) and Gray code GC(3,4,4,4) and their corresponding reference voltages. During read operations, the corresponding reference voltage is used to sense the flash memory cell, depending on the Gray code type. This invention is enabled at the block level, meaning each block supports one type of Gray code. This invention can also be enabled at different levels, such as the wordline level or the chip level. The basic implementation concept remains the same.
[0028] This invention analyzes existing single Gray codes and explores the advantages and disadvantages of each Gray code. Experiments revealed that Gray codes supported by algorithms that enable fast programming exhibit poor and unstable read performance, while Gray codes that achieve better read performance can only be supported by programming algorithms with poor write performance. To address this issue, multiple control circuits are added to the flash memory controller to support different Gray codes. Secondly, a Gray code arbitration mechanism is added to the flash memory transport layer, including an initial Gray code arbitration method for data and a Gray code arbitration method for hot-read data. This Gray code arbitration method optimizes read and write performance by arbitrating the data encoding method and incorporating the local access characteristics of the data. The basic concept of this invention is to use Gray codes with better read performance for hot-read data, while using Gray codes supported by fast programming algorithms for hot-write data. Based on this concept, the present invention balances read and write performance, optimizing flash memory read performance compared to the most advanced encoding methods. By arbitrating the data Gray code and, incorporating the data access characteristics, appropriately converting the hot data to Gray code effectively improves read and write performance.
[0029] The present invention is further described in detail below through specific implementations.
[0030] Example 1
[0031] See Figure 1 The present invention shows a multi-encoding architecture diagram. Two new components are added to the flash memory controller: an initial Gray code arbitration mechanism and a hot read data arbitration mechanism. This arbitration mechanism implements data encoding and decoding under different Gray codes by adding two sets of hardware circuits, encoding and decoding, within each plane of the flash memory array. The specific implementation includes the following steps:
[0032] 1) Two block-sized write heads are maintained inside each plane, and each write head corresponds to a type of Gray code.
[0033] 2) When the data is written for the first time, it is encoded using BGC; when the data is updated, it is encoded using UGC.
[0034] 3) When data is accessed, its access count is recorded. Frequently accessed data is further considered for migration to more reliable pages. At this time, if the access count of the current data exceeds the threshold, it is immediately marked and prepared for migration.
[0035] 4) During the migration process, if migrating to the BGC, only one word line of hot data needs to be collected before programming. If programming to the UGC is required, additional cold data must be actively found and combined with the current hot data before migration.
[0036] 5) When all data is ready, programming is performed. During programming, the corresponding translation circuit needs to be selected according to the specific programming algorithm to obtain the corresponding programming voltage.
[0037] The Gray code arbitration mechanism described above is based on two main principles: whether the data is being written for the first time, and the number of times the data is accessed. Whether the data is being written for the first time can be determined by querying the address mapping table, while the number of times the data is accessed is indicated by adding two bits to the mapping table. Furthermore, an LRU linked list is used to determine data access status within a certain period of time, thereby more accurately identifying data popularity. Using this implementation, the additional overhead incurred by the Gray code arbitration process is negligible.
[0038] See Figure 1The hardware modification primarily involves adding two pairs of mapping tables (information encoders and decoders) to the flash memory controller. Furthermore, the circuit logic requires mapping tables for data encoding and decoding. Previous work has shown that the cost of a mapping table does not exceed 0.07% of the total area. The proposed design doubles this cost, which is still negligible in 3D NAND flash memory chips.
[0039] The present invention performs Gray code arbitration on data of different operations and data of different access heat. Specifically, Gray code with better read performance is used to improve read performance for data written for the first time, and Gray code with better programming performance is used to improve write performance for updated data. Gray code arbitration is further performed on hot data and migrated to pages with better read performance. Exploration is carried out using QLC flash memory as the default memory, and it can also be easily extended to other types of high-density flash memory. The present invention optimizes the read and write performance of high-density flash memory. Data should be cached in DRAM in advance and programmed into the flash memory chip when they are ready. The above design has several advantages: First, if the data is read-only, they can directly use BGC encoding for read performance optimization. Second, once the data is frequently updated, they are encoded using TSP (4,16) and UGC when updated for write performance optimization. The present invention adopts Gray code GC(1,2,6,6) supported by the currently fastest two-step programming algorithm TSP(4,16) and Gray code GC(3,4,4,4) with the best overall read performance and its corresponding two-step programming algorithm TSP(16,16) as the default unbalanced Gray code and balanced Gray code.
[0040] The basic process of initial Gray code arbitration is as follows: Considering that data access characteristics are unknown during the first write, the present invention proposes an initial Gray code arbitration scheme whose basic design concept is to use BGC for the first write and UGC for subsequent updates. Initially, data is programmed using BGC, and once the data is updated, it is programmed using UGC. The reasons for this design are as follows: First, since the access characteristics are unknown during the first write, using BGC programming helps to ensure read performance. Second, the only impact is on programming performance during the first write. However, once the data is updated, UGC can be used to speed it up. Since write operations can be optimized through caching, the impact on write performance is minimal.
[0041] See Figure 1, data should be cached in DRAM in advance and programmed to the flash chip when they are ready. The above design has several advantages: First, if the data are read-only, they can be read directly using BGC for read performance optimization. Second, once the data are write-only, they can be updated with UGC for write performance optimization. Note that in the present invention, the Gray code GC (1,2,6,6) supported by the two-step programming algorithm TSP (4,16) with the fastest programming speed and the Gray code GC (3,4,4,4) with the overall optimal read performance and its corresponding two-step programming algorithm TSP (16,16) are used as the default unbalanced Gray code and balanced Gray code.
[0042] See Figure 2 , the Gray code conversion mechanism of the hot read data is as follows: Unlike writing, the data with read should be placed correctly according to its heat. The present invention proposes hot read data conversion, which includes two aspects: 1) hot read data on the TSB or MSB page of the UGC-based block; 2) hot read data on the BGC-based block page. For the first case, if the data from the TSB or MSB page of the UGC-based block is read for more than T UR Or due to low reliability and repeated reading, they should be transferred to the BGC-based blocks for read performance optimization. In this case, the data is first cached in the DRAM of the SSD controller. When four pages of data are cached, they will be encoded with BGC and written at once. During the programming process, they can be combined with the data written for the first time to form a word line granularity to avoid long waiting time in DRAM. For the second case, if the data on the page of the BGC-based block is frequently read and exceeds the threshold T BR , then this data can be transferred to the LSB or CSB page of the UGC-based block to further optimize the read performance.
[0043] A key issue in the above design is to determine T UR and T BR Two thresholds. T UR is the threshold for data migration based on the UGC block, and T BR is the threshold for data migration based on the BGC block. First, T UR A threshold designed to determine the transition from a TSB or MSB page of a UGC-based block to a BGC-based block. UR is set to 1 to avoid the degradation of read performance caused by reading on these two types of pages. That is, once the data on these two types of pages are read, they will be immediately migrated and encoded using BGC. BRA threshold designed to determine the transition from a page of a BGC-based block to an LSB or CSB page of a UGC-based block, in order to facilitate further read performance optimization. BR The value should not be too large or too small. BR If the setting is too large, the chance of optimizing read performance is small. BR If the setting is too small, many conversions may occur, thereby introducing a large number of additional write operations. BR The present invention combines the above two designs to achieve a more reliable encoding for hot read data to improve read performance, while a higher programming performance encoding is used for hot write data to improve write performance.
[0044] The above is only a further explanation of the present invention and is not intended to limit this patent. Any equivalent implementation of the present invention should be included in the scope of the claims of this patent.
Claims
1. A multi-coding implementation method based on high-density flash memory, characterized in that An arbitration mechanism including an initial Gray code arbitration method for data and a Gray code arbitration method for hot read data is set in the flash memory controller. Gray code arbitration is performed on data of different operations and data of different access heat. For the first written data, a single bit is added to the mapping table to identify the Gray code type. The programming algorithm TSP (16,16) supported by the Gray code GC (3,4,4,4) with better read performance is used to improve the read performance. For the updated data, the two-step programming algorithm TSP (4,16) is used to improve the write performance. Gray code arbitration is further performed for hot data. The balanced Gray code BGC with better overall reliability is used for the hot read data to ensure the read performance. Gray code GC(3,4,4,4) with the best overall read performance and its corresponding two-step programming algorithm TSP(16,16) are used. Unbalanced Gray code UGC, supported by a faster programming algorithm, is used for hot write data to ensure write performance. The unbalanced Gray code UGC uses Gray code GC(1,2,6,6), supported by TSP(4,16), the fastest two-step programming algorithm currently available.
2. The multi-coding implementation method based on high-density flash memory according to claim 1 is characterized in that The arbitration mechanism provided in the flash memory controller includes an initial Gray code arbitration method for data and a Gray code arbitration method for hot-read data. The arbitration mechanism implements encoding and decoding of data under different Gray codes by adding two sets of hardware circuits for encoding and decoding inside each plane in the flash memory array. The Gray code arbitration method arbitrates data in multiple encoding modes, adopts a default balanced Gray code for hot-read data, and adopts a default unbalanced Gray code for hot-write data. For each Gray code, the optimal programming algorithm that can be supported is selected, that is, Gray code GC (1,2,6,6) supported by the currently fastest two-step programming algorithm TSP (4,16) and Gray code GC (3,4,4,4) with the best overall read performance and its corresponding two-step programming algorithm TSP (16,16) are adopted as the default unbalanced Gray code and balanced Gray code to achieve optimal read and write performance.
3. The multi-coding implementation method based on high-density flash memory according to claim 2 is characterized in that The multi-coding refers to the balanced Gray code and unbalanced Gray code used in high-density flash memory; the balanced Gray code means that the number of reference voltages required when reading each page in a single word line is relatively balanced; the unbalanced Gray code means that the number of reference voltages required when reading between each page in a single word line varies greatly, so that when writing or updating data, the appropriate Gray code is selected for encoding.