Memory device and operating method thereof

Abstract

This disclosure relates to a memory device and its operation method. The memory device includes a plurality of memory cells, peripheral circuitry, and control logic. The peripheral circuitry programs the plurality of memory cells into a programming state among a plurality of programming states. The control logic controls the peripheral circuitry to perform a programming verification operation for at least one programming state among the plurality of programming states, counting bits having predetermined logic values ​​by comparing a programming verification voltage corresponding to a target programming state in the programming verification operation for the target programming state among the at least one programming state with threshold voltages of the plurality of memory cells, and determining the start time of a programming verification operation for a programming state above the target programming state among the plurality of programming states based on the number of bits having predetermined logic values.

Description

Technical Field

[0001] This disclosure generally relates to an electronic device, and more specifically, to a memory device and a method of operating the same. Background Technology

[0002] A storage device is a means of storing data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices are memory devices that store data only when power is supplied and lose the stored data when power is interrupted. Volatile memory devices can include static random access memory (SRAM) and dynamic random access memory (DRAM), etc.

[0004] Non-volatile memory devices are memory devices in which data is not lost even when power is interrupted. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), and flash memory, etc. Summary of the Invention

[0005] Embodiments of this disclosure provide a memory device with improved programming performance and a method for operating the memory device.

[0006] According to one aspect of this disclosure, a memory device is provided, the memory device comprising: a plurality of memory cells; peripheral circuitry configured to program the plurality of memory cells into programming states among a plurality of programming states; and control logic configured to control the peripheral circuitry to perform a programming verification operation for at least one programming state among the plurality of programming states, counting bits having predetermined logic values ​​by comparing a programming verification voltage corresponding to a target programming state in the programming verification operation for a target programming state among the at least one programming state with threshold voltages of the plurality of memory cells, and determining a start time for a programming verification operation for a programming state among the plurality of programming states higher than the target programming state based on the number of bits having predetermined logic values.

[0007] According to another aspect of this disclosure, a method for operating a memory device including a plurality of memory cells is provided, the method comprising the steps of: performing a programming verification operation for at least one of a plurality of programming states; counting bits having predetermined logic values ​​by comparing a programming verification voltage corresponding to a target programming state in the programming verification operation for a target programming state in the at least one programming state with threshold voltages of the plurality of memory cells; and determining a start time for a programming verification operation for a programming state higher than the target programming state among the plurality of programming states based on the number of bits having predetermined logic values.

[0008] According to one aspect of this disclosure, a memory device is provided, the memory device comprising: a plurality of memory cells; peripheral circuitry coupled to the plurality of memory cells; and control logic coupled to the peripheral circuitry and configured to control the peripheral circuitry to: program the plurality of memory cells to a target programming state among a plurality of programming states; perform a programming verification operation on the plurality of memory cells for the target programming state to verify whether the plurality of memory cells have the target programming state; determine a start time for programming verification operations of adjacent programming states for the target programming state based on the number of memory cells associated with the pass or failure of the programming verification operation for the target programming state; and perform programming verification operations of the adjacent programming states on the plurality of memory cells at the determined start time. Attached Figure Description

[0009] Various embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings; however, these embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0010] In the accompanying drawings, dimensions may be exaggerated for clarity. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. The same reference numerals always refer to the same element.

[0011] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0012] Figure 2 This is an example of an embodiment according to the present disclosure. Figure 1 A diagram showing the structure of the memory device.

[0013] Figure 3 This is an example of an embodiment according to the present disclosure. Figure 2The diagram shows the memory cell array.

[0014] Figure 4 This is an example of an embodiment according to the present disclosure. Figure 2 A diagram of another example of a memory cell array shown.

[0015] Figure 5 This is an example of an embodiment according to the present disclosure. Figure 4 The circuit diagram of the memory block shown.

[0016] Figure 6 This is an example of an embodiment according to the present disclosure. Figure 4 A circuit diagram of another example of a memory block within a memory block shown.

[0017] Figure 7 This is a diagram illustrating programming operations according to embodiments of the present disclosure.

[0018] Figure 8 This is a diagram illustrating the counting of bits with predetermined logic values ​​in a programming verification operation for a target programming state according to an embodiment of the present disclosure.

[0019] Figure 9 This is a diagram illustrating the start time of a programming verification operation for a programming state higher than the target programming state, according to an embodiment of the present disclosure.

[0020] Figure 10 This is an example of an embodiment according to the present disclosure. Figure 2 The diagram shows the page buffer.

[0021] Figure 11 This is an example of an embodiment according to the present disclosure. Figure 2 The diagram shows the page buffer.

[0022] Figure 12 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0023] Figure 13 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure to determine the start time of a programming verification operation for a programming state higher than the target programming state.

[0024] Figure 14 This is a flowchart illustrating the programming verification operation of a memory device according to an embodiment of the present disclosure.

[0025] Figure 15 This is a flowchart illustrating the programming verification operation of a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0026] The descriptions of specific structures or functions disclosed herein are merely for the purpose of describing embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0027] Figure 1 This is a diagram illustrating a storage device 50 according to an embodiment of the present disclosure.

[0028] Reference Figure 1 The storage device 50 may include a memory device 100 and a memory controller 200 configured to control the memory device 100 to perform operations on the memory device 100. The storage device 50 may be a device for storing data under the control of a host computer, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television, tablet computer, or in-vehicle infotainment system.

[0029] Storage device 50 can be manufactured as any of various types of storage devices according to a host interface that is at least one of various communication standards or interfaces with the host. For example, storage device 50 can be implemented as any of various types of storage devices such as solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), miniature MMCs (RS-MMCs), micro-MMCs (micro-MMCs), secure digital cards (SDs), mini SD cards, micro SD cards, universal serial bus (USB) storage devices, universal flash storage (UFS) devices, compact flash (CF) cards, smart media cards (SMCs), and memory sticks.

[0030] The storage device 50 can be manufactured in any of various package types. For example, the storage device 50 can be manufactured in any of various package types such as package-on-package (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0031] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array containing a plurality of memory cells for storing data.

[0032] Each memory cell can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0033] A memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In one embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100.

[0034] A memory block can be a unit used for erasing data. In one embodiment, the memory device 100 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin-Torque Random Access Memory (STT-RAM), etc. In this specification, the case where the memory device 100 is NAND flash memory is described by way of example and without any limitation.

[0035] Memory device 100 receives commands and addresses from memory controller 200 and accesses an address-selected region in the memory cell array. That is, memory device 100 can perform operations instructed by commands on the address-selected region. For example, memory device 100 can perform write (programming) operations, read operations, and erase operations. In a programming operation, memory device 100 can program data in the address-selected region. In a read operation, memory device 100 can read data from the address-selected region. In an erase operation, memory device 100 can erase data stored in the address-selected region.

[0036] The memory controller 200 can control the overall operation of the storage device 50.

[0037] When power is supplied to storage device 50, memory controller 200 may execute firmware (FW). When storage device 100 is a flash memory device, memory controller 200 may execute FW such as a flash translation layer (FTL) for controlling communication between the host and storage device 100.

[0038] In one embodiment, the memory controller 200 may receive data and logical block addresses (LBAs) from a host and translate the LBAs into physical block addresses (PBAs), which represent the addresses of memory cells in the memory device 100 where data is to be stored.

[0039] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, or erase operations in response to requests from the host. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, a PBA (Power-Only Controller), and data. During a read operation, the memory controller 200 can provide the memory device 100 with read commands and a PBA. During an erase operation, the memory controller 200 can provide the memory device 100 with erase commands and a PBA.

[0040] In one implementation, the memory controller 200 can autonomously generate commands, addresses, and data regardless of any requests from the host, and send the commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 to perform background operations such as programming operations for wear leveling and programming operations for garbage collection.

[0041] In one embodiment, the memory controller 200 can control at least two memory devices 100. The memory controller 200 can control the memory devices according to an interleaving scheme to improve operational performance. The interleaving scheme can be an operation scheme that allows the operation periods of at least two memory devices 100 to overlap with each other.

[0042] The host can communicate with the storage device 50 using at least one of various communication standards or interfaces such as Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Fast (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Away DIMM (LRDIMM).

[0043] Figure 2 This is an example of an embodiment according to the present disclosure. Figure 1 A diagram showing the structure of the memory device 100.

[0044] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0045] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz are connected to the read / write circuitry 123 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In one embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the multiple memory cells can be defined as a physical page. That is, the memory cell array 110 may be configured with multiple physical pages. According to one embodiment of this disclosure, each of the multiple memory blocks BLK1 to BLKz included in the memory cell array 110 may include multiple dummy cells. One or more dummy cells may be connected in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0046] Each memory cell of the memory device can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0047] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read / write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

[0048] Peripheral circuitry 120 drives memory cell array 110. For example, peripheral circuitry 120 can drive memory cell array 110 to perform programming operations, read operations, and erase operations.

[0049] Address decoder 121 is connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to one embodiment of this disclosure, word lines may include normal word lines and dummy word lines. According to one embodiment of this disclosure, row lines RL may also include pipe select lines.

[0050] Address decoder 121 can operate under the control of control logic 130. Address decoder 121 receives address ADDR from control logic 130.

[0051] Address decoder 121 can decode the block address in the received address ADDR. Address decoder 121 selects at least one memory block from memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can decode the row address in the received address ADDR. Address decoder 121 selects at least one word line from the word lines of the selected memory block based on the decoded row address. Address decoder 121 can apply an operating voltage Vop provided from voltage generator 122 to the selected word line.

[0052] During programming, address decoder 121 can apply a programming voltage to the selected word line and a pass voltage with a level lower than the programming voltage to the unselected word line. During programming verification, address decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage with a level higher than the verification voltage to the unselected word line.

[0053] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and a read pass voltage at a level higher than the read voltage to the unselected word lines.

[0054] According to one embodiment of this disclosure, an erase operation of the memory device 100 is performed on a block-by-block basis. During the erase operation, the address ADDR input to the memory device 100 includes a block address. An address decoder 121 can decode the block address and select at least one memory block based on the decoded block address. During the erase operation, the address decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0055] According to one embodiment of this disclosure, address decoder 121 can decode a column address in address ADDR sent thereto. The decoded column address can be sent to read / write circuitry 123. In one example, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0056] Voltage generator 122 can generate multiple operating voltages Vop by using the external power supply voltage provided to memory device 100. Voltage generator 122 operates under the control of control logic 130.

[0057] In one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 is used as the operating voltage of memory device 100.

[0058] In one embodiment, voltage generator 122 can generate multiple operating voltages Vop by using an external power supply voltage or an internal power supply voltage. Voltage generator 122 can generate various voltages required by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0059] To generate multiple operating voltages Vop with various voltage levels, voltage generator 122 may include multiple pumping capacitors for receiving internal power supply voltages, and generate multiple operating voltages Vop by selectively activating the multiple pumping capacitors under the control of control logic 130.

[0060] Multiple operating voltages Vop can be provided to the memory cell array 110 by the address decoder 121.

[0061] The read / write circuit 123 includes first page buffers PB1 to m-th page buffers PBm. First page buffers PB1 to m-th page buffers PBm are connected to the memory cell array 110 via corresponding first bit lines BL1 to m-th bit lines BLm. First page buffers PB1 to m-th page buffers PBm operate under the control of control logic 130.

[0062] The first page buffer PB1 to the m-th page buffer PBm communicate with the data input / output circuit 124 to exchange data DATA. During programming, the first page buffer PB1 to the m-th page buffer PBm receive the data DATA to be stored through the data input / output circuit 124 and the data line DL.

[0063] During programming, when a programming pulse is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transmit the data DATA received through the data input / output circuit 124 to the selected memory cell via bit lines BL1 to BLm. The selected memory cell is programmed based on the transmitted data DATA. Memory cells connected to bit lines through which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines through which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification, the first page buffer PB1 to the m-th page buffer PBm read the data DATA stored in the selected memory cell via bit lines BL1 to BLm.

[0064] In a read operation, the read / write circuit 123 can read data DATA from the memory cell of the selected page via the bit line BL and store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0065] During an erase operation, the read / write circuit 123 can float the bit line BL. In one embodiment, the read / write circuit 123 may include column select circuitry.

[0066] The data input / output circuit 124 is connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 operates under the control of the control logic 130.

[0067] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 may receive data DATA to be stored from an external controller (not shown). During reading operations, the data input / output circuit 124 outputs data sent from the first page buffer PB1 to the m-th page buffer PBm included in the read / write circuit 123 to the external controller.

[0068] During a read or verification operation, the sensing circuit 125 can generate a reference current in response to the enable bit VRYBIT signal generated by the control logic 130. Furthermore, the sensing circuit 125 can output a pass signal or a failure signal to the control logic 130 by comparing the sensed voltage VPB received from the read / write circuit 123 with the reference voltage generated from the reference current.

[0069] Control logic 130 can be connected to address decoder 121, voltage generator 122, read / write circuit 123, data input / output circuit 124, and sensing circuit 125. Control logic 130 can control the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from an external device (e.g., a memory controller).

[0070] Control logic 130 can control peripheral circuitry 120 by generating several signals in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, row address RADD, read / write circuit control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, row address RADD to address decoder 121, read / write circuit control signal PBSIGNALS to read / write circuit 123, and enable bit VRYBIT to sensing circuit 125. Furthermore, control logic 130 can determine whether the verification operation passed or failed in response to the pass signal or failure signal PASS / FAIL output by sensing circuit 125.

[0071] In one implementation, the peripheral circuitry 120 can program multiple memory cells into any of a plurality of programming states.

[0072] Control logic 130 can control peripheral circuitry 120 to perform programming verification operations on multiple memory cells for at least one of multiple programming states. Control logic 130 can determine the start time for programming verification operations on programming states higher than the target programming state based on the result of the programming verification operation on the target programming state among the at least one programming state. Control logic 130 can control peripheral circuitry 120 to begin programming verification operations on the ranked programming states from a programming loop corresponding to the determined start time.

[0073] In one implementation, control logic 130 may include bit line voltage controller 131 and programming verification controller 132.

[0074] Bit line voltage controller 131 can control peripheral circuitry 120 to precharge multiple bit lines connected to multiple memory cells. In one embodiment, bit line voltage controller 131 can control peripheral circuitry 120 to execute an All Bit Line (All BL) scheme for precharging all multiple bit lines connected to multiple memory cells during a programming verification operation for a target programming state. In another embodiment, bit line voltage controller 131 can control peripheral circuitry 120 to execute a Selected Bit Line (Sel BL) scheme for precharging selected bit lines among the multiple bit lines connected to multiple memory cells during a programming verification operation for a target programming state. The selected bit lines may be bit lines connected to memory cells that have been determined to have failed programming based on data stored in a sense latch within the memory cells programmed to the target programming state.

[0075] The programming verification controller 132 can compare the programming verification voltage corresponding to the target programming state with threshold voltages of a plurality of memory cells during a programming verification operation for a target programming state in at least one programming state. The programming verification controller 132 can count the number of bits having a predetermined logic value based on the comparison result. The target programming state can be the highest-ordered programming state among the at least one programming states. The target programming state can also be the programming state with the highest corresponding programming verification voltage among the at least one programming states.

[0076] The programming verification controller 132 can determine the start time of a programming verification operation for a programming state higher than the target programming state among a plurality of programming states based on the counted number of bits having a predetermined logic value. In one embodiment, the counted bits, according to the predetermined logic value, can be either the pass bit number or the failure bit number in the memory cell to be programmed to the target programming state. The number of memory cells to be programmed to the target programming state that have a threshold voltage lower than the programming verification voltage corresponding to the target programming state can be the pass bit number.

[0077] In one implementation, when the predetermined logic value is 1, the number of bits counted can represent the number of failures. When the predetermined logic value is 0, the number of bits counted can represent the number of successes. In another implementation, when the predetermined logic value is 0, the number of bits counted can represent the number of failures. When the predetermined logic value is 1, the number of bits counted can represent the number of successes.

[0078] For example, the programming verification controller 132 can count the number of failure bits as the number of memory cells among the memory cells to be programmed into the target programming state that are determined to have failed programming. The programming verification controller 132 can determine the start time of the programming verification operation for the high-order programming state based on the result obtained by comparing the number of failure bits with a reference value. When the number of failure bits is less than or equal to the reference value, the programming verification controller 132 can determine the programming loop following the currently executed programming loop as the start time of the programming verification operation for the high-order programming state.

[0079] Figure 3 This is an example of an embodiment according to the present disclosure. Figure 2 A diagram of the memory cell array 110 shown.

[0080] Reference Figure 3 The first storage block BLK1 to the z-th storage block BLKz are all connected to the first bit line BL1 to the m-th bit line BLm. Figure 3 The diagram illustrates, by way of example, the components included in the first storage block BLK1, which comprises multiple storage blocks BLK1 to BLKz, and omits the components included in each of the other storage blocks BLK2 to BLKz. It will be understood that each of the other storage blocks BLK2 to BLKz is configured in the same way as the first storage block BLK1.

[0081] The memory block BLK1 may include multiple cell strings CS1_1 to CS1_m (where m is a positive integer). The first cell string CS1_1 to the m-th cell string CS1_m are respectively connected to the first bit line BL1 to the m-th bit line BLm. Each of the first cell string CS1_1 to the m-th cell string CS1_m includes a drain selection transistor DST, multiple memory cells MC1 to MCn (where n is a positive integer) connected in series, and a source selection transistor SST.

[0082] The gate terminal of the drain select transistor DST in each of the first unit strings CS1_1 to the m-th unit strings CS1_m is connected to the drain select line DSL1. The gate terminals of the first memory cell MC1 to the n-th memory cell MCn in each of the first unit strings CS1_1 to the m-th unit strings CS1_m are respectively connected to the first word line WL1 to the n-th word line WLn. The gate terminal of the source select transistor SST in each of the first unit strings CS1_1 to the m-th unit strings CS1_m is connected to the source select line SSL1.

[0083] By way of example, the structure of the unit strings will be described based on the first unit string CS1_1 among multiple unit strings CS1_1 to CS1_m. However, it will be understood that each of the other unit strings CS1_2 to CS1_m is configured in the same way as the first unit string CS1_1.

[0084] The drain terminal of the drain selection transistor DST included in the first cell string CS1_1 is connected to the first bit line BL1. The source terminal of the drain selection transistor DST included in the first cell string CS1_1 is connected to the drain terminal of the first memory cell MC1 included in the first cell string CS1_1. The first memory cells MC1 to the nth memory cell MCn are connected in series with each other. The drain terminal of the source selection transistor SST included in the first cell string CS1_1 is connected to the source terminal of the nth memory cell MCn included in the first cell string CS1_1. The source terminal of the source selection transistor SST included in the first cell string CS1_1 is connected to the common source line CSL. In one embodiment, the common source line CSL may be connected to the first memory block BLK1 to the zth memory block BLKz.

[0085] Drain select line DSL1, first word line WL1 to nth word line WLn and source select line SSL1 are included Figure 2 In the row line RL shown, the drain selection line DSL1, the first word line WL1 to the nth word line WLn, and the source selection line SSL1 are connected by... Figure 2 The address decoder 121 shown is controlled by [the controller / controller]. The common source line CSL can be [controlled / managed / controlled]. Figure 2The control logic 130 shown is used for control. The first bit line BL1 to the m-th bit line BLm are controlled by... Figure 2 The read / write circuit 123 shown is used for control.

[0086] Figure 4 This is an example of an embodiment according to the present disclosure. Figure 2 A diagram of another example of the memory cell array 110 shown.

[0087] Reference Figure 4 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate (not shown). The multiple memory cells may be arranged along the +X, +Y, and +Z directions. (Refer to...) Figure 5 and Figure 6 Describe the structure of each storage block in more detail.

[0088] Figure 5 This is an example of an embodiment according to the present disclosure. Figure 4 The circuit diagram of memory block BLKa among memory blocks BLK1 to BLKz is shown.

[0089] Reference Figure 5 The storage block BLKa may include multiple cell strings CS11 to CS1m and CS21 to CS2m. In one implementation, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the storage block BLKa, m cell strings are arranged in the row direction (i.e., the +X direction). As an example, Figure 5 The example illustrates two unit strings arranged in the column direction (i.e., the +Y direction). However, it should be understood that three unit strings can be arranged in the column direction.

[0090] In one implementation, a storage block may include multiple sub-blocks. A sub-block may include a string of cells arranged in a U-shape in a column.

[0091] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0092] The selector transistors SST and DST, and the memory cells MC1 to MCn, can have structures similar to each other. In one embodiment, each of the selector transistors SST and DST, and the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. In one embodiment, a pillar for providing the channel layer may be provided in each cell string. In one embodiment, a pillar for providing at least one of the channel layer, tunneling insulating layer, charge storage layer, and barrier insulating layer may be provided in each cell string.

[0093] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0094] In one implementation, source-select transistors in cell strings arranged in the same row are connected to source-select lines extending in the row direction, and source-select transistors in cell strings arranged in different rows are connected to different source-select lines. Figure 5 In the first row, the source selection transistors of cell strings CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors of cell strings CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0095] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0096] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0097] The first memory cells MC1 to the nth memory cell MCn can be divided into first memory cells MC1 to the pth memory cells MCp and (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp are arranged sequentially in the direction opposite to the +Z direction and are connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are arranged sequentially in the +Z direction and are connected in series between the channel transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are connected through the channel transistor PT. The gates of the first memory cells MC1 to the nth memory cells MCn in each cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0098] The gate of the pipe transistor PT in each cell string is connected to the pipe line PL.

[0099] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0100] A string of cells arranged in the column direction is connected to a bit line extending in the column direction. Figure 5 In the diagram, cell strings CS11 and CS21 in the first column are connected to the first bit line BL1. Cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm.

[0101] Memory cells connected to the same word line in a cell string arranged in the row direction constitute a page. For example, memory cells in cell strings CS11 to CS1m in the first row that are connected to the first word line WL1 constitute one page. Memory cells in cell strings CS21 to CS2m in the second row that are connected to the first word line WL1 constitute another page. When one of the drain selection lines DSL1 and DSL2 is selected, a cell string arranged in one row direction can be selected. When one of the word lines WL1 to WLn is selected, a page can be selected from the selected cell string.

[0102] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be used to replace the first bit line BL1 to the m-th bit line BLm. Additionally, the even-numbered cell strings in the row-oriented cell strings CS11 to CS1m or CS21 to CS2m can be connected to the respective even-numbered bit lines, and the odd-numbered cell strings in the row-oriented cell strings CS11 to CS1m or CS21 to CS2m can be connected to the respective odd-numbered bit lines.

[0103] In one implementation, at least one of the first memory cell MC to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. When the number of dummy memory cells increases, the operational reliability of the memory block BLKa improves. On the other hand, the size of the memory block BLKa increases. When the number of dummy memory cells decreases, the size of the memory block BLA decreases. On the other hand, the operational reliability of the memory block BLA may decrease.

[0104] To effectively control at least one dummy memory cell, the dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after the erase operation of the memory block BLKa. When an erase operation is performed after programming, the threshold voltage control of the dummy memory cell applies to the voltage of the dummy word line connected to the corresponding dummy memory cell, thus allowing the dummy memory cell to have the desired threshold voltage.

[0105] Figure 6 This is an example of an embodiment according to the present disclosure. Figure 4 The circuit diagram shows another example of a memory block, BLKb, among the memory blocks BLK1 to BLKz shown.

[0106] Reference Figure 6 The memory block BLKb may include multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) beneath the memory block BLKb.

[0107] In one implementation, a storage block may include multiple sub-blocks. A sub-block may include a string of cells arranged in an "I" shape in a column.

[0108] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. The source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' may be connected to a single source select line.

[0109] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0110] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0111] Therefore, in addition to from Figure 6 Each cell string in the string excludes the pipe transistor PT. Figure 6 The storage block BLKb has the same characteristics as Figure 5 The circuitry is similar to that of the storage block BLKa.

[0112] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be used to replace the first bit line BL1 to the m-th bit line BLm. Additionally, even-numbered cell strings in the row-oriented cell strings CS11' to CS1m' or CS21' to CS2m' can be connected to the respective even-numbered bit lines, and odd-numbered cell strings in the row-oriented cell strings CS11' to CS1m' or CS21' to CS2m' can be connected to the respective odd-numbered bit lines.

[0113] In one implementation, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. When the number of dummy memory cells increases, the operational reliability of the memory block BLKb improves. On the other hand, the size of the memory block BLKb increases. When the number of dummy memory cells decreases, the size of the memory block BLKb decreases. On the other hand, the operational reliability of the memory block BLKb may decrease.

[0114] To effectively control at least one dummy memory cell, the dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after the erase operation of memory block BLKb. When the erase operation is performed after the programming operation, the threshold voltage control of the dummy memory cell is applied to the voltage of the dummy word line connected to the corresponding dummy memory cell, thus allowing the dummy memory cell to have the desired threshold voltage.

[0115] Figure 7 This is a diagram illustrating programming operations according to embodiments of the present disclosure.

[0116] exist Figure 7 In this example, the memory cell is a multi-level cell (MLC) that stores 2 bits of data. However, the scope of this disclosure is not limited to this; the memory cell may be a three-level cell (TLC) that stores 3 bits of data or a four-level cell (QLC) that stores 4 bits of data. The number of data bits stored by the memory cell may be one or more.

[0117] By executing multiple programming cycles PL1 to PLn, the memory device can program selected memory cells to have threshold voltages corresponding to any of the multiple programming states P1, P2, and P3.

[0118] Each of the multiple programming cycles PL1 to PLn may include a programming voltage application step PGM Step, which applies a programming voltage to a selected word line connected to the selected memory cell, and a programming verification step Verify Step, which determines whether the memory cell has been programmed by applying a verification voltage.

[0119] For example, when executing the first programming cycle PL1, after applying the first programming voltage Vpgm1, the first verification voltage V_vfy1 to the third verification voltage V_vfy3 are applied sequentially to verify the programming state of the selected memory cell. Memory cells whose target programming state is the first programming state P1 can be verified by the first verification voltage V_vfy1, memory cells whose target programming state is the second programming state P2 can be verified by the second verification voltage V_vfy2, and memory cells whose target programming state is the third programming state P3 can be verified by the third verification voltage V_vfy3.

[0120] In another embodiment, a third verification voltage V_vfy3 can be applied sequentially to the first verification voltage V_vfy1 to verify the programming state of the selected memory cell. That is, the verification voltages can be applied to the word lines connected to the selected memory cell in order from high voltage to low voltage.

[0121] It can be determined that each memory cell that passes verification by verification voltages V_vfy1 to V_vfy3 has a target programming state. Then, this memory cell can be disabled for programming in the second programming cycle PL2. In other words, a programming disable voltage can be applied to the bit line connected to the verified memory cell, starting from the second programming cycle PL2.

[0122] In the second programming cycle PL2, a second programming voltage Vpgm2, which is a unit voltage ΔVpgm higher than the first programming voltage Vpgm1, is applied to the selected word line to program memory cells other than those that are disabled for programming. Subsequently, a verification operation is performed in the same manner as in the first programming cycle PL1. In some embodiments, a successful verification indicates that the memory cell is read as an off-cell by the corresponding verification voltage.

[0123] As described above, when a memory device programs a multi-level cell (MLC) that stores two bits, the memory device can verify the memory cell with various programming states as the target programming state by using a first verification voltage V_vfy1 to a third verification voltage V_vfy3 respectively.

[0124] In the verification operation, a verification voltage is applied to the selected word line, which is connected to the selected memory cell, and Figure 2 The page buffer shown can determine whether a memory cell has been verified based on the current flowing through the bit lines connected to the selected memory cell or the voltage applied to the bit lines connected to the selected memory cell.

[0125] Figure 8 This is a diagram illustrating the counting of bits having predetermined logic values ​​during a programming verification operation for a target programming state, according to an embodiment of the present disclosure.

[0126] Reference Figure 8 The memory cell can be a three-level cell (TLC) that stores three data bits. The number of data bits stored by the memory cell is not limited to this implementation.

[0127] Multiple memory cells can be programmed into any of the programming states P1 to P7. During programming operations, the threshold voltage distribution of the memory cells can be sequentially formed from the first programming state P1 to the seventh programming state P7.

[0128] exist Figure 8 In this process, programming verification operations can be performed on multiple memory cells using programming verification voltages V_vfy1 to V_vfy3, respectively corresponding to first programming states P1 to third programming states P3. The third programming state P3, which is the highest-ranked programming state among the first programming states P1 to third programming states P3 where the programming verification operation is performed, can be the target programming state. The start time for the programming verification operation on the fourth programming state P4, which is a programming state higher than the target programming state, can be determined based on the result of the programming verification operation on the target programming state.

[0129] The number of memory cells to be programmed into the third programming state P3 that have a threshold voltage lower than the verification voltage V_vfy3 corresponding to the third programming state P3 can have a failure bit count FB_CNT. The number of memory cells to be programmed into the third programming state P3 that have a threshold voltage higher than or equal to the verification voltage V_vfy3 corresponding to the third programming state P3 can have a pass bit count PB_CNT.

[0130] In one implementation, the failure bit count FB_CNT can be the number of bits in the memory cell to be programmed into the third programming state P3 that have a predetermined logical value (e.g., 1). The bit count PB_CNT can also be the number of bits in the memory cell to be programmed into the third programming state P3 that have a predetermined logical value (e.g., 0). In another implementation, the failure bit count FB_CNT can be the number of bits in the memory cell to be programmed into the third programming state P3 that have a predetermined logical value (e.g., 0). The bit count PB_CNT can also be the number of bits in the memory cell to be programmed into the third programming state P3 that have a predetermined logical value (e.g., 1).

[0131] In one implementation, when the failure bit count FB_CNT is less than or equal to the failure reference value, the programming loop following the currently executing programming loop can be determined as the start time of the programming verification operation for the fourth programming state P4. In another implementation, when the pass bit count PB_CNT is greater than or equal to the pass reference value, the programming loop following the currently executing programming loop can be determined as the start time of the programming verification operation for the fourth programming state P4.

[0132] Figure 9 This is a diagram illustrating the start time of a programming verification operation for a programming state higher than the target programming state, according to an embodiment of the present disclosure.

[0133] Reference Figure 9 Programming verification operations targeting the first programming state P1 to the third programming state P3 can be performed at t1. The third programming state P3, which is the highest-ranked programming state among the first programming states P1 to the third programming states P3 targeted for the programming verification operation at t1, can be the target programming state.

[0134] The start time for the programming verification operation targeting the fourth programming state P4, which is a programming state higher than the third programming state P3, can be determined based on the result of the programming verification operation targeting the third programming state P3. In this embodiment, the programming state higher than the third programming state P3, which is the target programming state, is not limited to being interpreted as the fourth programming state P4. The programming state higher than the third programming state P3 can be interpreted as any programming state from the fourth programming state P4 to the seventh programming state P7.

[0135] At t1, when the number of bits with the predetermined logic value is the number of failure bits, the number of bits with the predetermined logic value counted in the programming verification operation for the third programming state P3 can be greater than the failure reference value. Alternatively, when the number of bits with the predetermined logic value is the number of success bits, the number of bits with the predetermined logic value counted in the programming verification operation for the third programming state P3 can be less than the success reference value.

[0136] Therefore, the start time of the programming verification operation for the fourth programming state P4 can be determined after programming loop PL4, which is executed after programming loop PL3 at t1.

[0137] At t2, when the number of bits with a predetermined logic value is the number of failure bits, the number of bits with a predetermined logic value counted in the programming verification operation for the third programming state P3 can be less than or equal to the failure reference value. Alternatively, when the number of bits with a predetermined logic value is the number of success bits, the number of bits with a predetermined logic value counted in the programming verification operation for the third programming state P3 can be greater than or equal to the success reference value.

[0138] Therefore, the start time of the programming verification operation for the fourth programming state P4 can be determined as the programming loop PL5 following the programming loop PL4 executed at t2.

[0139] Programming verification operations targeting the second programming states P2 through the fourth programming states P4 can be performed at t3. The fourth programming state P4, which is the highest-ranked programming state among the second programming states P2 through the fourth programming states P4 targeted by the programming verification operations performed at t3, can be the target programming state.

[0140] Similarly, the start time of the programming verification operation for the fifth programming state P5, which is a programming state higher than the fourth programming state P4, can be determined based on the result of the programming verification operation for the fourth programming state P4.

[0141] According to embodiments of this disclosure, based on the result of a programming verification operation targeting a target programming state among at least one programming state targeted by the current programming verification operation, programming operations targeting programming states higher than the target programming state can be started at an appropriate time. Therefore, it is possible to prevent programming verification operations targeting higher-order programming states from being performed unnecessarily early or late, and to reduce the total programming verification operation time.

[0142] Figure 10 This is an example of an embodiment according to the present disclosure. Figure 2 The diagram shows the page buffer.

[0143] Reference Figure 10 The page buffer can be connected to the memory cell via the bit line BL.

[0144] The page buffer may include a first precharge circuit (FPC) and a sense latch (QS Latch). The configuration of the circuitry included in the page buffer is not limited to this embodiment.

[0145] In the programming verification operation targeting the target programming state, the page buffer can precharge the bit line BL connected to the memory cell that is determined to be a programming failure based on the data QS stored in the sensing latch QS Latch in the memory cell to be programmed to the target programming state.

[0146] The sensing latch QS Latch can store data obtained by sensing the potential of the bit line BL connected to the memory cell via the sensing node SO. During the programming verification operation, the first precharge circuit FPC can precharge the bit line BL according to the first precharge signal SA_CSOC1 and the data QS.

[0147] In one implementation, during the programming verification operation for the target programming state, selected bit lines among multiple bit lines connected to multiple page buffers can be precharged according to the Sel BL scheme. The selected bit lines may be bit lines connected to memory cells in the memory cell to be programmed to the target programming state that have been determined to have failed programming based on data QS.

[0148] Before bit line BL is precharged, a bit line discharge signal BLDIS with a high level is applied, and thus the potential of bit line BL can be initialized to the ground voltage level. Subsequently, when bit line BL is precharged, a bit line discharge signal BLDIS with a low level and a page buffer control signal PB_SENSE with a high level can be applied.

[0149] During the programming verification operation, a first precharge signal SA_CSOC1 with a high level can be applied. When the data QS is low, the bit line BL can be precharged to a high level. When the data QS is high, the bit line BL can be discharged to a low level.

[0150] After the bit line BL is pre-charged, a programming verification voltage corresponding to the target programming state can be applied to the word line connected to the memory cell. When the programming verification voltage corresponding to the target programming state is applied to the word line, the number of failure bits—the number of memory cells determined to have failed programming—can be counted by sensing the potential or current of the bit line BL that changes according to the threshold voltage of the memory cell. The number of failure bits can be the number of bits with a predetermined logic value in the data sensed from the memory cell to be programmed into the target programming state.

[0151] Conversely, the number of passing bits can be counted by sensing the potential of the bit line BL, which changes according to the threshold voltage of the memory cell. This passing bit count can be a value obtained by inverting a predetermined logic value in the data sensed from the memory cell to be programmed into the target programming state.

[0152] Figure 11 This is an example of an embodiment according to the present disclosure. Figure 2 The diagram shows the page buffer.

[0153] Reference Figure 11 ,and Figure 10 Compared to the page buffer shown, the page buffer may also include a second precharge circuit SPC. During the programming verification operation, the second precharge circuit SPC can precharge the bit lines according to the second precharge signal SA_CSOC2.

[0154] In one implementation, during the programming verification operation for the target programming state, all multiple bit lines connected to multiple page buffers can be precharged according to the All BL scheme. The multiple bit lines can be precharged via a second precharge circuit (SPC), regardless of the data QS stored in the sense latch QS Latch.

[0155] Before bit line BL is precharged, a bit line discharge signal BLDIS with a high level is applied, and thus the potential of bit line BL can be initialized to the ground voltage level. When bit line BL is precharged, a bit line discharge signal BLDIS with a low level and a page buffer control signal PB_SENSE with a high level can be applied.

[0156] During the programming verification operation, a second precharge signal SA_CSOC2 with a high level can be applied, and the bit line BL can be precharged to a high level.

[0157] After the bit line BL is pre-charged, a programming verification voltage corresponding to the target programming state can be applied to the word line connected to the memory cell. When the programming verification voltage corresponding to the target programming state is applied to the word line, the number of failure bits—the number of memory cells determined to have failed programming—can be counted by sensing the potential or current of the bit line BL that changes according to the threshold voltage of the memory cell. The number of failure bits can be the number of bits with a predetermined logic value in the data sensed from the memory cell to be programmed into the target programming state.

[0158] Conversely, the number of passing bits can be counted by sensing the potential of the bit line BL, which changes according to the threshold voltage of the memory cell. This passing bit count can be a value obtained by inverting a predetermined logic value from the data sensed from the memory cell to be programmed into the target programming state.

[0159] Figure 12 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0160] Reference Figure 12 In operation S1201, the memory device can determine the start time of a programming verification operation for a programming state higher than the target programming state based on the result of a programming verification operation for a target programming state in at least one programming state in which a programming verification operation is performed.

[0161] In operation S1203, the memory device can begin a programming verification operation for a programming state higher than the target programming state from the programming cycle corresponding to the start time.

[0162] Figure 13 This is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure to determine the start time of a programming verification operation for a programming state higher than the target programming state.

[0163] Reference Figure 13 In operation S1301, the memory device can perform a programming verification operation for at least one of a plurality of programming states.

[0164] In operation S1303, the memory device may count the bits having a predetermined logic value in a programming verification operation for a target programming state in the at least one programming state.

[0165] In operation S1305, the memory device can determine the start time of the programming verification operation for a programming state higher than the target programming state based on the result obtained by comparing the number of bits of the count with a reference value.

[0166] Figure 14 This is a flowchart illustrating the programming verification operation of a memory device according to an embodiment of the present disclosure.

[0167] Reference Figure 14 In operation S1401, the memory device can select a bit line to be connected to a memory cell that is determined to be a programming failure based on data stored in the sense latch, among the memory cells to be programmed to the target programming state.

[0168] In operation S1403, during the programming verification operation for the target programming state, the memory device can precharge selected bit lines among multiple bit lines connected to multiple memory cells.

[0169] In operation S1405, the memory device can apply a programming verification voltage corresponding to the target programming state to the word lines connected to multiple memory cells.

[0170] In operation S1407, the memory device can count the number of bits having a predetermined logic value based on the value obtained by sensing the potential of the selected bit line.

[0171] Figure 15 This is a flowchart illustrating the programming verification operation of a memory device according to an embodiment of the present disclosure.

[0172] Reference Figure 15 In operation S1501, during the programming verification operation for the target programming state, the memory device can precharge all the multiple bit lines connected to multiple memory cells.

[0173] In operation S1503, the memory device can apply a programming verification voltage corresponding to the target programming state to the word lines connected to multiple memory cells.

[0174] In operation S1505, the memory device can count the number of bits having a predetermined logic value based on the value obtained by sensing the potential of multiple bit lines.

[0175] According to this disclosure, a memory device with improved programming performance and a method of operating the memory device are provided.

[0176] The methods, processes, and / or operations described herein can be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device.

[0177] When implemented at least partially in software, controllers, processors, managers, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing functions may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing apparatus. The computer, processor, microprocessor, controller, or other signal processing apparatus may be those apparatuses described herein or those other than those described herein. Because the algorithms constituting the method (or the operation of the computer, processor, microprocessor, controller, or other signal processing apparatus) are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing apparatus into a dedicated processor for executing the methods described herein.

[0178] While this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the exemplary embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

[0179] In the above embodiments, all steps may be selectively performed, or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described and may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0180] Furthermore, various embodiments of this disclosure have been described in the accompanying drawings and specification. While specific terminology is used herein, it is only for describing embodiments of this disclosure. Therefore, this disclosure is not limited to the described embodiments and many variations are possible within the spirit and scope of this disclosure. Those skilled in the art will understand that various modifications can be made beyond the embodiments disclosed herein, building upon the technical scope of this disclosure. Embodiments can be combined to form additional embodiments.

[0181] Cross-reference to related applications

[0182] This application claims priority to Korean Patent Application No. 10-2021-0023654, filed on February 22, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: Multiple memory units; Peripheral circuitry, wherein the peripheral circuitry programs the plurality of memory cells into a programming state among a plurality of programming states; as well as The control logic controls the peripheral circuitry to perform a programming verification operation for at least one of the plurality of programming states. This is achieved by comparing the programming verification voltage corresponding to the target programming state in the programming verification operation for the target programming state with threshold voltages of the plurality of memory cells to count the number of bits having a predetermined logic value. Furthermore, the start time of the programming verification operation for a higher-order programming state (above the target programming state) is determined based on a comparison between the number of bits having the predetermined logic value and a reference value. Specifically, the determination of the start time for executing programming verification operations for programming states higher than the target programming state whenever the target programming state changes.

2. The memory device according to claim 1, wherein, The target programming state is the highest programming state among the programming states in which programming operations have been performed.

3. The memory device according to claim 1, wherein, The control logic includes: Bit line voltage controller, the bit line voltage controller controlling the peripheral circuitry to precharge multiple bit lines connected to the plurality of memory cells; and A programming verification controller that determines the start time based on a result obtained by comparing the number of bits having the predetermined logic value with the reference value.

4. The memory device according to claim 3, wherein, The programming verification controller controls the peripheral circuit to start a programming verification operation for the programming state that is higher than the target programming state, from the programming loop corresponding to the start time.

5. The memory device according to claim 3, wherein, In a programming verification operation for the target programming state, the programming verification controller counts the number of failure bits (the number of memory cells determined to have failed programming) based on the number of bits having the predetermined logic value, and determines the start time of the programming verification operation for a programming state higher than the target programming state based on the result obtained by comparing the number of failure bits with the reference value.

6. The memory device according to claim 5, wherein, When the number of failures is less than or equal to the reference value, the programming verification controller controls the peripheral circuit to perform a programming verification operation for the programming state that is higher than the target programming state, starting from the programming loop following the current programming loop that is being executed.

7. The memory device according to claim 3, wherein, The peripheral circuitry includes multiple page buffers connected to the multiple memory cells via the multiple bit lines, and Each of the plurality of page buffers includes: A sense latch that stores data obtained by sensing the potential of a bit line connected to a memory cell via a sense node; and A first pre-charge circuit pre-charges the bit lines connected to the memory cell based on a first pre-charge signal and previous data stored in the sensing latch.

8. The memory device according to claim 7, wherein, The bit line voltage controller controls the first pre-charge circuit to pre-charge selected bit lines among the plurality of bit lines during the programming verification operation for the target programming state, and The selected bit line is a bit line connected to a memory cell in the memory cell to be programmed to the target programming state that was determined to be a programming failure based on the previous data stored in the sense latch.

9. The memory device according to claim 7, wherein, Each of the plurality of page buffers further includes a second precharge circuit that precharges the bit lines connected to the memory cell according to a second precharge signal.

10. The memory device according to claim 9, wherein, The bit line voltage controller controls the second precharge circuit to precharge all of the multiple bit lines during the programming verification operation for the target programming state.

11. A method for operating a memory device comprising a plurality of memory cells, the method comprising the steps of: Perform a programming verification operation for at least one of a plurality of programming states; The number of bits having a predetermined logic value is counted by comparing the programming verification voltage corresponding to the target programming state in the programming verification operation for the target programming state in the at least one programming state with the threshold voltage of the plurality of memory cells. as well as Whenever the target programming state changes, the start time of the programming verification operation for the programming state that is higher than the target programming state is determined based on a comparison between the number of bits having the predetermined logic value and a reference value.

12. The method of claim 11, further comprising the step of: The programming verification operation begins from the programming loop corresponding to the start time, targeting the programming state that is higher than the target programming state.

13. The method according to claim 11, wherein, The target programming state is the highest programming state among the programming states in which programming operations have been performed.

14. The method of claim 11, wherein, The step of determining the start time of the programming verification operation for a programming state higher than the target programming state includes the following steps: The number of failure bits is counted based on the number of memory cells determined to have failed programming, which are among the memory cells to be programmed into the target programming state, according to the number of bits having the predetermined logic value; and The start time for the programming verification operation for a programming state higher than the target programming state is determined based on the result obtained by comparing the number of failures with the reference value.

15. The method according to claim 14, wherein, When the number of failures is less than or equal to the reference value, the programming loop following the currently executing programming loop is determined as the start time of the programming verification operation for the programming state above the target programming state.

16. The method of claim 11, wherein, The steps of performing a programming verification operation for the target programming state in the at least one programming state include the following steps: Precharge all bit lines connected to the plurality of memory cells; and The programming verification voltage corresponding to the target programming state is applied to the word line connected to the plurality of memory cells.

17. The method according to claim 16, wherein, The step of counting the bits having the predetermined logic value includes the following steps: counting the number of memory cells among the plurality of memory cells that have a threshold voltage less than the programming verification voltage corresponding to the target programming state as the number of bits having the predetermined logic value.

18. The method according to claim 11, wherein, The steps of performing a programming verification operation for the target programming state in the at least one programming state include the following steps: Select the bit line connected to the memory cell that was determined to be a programming failure based on previous data stored in the sense latch, among the memory cells to be programmed to the target programming state. Precharge selected bit lines from among the multiple bit lines connected to the plurality of memory cells; and The programming verification voltage corresponding to the target programming state is applied to the word line connected to the plurality of memory cells.

19. The method according to claim 18, wherein, The step of counting the bits having the predetermined logic value includes the following steps: counting the number of memory cells in the memory cells to be programmed into the target programming state that have a threshold voltage less than the programming verification voltage corresponding to the target programming state as the number of bits having the predetermined logic value.

20. A memory device comprising: Multiple memory units; Peripheral circuitry, which is connected to the plurality of memory units; as well as Control logic, which is connected to the peripheral circuit and controls the peripheral circuit to: The plurality of memory units are programmed into a target programming state among a plurality of programming states; Perform a programming verification operation on the plurality of memory cells for the target programming state to verify whether the plurality of memory cells have the target programming state; The start time of the programming verification operation for the adjacent programming states to the target programming state is determined based on the number of memory cells associated with the pass or failure of the programming verification operation for the target programming state; and At the determined start time, a programming verification operation for the adjacent programming states is performed on the plurality of memory cells. Specifically, the start time for executing the programming verification operation for the adjacent programming state is determined whenever the target programming state changes.

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